2 * sata_sil.c - Silicon Image SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
33 * Other errata and documentation available under NDA.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.0"
55 SIL_FLAG_NO_SATA_IRQ
= (1 << 28),
56 SIL_FLAG_RERR_ON_DMA_ACT
= (1 << 29),
57 SIL_FLAG_MOD15WRITE
= (1 << 30),
59 SIL_DFL_HOST_FLAGS
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
60 ATA_FLAG_MMIO
| ATA_FLAG_HRST_TO_RESUME
,
66 sil_3112_no_sata_irq
= 1,
79 SIL_MASK_IDE0_INT
= (1 << 22),
80 SIL_MASK_IDE1_INT
= (1 << 23),
81 SIL_MASK_IDE2_INT
= (1 << 24),
82 SIL_MASK_IDE3_INT
= (1 << 25),
83 SIL_MASK_2PORT
= SIL_MASK_IDE0_INT
| SIL_MASK_IDE1_INT
,
84 SIL_MASK_4PORT
= SIL_MASK_2PORT
|
85 SIL_MASK_IDE2_INT
| SIL_MASK_IDE3_INT
,
88 SIL_INTR_STEERING
= (1 << 1),
90 SIL_DMA_ENABLE
= (1 << 0), /* DMA run switch */
91 SIL_DMA_RDWR
= (1 << 3), /* DMA Rd-Wr */
92 SIL_DMA_SATA_IRQ
= (1 << 4), /* OR of all SATA IRQs */
93 SIL_DMA_ACTIVE
= (1 << 16), /* DMA running */
94 SIL_DMA_ERROR
= (1 << 17), /* PCI bus error */
95 SIL_DMA_COMPLETE
= (1 << 18), /* cmd complete / IRQ pending */
96 SIL_DMA_N_SATA_IRQ
= (1 << 6), /* SATA_IRQ for the next channel */
97 SIL_DMA_N_ACTIVE
= (1 << 24), /* ACTIVE for the next channel */
98 SIL_DMA_N_ERROR
= (1 << 25), /* ERROR for the next channel */
99 SIL_DMA_N_COMPLETE
= (1 << 26), /* COMPLETE for the next channel */
102 SIL_SIEN_N
= (1 << 16), /* triggered by SError.N */
107 SIL_QUIRK_MOD15WRITE
= (1 << 0),
108 SIL_QUIRK_UDMA5MAX
= (1 << 1),
111 static int sil_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
112 static void sil_dev_config(struct ata_port
*ap
, struct ata_device
*dev
);
113 static u32
sil_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
114 static void sil_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
115 static void sil_post_set_mode (struct ata_port
*ap
);
116 static irqreturn_t
sil_interrupt(int irq
, void *dev_instance
,
117 struct pt_regs
*regs
);
118 static void sil_freeze(struct ata_port
*ap
);
119 static void sil_thaw(struct ata_port
*ap
);
122 static const struct pci_device_id sil_pci_tbl
[] = {
123 { 0x1095, 0x3112, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
124 { 0x1095, 0x0240, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
125 { 0x1095, 0x3512, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3512
},
126 { 0x1095, 0x3114, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3114
},
127 { 0x1002, 0x436e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
128 { 0x1002, 0x4379, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112_no_sata_irq
},
129 { 0x1002, 0x437a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112_no_sata_irq
},
130 { } /* terminate list */
134 /* TODO firmware versions should be added - eric */
135 static const struct sil_drivelist
{
136 const char * product
;
138 } sil_blacklist
[] = {
139 { "ST320012AS", SIL_QUIRK_MOD15WRITE
},
140 { "ST330013AS", SIL_QUIRK_MOD15WRITE
},
141 { "ST340017AS", SIL_QUIRK_MOD15WRITE
},
142 { "ST360015AS", SIL_QUIRK_MOD15WRITE
},
143 { "ST380013AS", SIL_QUIRK_MOD15WRITE
},
144 { "ST380023AS", SIL_QUIRK_MOD15WRITE
},
145 { "ST3120023AS", SIL_QUIRK_MOD15WRITE
},
146 { "ST3160023AS", SIL_QUIRK_MOD15WRITE
},
147 { "ST3120026AS", SIL_QUIRK_MOD15WRITE
},
148 { "ST3200822AS", SIL_QUIRK_MOD15WRITE
},
149 { "ST340014ASL", SIL_QUIRK_MOD15WRITE
},
150 { "ST360014ASL", SIL_QUIRK_MOD15WRITE
},
151 { "ST380011ASL", SIL_QUIRK_MOD15WRITE
},
152 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE
},
153 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE
},
154 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX
},
158 static struct pci_driver sil_pci_driver
= {
160 .id_table
= sil_pci_tbl
,
161 .probe
= sil_init_one
,
162 .remove
= ata_pci_remove_one
,
165 static struct scsi_host_template sil_sht
= {
166 .module
= THIS_MODULE
,
168 .ioctl
= ata_scsi_ioctl
,
169 .queuecommand
= ata_scsi_queuecmd
,
170 .can_queue
= ATA_DEF_QUEUE
,
171 .this_id
= ATA_SHT_THIS_ID
,
172 .sg_tablesize
= LIBATA_MAX_PRD
,
173 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
174 .emulated
= ATA_SHT_EMULATED
,
175 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
176 .proc_name
= DRV_NAME
,
177 .dma_boundary
= ATA_DMA_BOUNDARY
,
178 .slave_configure
= ata_scsi_slave_config
,
179 .slave_destroy
= ata_scsi_slave_destroy
,
180 .bios_param
= ata_std_bios_param
,
183 static const struct ata_port_operations sil_ops
= {
184 .port_disable
= ata_port_disable
,
185 .dev_config
= sil_dev_config
,
186 .tf_load
= ata_tf_load
,
187 .tf_read
= ata_tf_read
,
188 .check_status
= ata_check_status
,
189 .exec_command
= ata_exec_command
,
190 .dev_select
= ata_std_dev_select
,
191 .post_set_mode
= sil_post_set_mode
,
192 .bmdma_setup
= ata_bmdma_setup
,
193 .bmdma_start
= ata_bmdma_start
,
194 .bmdma_stop
= ata_bmdma_stop
,
195 .bmdma_status
= ata_bmdma_status
,
196 .qc_prep
= ata_qc_prep
,
197 .qc_issue
= ata_qc_issue_prot
,
198 .data_xfer
= ata_mmio_data_xfer
,
199 .freeze
= sil_freeze
,
201 .error_handler
= ata_bmdma_error_handler
,
202 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
203 .irq_handler
= sil_interrupt
,
204 .irq_clear
= ata_bmdma_irq_clear
,
205 .scr_read
= sil_scr_read
,
206 .scr_write
= sil_scr_write
,
207 .port_start
= ata_port_start
,
208 .port_stop
= ata_port_stop
,
209 .host_stop
= ata_pci_host_stop
,
212 static const struct ata_port_info sil_port_info
[] = {
216 .host_flags
= SIL_DFL_HOST_FLAGS
| SIL_FLAG_MOD15WRITE
,
217 .pio_mask
= 0x1f, /* pio0-4 */
218 .mwdma_mask
= 0x07, /* mwdma0-2 */
219 .udma_mask
= 0x3f, /* udma0-5 */
220 .port_ops
= &sil_ops
,
222 /* sil_3112_no_sata_irq */
225 .host_flags
= SIL_DFL_HOST_FLAGS
| SIL_FLAG_MOD15WRITE
|
226 SIL_FLAG_NO_SATA_IRQ
,
227 .pio_mask
= 0x1f, /* pio0-4 */
228 .mwdma_mask
= 0x07, /* mwdma0-2 */
229 .udma_mask
= 0x3f, /* udma0-5 */
230 .port_ops
= &sil_ops
,
235 .host_flags
= SIL_DFL_HOST_FLAGS
| SIL_FLAG_RERR_ON_DMA_ACT
,
236 .pio_mask
= 0x1f, /* pio0-4 */
237 .mwdma_mask
= 0x07, /* mwdma0-2 */
238 .udma_mask
= 0x3f, /* udma0-5 */
239 .port_ops
= &sil_ops
,
244 .host_flags
= SIL_DFL_HOST_FLAGS
| SIL_FLAG_RERR_ON_DMA_ACT
,
245 .pio_mask
= 0x1f, /* pio0-4 */
246 .mwdma_mask
= 0x07, /* mwdma0-2 */
247 .udma_mask
= 0x3f, /* udma0-5 */
248 .port_ops
= &sil_ops
,
252 /* per-port register offsets */
253 /* TODO: we can probably calculate rather than use a table */
254 static const struct {
255 unsigned long tf
; /* ATA taskfile register block */
256 unsigned long ctl
; /* ATA control/altstatus register block */
257 unsigned long bmdma
; /* DMA register block */
258 unsigned long bmdma2
; /* DMA register block #2 */
259 unsigned long fifo_cfg
; /* FIFO Valid Byte Count and Control */
260 unsigned long scr
; /* SATA control register block */
261 unsigned long sien
; /* SATA Interrupt Enable register */
262 unsigned long xfer_mode
;/* data transfer mode register */
263 unsigned long sfis_cfg
; /* SATA FIS reception config register */
266 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
267 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
268 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
269 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
273 MODULE_AUTHOR("Jeff Garzik");
274 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
275 MODULE_LICENSE("GPL");
276 MODULE_DEVICE_TABLE(pci
, sil_pci_tbl
);
277 MODULE_VERSION(DRV_VERSION
);
279 static int slow_down
= 0;
280 module_param(slow_down
, int, 0444);
281 MODULE_PARM_DESC(slow_down
, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
284 static unsigned char sil_get_device_cache_line(struct pci_dev
*pdev
)
287 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &cache_line
);
291 static void sil_post_set_mode (struct ata_port
*ap
)
293 struct ata_host_set
*host_set
= ap
->host_set
;
294 struct ata_device
*dev
;
296 host_set
->mmio_base
+ sil_port
[ap
->port_no
].xfer_mode
;
297 u32 tmp
, dev_mode
[2];
300 for (i
= 0; i
< 2; i
++) {
301 dev
= &ap
->device
[i
];
302 if (!ata_dev_enabled(dev
))
303 dev_mode
[i
] = 0; /* PIO0/1/2 */
304 else if (dev
->flags
& ATA_DFLAG_PIO
)
305 dev_mode
[i
] = 1; /* PIO3/4 */
307 dev_mode
[i
] = 3; /* UDMA */
308 /* value 2 indicates MDMA */
312 tmp
&= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
314 tmp
|= (dev_mode
[1] << 4);
316 readl(addr
); /* flush */
319 static inline unsigned long sil_scr_addr(struct ata_port
*ap
, unsigned int sc_reg
)
321 unsigned long offset
= ap
->ioaddr
.scr_addr
;
338 static u32
sil_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
340 void __iomem
*mmio
= (void __iomem
*) sil_scr_addr(ap
, sc_reg
);
346 static void sil_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
348 void *mmio
= (void __iomem
*) sil_scr_addr(ap
, sc_reg
);
353 static void sil_host_intr(struct ata_port
*ap
, u32 bmdma2
)
355 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
358 if (unlikely(bmdma2
& SIL_DMA_SATA_IRQ
)) {
361 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
362 * controllers continue to assert IRQ as long as
363 * SError bits are pending. Clear SError immediately.
365 serror
= sil_scr_read(ap
, SCR_ERROR
);
366 sil_scr_write(ap
, SCR_ERROR
, serror
);
368 /* Trigger hotplug and accumulate SError only if the
369 * port isn't already frozen. Otherwise, PHY events
370 * during hardreset makes controllers with broken SIEN
371 * repeat probing needlessly.
373 if (!(ap
->flags
& ATA_FLAG_FROZEN
)) {
374 ata_ehi_hotplugged(&ap
->eh_info
);
375 ap
->eh_info
.serror
|= serror
;
381 if (unlikely(!qc
|| qc
->tf
.ctl
& ATA_NIEN
))
384 /* Check whether we are expecting interrupt in this state */
385 switch (ap
->hsm_task_state
) {
387 /* Some pre-ATAPI-4 devices assert INTRQ
388 * at this state when ready to receive CDB.
391 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
392 * The flag was turned on only for atapi devices.
393 * No need to check is_atapi_taskfile(&qc->tf) again.
395 if (!(qc
->dev
->flags
& ATA_DFLAG_CDB_INTR
))
399 if (qc
->tf
.protocol
== ATA_PROT_DMA
||
400 qc
->tf
.protocol
== ATA_PROT_ATAPI_DMA
) {
401 /* clear DMA-Start bit */
402 ap
->ops
->bmdma_stop(qc
);
404 if (bmdma2
& SIL_DMA_ERROR
) {
405 qc
->err_mask
|= AC_ERR_HOST_BUS
;
406 ap
->hsm_task_state
= HSM_ST_ERR
;
416 /* check main status, clearing INTRQ */
417 status
= ata_chk_status(ap
);
418 if (unlikely(status
& ATA_BUSY
))
421 /* ack bmdma irq events */
422 ata_bmdma_irq_clear(ap
);
424 /* kick HSM in the ass */
425 ata_hsm_move(ap
, qc
, status
, 0);
430 qc
->err_mask
|= AC_ERR_HSM
;
435 static irqreturn_t
sil_interrupt(int irq
, void *dev_instance
,
436 struct pt_regs
*regs
)
438 struct ata_host_set
*host_set
= dev_instance
;
439 void __iomem
*mmio_base
= host_set
->mmio_base
;
443 spin_lock(&host_set
->lock
);
445 for (i
= 0; i
< host_set
->n_ports
; i
++) {
446 struct ata_port
*ap
= host_set
->ports
[i
];
447 u32 bmdma2
= readl(mmio_base
+ sil_port
[ap
->port_no
].bmdma2
);
449 if (unlikely(!ap
|| ap
->flags
& ATA_FLAG_DISABLED
))
452 /* turn off SATA_IRQ if not supported */
453 if (ap
->flags
& SIL_FLAG_NO_SATA_IRQ
)
454 bmdma2
&= ~SIL_DMA_SATA_IRQ
;
456 if (bmdma2
== 0xffffffff ||
457 !(bmdma2
& (SIL_DMA_COMPLETE
| SIL_DMA_SATA_IRQ
)))
460 sil_host_intr(ap
, bmdma2
);
464 spin_unlock(&host_set
->lock
);
466 return IRQ_RETVAL(handled
);
469 static void sil_freeze(struct ata_port
*ap
)
471 void __iomem
*mmio_base
= ap
->host_set
->mmio_base
;
474 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
475 writel(0, mmio_base
+ sil_port
[ap
->port_no
].sien
);
478 tmp
= readl(mmio_base
+ SIL_SYSCFG
);
479 tmp
|= SIL_MASK_IDE0_INT
<< ap
->port_no
;
480 writel(tmp
, mmio_base
+ SIL_SYSCFG
);
481 readl(mmio_base
+ SIL_SYSCFG
); /* flush */
484 static void sil_thaw(struct ata_port
*ap
)
486 void __iomem
*mmio_base
= ap
->host_set
->mmio_base
;
491 ata_bmdma_irq_clear(ap
);
493 /* turn on SATA IRQ if supported */
494 if (!(ap
->flags
& SIL_FLAG_NO_SATA_IRQ
))
495 writel(SIL_SIEN_N
, mmio_base
+ sil_port
[ap
->port_no
].sien
);
498 tmp
= readl(mmio_base
+ SIL_SYSCFG
);
499 tmp
&= ~(SIL_MASK_IDE0_INT
<< ap
->port_no
);
500 writel(tmp
, mmio_base
+ SIL_SYSCFG
);
504 * sil_dev_config - Apply device/host-specific errata fixups
505 * @ap: Port containing device to be examined
506 * @dev: Device to be examined
508 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
509 * device is known to be present, this function is called.
510 * We apply two errata fixups which are specific to Silicon Image,
511 * a Seagate and a Maxtor fixup.
513 * For certain Seagate devices, we must limit the maximum sectors
516 * For certain Maxtor devices, we must not program the drive
519 * Both fixups are unfairly pessimistic. As soon as I get more
520 * information on these errata, I will create a more exhaustive
521 * list, and apply the fixups to only the specific
522 * devices/hosts/firmwares that need it.
524 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
525 * The Maxtor quirk is in the blacklist, but I'm keeping the original
526 * pessimistic fix for the following reasons...
527 * - There seems to be less info on it, only one device gleaned off the
528 * Windows driver, maybe only one is affected. More info would be greatly
530 * - But then again UDMA5 is hardly anything to complain about
532 static void sil_dev_config(struct ata_port
*ap
, struct ata_device
*dev
)
534 unsigned int n
, quirks
= 0;
535 unsigned char model_num
[41];
537 ata_id_c_string(dev
->id
, model_num
, ATA_ID_PROD_OFS
, sizeof(model_num
));
539 for (n
= 0; sil_blacklist
[n
].product
; n
++)
540 if (!strcmp(sil_blacklist
[n
].product
, model_num
)) {
541 quirks
= sil_blacklist
[n
].quirk
;
545 /* limit requests to 15 sectors */
547 ((ap
->flags
& SIL_FLAG_MOD15WRITE
) &&
548 (quirks
& SIL_QUIRK_MOD15WRITE
))) {
549 ata_dev_printk(dev
, KERN_INFO
, "applying Seagate errata fix "
550 "(mod15write workaround)\n");
551 dev
->max_sectors
= 15;
556 if (quirks
& SIL_QUIRK_UDMA5MAX
) {
557 ata_dev_printk(dev
, KERN_INFO
,
558 "applying Maxtor errata fix %s\n", model_num
);
559 dev
->udma_mask
&= ATA_UDMA5
;
564 static int sil_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
566 static int printed_version
;
567 struct ata_probe_ent
*probe_ent
= NULL
;
569 void __iomem
*mmio_base
;
572 int pci_dev_busy
= 0;
576 if (!printed_version
++)
577 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
579 rc
= pci_enable_device(pdev
);
583 rc
= pci_request_regions(pdev
, DRV_NAME
);
589 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
591 goto err_out_regions
;
592 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
594 goto err_out_regions
;
596 probe_ent
= kzalloc(sizeof(*probe_ent
), GFP_KERNEL
);
597 if (probe_ent
== NULL
) {
599 goto err_out_regions
;
602 INIT_LIST_HEAD(&probe_ent
->node
);
603 probe_ent
->dev
= pci_dev_to_dev(pdev
);
604 probe_ent
->port_ops
= sil_port_info
[ent
->driver_data
].port_ops
;
605 probe_ent
->sht
= sil_port_info
[ent
->driver_data
].sht
;
606 probe_ent
->n_ports
= (ent
->driver_data
== sil_3114
) ? 4 : 2;
607 probe_ent
->pio_mask
= sil_port_info
[ent
->driver_data
].pio_mask
;
608 probe_ent
->mwdma_mask
= sil_port_info
[ent
->driver_data
].mwdma_mask
;
609 probe_ent
->udma_mask
= sil_port_info
[ent
->driver_data
].udma_mask
;
610 probe_ent
->irq
= pdev
->irq
;
611 probe_ent
->irq_flags
= SA_SHIRQ
;
612 probe_ent
->host_flags
= sil_port_info
[ent
->driver_data
].host_flags
;
614 mmio_base
= pci_iomap(pdev
, 5, 0);
615 if (mmio_base
== NULL
) {
617 goto err_out_free_ent
;
620 probe_ent
->mmio_base
= mmio_base
;
622 base
= (unsigned long) mmio_base
;
624 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
625 probe_ent
->port
[i
].cmd_addr
= base
+ sil_port
[i
].tf
;
626 probe_ent
->port
[i
].altstatus_addr
=
627 probe_ent
->port
[i
].ctl_addr
= base
+ sil_port
[i
].ctl
;
628 probe_ent
->port
[i
].bmdma_addr
= base
+ sil_port
[i
].bmdma
;
629 probe_ent
->port
[i
].scr_addr
= base
+ sil_port
[i
].scr
;
630 ata_std_ports(&probe_ent
->port
[i
]);
633 /* Initialize FIFO PCI bus arbitration */
634 cls
= sil_get_device_cache_line(pdev
);
637 cls
++; /* cls = (line_size/8)+1 */
638 for (i
= 0; i
< probe_ent
->n_ports
; i
++)
639 writew(cls
<< 8 | cls
,
640 mmio_base
+ sil_port
[i
].fifo_cfg
);
642 dev_printk(KERN_WARNING
, &pdev
->dev
,
643 "cache line size not set. Driver may not function\n");
645 /* Apply R_ERR on DMA activate FIS errata workaround */
646 if (probe_ent
->host_flags
& SIL_FLAG_RERR_ON_DMA_ACT
) {
649 for (i
= 0, cnt
= 0; i
< probe_ent
->n_ports
; i
++) {
650 tmp
= readl(mmio_base
+ sil_port
[i
].sfis_cfg
);
651 if ((tmp
& 0x3) != 0x01)
654 dev_printk(KERN_INFO
, &pdev
->dev
,
655 "Applying R_ERR on DMA activate "
657 writel(tmp
& ~0x3, mmio_base
+ sil_port
[i
].sfis_cfg
);
662 if (ent
->driver_data
== sil_3114
) {
663 /* flip the magic "make 4 ports work" bit */
664 tmp
= readl(mmio_base
+ sil_port
[2].bmdma
);
665 if ((tmp
& SIL_INTR_STEERING
) == 0)
666 writel(tmp
| SIL_INTR_STEERING
,
667 mmio_base
+ sil_port
[2].bmdma
);
670 pci_set_master(pdev
);
672 /* FIXME: check ata_device_add return value */
673 ata_device_add(probe_ent
);
681 pci_release_regions(pdev
);
684 pci_disable_device(pdev
);
688 static int __init
sil_init(void)
690 return pci_module_init(&sil_pci_driver
);
693 static void __exit
sil_exit(void)
695 pci_unregister_driver(&sil_pci_driver
);
699 module_init(sil_init
);
700 module_exit(sil_exit
);