arch/arm/mach-s3c2410/s3c2412.c

   1 /* linux/arch/arm/mach-s3c2410/s3c2412.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://armlinux.simtec.co.uk/.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Modifications:
  13  *     16-May-2003 BJD  Created initial version
  14  *     16-Aug-2003 BJD  Fixed header files and copyright, added URL
  15  *     05-Sep-2003 BJD  Moved to kernel v2.6
  16  *     18-Jan-2004 BJD  Added serial port configuration
  17  *     21-Aug-2004 BJD  Added new struct s3c2410_board handler
  18  *     28-Sep-2004 BJD  Updates for new serial port bits
  19  *     04-Nov-2004 BJD  Updated UART configuration process
  20  *     10-Jan-2005 BJD  Removed s3c2410_clock_tick_rate
  21  *     13-Aug-2005 DA   Removed UART from initial I/O mappings
  22 */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/types.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/list.h>
  28 #include <linux/timer.h>
  29 #include <linux/init.h>
  30 #include <linux/sysdev.h>
  31 #include <linux/platform_device.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach/irq.h>
  36
  37 #include <asm/hardware.h>
  38 #include <asm/proc-fns.h>
  39 #include <asm/io.h>
  40 #include <asm/irq.h>
  41
  42 #include <asm/arch/idle.h>
  43
  44 #include <asm/arch/regs-clock.h>
  45 #include <asm/arch/regs-serial.h>
  46 #include <asm/arch/regs-power.h>
  47 #include <asm/arch/regs-gpio.h>
  48 #include <asm/arch/regs-gpioj.h>
  49 #include <asm/arch/regs-dsc.h>
  50
  51 #include "s3c2412.h"
  52 #include "cpu.h"
  53 #include "devs.h"
  54 #include "clock.h"
  55 #include "pm.h"
  56
  57 #ifndef CONFIG_CPU_S3C2412_ONLY
  58 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
  59
  60 static inline void s3c2412_init_gpio2(void)
  61 {
  62         s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
  63 }
  64 #else
  65 #define s3c2412_init_gpio2() do { } while(0)
  66 #endif
  67
  68 /* Initial IO mappings */
  69
  70 static struct map_desc s3c2412_iodesc[] __initdata = {
  71         IODESC_ENT(CLKPWR),
  72         IODESC_ENT(LCD),
  73         IODESC_ENT(TIMER),
  74         IODESC_ENT(ADC),
  75         IODESC_ENT(WATCHDOG),
  76 };
  77
  78 /* uart registration process */
  79
  80 void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  81 {
  82         s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
  83
  84         /* rename devices that are s3c2412/s3c2413 specific */
  85         s3c_device_sdi.name  = "s3c2412-sdi";
  86         s3c_device_lcd.name  = "s3c2412-lcd";
  87         s3c_device_nand.name = "s3c2412-nand";
  88 }
  89
  90 /* s3c2412_idle
  91  *
  92  * use the standard idle call by ensuring the idle mode
  93  * in power config, then issuing the idle co-processor
  94  * instruction
  95 */
  96
  97 static void s3c2412_idle(void)
  98 {
  99         unsigned long tmp;
 100
 101         /* ensure our idle mode is to go to idle */
 102
 103         tmp = __raw_readl(S3C2412_PWRCFG);
 104         tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
 105         tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
 106         __raw_writel(tmp, S3C2412_PWRCFG);
 107
 108         cpu_do_idle();
 109 }
 110
 111 /* s3c2412_map_io
 112  *
 113  * register the standard cpu IO areas, and any passed in from the
 114  * machine specific initialisation.
 115 */
 116
 117 void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
 118 {
 119         /* move base of IO */
 120
 121         s3c2412_init_gpio2();
 122
 123         /* set our idle function */
 124
 125         s3c24xx_idle = s3c2412_idle;
 126
 127         /* register our io-tables */
 128
 129         iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
 130         iotable_init(mach_desc, mach_size);
 131 }
 132
 133 void __init s3c2412_init_clocks(int xtal)
 134 {
 135         unsigned long tmp;
 136         unsigned long fclk;
 137         unsigned long hclk;
 138         unsigned long pclk;
 139
 140         /* now we've got our machine bits initialised, work out what
 141          * clocks we've got */
 142
 143         fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
 144
 145         tmp = __raw_readl(S3C2410_CLKDIVN);
 146
 147         /* work out clock scalings */
 148
 149         hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
 150         hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
 151         pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
 152
 153         /* print brieft summary of clocks, etc */
 154
 155         printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
 156                print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
 157
 158         /* initialise the clocks here, to allow other things like the
 159          * console to use them
 160          */
 161
 162         s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
 163         s3c2412_baseclk_add();
 164 }
 165
 166 /* need to register class before we actually register the device, and
 167  * we also need to ensure that it has been initialised before any of the
 168  * drivers even try to use it (even if not on an s3c2412 based system)
 169  * as a driver which may support both 2410 and 2440 may try and use it.
 170 */
 171
 172 #ifdef CONFIG_PM
 173 static struct sleep_save s3c2412_sleep[] = {
 174         SAVE_ITEM(S3C2412_DSC0),
 175         SAVE_ITEM(S3C2412_DSC1),
 176         SAVE_ITEM(S3C2413_GPJDAT),
 177         SAVE_ITEM(S3C2413_GPJCON),
 178         SAVE_ITEM(S3C2413_GPJUP),
 179
 180         /* save the sleep configuration anyway, just in case these
 181          * get damaged during wakeup */
 182
 183         SAVE_ITEM(S3C2412_GPBSLPCON),
 184         SAVE_ITEM(S3C2412_GPCSLPCON),
 185         SAVE_ITEM(S3C2412_GPDSLPCON),
 186         SAVE_ITEM(S3C2412_GPESLPCON),
 187         SAVE_ITEM(S3C2412_GPFSLPCON),
 188         SAVE_ITEM(S3C2412_GPGSLPCON),
 189         SAVE_ITEM(S3C2412_GPHSLPCON),
 190         SAVE_ITEM(S3C2413_GPJSLPCON),
 191 };
 192
 193 static int s3c2412_suspend(struct sys_device *dev, pm_message_t state)
 194 {
 195         s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
 196         return 0;
 197 }
 198
 199 static int s3c2412_resume(struct sys_device *dev)
 200 {
 201         s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
 202         return 0;
 203 }
 204
 205 #else
 206 #define s3c2412_suspend NULL
 207 #define s3c2412_resume  NULL
 208 #endif
 209
 210 struct sysdev_class s3c2412_sysclass = {
 211         set_kset_name("s3c2412-core"),
 212         .suspend        = s3c2412_suspend,
 213         .resume         = s3c2412_resume
 214 };
 215
 216 static int __init s3c2412_core_init(void)
 217 {
 218         return sysdev_class_register(&s3c2412_sysclass);
 219 }
 220
 221 core_initcall(s3c2412_core_init);
 222
 223 static struct sys_device s3c2412_sysdev = {
 224         .cls            = &s3c2412_sysclass,
 225 };
 226
 227 int __init s3c2412_init(void)
 228 {
 229         printk("S3C2412: Initialising architecture\n");
 230
 231         return sysdev_register(&s3c2412_sysdev);
 232 }