2 * drivers/dma/imx-sdma.c
4 * This file contains a driver for the Freescale Smart DMA engine
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Based on code from Freescale:
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
20 #include <linux/init.h>
21 #include <linux/types.h>
23 #include <linux/interrupt.h>
24 #include <linux/clk.h>
25 #include <linux/wait.h>
26 #include <linux/sched.h>
27 #include <linux/semaphore.h>
28 #include <linux/spinlock.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/firmware.h>
32 #include <linux/slab.h>
33 #include <linux/platform_device.h>
34 #include <linux/dmaengine.h>
37 #include <mach/sdma.h>
39 #include <mach/hardware.h>
42 #define SDMA_H_C0PTR 0x000
43 #define SDMA_H_INTR 0x004
44 #define SDMA_H_STATSTOP 0x008
45 #define SDMA_H_START 0x00c
46 #define SDMA_H_EVTOVR 0x010
47 #define SDMA_H_DSPOVR 0x014
48 #define SDMA_H_HOSTOVR 0x018
49 #define SDMA_H_EVTPEND 0x01c
50 #define SDMA_H_DSPENBL 0x020
51 #define SDMA_H_RESET 0x024
52 #define SDMA_H_EVTERR 0x028
53 #define SDMA_H_INTRMSK 0x02c
54 #define SDMA_H_PSW 0x030
55 #define SDMA_H_EVTERRDBG 0x034
56 #define SDMA_H_CONFIG 0x038
57 #define SDMA_ONCE_ENB 0x040
58 #define SDMA_ONCE_DATA 0x044
59 #define SDMA_ONCE_INSTR 0x048
60 #define SDMA_ONCE_STAT 0x04c
61 #define SDMA_ONCE_CMD 0x050
62 #define SDMA_EVT_MIRROR 0x054
63 #define SDMA_ILLINSTADDR 0x058
64 #define SDMA_CHN0ADDR 0x05c
65 #define SDMA_ONCE_RTB 0x060
66 #define SDMA_XTRIG_CONF1 0x070
67 #define SDMA_XTRIG_CONF2 0x074
68 #define SDMA_CHNENBL0_V2 0x200
69 #define SDMA_CHNENBL0_V1 0x080
70 #define SDMA_CHNPRI_0 0x100
73 * Buffer descriptor status values.
84 * Data Node descriptor status values.
86 #define DND_END_OF_FRAME 0x80
87 #define DND_END_OF_XFER 0x40
89 #define DND_UNUSED 0x01
92 * IPCV2 descriptor status values.
94 #define BD_IPCV2_END_OF_FRAME 0x40
96 #define IPCV2_MAX_NODES 50
98 * Error bit set in the CCB status field by the SDMA,
99 * in setbd routine, in case of a transfer error
101 #define DATA_ERROR 0x10000000
104 * Buffer descriptor commands.
109 #define C0_SETCTX 0x07
110 #define C0_GETCTX 0x03
111 #define C0_SETDM 0x01
112 #define C0_SETPM 0x04
113 #define C0_GETDM 0x02
114 #define C0_GETPM 0x08
116 * Change endianness indicator in the BD command field
118 #define CHANGE_ENDIANNESS 0x80
121 * Mode/Count of data node descriptors - IPCv2
123 struct sdma_mode_count
{
124 u32 count
: 16; /* size of the buffer pointed by this BD */
125 u32 status
: 8; /* E,R,I,C,W,D status bits stored here */
126 u32 command
: 8; /* command mostlky used for channel 0 */
132 struct sdma_buffer_descriptor
{
133 struct sdma_mode_count mode
;
134 u32 buffer_addr
; /* address of the buffer described */
135 u32 ext_buffer_addr
; /* extended buffer address */
136 } __attribute__ ((packed
));
139 * struct sdma_channel_control - Channel control Block
141 * @current_bd_ptr current buffer descriptor processed
142 * @base_bd_ptr first element of buffer descriptor array
143 * @unused padding. The SDMA engine expects an array of 128 byte
146 struct sdma_channel_control
{
150 } __attribute__ ((packed
));
153 * struct sdma_state_registers - SDMA context for a channel
155 * @pc: program counter
156 * @t: test bit: status of arithmetic & test instruction
157 * @rpc: return program counter
158 * @sf: source fault while loading data
159 * @spc: loop start program counter
160 * @df: destination fault while storing data
161 * @epc: loop end program counter
164 struct sdma_state_registers
{
176 } __attribute__ ((packed
));
179 * struct sdma_context_data - sdma context specific to a channel
181 * @channel_state: channel state bits
182 * @gReg: general registers
183 * @mda: burst dma destination address register
184 * @msa: burst dma source address register
185 * @ms: burst dma status register
186 * @md: burst dma data register
187 * @pda: peripheral dma destination address register
188 * @psa: peripheral dma source address register
189 * @ps: peripheral dma status register
190 * @pd: peripheral dma data register
191 * @ca: CRC polynomial register
192 * @cs: CRC accumulator register
193 * @dda: dedicated core destination address register
194 * @dsa: dedicated core source address register
195 * @ds: dedicated core status register
196 * @dd: dedicated core data register
198 struct sdma_context_data
{
199 struct sdma_state_registers channel_state
;
223 } __attribute__ ((packed
));
225 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
230 * struct sdma_channel - housekeeping for a SDMA channel
232 * @sdma pointer to the SDMA engine for this channel
233 * @channel the channel number, matches dmaengine chan_id
234 * @direction transfer type. Needed for setting SDMA script
235 * @peripheral_type Peripheral type. Needed for setting SDMA script
236 * @event_id0 aka dma request line
237 * @event_id1 for channels that use 2 events
238 * @word_size peripheral access size
239 * @buf_tail ID of the buffer that was processed
240 * @done channel completion
241 * @num_bd max NUM_BD. number of descriptors currently handling
243 struct sdma_channel
{
244 struct sdma_engine
*sdma
;
245 unsigned int channel
;
246 enum dma_data_direction direction
;
247 enum sdma_peripheral_type peripheral_type
;
248 unsigned int event_id0
;
249 unsigned int event_id1
;
250 enum dma_slave_buswidth word_size
;
251 unsigned int buf_tail
;
252 struct completion done
;
254 struct sdma_buffer_descriptor
*bd
;
256 unsigned int pc_from_device
, pc_to_device
;
258 dma_addr_t per_address
;
259 u32 event_mask0
, event_mask1
;
261 u32 shp_addr
, per_addr
;
262 struct dma_chan chan
;
264 struct dma_async_tx_descriptor desc
;
265 dma_cookie_t last_completed
;
266 enum dma_status status
;
269 #define IMX_DMA_SG_LOOP (1 << 0)
271 #define MAX_DMA_CHANNELS 32
272 #define MXC_SDMA_DEFAULT_PRIORITY 1
273 #define MXC_SDMA_MIN_PRIORITY 1
274 #define MXC_SDMA_MAX_PRIORITY 7
276 #define SDMA_FIRMWARE_MAGIC 0x414d4453
279 * struct sdma_firmware_header - Layout of the firmware image
282 * @version_major increased whenever layout of struct sdma_script_start_addrs
284 * @version_minor firmware minor version (for binary compatible changes)
285 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
286 * @num_script_addrs Number of script addresses in this image
287 * @ram_code_start offset of SDMA ram image in this firmware image
288 * @ram_code_size size of SDMA ram image
289 * @script_addrs Stores the start address of the SDMA scripts
290 * (in SDMA memory space)
292 struct sdma_firmware_header
{
296 u32 script_addrs_start
;
297 u32 num_script_addrs
;
304 struct device_dma_parameters dma_parms
;
305 struct sdma_channel channel
[MAX_DMA_CHANNELS
];
306 struct sdma_channel_control
*channel_control
;
308 unsigned int version
;
309 unsigned int num_events
;
310 struct sdma_context_data
*context
;
311 dma_addr_t context_phys
;
312 struct dma_device dma_device
;
314 struct sdma_script_start_addrs
*script_addrs
;
317 #define SDMA_H_CONFIG_DSPDMA (1 << 12) /* indicates if the DSPDMA is used */
318 #define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
319 #define SDMA_H_CONFIG_ACR (1 << 4) /* indicates if AHB freq /core freq = 2 or 1 */
320 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
322 static inline u32
chnenbl_ofs(struct sdma_engine
*sdma
, unsigned int event
)
324 u32 chnenbl0
= (sdma
->version
== 2 ? SDMA_CHNENBL0_V2
: SDMA_CHNENBL0_V1
);
326 return chnenbl0
+ event
* 4;
329 static int sdma_config_ownership(struct sdma_channel
*sdmac
,
330 bool event_override
, bool mcu_override
, bool dsp_override
)
332 struct sdma_engine
*sdma
= sdmac
->sdma
;
333 int channel
= sdmac
->channel
;
336 if (event_override
&& mcu_override
&& dsp_override
)
339 evt
= __raw_readl(sdma
->regs
+ SDMA_H_EVTOVR
);
340 mcu
= __raw_readl(sdma
->regs
+ SDMA_H_HOSTOVR
);
341 dsp
= __raw_readl(sdma
->regs
+ SDMA_H_DSPOVR
);
344 dsp
&= ~(1 << channel
);
346 dsp
|= (1 << channel
);
349 evt
&= ~(1 << channel
);
351 evt
|= (1 << channel
);
354 mcu
&= ~(1 << channel
);
356 mcu
|= (1 << channel
);
358 __raw_writel(evt
, sdma
->regs
+ SDMA_H_EVTOVR
);
359 __raw_writel(mcu
, sdma
->regs
+ SDMA_H_HOSTOVR
);
360 __raw_writel(dsp
, sdma
->regs
+ SDMA_H_DSPOVR
);
366 * sdma_run_channel - run a channel and wait till it's done
368 static int sdma_run_channel(struct sdma_channel
*sdmac
)
370 struct sdma_engine
*sdma
= sdmac
->sdma
;
371 int channel
= sdmac
->channel
;
374 init_completion(&sdmac
->done
);
376 __raw_writel(1 << channel
, sdma
->regs
+ SDMA_H_START
);
378 ret
= wait_for_completion_timeout(&sdmac
->done
, HZ
);
380 return ret
? 0 : -ETIMEDOUT
;
383 static int sdma_load_script(struct sdma_engine
*sdma
, void *buf
, int size
,
386 struct sdma_buffer_descriptor
*bd0
= sdma
->channel
[0].bd
;
391 buf_virt
= dma_alloc_coherent(NULL
,
393 &buf_phys
, GFP_KERNEL
);
397 bd0
->mode
.command
= C0_SETPM
;
398 bd0
->mode
.status
= BD_DONE
| BD_INTR
| BD_WRAP
| BD_EXTD
;
399 bd0
->mode
.count
= size
/ 2;
400 bd0
->buffer_addr
= buf_phys
;
401 bd0
->ext_buffer_addr
= address
;
403 memcpy(buf_virt
, buf
, size
);
405 ret
= sdma_run_channel(&sdma
->channel
[0]);
407 dma_free_coherent(NULL
, size
, buf_virt
, buf_phys
);
412 static void sdma_event_enable(struct sdma_channel
*sdmac
, unsigned int event
)
414 struct sdma_engine
*sdma
= sdmac
->sdma
;
415 int channel
= sdmac
->channel
;
417 u32 chnenbl
= chnenbl_ofs(sdma
, event
);
419 val
= __raw_readl(sdma
->regs
+ chnenbl
);
420 val
|= (1 << channel
);
421 __raw_writel(val
, sdma
->regs
+ chnenbl
);
424 static void sdma_event_disable(struct sdma_channel
*sdmac
, unsigned int event
)
426 struct sdma_engine
*sdma
= sdmac
->sdma
;
427 int channel
= sdmac
->channel
;
428 u32 chnenbl
= chnenbl_ofs(sdma
, event
);
431 val
= __raw_readl(sdma
->regs
+ chnenbl
);
432 val
&= ~(1 << channel
);
433 __raw_writel(val
, sdma
->regs
+ chnenbl
);
436 static void sdma_handle_channel_loop(struct sdma_channel
*sdmac
)
438 struct sdma_buffer_descriptor
*bd
;
441 * loop mode. Iterate over descriptors, re-setup them and
442 * call callback function.
445 bd
= &sdmac
->bd
[sdmac
->buf_tail
];
447 if (bd
->mode
.status
& BD_DONE
)
450 if (bd
->mode
.status
& BD_RROR
)
451 sdmac
->status
= DMA_ERROR
;
453 sdmac
->status
= DMA_SUCCESS
;
455 bd
->mode
.status
|= BD_DONE
;
457 sdmac
->buf_tail
%= sdmac
->num_bd
;
459 if (sdmac
->desc
.callback
)
460 sdmac
->desc
.callback(sdmac
->desc
.callback_param
);
464 static void mxc_sdma_handle_channel_normal(struct sdma_channel
*sdmac
)
466 struct sdma_buffer_descriptor
*bd
;
470 * non loop mode. Iterate over all descriptors, collect
471 * errors and call callback function
473 for (i
= 0; i
< sdmac
->num_bd
; i
++) {
476 if (bd
->mode
.status
& (BD_DONE
| BD_RROR
))
481 sdmac
->status
= DMA_ERROR
;
483 sdmac
->status
= DMA_SUCCESS
;
485 if (sdmac
->desc
.callback
)
486 sdmac
->desc
.callback(sdmac
->desc
.callback_param
);
487 sdmac
->last_completed
= sdmac
->desc
.cookie
;
490 static void mxc_sdma_handle_channel(struct sdma_channel
*sdmac
)
492 complete(&sdmac
->done
);
494 /* not interested in channel 0 interrupts */
495 if (sdmac
->channel
== 0)
498 if (sdmac
->flags
& IMX_DMA_SG_LOOP
)
499 sdma_handle_channel_loop(sdmac
);
501 mxc_sdma_handle_channel_normal(sdmac
);
504 static irqreturn_t
sdma_int_handler(int irq
, void *dev_id
)
506 struct sdma_engine
*sdma
= dev_id
;
509 stat
= __raw_readl(sdma
->regs
+ SDMA_H_INTR
);
510 __raw_writel(stat
, sdma
->regs
+ SDMA_H_INTR
);
513 int channel
= fls(stat
) - 1;
514 struct sdma_channel
*sdmac
= &sdma
->channel
[channel
];
516 mxc_sdma_handle_channel(sdmac
);
518 stat
&= ~(1 << channel
);
525 * sets the pc of SDMA script according to the peripheral type
527 static void sdma_get_pc(struct sdma_channel
*sdmac
,
528 enum sdma_peripheral_type peripheral_type
)
530 struct sdma_engine
*sdma
= sdmac
->sdma
;
531 int per_2_emi
= 0, emi_2_per
= 0;
533 * These are needed once we start to support transfers between
534 * two peripherals or memory-to-memory transfers
536 int per_2_per
= 0, emi_2_emi
= 0;
538 sdmac
->pc_from_device
= 0;
539 sdmac
->pc_to_device
= 0;
541 switch (peripheral_type
) {
542 case IMX_DMATYPE_MEMORY
:
543 emi_2_emi
= sdma
->script_addrs
->ap_2_ap_addr
;
545 case IMX_DMATYPE_DSP
:
546 emi_2_per
= sdma
->script_addrs
->bp_2_ap_addr
;
547 per_2_emi
= sdma
->script_addrs
->ap_2_bp_addr
;
549 case IMX_DMATYPE_FIRI
:
550 per_2_emi
= sdma
->script_addrs
->firi_2_mcu_addr
;
551 emi_2_per
= sdma
->script_addrs
->mcu_2_firi_addr
;
553 case IMX_DMATYPE_UART
:
554 per_2_emi
= sdma
->script_addrs
->uart_2_mcu_addr
;
555 emi_2_per
= sdma
->script_addrs
->mcu_2_app_addr
;
557 case IMX_DMATYPE_UART_SP
:
558 per_2_emi
= sdma
->script_addrs
->uartsh_2_mcu_addr
;
559 emi_2_per
= sdma
->script_addrs
->mcu_2_shp_addr
;
561 case IMX_DMATYPE_ATA
:
562 per_2_emi
= sdma
->script_addrs
->ata_2_mcu_addr
;
563 emi_2_per
= sdma
->script_addrs
->mcu_2_ata_addr
;
565 case IMX_DMATYPE_CSPI
:
566 case IMX_DMATYPE_EXT
:
567 case IMX_DMATYPE_SSI
:
568 per_2_emi
= sdma
->script_addrs
->app_2_mcu_addr
;
569 emi_2_per
= sdma
->script_addrs
->mcu_2_app_addr
;
571 case IMX_DMATYPE_SSI_SP
:
572 case IMX_DMATYPE_MMC
:
573 case IMX_DMATYPE_SDHC
:
574 case IMX_DMATYPE_CSPI_SP
:
575 case IMX_DMATYPE_ESAI
:
576 case IMX_DMATYPE_MSHC_SP
:
577 per_2_emi
= sdma
->script_addrs
->shp_2_mcu_addr
;
578 emi_2_per
= sdma
->script_addrs
->mcu_2_shp_addr
;
580 case IMX_DMATYPE_ASRC
:
581 per_2_emi
= sdma
->script_addrs
->asrc_2_mcu_addr
;
582 emi_2_per
= sdma
->script_addrs
->asrc_2_mcu_addr
;
583 per_2_per
= sdma
->script_addrs
->per_2_per_addr
;
585 case IMX_DMATYPE_MSHC
:
586 per_2_emi
= sdma
->script_addrs
->mshc_2_mcu_addr
;
587 emi_2_per
= sdma
->script_addrs
->mcu_2_mshc_addr
;
589 case IMX_DMATYPE_CCM
:
590 per_2_emi
= sdma
->script_addrs
->dptc_dvfs_addr
;
592 case IMX_DMATYPE_SPDIF
:
593 per_2_emi
= sdma
->script_addrs
->spdif_2_mcu_addr
;
594 emi_2_per
= sdma
->script_addrs
->mcu_2_spdif_addr
;
596 case IMX_DMATYPE_IPU_MEMORY
:
597 emi_2_per
= sdma
->script_addrs
->ext_mem_2_ipu_addr
;
603 sdmac
->pc_from_device
= per_2_emi
;
604 sdmac
->pc_to_device
= emi_2_per
;
607 static int sdma_load_context(struct sdma_channel
*sdmac
)
609 struct sdma_engine
*sdma
= sdmac
->sdma
;
610 int channel
= sdmac
->channel
;
612 struct sdma_context_data
*context
= sdma
->context
;
613 struct sdma_buffer_descriptor
*bd0
= sdma
->channel
[0].bd
;
616 if (sdmac
->direction
== DMA_FROM_DEVICE
) {
617 load_address
= sdmac
->pc_from_device
;
619 load_address
= sdmac
->pc_to_device
;
622 if (load_address
< 0)
625 dev_dbg(sdma
->dev
, "load_address = %d\n", load_address
);
626 dev_dbg(sdma
->dev
, "wml = 0x%08x\n", sdmac
->watermark_level
);
627 dev_dbg(sdma
->dev
, "shp_addr = 0x%08x\n", sdmac
->shp_addr
);
628 dev_dbg(sdma
->dev
, "per_addr = 0x%08x\n", sdmac
->per_addr
);
629 dev_dbg(sdma
->dev
, "event_mask0 = 0x%08x\n", sdmac
->event_mask0
);
630 dev_dbg(sdma
->dev
, "event_mask1 = 0x%08x\n", sdmac
->event_mask1
);
632 memset(context
, 0, sizeof(*context
));
633 context
->channel_state
.pc
= load_address
;
635 /* Send by context the event mask,base address for peripheral
636 * and watermark level
638 context
->gReg
[0] = sdmac
->event_mask1
;
639 context
->gReg
[1] = sdmac
->event_mask0
;
640 context
->gReg
[2] = sdmac
->per_addr
;
641 context
->gReg
[6] = sdmac
->shp_addr
;
642 context
->gReg
[7] = sdmac
->watermark_level
;
644 bd0
->mode
.command
= C0_SETDM
;
645 bd0
->mode
.status
= BD_DONE
| BD_INTR
| BD_WRAP
| BD_EXTD
;
646 bd0
->mode
.count
= sizeof(*context
) / 4;
647 bd0
->buffer_addr
= sdma
->context_phys
;
648 bd0
->ext_buffer_addr
= 2048 + (sizeof(*context
) / 4) * channel
;
650 ret
= sdma_run_channel(&sdma
->channel
[0]);
655 static void sdma_disable_channel(struct sdma_channel
*sdmac
)
657 struct sdma_engine
*sdma
= sdmac
->sdma
;
658 int channel
= sdmac
->channel
;
660 __raw_writel(1 << channel
, sdma
->regs
+ SDMA_H_STATSTOP
);
661 sdmac
->status
= DMA_ERROR
;
664 static int sdma_config_channel(struct sdma_channel
*sdmac
)
668 sdma_disable_channel(sdmac
);
670 sdmac
->event_mask0
= 0;
671 sdmac
->event_mask1
= 0;
675 if (sdmac
->event_id0
) {
676 if (sdmac
->event_id0
> 32)
678 sdma_event_enable(sdmac
, sdmac
->event_id0
);
681 switch (sdmac
->peripheral_type
) {
682 case IMX_DMATYPE_DSP
:
683 sdma_config_ownership(sdmac
, false, true, true);
685 case IMX_DMATYPE_MEMORY
:
686 sdma_config_ownership(sdmac
, false, true, false);
689 sdma_config_ownership(sdmac
, true, true, false);
693 sdma_get_pc(sdmac
, sdmac
->peripheral_type
);
695 if ((sdmac
->peripheral_type
!= IMX_DMATYPE_MEMORY
) &&
696 (sdmac
->peripheral_type
!= IMX_DMATYPE_DSP
)) {
697 /* Handle multiple event channels differently */
698 if (sdmac
->event_id1
) {
699 sdmac
->event_mask1
= 1 << (sdmac
->event_id1
% 32);
700 if (sdmac
->event_id1
> 31)
701 sdmac
->watermark_level
|= 1 << 31;
702 sdmac
->event_mask0
= 1 << (sdmac
->event_id0
% 32);
703 if (sdmac
->event_id0
> 31)
704 sdmac
->watermark_level
|= 1 << 30;
706 sdmac
->event_mask0
= 1 << sdmac
->event_id0
;
707 sdmac
->event_mask1
= 1 << (sdmac
->event_id0
- 32);
709 /* Watermark Level */
710 sdmac
->watermark_level
|= sdmac
->watermark_level
;
712 sdmac
->shp_addr
= sdmac
->per_address
;
714 sdmac
->watermark_level
= 0; /* FIXME: M3_BASE_ADDRESS */
717 ret
= sdma_load_context(sdmac
);
722 static int sdma_set_channel_priority(struct sdma_channel
*sdmac
,
723 unsigned int priority
)
725 struct sdma_engine
*sdma
= sdmac
->sdma
;
726 int channel
= sdmac
->channel
;
728 if (priority
< MXC_SDMA_MIN_PRIORITY
729 || priority
> MXC_SDMA_MAX_PRIORITY
) {
733 __raw_writel(priority
, sdma
->regs
+ SDMA_CHNPRI_0
+ 4 * channel
);
738 static int sdma_request_channel(struct sdma_channel
*sdmac
)
740 struct sdma_engine
*sdma
= sdmac
->sdma
;
741 int channel
= sdmac
->channel
;
744 sdmac
->bd
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &sdmac
->bd_phys
, GFP_KERNEL
);
750 memset(sdmac
->bd
, 0, PAGE_SIZE
);
752 sdma
->channel_control
[channel
].base_bd_ptr
= sdmac
->bd_phys
;
753 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
755 clk_enable(sdma
->clk
);
757 sdma_set_channel_priority(sdmac
, MXC_SDMA_DEFAULT_PRIORITY
);
759 init_completion(&sdmac
->done
);
769 static void sdma_enable_channel(struct sdma_engine
*sdma
, int channel
)
771 __raw_writel(1 << channel
, sdma
->regs
+ SDMA_H_START
);
774 static dma_cookie_t
sdma_assign_cookie(struct sdma_channel
*sdma
)
776 dma_cookie_t cookie
= sdma
->chan
.cookie
;
781 sdma
->chan
.cookie
= cookie
;
782 sdma
->desc
.cookie
= cookie
;
787 static struct sdma_channel
*to_sdma_chan(struct dma_chan
*chan
)
789 return container_of(chan
, struct sdma_channel
, chan
);
792 static dma_cookie_t
sdma_tx_submit(struct dma_async_tx_descriptor
*tx
)
794 struct sdma_channel
*sdmac
= to_sdma_chan(tx
->chan
);
795 struct sdma_engine
*sdma
= sdmac
->sdma
;
798 spin_lock_irq(&sdmac
->lock
);
800 cookie
= sdma_assign_cookie(sdmac
);
802 sdma_enable_channel(sdma
, tx
->chan
->chan_id
);
804 spin_unlock_irq(&sdmac
->lock
);
809 static int sdma_alloc_chan_resources(struct dma_chan
*chan
)
811 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
812 struct imx_dma_data
*data
= chan
->private;
815 /* No need to execute this for internal channel 0 */
816 if (chan
->chan_id
== 0)
822 switch (data
->priority
) {
826 case DMA_PRIO_MEDIUM
:
835 sdmac
->peripheral_type
= data
->peripheral_type
;
836 sdmac
->event_id0
= data
->dma_request
;
837 ret
= sdma_set_channel_priority(sdmac
, prio
);
841 ret
= sdma_request_channel(sdmac
);
845 dma_async_tx_descriptor_init(&sdmac
->desc
, chan
);
846 sdmac
->desc
.tx_submit
= sdma_tx_submit
;
847 /* txd.flags will be overwritten in prep funcs */
848 sdmac
->desc
.flags
= DMA_CTRL_ACK
;
853 static void sdma_free_chan_resources(struct dma_chan
*chan
)
855 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
856 struct sdma_engine
*sdma
= sdmac
->sdma
;
858 sdma_disable_channel(sdmac
);
860 if (sdmac
->event_id0
)
861 sdma_event_disable(sdmac
, sdmac
->event_id0
);
862 if (sdmac
->event_id1
)
863 sdma_event_disable(sdmac
, sdmac
->event_id1
);
865 sdmac
->event_id0
= 0;
866 sdmac
->event_id1
= 0;
868 sdma_set_channel_priority(sdmac
, 0);
870 dma_free_coherent(NULL
, PAGE_SIZE
, sdmac
->bd
, sdmac
->bd_phys
);
872 clk_disable(sdma
->clk
);
875 static struct dma_async_tx_descriptor
*sdma_prep_slave_sg(
876 struct dma_chan
*chan
, struct scatterlist
*sgl
,
877 unsigned int sg_len
, enum dma_data_direction direction
,
880 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
881 struct sdma_engine
*sdma
= sdmac
->sdma
;
883 int channel
= chan
->chan_id
;
884 struct scatterlist
*sg
;
886 if (sdmac
->status
== DMA_IN_PROGRESS
)
888 sdmac
->status
= DMA_IN_PROGRESS
;
892 dev_dbg(sdma
->dev
, "setting up %d entries for channel %d.\n",
895 sdmac
->direction
= direction
;
896 ret
= sdma_load_context(sdmac
);
900 if (sg_len
> NUM_BD
) {
901 dev_err(sdma
->dev
, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
902 channel
, sg_len
, NUM_BD
);
907 for_each_sg(sgl
, sg
, sg_len
, i
) {
908 struct sdma_buffer_descriptor
*bd
= &sdmac
->bd
[i
];
911 bd
->buffer_addr
= sg
->dma_address
;
915 if (count
> 0xffff) {
916 dev_err(sdma
->dev
, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
917 channel
, count
, 0xffff);
922 bd
->mode
.count
= count
;
924 if (sdmac
->word_size
> DMA_SLAVE_BUSWIDTH_4_BYTES
) {
929 switch (sdmac
->word_size
) {
930 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
931 bd
->mode
.command
= 0;
932 if (count
& 3 || sg
->dma_address
& 3)
935 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
936 bd
->mode
.command
= 2;
937 if (count
& 1 || sg
->dma_address
& 1)
940 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
941 bd
->mode
.command
= 1;
947 param
= BD_DONE
| BD_EXTD
| BD_CONT
;
949 if (sdmac
->flags
& IMX_DMA_SG_LOOP
) {
958 dev_dbg(sdma
->dev
, "entry %d: count: %d dma: 0x%08x %s%s\n",
959 i
, count
, sg
->dma_address
,
960 param
& BD_WRAP
? "wrap" : "",
961 param
& BD_INTR
? " intr" : "");
963 bd
->mode
.status
= param
;
966 sdmac
->num_bd
= sg_len
;
967 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
974 static struct dma_async_tx_descriptor
*sdma_prep_dma_cyclic(
975 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t buf_len
,
976 size_t period_len
, enum dma_data_direction direction
)
978 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
979 struct sdma_engine
*sdma
= sdmac
->sdma
;
980 int num_periods
= buf_len
/ period_len
;
981 int channel
= chan
->chan_id
;
982 int ret
, i
= 0, buf
= 0;
984 dev_dbg(sdma
->dev
, "%s channel: %d\n", __func__
, channel
);
986 if (sdmac
->status
== DMA_IN_PROGRESS
)
989 sdmac
->status
= DMA_IN_PROGRESS
;
991 sdmac
->flags
|= IMX_DMA_SG_LOOP
;
992 sdmac
->direction
= direction
;
993 ret
= sdma_load_context(sdmac
);
997 if (num_periods
> NUM_BD
) {
998 dev_err(sdma
->dev
, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
999 channel
, num_periods
, NUM_BD
);
1003 if (period_len
> 0xffff) {
1004 dev_err(sdma
->dev
, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1005 channel
, period_len
, 0xffff);
1009 while (buf
< buf_len
) {
1010 struct sdma_buffer_descriptor
*bd
= &sdmac
->bd
[i
];
1013 bd
->buffer_addr
= dma_addr
;
1015 bd
->mode
.count
= period_len
;
1017 if (sdmac
->word_size
> DMA_SLAVE_BUSWIDTH_4_BYTES
)
1019 if (sdmac
->word_size
== DMA_SLAVE_BUSWIDTH_4_BYTES
)
1020 bd
->mode
.command
= 0;
1022 bd
->mode
.command
= sdmac
->word_size
;
1024 param
= BD_DONE
| BD_EXTD
| BD_CONT
| BD_INTR
;
1025 if (i
+ 1 == num_periods
)
1028 dev_dbg(sdma
->dev
, "entry %d: count: %d dma: 0x%08x %s%s\n",
1029 i
, period_len
, dma_addr
,
1030 param
& BD_WRAP
? "wrap" : "",
1031 param
& BD_INTR
? " intr" : "");
1033 bd
->mode
.status
= param
;
1035 dma_addr
+= period_len
;
1041 sdmac
->num_bd
= num_periods
;
1042 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
1044 return &sdmac
->desc
;
1046 sdmac
->status
= DMA_ERROR
;
1050 static int sdma_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1053 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1054 struct dma_slave_config
*dmaengine_cfg
= (void *)arg
;
1057 case DMA_TERMINATE_ALL
:
1058 sdma_disable_channel(sdmac
);
1060 case DMA_SLAVE_CONFIG
:
1061 if (dmaengine_cfg
->direction
== DMA_FROM_DEVICE
) {
1062 sdmac
->per_address
= dmaengine_cfg
->src_addr
;
1063 sdmac
->watermark_level
= dmaengine_cfg
->src_maxburst
;
1064 sdmac
->word_size
= dmaengine_cfg
->src_addr_width
;
1066 sdmac
->per_address
= dmaengine_cfg
->dst_addr
;
1067 sdmac
->watermark_level
= dmaengine_cfg
->dst_maxburst
;
1068 sdmac
->word_size
= dmaengine_cfg
->dst_addr_width
;
1070 return sdma_config_channel(sdmac
);
1078 static enum dma_status
sdma_tx_status(struct dma_chan
*chan
,
1079 dma_cookie_t cookie
,
1080 struct dma_tx_state
*txstate
)
1082 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1083 dma_cookie_t last_used
;
1084 enum dma_status ret
;
1086 last_used
= chan
->cookie
;
1088 ret
= dma_async_is_complete(cookie
, sdmac
->last_completed
, last_used
);
1089 dma_set_tx_state(txstate
, sdmac
->last_completed
, last_used
, 0);
1094 static void sdma_issue_pending(struct dma_chan
*chan
)
1097 * Nothing to do. We only have a single descriptor
1101 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1103 static void sdma_add_scripts(struct sdma_engine
*sdma
,
1104 const struct sdma_script_start_addrs
*addr
)
1106 s32
*addr_arr
= (u32
*)addr
;
1107 s32
*saddr_arr
= (u32
*)sdma
->script_addrs
;
1110 for (i
= 0; i
< SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1
; i
++)
1111 if (addr_arr
[i
] > 0)
1112 saddr_arr
[i
] = addr_arr
[i
];
1115 static int __init
sdma_get_firmware(struct sdma_engine
*sdma
,
1116 const char *cpu_name
, int to_version
)
1118 const struct firmware
*fw
;
1120 const struct sdma_firmware_header
*header
;
1122 const struct sdma_script_start_addrs
*addr
;
1123 unsigned short *ram_code
;
1125 fwname
= kasprintf(GFP_KERNEL
, "sdma-%s-to%d.bin", cpu_name
, to_version
);
1129 ret
= request_firmware(&fw
, fwname
, sdma
->dev
);
1136 if (fw
->size
< sizeof(*header
))
1139 header
= (struct sdma_firmware_header
*)fw
->data
;
1141 if (header
->magic
!= SDMA_FIRMWARE_MAGIC
)
1143 if (header
->ram_code_start
+ header
->ram_code_size
> fw
->size
)
1146 addr
= (void *)header
+ header
->script_addrs_start
;
1147 ram_code
= (void *)header
+ header
->ram_code_start
;
1149 clk_enable(sdma
->clk
);
1150 /* download the RAM image for SDMA */
1151 sdma_load_script(sdma
, ram_code
,
1152 header
->ram_code_size
,
1153 sdma
->script_addrs
->ram_code_start_addr
);
1154 clk_disable(sdma
->clk
);
1156 sdma_add_scripts(sdma
, addr
);
1158 dev_info(sdma
->dev
, "loaded firmware %d.%d\n",
1159 header
->version_major
,
1160 header
->version_minor
);
1163 release_firmware(fw
);
1168 static int __init
sdma_init(struct sdma_engine
*sdma
)
1171 dma_addr_t ccb_phys
;
1173 switch (sdma
->version
) {
1175 sdma
->num_events
= 32;
1178 sdma
->num_events
= 48;
1181 dev_err(sdma
->dev
, "Unknown version %d. aborting\n", sdma
->version
);
1185 clk_enable(sdma
->clk
);
1187 /* Be sure SDMA has not started yet */
1188 __raw_writel(0, sdma
->regs
+ SDMA_H_C0PTR
);
1190 sdma
->channel_control
= dma_alloc_coherent(NULL
,
1191 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
) +
1192 sizeof(struct sdma_context_data
),
1193 &ccb_phys
, GFP_KERNEL
);
1195 if (!sdma
->channel_control
) {
1200 sdma
->context
= (void *)sdma
->channel_control
+
1201 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
);
1202 sdma
->context_phys
= ccb_phys
+
1203 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
);
1205 /* Zero-out the CCB structures array just allocated */
1206 memset(sdma
->channel_control
, 0,
1207 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
));
1209 /* disable all channels */
1210 for (i
= 0; i
< sdma
->num_events
; i
++)
1211 __raw_writel(0, sdma
->regs
+ chnenbl_ofs(sdma
, i
));
1213 /* All channels have priority 0 */
1214 for (i
= 0; i
< MAX_DMA_CHANNELS
; i
++)
1215 __raw_writel(0, sdma
->regs
+ SDMA_CHNPRI_0
+ i
* 4);
1217 ret
= sdma_request_channel(&sdma
->channel
[0]);
1221 sdma_config_ownership(&sdma
->channel
[0], false, true, false);
1223 /* Set Command Channel (Channel Zero) */
1224 __raw_writel(0x4050, sdma
->regs
+ SDMA_CHN0ADDR
);
1226 /* Set bits of CONFIG register but with static context switching */
1227 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1228 __raw_writel(0, sdma
->regs
+ SDMA_H_CONFIG
);
1230 __raw_writel(ccb_phys
, sdma
->regs
+ SDMA_H_C0PTR
);
1232 /* Set bits of CONFIG register with given context switching mode */
1233 __raw_writel(SDMA_H_CONFIG_CSM
, sdma
->regs
+ SDMA_H_CONFIG
);
1235 /* Initializes channel's priorities */
1236 sdma_set_channel_priority(&sdma
->channel
[0], 7);
1238 clk_disable(sdma
->clk
);
1243 clk_disable(sdma
->clk
);
1244 dev_err(sdma
->dev
, "initialisation failed with %d\n", ret
);
1248 static int __init
sdma_probe(struct platform_device
*pdev
)
1252 struct resource
*iores
;
1253 struct sdma_platform_data
*pdata
= pdev
->dev
.platform_data
;
1255 dma_cap_mask_t mask
;
1256 struct sdma_engine
*sdma
;
1258 sdma
= kzalloc(sizeof(*sdma
), GFP_KERNEL
);
1262 sdma
->dev
= &pdev
->dev
;
1264 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1265 irq
= platform_get_irq(pdev
, 0);
1266 if (!iores
|| irq
< 0 || !pdata
) {
1271 if (!request_mem_region(iores
->start
, resource_size(iores
), pdev
->name
)) {
1273 goto err_request_region
;
1276 sdma
->clk
= clk_get(&pdev
->dev
, NULL
);
1277 if (IS_ERR(sdma
->clk
)) {
1278 ret
= PTR_ERR(sdma
->clk
);
1282 sdma
->regs
= ioremap(iores
->start
, resource_size(iores
));
1288 ret
= request_irq(irq
, sdma_int_handler
, 0, "sdma", sdma
);
1290 goto err_request_irq
;
1292 sdma
->script_addrs
= kzalloc(sizeof(*sdma
->script_addrs
), GFP_KERNEL
);
1293 if (!sdma
->script_addrs
)
1296 sdma
->version
= pdata
->sdma_version
;
1298 dma_cap_set(DMA_SLAVE
, sdma
->dma_device
.cap_mask
);
1299 dma_cap_set(DMA_CYCLIC
, sdma
->dma_device
.cap_mask
);
1301 INIT_LIST_HEAD(&sdma
->dma_device
.channels
);
1302 /* Initialize channel parameters */
1303 for (i
= 0; i
< MAX_DMA_CHANNELS
; i
++) {
1304 struct sdma_channel
*sdmac
= &sdma
->channel
[i
];
1307 spin_lock_init(&sdmac
->lock
);
1309 sdmac
->chan
.device
= &sdma
->dma_device
;
1312 /* Add the channel to the DMAC list */
1313 list_add_tail(&sdmac
->chan
.device_node
, &sdma
->dma_device
.channels
);
1316 ret
= sdma_init(sdma
);
1320 if (pdata
->script_addrs
)
1321 sdma_add_scripts(sdma
, pdata
->script_addrs
);
1323 sdma_get_firmware(sdma
, pdata
->cpu_name
, pdata
->to_version
);
1325 sdma
->dma_device
.dev
= &pdev
->dev
;
1327 sdma
->dma_device
.device_alloc_chan_resources
= sdma_alloc_chan_resources
;
1328 sdma
->dma_device
.device_free_chan_resources
= sdma_free_chan_resources
;
1329 sdma
->dma_device
.device_tx_status
= sdma_tx_status
;
1330 sdma
->dma_device
.device_prep_slave_sg
= sdma_prep_slave_sg
;
1331 sdma
->dma_device
.device_prep_dma_cyclic
= sdma_prep_dma_cyclic
;
1332 sdma
->dma_device
.device_control
= sdma_control
;
1333 sdma
->dma_device
.device_issue_pending
= sdma_issue_pending
;
1334 sdma
->dma_device
.dev
->dma_parms
= &sdma
->dma_parms
;
1335 dma_set_max_seg_size(sdma
->dma_device
.dev
, 65535);
1337 ret
= dma_async_device_register(&sdma
->dma_device
);
1339 dev_err(&pdev
->dev
, "unable to register\n");
1343 /* request channel 0. This is an internal control channel
1344 * to the SDMA engine and not available to clients.
1347 dma_cap_set(DMA_SLAVE
, mask
);
1348 dma_request_channel(mask
, NULL
, NULL
);
1350 dev_info(sdma
->dev
, "initialized\n");
1355 kfree(sdma
->script_addrs
);
1357 free_irq(irq
, sdma
);
1359 iounmap(sdma
->regs
);
1363 release_mem_region(iores
->start
, resource_size(iores
));
1370 static int __exit
sdma_remove(struct platform_device
*pdev
)
1375 static struct platform_driver sdma_driver
= {
1379 .remove
= __exit_p(sdma_remove
),
1382 static int __init
sdma_module_init(void)
1384 return platform_driver_probe(&sdma_driver
, sdma_probe
);
1386 module_init(sdma_module_init
);
1388 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1389 MODULE_DESCRIPTION("i.MX SDMA driver");
1390 MODULE_LICENSE("GPL");