1 /* linux/drivers/video/s3c2410fb.c
2 * Copyright (c) 2004,2005 Arnaud Patard
3 * Copyright (c) 2004-2008 Ben Dooks
5 * S3C2410 LCD Framebuffer Driver
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
11 * Driver based on skeletonfb.c, sa1100fb.c and others.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/cpufreq.h>
31 #include <asm/div64.h>
33 #include <asm/mach/map.h>
34 #include <mach/regs-lcd.h>
35 #include <mach/regs-gpio.h>
42 #include "s3c2410fb.h"
45 #ifdef CONFIG_FB_S3C2410_DEBUG
51 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
53 /* useful functions */
55 static int is_s3c2412(struct s3c2410fb_info
*fbi
)
57 return (fbi
->drv_type
== DRV_S3C2412
);
60 /* s3c2410fb_set_lcdaddr
62 * initialise lcd controller address pointers
64 static void s3c2410fb_set_lcdaddr(struct fb_info
*info
)
66 unsigned long saddr1
, saddr2
, saddr3
;
67 struct s3c2410fb_info
*fbi
= info
->par
;
68 void __iomem
*regs
= fbi
->io
;
70 saddr1
= info
->fix
.smem_start
>> 1;
71 saddr2
= info
->fix
.smem_start
;
72 saddr2
+= info
->fix
.line_length
* info
->var
.yres
;
75 saddr3
= S3C2410_OFFSIZE(0) |
76 S3C2410_PAGEWIDTH((info
->fix
.line_length
/ 2) & 0x3ff);
78 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1
);
79 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2
);
80 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3
);
82 writel(saddr1
, regs
+ S3C2410_LCDSADDR1
);
83 writel(saddr2
, regs
+ S3C2410_LCDSADDR2
);
84 writel(saddr3
, regs
+ S3C2410_LCDSADDR3
);
87 /* s3c2410fb_calc_pixclk()
89 * calculate divisor for clk->pixclk
91 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info
*fbi
,
94 unsigned long clk
= fbi
->clk_rate
;
95 unsigned long long div
;
97 /* pixclk is in picoseconds, our clock is in Hz
99 * Hz -> picoseconds is / 10^-12
102 div
= (unsigned long long)clk
* pixclk
;
103 div
>>= 12; /* div / 2^12 */
104 do_div(div
, 625 * 625UL * 625); /* div / 5^12 */
106 dprintk("pixclk %ld, divisor is %ld\n", pixclk
, (long)div
);
111 * s3c2410fb_check_var():
112 * Get the video params out of 'var'. If a value doesn't fit, round it up,
113 * if it's too big, return -EINVAL.
116 static int s3c2410fb_check_var(struct fb_var_screeninfo
*var
,
117 struct fb_info
*info
)
119 struct s3c2410fb_info
*fbi
= info
->par
;
120 struct s3c2410fb_mach_info
*mach_info
= fbi
->dev
->platform_data
;
121 struct s3c2410fb_display
*display
= NULL
;
122 struct s3c2410fb_display
*default_display
= mach_info
->displays
+
123 mach_info
->default_display
;
124 int type
= default_display
->type
;
127 dprintk("check_var(var=%p, info=%p)\n", var
, info
);
129 /* validate x/y resolution */
130 /* choose default mode if possible */
131 if (var
->yres
== default_display
->yres
&&
132 var
->xres
== default_display
->xres
&&
133 var
->bits_per_pixel
== default_display
->bpp
)
134 display
= default_display
;
136 for (i
= 0; i
< mach_info
->num_displays
; i
++)
137 if (type
== mach_info
->displays
[i
].type
&&
138 var
->yres
== mach_info
->displays
[i
].yres
&&
139 var
->xres
== mach_info
->displays
[i
].xres
&&
140 var
->bits_per_pixel
== mach_info
->displays
[i
].bpp
) {
141 display
= mach_info
->displays
+ i
;
146 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
147 var
->xres
, var
->yres
, var
->bits_per_pixel
);
151 /* it is always the size as the display */
152 var
->xres_virtual
= display
->xres
;
153 var
->yres_virtual
= display
->yres
;
154 var
->height
= display
->height
;
155 var
->width
= display
->width
;
157 /* copy lcd settings */
158 var
->pixclock
= display
->pixclock
;
159 var
->left_margin
= display
->left_margin
;
160 var
->right_margin
= display
->right_margin
;
161 var
->upper_margin
= display
->upper_margin
;
162 var
->lower_margin
= display
->lower_margin
;
163 var
->vsync_len
= display
->vsync_len
;
164 var
->hsync_len
= display
->hsync_len
;
166 fbi
->regs
.lcdcon5
= display
->lcdcon5
;
167 /* set display type */
168 fbi
->regs
.lcdcon1
= display
->type
;
170 var
->transp
.offset
= 0;
171 var
->transp
.length
= 0;
172 /* set r/g/b positions */
173 switch (var
->bits_per_pixel
) {
178 var
->red
.length
= var
->bits_per_pixel
;
179 var
->green
= var
->red
;
180 var
->blue
= var
->red
;
183 if (display
->type
!= S3C2410_LCDCON1_TFT
) {
187 var
->green
.length
= 3;
188 var
->green
.offset
= 2;
189 var
->blue
.length
= 2;
190 var
->blue
.offset
= 0;
194 var
->green
= var
->red
;
195 var
->blue
= var
->red
;
202 var
->green
.length
= 4;
203 var
->green
.offset
= 4;
204 var
->blue
.length
= 4;
205 var
->blue
.offset
= 0;
210 if (display
->lcdcon5
& S3C2410_LCDCON5_FRM565
) {
211 /* 16 bpp, 565 format */
212 var
->red
.offset
= 11;
213 var
->green
.offset
= 5;
214 var
->blue
.offset
= 0;
216 var
->green
.length
= 6;
217 var
->blue
.length
= 5;
219 /* 16 bpp, 5551 format */
220 var
->red
.offset
= 11;
221 var
->green
.offset
= 6;
222 var
->blue
.offset
= 1;
224 var
->green
.length
= 5;
225 var
->blue
.length
= 5;
229 /* 24 bpp 888 and 8 dummy */
231 var
->red
.offset
= 16;
232 var
->green
.length
= 8;
233 var
->green
.offset
= 8;
234 var
->blue
.length
= 8;
235 var
->blue
.offset
= 0;
241 /* s3c2410fb_calculate_stn_lcd_regs
243 * calculate register values from var settings
245 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info
*info
,
246 struct s3c2410fb_hw
*regs
)
248 const struct s3c2410fb_info
*fbi
= info
->par
;
249 const struct fb_var_screeninfo
*var
= &info
->var
;
250 int type
= regs
->lcdcon1
& ~S3C2410_LCDCON1_TFT
;
251 int hs
= var
->xres
>> 2;
252 unsigned wdly
= (var
->left_margin
>> 4) - 1;
253 unsigned wlh
= (var
->hsync_len
>> 4) - 1;
255 if (type
!= S3C2410_LCDCON1_STN4
)
258 switch (var
->bits_per_pixel
) {
260 regs
->lcdcon1
|= S3C2410_LCDCON1_STN1BPP
;
263 regs
->lcdcon1
|= S3C2410_LCDCON1_STN2GREY
;
266 regs
->lcdcon1
|= S3C2410_LCDCON1_STN4GREY
;
269 regs
->lcdcon1
|= S3C2410_LCDCON1_STN8BPP
;
273 regs
->lcdcon1
|= S3C2410_LCDCON1_STN12BPP
;
278 /* invalid pixel depth */
279 dev_err(fbi
->dev
, "invalid bpp %d\n",
280 var
->bits_per_pixel
);
282 /* update X/Y info */
283 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
284 var
->left_margin
, var
->right_margin
, var
->hsync_len
);
286 regs
->lcdcon2
= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1);
294 regs
->lcdcon3
= S3C2410_LCDCON3_WDLY(wdly
) |
295 S3C2410_LCDCON3_LINEBLANK(var
->right_margin
/ 8) |
296 S3C2410_LCDCON3_HOZVAL(hs
- 1);
298 regs
->lcdcon4
= S3C2410_LCDCON4_WLH(wlh
);
301 /* s3c2410fb_calculate_tft_lcd_regs
303 * calculate register values from var settings
305 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info
*info
,
306 struct s3c2410fb_hw
*regs
)
308 const struct s3c2410fb_info
*fbi
= info
->par
;
309 const struct fb_var_screeninfo
*var
= &info
->var
;
311 switch (var
->bits_per_pixel
) {
313 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT1BPP
;
316 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT2BPP
;
319 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT4BPP
;
322 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT8BPP
;
323 regs
->lcdcon5
|= S3C2410_LCDCON5_BSWP
|
324 S3C2410_LCDCON5_FRM565
;
325 regs
->lcdcon5
&= ~S3C2410_LCDCON5_HWSWP
;
328 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT16BPP
;
329 regs
->lcdcon5
&= ~S3C2410_LCDCON5_BSWP
;
330 regs
->lcdcon5
|= S3C2410_LCDCON5_HWSWP
;
333 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT24BPP
;
334 regs
->lcdcon5
&= ~(S3C2410_LCDCON5_BSWP
|
335 S3C2410_LCDCON5_HWSWP
|
336 S3C2410_LCDCON5_BPP24BL
);
339 /* invalid pixel depth */
340 dev_err(fbi
->dev
, "invalid bpp %d\n",
341 var
->bits_per_pixel
);
343 /* update X/Y info */
344 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
345 var
->upper_margin
, var
->lower_margin
, var
->vsync_len
);
347 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
348 var
->left_margin
, var
->right_margin
, var
->hsync_len
);
350 regs
->lcdcon2
= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1) |
351 S3C2410_LCDCON2_VBPD(var
->upper_margin
- 1) |
352 S3C2410_LCDCON2_VFPD(var
->lower_margin
- 1) |
353 S3C2410_LCDCON2_VSPW(var
->vsync_len
- 1);
355 regs
->lcdcon3
= S3C2410_LCDCON3_HBPD(var
->right_margin
- 1) |
356 S3C2410_LCDCON3_HFPD(var
->left_margin
- 1) |
357 S3C2410_LCDCON3_HOZVAL(var
->xres
- 1);
359 regs
->lcdcon4
= S3C2410_LCDCON4_HSPW(var
->hsync_len
- 1);
362 /* s3c2410fb_activate_var
364 * activate (set) the controller from the given framebuffer
367 static void s3c2410fb_activate_var(struct fb_info
*info
)
369 struct s3c2410fb_info
*fbi
= info
->par
;
370 void __iomem
*regs
= fbi
->io
;
371 int type
= fbi
->regs
.lcdcon1
& S3C2410_LCDCON1_TFT
;
372 struct fb_var_screeninfo
*var
= &info
->var
;
375 clkdiv
= DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi
, var
->pixclock
), 2);
377 dprintk("%s: var->xres = %d\n", __func__
, var
->xres
);
378 dprintk("%s: var->yres = %d\n", __func__
, var
->yres
);
379 dprintk("%s: var->bpp = %d\n", __func__
, var
->bits_per_pixel
);
381 if (type
== S3C2410_LCDCON1_TFT
) {
382 s3c2410fb_calculate_tft_lcd_regs(info
, &fbi
->regs
);
387 s3c2410fb_calculate_stn_lcd_regs(info
, &fbi
->regs
);
392 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_CLKVAL(clkdiv
);
394 /* write new registers */
396 dprintk("new register set:\n");
397 dprintk("lcdcon[1] = 0x%08lx\n", fbi
->regs
.lcdcon1
);
398 dprintk("lcdcon[2] = 0x%08lx\n", fbi
->regs
.lcdcon2
);
399 dprintk("lcdcon[3] = 0x%08lx\n", fbi
->regs
.lcdcon3
);
400 dprintk("lcdcon[4] = 0x%08lx\n", fbi
->regs
.lcdcon4
);
401 dprintk("lcdcon[5] = 0x%08lx\n", fbi
->regs
.lcdcon5
);
403 writel(fbi
->regs
.lcdcon1
& ~S3C2410_LCDCON1_ENVID
,
404 regs
+ S3C2410_LCDCON1
);
405 writel(fbi
->regs
.lcdcon2
, regs
+ S3C2410_LCDCON2
);
406 writel(fbi
->regs
.lcdcon3
, regs
+ S3C2410_LCDCON3
);
407 writel(fbi
->regs
.lcdcon4
, regs
+ S3C2410_LCDCON4
);
408 writel(fbi
->regs
.lcdcon5
, regs
+ S3C2410_LCDCON5
);
410 /* set lcd address pointers */
411 s3c2410fb_set_lcdaddr(info
);
413 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_ENVID
,
414 writel(fbi
->regs
.lcdcon1
, regs
+ S3C2410_LCDCON1
);
418 * s3c2410fb_set_par - Alters the hardware state.
419 * @info: frame buffer structure that represents a single frame buffer
422 static int s3c2410fb_set_par(struct fb_info
*info
)
424 struct fb_var_screeninfo
*var
= &info
->var
;
426 switch (var
->bits_per_pixel
) {
430 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
433 info
->fix
.visual
= FB_VISUAL_MONO01
;
436 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
440 info
->fix
.line_length
= (var
->xres_virtual
* var
->bits_per_pixel
) / 8;
442 /* activate this new configuration */
444 s3c2410fb_activate_var(info
);
448 static void schedule_palette_update(struct s3c2410fb_info
*fbi
,
449 unsigned int regno
, unsigned int val
)
453 void __iomem
*irq_base
= fbi
->irq_base
;
455 local_irq_save(flags
);
457 fbi
->palette_buffer
[regno
] = val
;
459 if (!fbi
->palette_ready
) {
460 fbi
->palette_ready
= 1;
463 irqen
= readl(irq_base
+ S3C24XX_LCDINTMSK
);
464 irqen
&= ~S3C2410_LCDINT_FRSYNC
;
465 writel(irqen
, irq_base
+ S3C24XX_LCDINTMSK
);
468 local_irq_restore(flags
);
472 static inline unsigned int chan_to_field(unsigned int chan
,
473 struct fb_bitfield
*bf
)
476 chan
>>= 16 - bf
->length
;
477 return chan
<< bf
->offset
;
480 static int s3c2410fb_setcolreg(unsigned regno
,
481 unsigned red
, unsigned green
, unsigned blue
,
482 unsigned transp
, struct fb_info
*info
)
484 struct s3c2410fb_info
*fbi
= info
->par
;
485 void __iomem
*regs
= fbi
->io
;
488 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
489 regno, red, green, blue); */
491 switch (info
->fix
.visual
) {
492 case FB_VISUAL_TRUECOLOR
:
493 /* true-colour, use pseudo-palette */
496 u32
*pal
= info
->pseudo_palette
;
498 val
= chan_to_field(red
, &info
->var
.red
);
499 val
|= chan_to_field(green
, &info
->var
.green
);
500 val
|= chan_to_field(blue
, &info
->var
.blue
);
506 case FB_VISUAL_PSEUDOCOLOR
:
508 /* currently assume RGB 5-6-5 mode */
510 val
= (red
>> 0) & 0xf800;
511 val
|= (green
>> 5) & 0x07e0;
512 val
|= (blue
>> 11) & 0x001f;
514 writel(val
, regs
+ S3C2410_TFTPAL(regno
));
515 schedule_palette_update(fbi
, regno
, val
);
521 return 1; /* unknown type */
527 /* s3c2410fb_lcd_enable
529 * shutdown the lcd controller
531 static void s3c2410fb_lcd_enable(struct s3c2410fb_info
*fbi
, int enable
)
535 local_irq_save(flags
);
538 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_ENVID
;
540 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
542 writel(fbi
->regs
.lcdcon1
, fbi
->io
+ S3C2410_LCDCON1
);
544 local_irq_restore(flags
);
550 * @blank_mode: the blank mode we want.
551 * @info: frame buffer structure that represents a single frame buffer
553 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
554 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
555 * video mode which doesn't support it. Implements VESA suspend
556 * and powerdown modes on hardware that supports disabling hsync/vsync:
558 * Returns negative errno on error, or zero on success.
561 static int s3c2410fb_blank(int blank_mode
, struct fb_info
*info
)
563 struct s3c2410fb_info
*fbi
= info
->par
;
564 void __iomem
*tpal_reg
= fbi
->io
;
566 dprintk("blank(mode=%d, info=%p)\n", blank_mode
, info
);
568 tpal_reg
+= is_s3c2412(fbi
) ? S3C2412_TPAL
: S3C2410_TPAL
;
570 if (blank_mode
== FB_BLANK_POWERDOWN
) {
571 s3c2410fb_lcd_enable(fbi
, 0);
573 s3c2410fb_lcd_enable(fbi
, 1);
576 if (blank_mode
== FB_BLANK_UNBLANK
)
577 writel(0x0, tpal_reg
);
579 dprintk("setting TPAL to output 0x000000\n");
580 writel(S3C2410_TPAL_EN
, tpal_reg
);
586 static int s3c2410fb_debug_show(struct device
*dev
,
587 struct device_attribute
*attr
, char *buf
)
589 return snprintf(buf
, PAGE_SIZE
, "%s\n", debug
? "on" : "off");
592 static int s3c2410fb_debug_store(struct device
*dev
,
593 struct device_attribute
*attr
,
594 const char *buf
, size_t len
)
599 if (strnicmp(buf
, "on", 2) == 0 ||
600 strnicmp(buf
, "1", 1) == 0) {
602 printk(KERN_DEBUG
"s3c2410fb: Debug On");
603 } else if (strnicmp(buf
, "off", 3) == 0 ||
604 strnicmp(buf
, "0", 1) == 0) {
606 printk(KERN_DEBUG
"s3c2410fb: Debug Off");
614 static DEVICE_ATTR(debug
, 0666, s3c2410fb_debug_show
, s3c2410fb_debug_store
);
616 static struct fb_ops s3c2410fb_ops
= {
617 .owner
= THIS_MODULE
,
618 .fb_check_var
= s3c2410fb_check_var
,
619 .fb_set_par
= s3c2410fb_set_par
,
620 .fb_blank
= s3c2410fb_blank
,
621 .fb_setcolreg
= s3c2410fb_setcolreg
,
622 .fb_fillrect
= cfb_fillrect
,
623 .fb_copyarea
= cfb_copyarea
,
624 .fb_imageblit
= cfb_imageblit
,
628 * s3c2410fb_map_video_memory():
629 * Allocates the DRAM memory for the frame buffer. This buffer is
630 * remapped into a non-cached, non-buffered, memory region to
631 * allow palette and pixel writes to occur without flushing the
632 * cache. Once this area is remapped, all virtual memory
633 * access to the video memory should occur at the new region.
635 static int __devinit
s3c2410fb_map_video_memory(struct fb_info
*info
)
637 struct s3c2410fb_info
*fbi
= info
->par
;
639 unsigned map_size
= PAGE_ALIGN(info
->fix
.smem_len
);
641 dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi
, map_size
);
643 info
->screen_base
= dma_alloc_writecombine(fbi
->dev
, map_size
,
644 &map_dma
, GFP_KERNEL
);
646 if (info
->screen_base
) {
647 /* prevent initial garbage on screen */
648 dprintk("map_video_memory: clear %p:%08x\n",
649 info
->screen_base
, map_size
);
650 memset(info
->screen_base
, 0x00, map_size
);
652 info
->fix
.smem_start
= map_dma
;
654 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
655 info
->fix
.smem_start
, info
->screen_base
, map_size
);
658 return info
->screen_base
? 0 : -ENOMEM
;
661 static inline void s3c2410fb_unmap_video_memory(struct fb_info
*info
)
663 struct s3c2410fb_info
*fbi
= info
->par
;
665 dma_free_writecombine(fbi
->dev
, PAGE_ALIGN(info
->fix
.smem_len
),
666 info
->screen_base
, info
->fix
.smem_start
);
669 static inline void modify_gpio(void __iomem
*reg
,
670 unsigned long set
, unsigned long mask
)
674 tmp
= readl(reg
) & ~mask
;
675 writel(tmp
| set
, reg
);
679 * s3c2410fb_init_registers - Initialise all LCD-related registers
681 static int s3c2410fb_init_registers(struct fb_info
*info
)
683 struct s3c2410fb_info
*fbi
= info
->par
;
684 struct s3c2410fb_mach_info
*mach_info
= fbi
->dev
->platform_data
;
686 void __iomem
*regs
= fbi
->io
;
688 void __iomem
*lpcsel
;
690 if (is_s3c2412(fbi
)) {
691 tpal
= regs
+ S3C2412_TPAL
;
692 lpcsel
= regs
+ S3C2412_TCONSEL
;
694 tpal
= regs
+ S3C2410_TPAL
;
695 lpcsel
= regs
+ S3C2410_LPCSEL
;
698 /* Initialise LCD with values from haret */
700 local_irq_save(flags
);
702 /* modify the gpio(s) with interrupts set (bjd) */
704 modify_gpio(S3C2410_GPCUP
, mach_info
->gpcup
, mach_info
->gpcup_mask
);
705 modify_gpio(S3C2410_GPCCON
, mach_info
->gpccon
, mach_info
->gpccon_mask
);
706 modify_gpio(S3C2410_GPDUP
, mach_info
->gpdup
, mach_info
->gpdup_mask
);
707 modify_gpio(S3C2410_GPDCON
, mach_info
->gpdcon
, mach_info
->gpdcon_mask
);
709 local_irq_restore(flags
);
711 dprintk("LPCSEL = 0x%08lx\n", mach_info
->lpcsel
);
712 writel(mach_info
->lpcsel
, lpcsel
);
714 dprintk("replacing TPAL %08x\n", readl(tpal
));
716 /* ensure temporary palette disabled */
722 static void s3c2410fb_write_palette(struct s3c2410fb_info
*fbi
)
725 void __iomem
*regs
= fbi
->io
;
727 fbi
->palette_ready
= 0;
729 for (i
= 0; i
< 256; i
++) {
730 unsigned long ent
= fbi
->palette_buffer
[i
];
731 if (ent
== PALETTE_BUFF_CLEAR
)
734 writel(ent
, regs
+ S3C2410_TFTPAL(i
));
736 /* it seems the only way to know exactly
737 * if the palette wrote ok, is to check
738 * to see if the value verifies ok
741 if (readw(regs
+ S3C2410_TFTPAL(i
)) == ent
)
742 fbi
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
744 fbi
->palette_ready
= 1; /* retry */
748 static irqreturn_t
s3c2410fb_irq(int irq
, void *dev_id
)
750 struct s3c2410fb_info
*fbi
= dev_id
;
751 void __iomem
*irq_base
= fbi
->irq_base
;
752 unsigned long lcdirq
= readl(irq_base
+ S3C24XX_LCDINTPND
);
754 if (lcdirq
& S3C2410_LCDINT_FRSYNC
) {
755 if (fbi
->palette_ready
)
756 s3c2410fb_write_palette(fbi
);
758 writel(S3C2410_LCDINT_FRSYNC
, irq_base
+ S3C24XX_LCDINTPND
);
759 writel(S3C2410_LCDINT_FRSYNC
, irq_base
+ S3C24XX_LCDSRCPND
);
765 #ifdef CONFIG_CPU_FREQ
767 static int s3c2410fb_cpufreq_transition(struct notifier_block
*nb
,
768 unsigned long val
, void *data
)
770 struct cpufreq_freqs
*freqs
= data
;
771 struct s3c2410fb_info
*info
;
772 struct fb_info
*fbinfo
;
775 info
= container_of(nb
, struct s3c2410fb_info
, freq_transition
);
776 fbinfo
= platform_get_drvdata(to_platform_device(info
->dev
));
778 /* work out change, <0 for speed-up */
779 delta_f
= info
->clk_rate
- clk_get_rate(info
->clk
);
781 if ((val
== CPUFREQ_POSTCHANGE
&& delta_f
> 0) ||
782 (val
== CPUFREQ_PRECHANGE
&& delta_f
< 0)) {
783 info
->clk_rate
= clk_get_rate(info
->clk
);
784 s3c2410fb_activate_var(fbinfo
);
790 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info
*info
)
792 info
->freq_transition
.notifier_call
= s3c2410fb_cpufreq_transition
;
794 return cpufreq_register_notifier(&info
->freq_transition
,
795 CPUFREQ_TRANSITION_NOTIFIER
);
798 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info
*info
)
800 cpufreq_unregister_notifier(&info
->freq_transition
,
801 CPUFREQ_TRANSITION_NOTIFIER
);
805 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info
*info
)
810 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info
*info
)
816 static char driver_name
[] = "s3c2410fb";
818 static int __devinit
s3c24xxfb_probe(struct platform_device
*pdev
,
819 enum s3c_drv_type drv_type
)
821 struct s3c2410fb_info
*info
;
822 struct s3c2410fb_display
*display
;
823 struct fb_info
*fbinfo
;
824 struct s3c2410fb_mach_info
*mach_info
;
825 struct resource
*res
;
832 mach_info
= pdev
->dev
.platform_data
;
833 if (mach_info
== NULL
) {
835 "no platform data for lcd, cannot attach\n");
839 if (mach_info
->default_display
>= mach_info
->num_displays
) {
840 dev_err(&pdev
->dev
, "default is %d but only %d displays\n",
841 mach_info
->default_display
, mach_info
->num_displays
);
845 display
= mach_info
->displays
+ mach_info
->default_display
;
847 irq
= platform_get_irq(pdev
, 0);
849 dev_err(&pdev
->dev
, "no irq for device\n");
853 fbinfo
= framebuffer_alloc(sizeof(struct s3c2410fb_info
), &pdev
->dev
);
857 platform_set_drvdata(pdev
, fbinfo
);
860 info
->dev
= &pdev
->dev
;
861 info
->drv_type
= drv_type
;
863 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
865 dev_err(&pdev
->dev
, "failed to get memory registers\n");
870 size
= (res
->end
- res
->start
) + 1;
871 info
->mem
= request_mem_region(res
->start
, size
, pdev
->name
);
872 if (info
->mem
== NULL
) {
873 dev_err(&pdev
->dev
, "failed to get memory region\n");
878 info
->io
= ioremap(res
->start
, size
);
879 if (info
->io
== NULL
) {
880 dev_err(&pdev
->dev
, "ioremap() of registers failed\n");
885 info
->irq_base
= info
->io
+ ((drv_type
== DRV_S3C2412
) ? S3C2412_LCDINTBASE
: S3C2410_LCDINTBASE
);
887 dprintk("devinit\n");
889 strcpy(fbinfo
->fix
.id
, driver_name
);
892 lcdcon1
= readl(info
->io
+ S3C2410_LCDCON1
);
893 writel(lcdcon1
& ~S3C2410_LCDCON1_ENVID
, info
->io
+ S3C2410_LCDCON1
);
895 fbinfo
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
896 fbinfo
->fix
.type_aux
= 0;
897 fbinfo
->fix
.xpanstep
= 0;
898 fbinfo
->fix
.ypanstep
= 0;
899 fbinfo
->fix
.ywrapstep
= 0;
900 fbinfo
->fix
.accel
= FB_ACCEL_NONE
;
902 fbinfo
->var
.nonstd
= 0;
903 fbinfo
->var
.activate
= FB_ACTIVATE_NOW
;
904 fbinfo
->var
.accel_flags
= 0;
905 fbinfo
->var
.vmode
= FB_VMODE_NONINTERLACED
;
907 fbinfo
->fbops
= &s3c2410fb_ops
;
908 fbinfo
->flags
= FBINFO_FLAG_DEFAULT
;
909 fbinfo
->pseudo_palette
= &info
->pseudo_pal
;
911 for (i
= 0; i
< 256; i
++)
912 info
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
914 ret
= request_irq(irq
, s3c2410fb_irq
, IRQF_DISABLED
, pdev
->name
, info
);
916 dev_err(&pdev
->dev
, "cannot get irq %d - err %d\n", irq
, ret
);
921 info
->clk
= clk_get(NULL
, "lcd");
922 if (IS_ERR(info
->clk
)) {
923 printk(KERN_ERR
"failed to get lcd clock source\n");
924 ret
= PTR_ERR(info
->clk
);
928 clk_enable(info
->clk
);
929 dprintk("got and enabled clock\n");
933 info
->clk_rate
= clk_get_rate(info
->clk
);
935 /* find maximum required memory size for display */
936 for (i
= 0; i
< mach_info
->num_displays
; i
++) {
937 unsigned long smem_len
= mach_info
->displays
[i
].xres
;
939 smem_len
*= mach_info
->displays
[i
].yres
;
940 smem_len
*= mach_info
->displays
[i
].bpp
;
942 if (fbinfo
->fix
.smem_len
< smem_len
)
943 fbinfo
->fix
.smem_len
= smem_len
;
946 /* Initialize video memory */
947 ret
= s3c2410fb_map_video_memory(fbinfo
);
949 printk(KERN_ERR
"Failed to allocate video RAM: %d\n", ret
);
954 dprintk("got video memory\n");
956 fbinfo
->var
.xres
= display
->xres
;
957 fbinfo
->var
.yres
= display
->yres
;
958 fbinfo
->var
.bits_per_pixel
= display
->bpp
;
960 s3c2410fb_init_registers(fbinfo
);
962 s3c2410fb_check_var(&fbinfo
->var
, fbinfo
);
964 ret
= s3c2410fb_cpufreq_register(info
);
966 dev_err(&pdev
->dev
, "Failed to register cpufreq\n");
967 goto free_video_memory
;
970 ret
= register_framebuffer(fbinfo
);
972 printk(KERN_ERR
"Failed to register framebuffer device: %d\n",
977 /* create device files */
978 ret
= device_create_file(&pdev
->dev
, &dev_attr_debug
);
980 printk(KERN_ERR
"failed to add debug attribute\n");
983 printk(KERN_INFO
"fb%d: %s frame buffer device\n",
984 fbinfo
->node
, fbinfo
->fix
.id
);
989 s3c2410fb_cpufreq_deregister(info
);
991 s3c2410fb_unmap_video_memory(fbinfo
);
993 clk_disable(info
->clk
);
1000 release_resource(info
->mem
);
1003 platform_set_drvdata(pdev
, NULL
);
1004 framebuffer_release(fbinfo
);
1008 static int __devinit
s3c2410fb_probe(struct platform_device
*pdev
)
1010 return s3c24xxfb_probe(pdev
, DRV_S3C2410
);
1013 static int __devinit
s3c2412fb_probe(struct platform_device
*pdev
)
1015 return s3c24xxfb_probe(pdev
, DRV_S3C2412
);
1022 static int __devexit
s3c2410fb_remove(struct platform_device
*pdev
)
1024 struct fb_info
*fbinfo
= platform_get_drvdata(pdev
);
1025 struct s3c2410fb_info
*info
= fbinfo
->par
;
1028 unregister_framebuffer(fbinfo
);
1029 s3c2410fb_cpufreq_deregister(info
);
1031 s3c2410fb_lcd_enable(info
, 0);
1034 s3c2410fb_unmap_video_memory(fbinfo
);
1037 clk_disable(info
->clk
);
1042 irq
= platform_get_irq(pdev
, 0);
1043 free_irq(irq
, info
);
1047 release_resource(info
->mem
);
1050 platform_set_drvdata(pdev
, NULL
);
1051 framebuffer_release(fbinfo
);
1058 /* suspend and resume support for the lcd controller */
1059 static int s3c2410fb_suspend(struct platform_device
*dev
, pm_message_t state
)
1061 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1062 struct s3c2410fb_info
*info
= fbinfo
->par
;
1064 s3c2410fb_lcd_enable(info
, 0);
1066 /* sleep before disabling the clock, we need to ensure
1067 * the LCD DMA engine is not going to get back on the bus
1068 * before the clock goes off again (bjd) */
1071 clk_disable(info
->clk
);
1076 static int s3c2410fb_resume(struct platform_device
*dev
)
1078 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1079 struct s3c2410fb_info
*info
= fbinfo
->par
;
1081 clk_enable(info
->clk
);
1084 s3c2410fb_init_registers(fbinfo
);
1086 /* re-activate our display after resume */
1087 s3c2410fb_activate_var(fbinfo
);
1088 s3c2410fb_blank(FB_BLANK_UNBLANK
, fbinfo
);
1094 #define s3c2410fb_suspend NULL
1095 #define s3c2410fb_resume NULL
1098 static struct platform_driver s3c2410fb_driver
= {
1099 .probe
= s3c2410fb_probe
,
1100 .remove
= __devexit_p(s3c2410fb_remove
),
1101 .suspend
= s3c2410fb_suspend
,
1102 .resume
= s3c2410fb_resume
,
1104 .name
= "s3c2410-lcd",
1105 .owner
= THIS_MODULE
,
1109 static struct platform_driver s3c2412fb_driver
= {
1110 .probe
= s3c2412fb_probe
,
1111 .remove
= __devexit_p(s3c2410fb_remove
),
1112 .suspend
= s3c2410fb_suspend
,
1113 .resume
= s3c2410fb_resume
,
1115 .name
= "s3c2412-lcd",
1116 .owner
= THIS_MODULE
,
1120 int __init
s3c2410fb_init(void)
1122 int ret
= platform_driver_register(&s3c2410fb_driver
);
1125 ret
= platform_driver_register(&s3c2412fb_driver
);
1130 static void __exit
s3c2410fb_cleanup(void)
1132 platform_driver_unregister(&s3c2410fb_driver
);
1133 platform_driver_unregister(&s3c2412fb_driver
);
1136 module_init(s3c2410fb_init
);
1137 module_exit(s3c2410fb_cleanup
);
1139 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1140 "Ben Dooks <ben-linux@fluff.org>");
1141 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1142 MODULE_LICENSE("GPL");
1143 MODULE_ALIAS("platform:s3c2410-lcd");
1144 MODULE_ALIAS("platform:s3c2412-lcd");