Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6/kvm.git] / drivers / video / s3c-fb.c
blob83ce9a04d872427013348665a58b89789bfdfc8f
1 /* linux/drivers/video/s3c-fb.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * Samsung SoC Framebuffer driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software FoundatIon.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/fb.h>
23 #include <linux/io.h>
24 #include <linux/uaccess.h>
25 #include <linux/interrupt.h>
26 #include <linux/pm_runtime.h>
28 #include <mach/map.h>
29 #include <plat/regs-fb-v4.h>
30 #include <plat/fb.h>
32 /* This driver will export a number of framebuffer interfaces depending
33 * on the configuration passed in via the platform data. Each fb instance
34 * maps to a hardware window. Currently there is no support for runtime
35 * setting of the alpha-blending functions that each window has, so only
36 * window 0 is actually useful.
38 * Window 0 is treated specially, it is used for the basis of the LCD
39 * output timings and as the control for the output power-down state.
42 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
43 * has been replaced by using the platform device name to pick the correct
44 * configuration data for the system.
47 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
48 #undef writel
49 #define writel(v, r) do { \
50 printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
51 __raw_writel(v, r); } while(0)
52 #endif /* FB_S3C_DEBUG_REGWRITE */
54 /* irq_flags bits */
55 #define S3C_FB_VSYNC_IRQ_EN 0
57 #define VSYNC_TIMEOUT_MSEC 50
59 struct s3c_fb;
61 #define VALID_BPP(x) (1 << ((x) - 1))
63 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
64 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
65 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
66 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
67 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
69 /**
70 * struct s3c_fb_variant - fb variant information
71 * @is_2443: Set if S3C2443/S3C2416 style hardware.
72 * @nr_windows: The number of windows.
73 * @vidtcon: The base for the VIDTCONx registers
74 * @wincon: The base for the WINxCON registers.
75 * @winmap: The base for the WINxMAP registers.
76 * @keycon: The abse for the WxKEYCON registers.
77 * @buf_start: Offset of buffer start registers.
78 * @buf_size: Offset of buffer size registers.
79 * @buf_end: Offset of buffer end registers.
80 * @osd: The base for the OSD registers.
81 * @palette: Address of palette memory, or 0 if none.
82 * @has_prtcon: Set if has PRTCON register.
83 * @has_shadowcon: Set if has SHADOWCON register.
85 struct s3c_fb_variant {
86 unsigned int is_2443:1;
87 unsigned short nr_windows;
88 unsigned short vidtcon;
89 unsigned short wincon;
90 unsigned short winmap;
91 unsigned short keycon;
92 unsigned short buf_start;
93 unsigned short buf_end;
94 unsigned short buf_size;
95 unsigned short osd;
96 unsigned short osd_stride;
97 unsigned short palette[S3C_FB_MAX_WIN];
99 unsigned int has_prtcon:1;
100 unsigned int has_shadowcon:1;
104 * struct s3c_fb_win_variant
105 * @has_osd_c: Set if has OSD C register.
106 * @has_osd_d: Set if has OSD D register.
107 * @has_osd_alpha: Set if can change alpha transparency for a window.
108 * @palette_sz: Size of palette in entries.
109 * @palette_16bpp: Set if palette is 16bits wide.
110 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
111 * register is located at the given offset from OSD_BASE.
112 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
114 * valid_bpp bit x is set if (x+1)BPP is supported.
116 struct s3c_fb_win_variant {
117 unsigned int has_osd_c:1;
118 unsigned int has_osd_d:1;
119 unsigned int has_osd_alpha:1;
120 unsigned int palette_16bpp:1;
121 unsigned short osd_size_off;
122 unsigned short palette_sz;
123 u32 valid_bpp;
127 * struct s3c_fb_driverdata - per-device type driver data for init time.
128 * @variant: The variant information for this driver.
129 * @win: The window information for each window.
131 struct s3c_fb_driverdata {
132 struct s3c_fb_variant variant;
133 struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
137 * struct s3c_fb_palette - palette information
138 * @r: Red bitfield.
139 * @g: Green bitfield.
140 * @b: Blue bitfield.
141 * @a: Alpha bitfield.
143 struct s3c_fb_palette {
144 struct fb_bitfield r;
145 struct fb_bitfield g;
146 struct fb_bitfield b;
147 struct fb_bitfield a;
151 * struct s3c_fb_win - per window private data for each framebuffer.
152 * @windata: The platform data supplied for the window configuration.
153 * @parent: The hardware that this window is part of.
154 * @fbinfo: Pointer pack to the framebuffer info for this window.
155 * @varint: The variant information for this window.
156 * @palette_buffer: Buffer/cache to hold palette entries.
157 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
158 * @index: The window number of this window.
159 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
161 struct s3c_fb_win {
162 struct s3c_fb_pd_win *windata;
163 struct s3c_fb *parent;
164 struct fb_info *fbinfo;
165 struct s3c_fb_palette palette;
166 struct s3c_fb_win_variant variant;
168 u32 *palette_buffer;
169 u32 pseudo_palette[16];
170 unsigned int index;
174 * struct s3c_fb_vsync - vsync information
175 * @wait: a queue for processes waiting for vsync
176 * @count: vsync interrupt count
178 struct s3c_fb_vsync {
179 wait_queue_head_t wait;
180 unsigned int count;
184 * struct s3c_fb - overall hardware state of the hardware
185 * @dev: The device that we bound to, for printing, etc.
186 * @regs_res: The resource we claimed for the IO registers.
187 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
188 * @regs: The mapped hardware registers.
189 * @variant: Variant information for this hardware.
190 * @enabled: A bitmask of enabled hardware windows.
191 * @pdata: The platform configuration data passed with the device.
192 * @windows: The hardware windows that have been claimed.
193 * @irq_no: IRQ line number
194 * @irq_flags: irq flags
195 * @vsync_info: VSYNC-related information (count, queues...)
197 struct s3c_fb {
198 struct device *dev;
199 struct resource *regs_res;
200 struct clk *bus_clk;
201 void __iomem *regs;
202 struct s3c_fb_variant variant;
204 unsigned char enabled;
206 struct s3c_fb_platdata *pdata;
207 struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
209 int irq_no;
210 unsigned long irq_flags;
211 struct s3c_fb_vsync vsync_info;
215 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
216 * @win: The device window.
217 * @bpp: The bit depth.
219 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
221 return win->variant.valid_bpp & VALID_BPP(bpp);
225 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
226 * @var: The screen information to verify.
227 * @info: The framebuffer device.
229 * Framebuffer layer call to verify the given information and allow us to
230 * update various information depending on the hardware capabilities.
232 static int s3c_fb_check_var(struct fb_var_screeninfo *var,
233 struct fb_info *info)
235 struct s3c_fb_win *win = info->par;
236 struct s3c_fb_pd_win *windata = win->windata;
237 struct s3c_fb *sfb = win->parent;
239 dev_dbg(sfb->dev, "checking parameters\n");
241 var->xres_virtual = max((unsigned int)windata->virtual_x, var->xres);
242 var->yres_virtual = max((unsigned int)windata->virtual_y, var->yres);
244 if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
245 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
246 win->index, var->bits_per_pixel);
247 return -EINVAL;
250 /* always ensure these are zero, for drop through cases below */
251 var->transp.offset = 0;
252 var->transp.length = 0;
254 switch (var->bits_per_pixel) {
255 case 1:
256 case 2:
257 case 4:
258 case 8:
259 if (sfb->variant.palette[win->index] != 0) {
260 /* non palletised, A:1,R:2,G:3,B:2 mode */
261 var->red.offset = 4;
262 var->green.offset = 2;
263 var->blue.offset = 0;
264 var->red.length = 5;
265 var->green.length = 3;
266 var->blue.length = 2;
267 var->transp.offset = 7;
268 var->transp.length = 1;
269 } else {
270 var->red.offset = 0;
271 var->red.length = var->bits_per_pixel;
272 var->green = var->red;
273 var->blue = var->red;
275 break;
277 case 19:
278 /* 666 with one bit alpha/transparency */
279 var->transp.offset = 18;
280 var->transp.length = 1;
281 case 18:
282 var->bits_per_pixel = 32;
284 /* 666 format */
285 var->red.offset = 12;
286 var->green.offset = 6;
287 var->blue.offset = 0;
288 var->red.length = 6;
289 var->green.length = 6;
290 var->blue.length = 6;
291 break;
293 case 16:
294 /* 16 bpp, 565 format */
295 var->red.offset = 11;
296 var->green.offset = 5;
297 var->blue.offset = 0;
298 var->red.length = 5;
299 var->green.length = 6;
300 var->blue.length = 5;
301 break;
303 case 28:
304 case 25:
305 var->transp.length = var->bits_per_pixel - 24;
306 var->transp.offset = 24;
307 /* drop through */
308 case 24:
309 /* our 24bpp is unpacked, so 32bpp */
310 var->bits_per_pixel = 32;
311 case 32:
312 var->red.offset = 16;
313 var->red.length = 8;
314 var->green.offset = 8;
315 var->green.length = 8;
316 var->blue.offset = 0;
317 var->blue.length = 8;
318 break;
320 default:
321 dev_err(sfb->dev, "invalid bpp\n");
324 dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
325 return 0;
329 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
330 * @sfb: The hardware state.
331 * @pixclock: The pixel clock wanted, in picoseconds.
333 * Given the specified pixel clock, work out the necessary divider to get
334 * close to the output frequency.
336 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
338 unsigned long clk = clk_get_rate(sfb->bus_clk);
339 unsigned long long tmp;
340 unsigned int result;
342 tmp = (unsigned long long)clk;
343 tmp *= pixclk;
345 do_div(tmp, 1000000000UL);
346 result = (unsigned int)tmp / 1000;
348 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
349 pixclk, clk, result, clk / result);
351 return result;
355 * s3c_fb_align_word() - align pixel count to word boundary
356 * @bpp: The number of bits per pixel
357 * @pix: The value to be aligned.
359 * Align the given pixel count so that it will start on an 32bit word
360 * boundary.
362 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
364 int pix_per_word;
366 if (bpp > 16)
367 return pix;
369 pix_per_word = (8 * 32) / bpp;
370 return ALIGN(pix, pix_per_word);
374 * vidosd_set_size() - set OSD size for a window
376 * @win: the window to set OSD size for
377 * @size: OSD size register value
379 static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
381 struct s3c_fb *sfb = win->parent;
383 /* OSD can be set up if osd_size_off != 0 for this window */
384 if (win->variant.osd_size_off)
385 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
386 + win->variant.osd_size_off);
390 * vidosd_set_alpha() - set alpha transparency for a window
392 * @win: the window to set OSD size for
393 * @alpha: alpha register value
395 static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
397 struct s3c_fb *sfb = win->parent;
399 if (win->variant.has_osd_alpha)
400 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
404 * shadow_protect_win() - disable updating values from shadow registers at vsync
406 * @win: window to protect registers for
407 * @protect: 1 to protect (disable updates)
409 static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
411 struct s3c_fb *sfb = win->parent;
412 u32 reg;
414 if (protect) {
415 if (sfb->variant.has_prtcon) {
416 writel(PRTCON_PROTECT, sfb->regs + PRTCON);
417 } else if (sfb->variant.has_shadowcon) {
418 reg = readl(sfb->regs + SHADOWCON);
419 writel(reg | SHADOWCON_WINx_PROTECT(win->index),
420 sfb->regs + SHADOWCON);
422 } else {
423 if (sfb->variant.has_prtcon) {
424 writel(0, sfb->regs + PRTCON);
425 } else if (sfb->variant.has_shadowcon) {
426 reg = readl(sfb->regs + SHADOWCON);
427 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
428 sfb->regs + SHADOWCON);
434 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
435 * @info: The framebuffer to change.
437 * Framebuffer layer request to set a new mode for the specified framebuffer
439 static int s3c_fb_set_par(struct fb_info *info)
441 struct fb_var_screeninfo *var = &info->var;
442 struct s3c_fb_win *win = info->par;
443 struct s3c_fb *sfb = win->parent;
444 void __iomem *regs = sfb->regs;
445 void __iomem *buf = regs;
446 int win_no = win->index;
447 u32 alpha = 0;
448 u32 data;
449 u32 pagewidth;
450 int clkdiv;
452 dev_dbg(sfb->dev, "setting framebuffer parameters\n");
454 shadow_protect_win(win, 1);
456 switch (var->bits_per_pixel) {
457 case 32:
458 case 24:
459 case 16:
460 case 12:
461 info->fix.visual = FB_VISUAL_TRUECOLOR;
462 break;
463 case 8:
464 if (win->variant.palette_sz >= 256)
465 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
466 else
467 info->fix.visual = FB_VISUAL_TRUECOLOR;
468 break;
469 case 1:
470 info->fix.visual = FB_VISUAL_MONO01;
471 break;
472 default:
473 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
474 break;
477 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
479 info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
480 info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
482 /* disable the window whilst we update it */
483 writel(0, regs + WINCON(win_no));
485 /* use platform specified window as the basis for the lcd timings */
487 if (win_no == sfb->pdata->default_win) {
488 clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
490 data = sfb->pdata->vidcon0;
491 data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
493 if (clkdiv > 1)
494 data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
495 else
496 data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
498 /* write the timing data to the panel */
500 if (sfb->variant.is_2443)
501 data |= (1 << 5);
503 data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
504 writel(data, regs + VIDCON0);
506 data = VIDTCON0_VBPD(var->upper_margin - 1) |
507 VIDTCON0_VFPD(var->lower_margin - 1) |
508 VIDTCON0_VSPW(var->vsync_len - 1);
510 writel(data, regs + sfb->variant.vidtcon);
512 data = VIDTCON1_HBPD(var->left_margin - 1) |
513 VIDTCON1_HFPD(var->right_margin - 1) |
514 VIDTCON1_HSPW(var->hsync_len - 1);
516 /* VIDTCON1 */
517 writel(data, regs + sfb->variant.vidtcon + 4);
519 data = VIDTCON2_LINEVAL(var->yres - 1) |
520 VIDTCON2_HOZVAL(var->xres - 1);
521 writel(data, regs +sfb->variant.vidtcon + 8 );
524 /* write the buffer address */
526 /* start and end registers stride is 8 */
527 buf = regs + win_no * 8;
529 writel(info->fix.smem_start, buf + sfb->variant.buf_start);
531 data = info->fix.smem_start + info->fix.line_length * var->yres;
532 writel(data, buf + sfb->variant.buf_end);
534 pagewidth = (var->xres * var->bits_per_pixel) >> 3;
535 data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
536 VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
537 writel(data, regs + sfb->variant.buf_size + (win_no * 4));
539 /* write 'OSD' registers to control position of framebuffer */
541 data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
542 writel(data, regs + VIDOSD_A(win_no, sfb->variant));
544 data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
545 var->xres - 1)) |
546 VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
548 writel(data, regs + VIDOSD_B(win_no, sfb->variant));
550 data = var->xres * var->yres;
552 alpha = VIDISD14C_ALPHA1_R(0xf) |
553 VIDISD14C_ALPHA1_G(0xf) |
554 VIDISD14C_ALPHA1_B(0xf);
556 vidosd_set_alpha(win, alpha);
557 vidosd_set_size(win, data);
559 data = WINCONx_ENWIN;
561 /* note, since we have to round up the bits-per-pixel, we end up
562 * relying on the bitfield information for r/g/b/a to work out
563 * exactly which mode of operation is intended. */
565 switch (var->bits_per_pixel) {
566 case 1:
567 data |= WINCON0_BPPMODE_1BPP;
568 data |= WINCONx_BITSWP;
569 data |= WINCONx_BURSTLEN_4WORD;
570 break;
571 case 2:
572 data |= WINCON0_BPPMODE_2BPP;
573 data |= WINCONx_BITSWP;
574 data |= WINCONx_BURSTLEN_8WORD;
575 break;
576 case 4:
577 data |= WINCON0_BPPMODE_4BPP;
578 data |= WINCONx_BITSWP;
579 data |= WINCONx_BURSTLEN_8WORD;
580 break;
581 case 8:
582 if (var->transp.length != 0)
583 data |= WINCON1_BPPMODE_8BPP_1232;
584 else
585 data |= WINCON0_BPPMODE_8BPP_PALETTE;
586 data |= WINCONx_BURSTLEN_8WORD;
587 data |= WINCONx_BYTSWP;
588 break;
589 case 16:
590 if (var->transp.length != 0)
591 data |= WINCON1_BPPMODE_16BPP_A1555;
592 else
593 data |= WINCON0_BPPMODE_16BPP_565;
594 data |= WINCONx_HAWSWP;
595 data |= WINCONx_BURSTLEN_16WORD;
596 break;
597 case 24:
598 case 32:
599 if (var->red.length == 6) {
600 if (var->transp.length != 0)
601 data |= WINCON1_BPPMODE_19BPP_A1666;
602 else
603 data |= WINCON1_BPPMODE_18BPP_666;
604 } else if (var->transp.length == 1)
605 data |= WINCON1_BPPMODE_25BPP_A1888
606 | WINCON1_BLD_PIX;
607 else if (var->transp.length == 4)
608 data |= WINCON1_BPPMODE_28BPP_A4888
609 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
610 else
611 data |= WINCON0_BPPMODE_24BPP_888;
613 data |= WINCONx_WSWP;
614 data |= WINCONx_BURSTLEN_16WORD;
615 break;
618 /* Enable the colour keying for the window below this one */
619 if (win_no > 0) {
620 u32 keycon0_data = 0, keycon1_data = 0;
621 void __iomem *keycon = regs + sfb->variant.keycon;
623 keycon0_data = ~(WxKEYCON0_KEYBL_EN |
624 WxKEYCON0_KEYEN_F |
625 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
627 keycon1_data = WxKEYCON1_COLVAL(0xffffff);
629 keycon += (win_no - 1) * 8;
631 writel(keycon0_data, keycon + WKEYCON0);
632 writel(keycon1_data, keycon + WKEYCON1);
635 writel(data, regs + sfb->variant.wincon + (win_no * 4));
636 writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
638 /* Enable DMA channel for this window */
639 if (sfb->variant.has_shadowcon) {
640 data = readl(sfb->regs + SHADOWCON);
641 data |= SHADOWCON_CHx_ENABLE(win_no);
642 writel(data, sfb->regs + SHADOWCON);
645 shadow_protect_win(win, 0);
647 return 0;
651 * s3c_fb_update_palette() - set or schedule a palette update.
652 * @sfb: The hardware information.
653 * @win: The window being updated.
654 * @reg: The palette index being changed.
655 * @value: The computed palette value.
657 * Change the value of a palette register, either by directly writing to
658 * the palette (this requires the palette RAM to be disconnected from the
659 * hardware whilst this is in progress) or schedule the update for later.
661 * At the moment, since we have no VSYNC interrupt support, we simply set
662 * the palette entry directly.
664 static void s3c_fb_update_palette(struct s3c_fb *sfb,
665 struct s3c_fb_win *win,
666 unsigned int reg,
667 u32 value)
669 void __iomem *palreg;
670 u32 palcon;
672 palreg = sfb->regs + sfb->variant.palette[win->index];
674 dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
675 __func__, win->index, reg, palreg, value);
677 win->palette_buffer[reg] = value;
679 palcon = readl(sfb->regs + WPALCON);
680 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
682 if (win->variant.palette_16bpp)
683 writew(value, palreg + (reg * 2));
684 else
685 writel(value, palreg + (reg * 4));
687 writel(palcon, sfb->regs + WPALCON);
690 static inline unsigned int chan_to_field(unsigned int chan,
691 struct fb_bitfield *bf)
693 chan &= 0xffff;
694 chan >>= 16 - bf->length;
695 return chan << bf->offset;
699 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
700 * @regno: The palette index to change.
701 * @red: The red field for the palette data.
702 * @green: The green field for the palette data.
703 * @blue: The blue field for the palette data.
704 * @trans: The transparency (alpha) field for the palette data.
705 * @info: The framebuffer being changed.
707 static int s3c_fb_setcolreg(unsigned regno,
708 unsigned red, unsigned green, unsigned blue,
709 unsigned transp, struct fb_info *info)
711 struct s3c_fb_win *win = info->par;
712 struct s3c_fb *sfb = win->parent;
713 unsigned int val;
715 dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
716 __func__, win->index, regno, red, green, blue);
718 switch (info->fix.visual) {
719 case FB_VISUAL_TRUECOLOR:
720 /* true-colour, use pseudo-palette */
722 if (regno < 16) {
723 u32 *pal = info->pseudo_palette;
725 val = chan_to_field(red, &info->var.red);
726 val |= chan_to_field(green, &info->var.green);
727 val |= chan_to_field(blue, &info->var.blue);
729 pal[regno] = val;
731 break;
733 case FB_VISUAL_PSEUDOCOLOR:
734 if (regno < win->variant.palette_sz) {
735 val = chan_to_field(red, &win->palette.r);
736 val |= chan_to_field(green, &win->palette.g);
737 val |= chan_to_field(blue, &win->palette.b);
739 s3c_fb_update_palette(sfb, win, regno, val);
742 break;
744 default:
745 return 1; /* unknown type */
748 return 0;
752 * s3c_fb_enable() - Set the state of the main LCD output
753 * @sfb: The main framebuffer state.
754 * @enable: The state to set.
756 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
758 u32 vidcon0 = readl(sfb->regs + VIDCON0);
760 if (enable)
761 vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
762 else {
763 /* see the note in the framebuffer datasheet about
764 * why you cannot take both of these bits down at the
765 * same time. */
767 if (!(vidcon0 & VIDCON0_ENVID))
768 return;
770 vidcon0 |= VIDCON0_ENVID;
771 vidcon0 &= ~VIDCON0_ENVID_F;
774 writel(vidcon0, sfb->regs + VIDCON0);
778 * s3c_fb_blank() - blank or unblank the given window
779 * @blank_mode: The blank state from FB_BLANK_*
780 * @info: The framebuffer to blank.
782 * Framebuffer layer request to change the power state.
784 static int s3c_fb_blank(int blank_mode, struct fb_info *info)
786 struct s3c_fb_win *win = info->par;
787 struct s3c_fb *sfb = win->parent;
788 unsigned int index = win->index;
789 u32 wincon;
791 dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
793 wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
795 switch (blank_mode) {
796 case FB_BLANK_POWERDOWN:
797 wincon &= ~WINCONx_ENWIN;
798 sfb->enabled &= ~(1 << index);
799 /* fall through to FB_BLANK_NORMAL */
801 case FB_BLANK_NORMAL:
802 /* disable the DMA and display 0x0 (black) */
803 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
804 sfb->regs + sfb->variant.winmap + (index * 4));
805 break;
807 case FB_BLANK_UNBLANK:
808 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
809 wincon |= WINCONx_ENWIN;
810 sfb->enabled |= (1 << index);
811 break;
813 case FB_BLANK_VSYNC_SUSPEND:
814 case FB_BLANK_HSYNC_SUSPEND:
815 default:
816 return 1;
819 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
821 /* Check the enabled state to see if we need to be running the
822 * main LCD interface, as if there are no active windows then
823 * it is highly likely that we also do not need to output
824 * anything.
827 /* We could do something like the following code, but the current
828 * system of using framebuffer events means that we cannot make
829 * the distinction between just window 0 being inactive and all
830 * the windows being down.
832 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
835 /* we're stuck with this until we can do something about overriding
836 * the power control using the blanking event for a single fb.
838 if (index == sfb->pdata->default_win)
839 s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
841 return 0;
845 * s3c_fb_pan_display() - Pan the display.
847 * Note that the offsets can be written to the device at any time, as their
848 * values are latched at each vsync automatically. This also means that only
849 * the last call to this function will have any effect on next vsync, but
850 * there is no need to sleep waiting for it to prevent tearing.
852 * @var: The screen information to verify.
853 * @info: The framebuffer device.
855 static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
856 struct fb_info *info)
858 struct s3c_fb_win *win = info->par;
859 struct s3c_fb *sfb = win->parent;
860 void __iomem *buf = sfb->regs + win->index * 8;
861 unsigned int start_boff, end_boff;
863 /* Offset in bytes to the start of the displayed area */
864 start_boff = var->yoffset * info->fix.line_length;
865 /* X offset depends on the current bpp */
866 if (info->var.bits_per_pixel >= 8) {
867 start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
868 } else {
869 switch (info->var.bits_per_pixel) {
870 case 4:
871 start_boff += var->xoffset >> 1;
872 break;
873 case 2:
874 start_boff += var->xoffset >> 2;
875 break;
876 case 1:
877 start_boff += var->xoffset >> 3;
878 break;
879 default:
880 dev_err(sfb->dev, "invalid bpp\n");
881 return -EINVAL;
884 /* Offset in bytes to the end of the displayed area */
885 end_boff = start_boff + var->yres * info->fix.line_length;
887 /* Temporarily turn off per-vsync update from shadow registers until
888 * both start and end addresses are updated to prevent corruption */
889 shadow_protect_win(win, 1);
891 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
892 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
894 shadow_protect_win(win, 0);
896 return 0;
900 * s3c_fb_enable_irq() - enable framebuffer interrupts
901 * @sfb: main hardware state
903 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
905 void __iomem *regs = sfb->regs;
906 u32 irq_ctrl_reg;
908 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
909 /* IRQ disabled, enable it */
910 irq_ctrl_reg = readl(regs + VIDINTCON0);
912 irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
913 irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
915 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
916 irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
917 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
918 irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
920 writel(irq_ctrl_reg, regs + VIDINTCON0);
925 * s3c_fb_disable_irq() - disable framebuffer interrupts
926 * @sfb: main hardware state
928 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
930 void __iomem *regs = sfb->regs;
931 u32 irq_ctrl_reg;
933 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
934 /* IRQ enabled, disable it */
935 irq_ctrl_reg = readl(regs + VIDINTCON0);
937 irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
938 irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
940 writel(irq_ctrl_reg, regs + VIDINTCON0);
944 static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
946 struct s3c_fb *sfb = dev_id;
947 void __iomem *regs = sfb->regs;
948 u32 irq_sts_reg;
950 irq_sts_reg = readl(regs + VIDINTCON1);
952 if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
954 /* VSYNC interrupt, accept it */
955 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
957 sfb->vsync_info.count++;
958 wake_up_interruptible(&sfb->vsync_info.wait);
961 /* We only support waiting for VSYNC for now, so it's safe
962 * to always disable irqs here.
964 s3c_fb_disable_irq(sfb);
966 return IRQ_HANDLED;
970 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
971 * @sfb: main hardware state
972 * @crtc: head index.
974 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
976 unsigned long count;
977 int ret;
979 if (crtc != 0)
980 return -ENODEV;
982 count = sfb->vsync_info.count;
983 s3c_fb_enable_irq(sfb);
984 ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
985 count != sfb->vsync_info.count,
986 msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
987 if (ret == 0)
988 return -ETIMEDOUT;
990 return 0;
993 static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
994 unsigned long arg)
996 struct s3c_fb_win *win = info->par;
997 struct s3c_fb *sfb = win->parent;
998 int ret;
999 u32 crtc;
1001 switch (cmd) {
1002 case FBIO_WAITFORVSYNC:
1003 if (get_user(crtc, (u32 __user *)arg)) {
1004 ret = -EFAULT;
1005 break;
1008 ret = s3c_fb_wait_for_vsync(sfb, crtc);
1009 break;
1010 default:
1011 ret = -ENOTTY;
1014 return ret;
1017 static int s3c_fb_open(struct fb_info *info, int user)
1019 struct s3c_fb_win *win = info->par;
1020 struct s3c_fb *sfb = win->parent;
1022 pm_runtime_get_sync(sfb->dev);
1024 return 0;
1027 static int s3c_fb_release(struct fb_info *info, int user)
1029 struct s3c_fb_win *win = info->par;
1030 struct s3c_fb *sfb = win->parent;
1032 pm_runtime_put_sync(sfb->dev);
1034 return 0;
1037 static struct fb_ops s3c_fb_ops = {
1038 .owner = THIS_MODULE,
1039 .fb_open = s3c_fb_open,
1040 .fb_release = s3c_fb_release,
1041 .fb_check_var = s3c_fb_check_var,
1042 .fb_set_par = s3c_fb_set_par,
1043 .fb_blank = s3c_fb_blank,
1044 .fb_setcolreg = s3c_fb_setcolreg,
1045 .fb_fillrect = cfb_fillrect,
1046 .fb_copyarea = cfb_copyarea,
1047 .fb_imageblit = cfb_imageblit,
1048 .fb_pan_display = s3c_fb_pan_display,
1049 .fb_ioctl = s3c_fb_ioctl,
1053 * s3c_fb_missing_pixclock() - calculates pixel clock
1054 * @mode: The video mode to change.
1056 * Calculate the pixel clock when none has been given through platform data.
1058 static void __devinit s3c_fb_missing_pixclock(struct fb_videomode *mode)
1060 u64 pixclk = 1000000000000ULL;
1061 u32 div;
1063 div = mode->left_margin + mode->hsync_len + mode->right_margin +
1064 mode->xres;
1065 div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1066 mode->yres;
1067 div *= mode->refresh ? : 60;
1069 do_div(pixclk, div);
1071 mode->pixclock = pixclk;
1075 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1076 * @sfb: The base resources for the hardware.
1077 * @win: The window to initialise memory for.
1079 * Allocate memory for the given framebuffer.
1081 static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
1082 struct s3c_fb_win *win)
1084 struct s3c_fb_pd_win *windata = win->windata;
1085 unsigned int real_size, virt_size, size;
1086 struct fb_info *fbi = win->fbinfo;
1087 dma_addr_t map_dma;
1089 dev_dbg(sfb->dev, "allocating memory for display\n");
1091 real_size = windata->win_mode.xres * windata->win_mode.yres;
1092 virt_size = windata->virtual_x * windata->virtual_y;
1094 dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1095 real_size, windata->win_mode.xres, windata->win_mode.yres,
1096 virt_size, windata->virtual_x, windata->virtual_y);
1098 size = (real_size > virt_size) ? real_size : virt_size;
1099 size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1100 size /= 8;
1102 fbi->fix.smem_len = size;
1103 size = PAGE_ALIGN(size);
1105 dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1107 fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
1108 &map_dma, GFP_KERNEL);
1109 if (!fbi->screen_base)
1110 return -ENOMEM;
1112 dev_dbg(sfb->dev, "mapped %x to %p\n",
1113 (unsigned int)map_dma, fbi->screen_base);
1115 memset(fbi->screen_base, 0x0, size);
1116 fbi->fix.smem_start = map_dma;
1118 return 0;
1122 * s3c_fb_free_memory() - free the display memory for the given window
1123 * @sfb: The base resources for the hardware.
1124 * @win: The window to free the display memory for.
1126 * Free the display memory allocated by s3c_fb_alloc_memory().
1128 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1130 struct fb_info *fbi = win->fbinfo;
1132 if (fbi->screen_base)
1133 dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1134 fbi->screen_base, fbi->fix.smem_start);
1138 * s3c_fb_release_win() - release resources for a framebuffer window.
1139 * @win: The window to cleanup the resources for.
1141 * Release the resources that where claimed for the hardware window,
1142 * such as the framebuffer instance and any memory claimed for it.
1144 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1146 u32 data;
1148 if (win->fbinfo) {
1149 if (sfb->variant.has_shadowcon) {
1150 data = readl(sfb->regs + SHADOWCON);
1151 data &= ~SHADOWCON_CHx_ENABLE(win->index);
1152 data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1153 writel(data, sfb->regs + SHADOWCON);
1155 unregister_framebuffer(win->fbinfo);
1156 if (win->fbinfo->cmap.len)
1157 fb_dealloc_cmap(&win->fbinfo->cmap);
1158 s3c_fb_free_memory(sfb, win);
1159 framebuffer_release(win->fbinfo);
1164 * s3c_fb_probe_win() - register an hardware window
1165 * @sfb: The base resources for the hardware
1166 * @variant: The variant information for this window.
1167 * @res: Pointer to where to place the resultant window.
1169 * Allocate and do the basic initialisation for one of the hardware's graphics
1170 * windows.
1172 static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1173 struct s3c_fb_win_variant *variant,
1174 struct s3c_fb_win **res)
1176 struct fb_var_screeninfo *var;
1177 struct fb_videomode *initmode;
1178 struct s3c_fb_pd_win *windata;
1179 struct s3c_fb_win *win;
1180 struct fb_info *fbinfo;
1181 int palette_size;
1182 int ret;
1184 dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1186 init_waitqueue_head(&sfb->vsync_info.wait);
1188 palette_size = variant->palette_sz * 4;
1190 fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1191 palette_size * sizeof(u32), sfb->dev);
1192 if (!fbinfo) {
1193 dev_err(sfb->dev, "failed to allocate framebuffer\n");
1194 return -ENOENT;
1197 windata = sfb->pdata->win[win_no];
1198 initmode = &windata->win_mode;
1200 WARN_ON(windata->max_bpp == 0);
1201 WARN_ON(windata->win_mode.xres == 0);
1202 WARN_ON(windata->win_mode.yres == 0);
1204 win = fbinfo->par;
1205 *res = win;
1206 var = &fbinfo->var;
1207 win->variant = *variant;
1208 win->fbinfo = fbinfo;
1209 win->parent = sfb;
1210 win->windata = windata;
1211 win->index = win_no;
1212 win->palette_buffer = (u32 *)(win + 1);
1214 ret = s3c_fb_alloc_memory(sfb, win);
1215 if (ret) {
1216 dev_err(sfb->dev, "failed to allocate display memory\n");
1217 return ret;
1220 /* setup the r/b/g positions for the window's palette */
1221 if (win->variant.palette_16bpp) {
1222 /* Set RGB 5:6:5 as default */
1223 win->palette.r.offset = 11;
1224 win->palette.r.length = 5;
1225 win->palette.g.offset = 5;
1226 win->palette.g.length = 6;
1227 win->palette.b.offset = 0;
1228 win->palette.b.length = 5;
1230 } else {
1231 /* Set 8bpp or 8bpp and 1bit alpha */
1232 win->palette.r.offset = 16;
1233 win->palette.r.length = 8;
1234 win->palette.g.offset = 8;
1235 win->palette.g.length = 8;
1236 win->palette.b.offset = 0;
1237 win->palette.b.length = 8;
1240 /* setup the initial video mode from the window */
1241 fb_videomode_to_var(&fbinfo->var, initmode);
1243 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
1244 fbinfo->fix.accel = FB_ACCEL_NONE;
1245 fbinfo->var.activate = FB_ACTIVATE_NOW;
1246 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
1247 fbinfo->var.bits_per_pixel = windata->default_bpp;
1248 fbinfo->fbops = &s3c_fb_ops;
1249 fbinfo->flags = FBINFO_FLAG_DEFAULT;
1250 fbinfo->pseudo_palette = &win->pseudo_palette;
1252 /* prepare to actually start the framebuffer */
1254 ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1255 if (ret < 0) {
1256 dev_err(sfb->dev, "check_var failed on initial video params\n");
1257 return ret;
1260 /* create initial colour map */
1262 ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1263 if (ret == 0)
1264 fb_set_cmap(&fbinfo->cmap, fbinfo);
1265 else
1266 dev_err(sfb->dev, "failed to allocate fb cmap\n");
1268 s3c_fb_set_par(fbinfo);
1270 dev_dbg(sfb->dev, "about to register framebuffer\n");
1272 /* run the check_var and set_par on our configuration. */
1274 ret = register_framebuffer(fbinfo);
1275 if (ret < 0) {
1276 dev_err(sfb->dev, "failed to register framebuffer\n");
1277 return ret;
1280 dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1282 return 0;
1286 * s3c_fb_clear_win() - clear hardware window registers.
1287 * @sfb: The base resources for the hardware.
1288 * @win: The window to process.
1290 * Reset the specific window registers to a known state.
1292 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1294 void __iomem *regs = sfb->regs;
1295 u32 reg;
1297 writel(0, regs + sfb->variant.wincon + (win * 4));
1298 writel(0, regs + VIDOSD_A(win, sfb->variant));
1299 writel(0, regs + VIDOSD_B(win, sfb->variant));
1300 writel(0, regs + VIDOSD_C(win, sfb->variant));
1301 reg = readl(regs + SHADOWCON);
1302 writel(reg & ~SHADOWCON_WINx_PROTECT(win), regs + SHADOWCON);
1305 static int __devinit s3c_fb_probe(struct platform_device *pdev)
1307 struct s3c_fb_driverdata *fbdrv;
1308 struct device *dev = &pdev->dev;
1309 struct s3c_fb_platdata *pd;
1310 struct s3c_fb *sfb;
1311 struct resource *res;
1312 int win;
1313 int ret = 0;
1315 fbdrv = (struct s3c_fb_driverdata *)platform_get_device_id(pdev)->driver_data;
1317 if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1318 dev_err(dev, "too many windows, cannot attach\n");
1319 return -EINVAL;
1322 pd = pdev->dev.platform_data;
1323 if (!pd) {
1324 dev_err(dev, "no platform data specified\n");
1325 return -EINVAL;
1328 sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
1329 if (!sfb) {
1330 dev_err(dev, "no memory for framebuffers\n");
1331 return -ENOMEM;
1334 dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1336 sfb->dev = dev;
1337 sfb->pdata = pd;
1338 sfb->variant = fbdrv->variant;
1340 sfb->bus_clk = clk_get(dev, "lcd");
1341 if (IS_ERR(sfb->bus_clk)) {
1342 dev_err(dev, "failed to get bus clock\n");
1343 goto err_sfb;
1346 clk_enable(sfb->bus_clk);
1348 pm_runtime_enable(sfb->dev);
1350 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1351 if (!res) {
1352 dev_err(dev, "failed to find registers\n");
1353 ret = -ENOENT;
1354 goto err_clk;
1357 sfb->regs_res = request_mem_region(res->start, resource_size(res),
1358 dev_name(dev));
1359 if (!sfb->regs_res) {
1360 dev_err(dev, "failed to claim register region\n");
1361 ret = -ENOENT;
1362 goto err_clk;
1365 sfb->regs = ioremap(res->start, resource_size(res));
1366 if (!sfb->regs) {
1367 dev_err(dev, "failed to map registers\n");
1368 ret = -ENXIO;
1369 goto err_req_region;
1372 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1373 if (!res) {
1374 dev_err(dev, "failed to acquire irq resource\n");
1375 ret = -ENOENT;
1376 goto err_ioremap;
1378 sfb->irq_no = res->start;
1379 ret = request_irq(sfb->irq_no, s3c_fb_irq,
1380 0, "s3c_fb", sfb);
1381 if (ret) {
1382 dev_err(dev, "irq request failed\n");
1383 goto err_ioremap;
1386 dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1388 platform_set_drvdata(pdev, sfb);
1389 pm_runtime_get_sync(sfb->dev);
1391 /* setup gpio and output polarity controls */
1393 pd->setup_gpio();
1395 writel(pd->vidcon1, sfb->regs + VIDCON1);
1397 /* zero all windows before we do anything */
1399 for (win = 0; win < fbdrv->variant.nr_windows; win++)
1400 s3c_fb_clear_win(sfb, win);
1402 /* initialise colour key controls */
1403 for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1404 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1406 regs += (win * 8);
1407 writel(0xffffff, regs + WKEYCON0);
1408 writel(0xffffff, regs + WKEYCON1);
1411 /* we have the register setup, start allocating framebuffers */
1413 for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1414 if (!pd->win[win])
1415 continue;
1417 if (!pd->win[win]->win_mode.pixclock)
1418 s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
1420 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1421 &sfb->windows[win]);
1422 if (ret < 0) {
1423 dev_err(dev, "failed to create window %d\n", win);
1424 for (; win >= 0; win--)
1425 s3c_fb_release_win(sfb, sfb->windows[win]);
1426 goto err_irq;
1430 platform_set_drvdata(pdev, sfb);
1431 pm_runtime_put_sync(sfb->dev);
1433 return 0;
1435 err_irq:
1436 free_irq(sfb->irq_no, sfb);
1438 err_ioremap:
1439 iounmap(sfb->regs);
1441 err_req_region:
1442 release_resource(sfb->regs_res);
1443 kfree(sfb->regs_res);
1445 err_clk:
1446 clk_disable(sfb->bus_clk);
1447 clk_put(sfb->bus_clk);
1449 err_sfb:
1450 kfree(sfb);
1451 return ret;
1455 * s3c_fb_remove() - Cleanup on module finalisation
1456 * @pdev: The platform device we are bound to.
1458 * Shutdown and then release all the resources that the driver allocated
1459 * on initialisation.
1461 static int __devexit s3c_fb_remove(struct platform_device *pdev)
1463 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1464 int win;
1466 pm_runtime_get_sync(sfb->dev);
1468 for (win = 0; win < S3C_FB_MAX_WIN; win++)
1469 if (sfb->windows[win])
1470 s3c_fb_release_win(sfb, sfb->windows[win]);
1472 free_irq(sfb->irq_no, sfb);
1474 iounmap(sfb->regs);
1476 clk_disable(sfb->bus_clk);
1477 clk_put(sfb->bus_clk);
1479 release_resource(sfb->regs_res);
1480 kfree(sfb->regs_res);
1482 kfree(sfb);
1484 pm_runtime_put_sync(sfb->dev);
1485 pm_runtime_disable(sfb->dev);
1487 return 0;
1490 #ifdef CONFIG_PM
1491 static int s3c_fb_suspend(struct device *dev)
1493 struct platform_device *pdev = to_platform_device(dev);
1494 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1495 struct s3c_fb_win *win;
1496 int win_no;
1498 for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1499 win = sfb->windows[win_no];
1500 if (!win)
1501 continue;
1503 /* use the blank function to push into power-down */
1504 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1507 clk_disable(sfb->bus_clk);
1508 return 0;
1511 static int s3c_fb_resume(struct device *dev)
1513 struct platform_device *pdev = to_platform_device(dev);
1514 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1515 struct s3c_fb_platdata *pd = sfb->pdata;
1516 struct s3c_fb_win *win;
1517 int win_no;
1519 clk_enable(sfb->bus_clk);
1521 /* setup registers */
1522 writel(pd->vidcon1, sfb->regs + VIDCON1);
1524 /* zero all windows before we do anything */
1525 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1526 s3c_fb_clear_win(sfb, win_no);
1528 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1529 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1531 regs += (win_no * 8);
1532 writel(0xffffff, regs + WKEYCON0);
1533 writel(0xffffff, regs + WKEYCON1);
1536 /* restore framebuffers */
1537 for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1538 win = sfb->windows[win_no];
1539 if (!win)
1540 continue;
1542 dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
1543 s3c_fb_set_par(win->fbinfo);
1546 return 0;
1549 int s3c_fb_runtime_suspend(struct device *dev)
1551 struct platform_device *pdev = to_platform_device(dev);
1552 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1553 struct s3c_fb_win *win;
1554 int win_no;
1556 for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1557 win = sfb->windows[win_no];
1558 if (!win)
1559 continue;
1561 /* use the blank function to push into power-down */
1562 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1565 clk_disable(sfb->bus_clk);
1566 return 0;
1569 int s3c_fb_runtime_resume(struct device *dev)
1571 struct platform_device *pdev = to_platform_device(dev);
1572 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1573 struct s3c_fb_platdata *pd = sfb->pdata;
1574 struct s3c_fb_win *win;
1575 int win_no;
1577 clk_enable(sfb->bus_clk);
1579 /* setup registers */
1580 writel(pd->vidcon1, sfb->regs + VIDCON1);
1582 /* zero all windows before we do anything */
1583 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1584 s3c_fb_clear_win(sfb, win_no);
1586 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1587 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1589 regs += (win_no * 8);
1590 writel(0xffffff, regs + WKEYCON0);
1591 writel(0xffffff, regs + WKEYCON1);
1594 /* restore framebuffers */
1595 for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1596 win = sfb->windows[win_no];
1597 if (!win)
1598 continue;
1600 dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
1601 s3c_fb_set_par(win->fbinfo);
1604 return 0;
1607 #else
1608 #define s3c_fb_suspend NULL
1609 #define s3c_fb_resume NULL
1610 #define s3c_fb_runtime_suspend NULL
1611 #define s3c_fb_runtime_resume NULL
1612 #endif
1615 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1616 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1618 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1619 [0] = {
1620 .has_osd_c = 1,
1621 .osd_size_off = 0x8,
1622 .palette_sz = 256,
1623 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1625 [1] = {
1626 .has_osd_c = 1,
1627 .has_osd_d = 1,
1628 .osd_size_off = 0x12,
1629 .has_osd_alpha = 1,
1630 .palette_sz = 256,
1631 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1632 VALID_BPP(18) | VALID_BPP(19) |
1633 VALID_BPP(24) | VALID_BPP(25)),
1635 [2] = {
1636 .has_osd_c = 1,
1637 .has_osd_d = 1,
1638 .osd_size_off = 0x12,
1639 .has_osd_alpha = 1,
1640 .palette_sz = 16,
1641 .palette_16bpp = 1,
1642 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1643 VALID_BPP(18) | VALID_BPP(19) |
1644 VALID_BPP(24) | VALID_BPP(25)),
1646 [3] = {
1647 .has_osd_c = 1,
1648 .has_osd_alpha = 1,
1649 .palette_sz = 16,
1650 .palette_16bpp = 1,
1651 .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
1652 VALID_BPP(18) | VALID_BPP(19) |
1653 VALID_BPP(24) | VALID_BPP(25)),
1655 [4] = {
1656 .has_osd_c = 1,
1657 .has_osd_alpha = 1,
1658 .palette_sz = 4,
1659 .palette_16bpp = 1,
1660 .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
1661 VALID_BPP(16) | VALID_BPP(18) |
1662 VALID_BPP(24) | VALID_BPP(25)),
1666 static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1667 .variant = {
1668 .nr_windows = 5,
1669 .vidtcon = VIDTCON0,
1670 .wincon = WINCON(0),
1671 .winmap = WINxMAP(0),
1672 .keycon = WKEYCON,
1673 .osd = VIDOSD_BASE,
1674 .osd_stride = 16,
1675 .buf_start = VIDW_BUF_START(0),
1676 .buf_size = VIDW_BUF_SIZE(0),
1677 .buf_end = VIDW_BUF_END(0),
1679 .palette = {
1680 [0] = 0x400,
1681 [1] = 0x800,
1682 [2] = 0x300,
1683 [3] = 0x320,
1684 [4] = 0x340,
1687 .has_prtcon = 1,
1689 .win[0] = &s3c_fb_data_64xx_wins[0],
1690 .win[1] = &s3c_fb_data_64xx_wins[1],
1691 .win[2] = &s3c_fb_data_64xx_wins[2],
1692 .win[3] = &s3c_fb_data_64xx_wins[3],
1693 .win[4] = &s3c_fb_data_64xx_wins[4],
1696 static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1697 .variant = {
1698 .nr_windows = 5,
1699 .vidtcon = VIDTCON0,
1700 .wincon = WINCON(0),
1701 .winmap = WINxMAP(0),
1702 .keycon = WKEYCON,
1703 .osd = VIDOSD_BASE,
1704 .osd_stride = 16,
1705 .buf_start = VIDW_BUF_START(0),
1706 .buf_size = VIDW_BUF_SIZE(0),
1707 .buf_end = VIDW_BUF_END(0),
1709 .palette = {
1710 [0] = 0x2400,
1711 [1] = 0x2800,
1712 [2] = 0x2c00,
1713 [3] = 0x3000,
1714 [4] = 0x3400,
1717 .has_prtcon = 1,
1719 .win[0] = &s3c_fb_data_64xx_wins[0],
1720 .win[1] = &s3c_fb_data_64xx_wins[1],
1721 .win[2] = &s3c_fb_data_64xx_wins[2],
1722 .win[3] = &s3c_fb_data_64xx_wins[3],
1723 .win[4] = &s3c_fb_data_64xx_wins[4],
1726 static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1727 .variant = {
1728 .nr_windows = 5,
1729 .vidtcon = VIDTCON0,
1730 .wincon = WINCON(0),
1731 .winmap = WINxMAP(0),
1732 .keycon = WKEYCON,
1733 .osd = VIDOSD_BASE,
1734 .osd_stride = 16,
1735 .buf_start = VIDW_BUF_START(0),
1736 .buf_size = VIDW_BUF_SIZE(0),
1737 .buf_end = VIDW_BUF_END(0),
1739 .palette = {
1740 [0] = 0x2400,
1741 [1] = 0x2800,
1742 [2] = 0x2c00,
1743 [3] = 0x3000,
1744 [4] = 0x3400,
1747 .has_shadowcon = 1,
1749 .win[0] = &s3c_fb_data_64xx_wins[0],
1750 .win[1] = &s3c_fb_data_64xx_wins[1],
1751 .win[2] = &s3c_fb_data_64xx_wins[2],
1752 .win[3] = &s3c_fb_data_64xx_wins[3],
1753 .win[4] = &s3c_fb_data_64xx_wins[4],
1756 /* S3C2443/S3C2416 style hardware */
1757 static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1758 .variant = {
1759 .nr_windows = 2,
1760 .is_2443 = 1,
1762 .vidtcon = 0x08,
1763 .wincon = 0x14,
1764 .winmap = 0xd0,
1765 .keycon = 0xb0,
1766 .osd = 0x28,
1767 .osd_stride = 12,
1768 .buf_start = 0x64,
1769 .buf_size = 0x94,
1770 .buf_end = 0x7c,
1772 .palette = {
1773 [0] = 0x400,
1774 [1] = 0x800,
1777 .win[0] = &(struct s3c_fb_win_variant) {
1778 .palette_sz = 256,
1779 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1781 .win[1] = &(struct s3c_fb_win_variant) {
1782 .has_osd_c = 1,
1783 .has_osd_alpha = 1,
1784 .palette_sz = 256,
1785 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1786 VALID_BPP(18) | VALID_BPP(19) |
1787 VALID_BPP(24) | VALID_BPP(25) |
1788 VALID_BPP(28)),
1792 static struct platform_device_id s3c_fb_driver_ids[] = {
1794 .name = "s3c-fb",
1795 .driver_data = (unsigned long)&s3c_fb_data_64xx,
1796 }, {
1797 .name = "s5pc100-fb",
1798 .driver_data = (unsigned long)&s3c_fb_data_s5pc100,
1799 }, {
1800 .name = "s5pv210-fb",
1801 .driver_data = (unsigned long)&s3c_fb_data_s5pv210,
1802 }, {
1803 .name = "s3c2443-fb",
1804 .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
1808 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
1810 static const struct dev_pm_ops s3cfb_pm_ops = {
1811 .suspend = s3c_fb_suspend,
1812 .resume = s3c_fb_resume,
1813 .runtime_suspend = s3c_fb_runtime_suspend,
1814 .runtime_resume = s3c_fb_runtime_resume,
1817 static struct platform_driver s3c_fb_driver = {
1818 .probe = s3c_fb_probe,
1819 .remove = __devexit_p(s3c_fb_remove),
1820 .id_table = s3c_fb_driver_ids,
1821 .driver = {
1822 .name = "s3c-fb",
1823 .owner = THIS_MODULE,
1824 .pm = &s3cfb_pm_ops,
1828 static int __init s3c_fb_init(void)
1830 return platform_driver_register(&s3c_fb_driver);
1833 static void __exit s3c_fb_cleanup(void)
1835 platform_driver_unregister(&s3c_fb_driver);
1838 module_init(s3c_fb_init);
1839 module_exit(s3c_fb_cleanup);
1841 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1842 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
1843 MODULE_LICENSE("GPL");
1844 MODULE_ALIAS("platform:s3c-fb");