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Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6/kvm.git] / drivers / mmc / host / mmci.c
blob2d6de3e03e2dcca2e01f9322ef5c306d5bb473af
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson AB.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/highmem.h>
21 #include <linux/log2.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/amba/bus.h>
25 #include <linux/clk.h>
26 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/amba/mmci.h>
29 #include <linux/regulator/consumer.h>
30
31 #include <asm/div64.h>
32 #include <asm/io.h>
33 #include <asm/sizes.h>
34
35 #include "mmci.h"
36
37 #define DRIVER_NAME "mmci-pl18x"
38
39 static unsigned int fmax = 515633;
40
41 /**
42 * struct variant_data - MMCI variant-specific quirks
43 * @clkreg: default value for MCICLOCK register
44 * @clkreg_enable: enable value for MMCICLOCK register
45 * @datalength_bits: number of bits in the MMCIDATALENGTH register
46 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
47 * is asserted (likewise for RX)
48 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
49 * is asserted (likewise for RX)
50 * @sdio: variant supports SDIO
51 * @st_clkdiv: true if using a ST-specific clock divider algorithm
52 */
53 struct variant_data {
54 unsigned int clkreg;
55 unsigned int clkreg_enable;
56 unsigned int datalength_bits;
57 unsigned int fifosize;
58 unsigned int fifohalfsize;
59 bool sdio;
60 bool st_clkdiv;
61 };
62
63 static struct variant_data variant_arm = {
64 .fifosize = 16 * 4,
65 .fifohalfsize = 8 * 4,
66 .datalength_bits = 16,
67 };
68
69 static struct variant_data variant_u300 = {
70 .fifosize = 16 * 4,
71 .fifohalfsize = 8 * 4,
72 .clkreg_enable = 1 << 13, /* HWFCEN */
73 .datalength_bits = 16,
74 .sdio = true,
75 };
76
77 static struct variant_data variant_ux500 = {
78 .fifosize = 30 * 4,
79 .fifohalfsize = 8 * 4,
80 .clkreg = MCI_CLK_ENABLE,
81 .clkreg_enable = 1 << 14, /* HWFCEN */
82 .datalength_bits = 24,
83 .sdio = true,
84 .st_clkdiv = true,
85 };
86
87 /*
88 * This must be called with host->lock held
89 */
90 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
91 {
92 struct variant_data *variant = host->variant;
93 u32 clk = variant->clkreg;
94
95 if (desired) {
96 if (desired >= host->mclk) {
97 clk = MCI_CLK_BYPASS;
98 host->cclk = host->mclk;
99 } else if (variant->st_clkdiv) {
100 /*
101 * DB8500 TRM says f = mclk / (clkdiv + 2)
102 * => clkdiv = (mclk / f) - 2
103 * Round the divider up so we don't exceed the max
104 * frequency
105 */
106 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
107 if (clk >= 256)
108 clk = 255;
109 host->cclk = host->mclk / (clk + 2);
110 } else {
111 /*
112 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
113 * => clkdiv = mclk / (2 * f) - 1
114 */
115 clk = host->mclk / (2 * desired) - 1;
116 if (clk >= 256)
117 clk = 255;
118 host->cclk = host->mclk / (2 * (clk + 1));
119 }
120
121 clk |= variant->clkreg_enable;
122 clk |= MCI_CLK_ENABLE;
123 /* This hasn't proven to be worthwhile */
124 /* clk |= MCI_CLK_PWRSAVE; */
125 }
126
127 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
128 clk |= MCI_4BIT_BUS;
129 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
130 clk |= MCI_ST_8BIT_BUS;
131
132 writel(clk, host->base + MMCICLOCK);
133 }
134
135 static void
136 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
137 {
138 writel(0, host->base + MMCICOMMAND);
139
140 BUG_ON(host->data);
141
142 host->mrq = NULL;
143 host->cmd = NULL;
144
145 if (mrq->data)
146 mrq->data->bytes_xfered = host->data_xfered;
147
148 /*
149 * Need to drop the host lock here; mmc_request_done may call
150 * back into the driver...
151 */
152 spin_unlock(&host->lock);
153 mmc_request_done(host->mmc, mrq);
154 spin_lock(&host->lock);
155 }
156
157 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
158 {
159 void __iomem *base = host->base;
160
161 if (host->singleirq) {
162 unsigned int mask0 = readl(base + MMCIMASK0);
163
164 mask0 &= ~MCI_IRQ1MASK;
165 mask0 |= mask;
166
167 writel(mask0, base + MMCIMASK0);
168 }
169
170 writel(mask, base + MMCIMASK1);
171 }
172
173 static void mmci_stop_data(struct mmci_host *host)
174 {
175 writel(0, host->base + MMCIDATACTRL);
176 mmci_set_mask1(host, 0);
177 host->data = NULL;
178 }
179
180 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
181 {
182 unsigned int flags = SG_MITER_ATOMIC;
183
184 if (data->flags & MMC_DATA_READ)
185 flags |= SG_MITER_TO_SG;
186 else
187 flags |= SG_MITER_FROM_SG;
188
189 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
190 }
191
192 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
193 {
194 struct variant_data *variant = host->variant;
195 unsigned int datactrl, timeout, irqmask;
196 unsigned long long clks;
197 void __iomem *base;
198 int blksz_bits;
199
200 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
201 data->blksz, data->blocks, data->flags);
202
203 host->data = data;
204 host->size = data->blksz * data->blocks;
205 host->data_xfered = 0;
206
207 mmci_init_sg(host, data);
208
209 clks = (unsigned long long)data->timeout_ns * host->cclk;
210 do_div(clks, 1000000000UL);
211
212 timeout = data->timeout_clks + (unsigned int)clks;
213
214 base = host->base;
215 writel(timeout, base + MMCIDATATIMER);
216 writel(host->size, base + MMCIDATALENGTH);
217
218 blksz_bits = ffs(data->blksz) - 1;
219 BUG_ON(1 << blksz_bits != data->blksz);
220
221 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
222 if (data->flags & MMC_DATA_READ) {
223 datactrl |= MCI_DPSM_DIRECTION;
224 irqmask = MCI_RXFIFOHALFFULLMASK;
225
226 /*
227 * If we have less than a FIFOSIZE of bytes to transfer,
228 * trigger a PIO interrupt as soon as any data is available.
229 */
230 if (host->size < variant->fifosize)
231 irqmask |= MCI_RXDATAAVLBLMASK;
232 } else {
233 /*
234 * We don't actually need to include "FIFO empty" here
235 * since its implicit in "FIFO half empty".
236 */
237 irqmask = MCI_TXFIFOHALFEMPTYMASK;
238 }
239
240 /* The ST Micro variants has a special bit to enable SDIO */
241 if (variant->sdio && host->mmc->card)
242 if (mmc_card_sdio(host->mmc->card))
243 datactrl |= MCI_ST_DPSM_SDIOEN;
244
245 writel(datactrl, base + MMCIDATACTRL);
246 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
247 mmci_set_mask1(host, irqmask);
248 }
249
250 static void
251 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
252 {
253 void __iomem *base = host->base;
254
255 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
256 cmd->opcode, cmd->arg, cmd->flags);
257
258 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
259 writel(0, base + MMCICOMMAND);
260 udelay(1);
261 }
262
263 c |= cmd->opcode | MCI_CPSM_ENABLE;
264 if (cmd->flags & MMC_RSP_PRESENT) {
265 if (cmd->flags & MMC_RSP_136)
266 c |= MCI_CPSM_LONGRSP;
267 c |= MCI_CPSM_RESPONSE;
268 }
269 if (/*interrupt*/0)
270 c |= MCI_CPSM_INTERRUPT;
271
272 host->cmd = cmd;
273
274 writel(cmd->arg, base + MMCIARGUMENT);
275 writel(c, base + MMCICOMMAND);
276 }
277
278 static void
279 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
280 unsigned int status)
281 {
282 /* First check for errors */
283 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
284 u32 remain, success;
285
286 /* Calculate how far we are into the transfer */
287 remain = readl(host->base + MMCIDATACNT);
288 success = data->blksz * data->blocks - remain;
289
290 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
291 if (status & MCI_DATACRCFAIL) {
292 /* Last block was not successful */
293 host->data_xfered = round_down(success - 1, data->blksz);
294 data->error = -EILSEQ;
295 } else if (status & MCI_DATATIMEOUT) {
296 host->data_xfered = round_down(success, data->blksz);
297 data->error = -ETIMEDOUT;
298 } else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
299 host->data_xfered = round_down(success, data->blksz);
300 data->error = -EIO;
301 }
302
303 /*
304 * We hit an error condition. Ensure that any data
305 * partially written to a page is properly coherent.
306 */
307 if (data->flags & MMC_DATA_READ) {
308 struct sg_mapping_iter *sg_miter = &host->sg_miter;
309 unsigned long flags;
310
311 local_irq_save(flags);
312 if (sg_miter_next(sg_miter)) {
313 flush_dcache_page(sg_miter->page);
314 sg_miter_stop(sg_miter);
315 }
316 local_irq_restore(flags);
317 }
318 }
319
320 if (status & MCI_DATABLOCKEND)
321 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
322
323 if (status & MCI_DATAEND || data->error) {
324 mmci_stop_data(host);
325
326 if (!data->error)
327 /* The error clause is handled above, success! */
328 host->data_xfered += data->blksz * data->blocks;
329
330 if (!data->stop) {
331 mmci_request_end(host, data->mrq);
332 } else {
333 mmci_start_command(host, data->stop, 0);
334 }
335 }
336 }
337
338 static void
339 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
340 unsigned int status)
341 {
342 void __iomem *base = host->base;
343
344 host->cmd = NULL;
345
346 if (status & MCI_CMDTIMEOUT) {
347 cmd->error = -ETIMEDOUT;
348 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
349 cmd->error = -EILSEQ;
350 } else {
351 cmd->resp[0] = readl(base + MMCIRESPONSE0);
352 cmd->resp[1] = readl(base + MMCIRESPONSE1);
353 cmd->resp[2] = readl(base + MMCIRESPONSE2);
354 cmd->resp[3] = readl(base + MMCIRESPONSE3);
355 }
356
357 if (!cmd->data || cmd->error) {
358 if (host->data)
359 mmci_stop_data(host);
360 mmci_request_end(host, cmd->mrq);
361 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
362 mmci_start_data(host, cmd->data);
363 }
364 }
365
366 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
367 {
368 void __iomem *base = host->base;
369 char *ptr = buffer;
370 u32 status;
371 int host_remain = host->size;
372
373 do {
374 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
375
376 if (count > remain)
377 count = remain;
378
379 if (count <= 0)
380 break;
381
382 readsl(base + MMCIFIFO, ptr, count >> 2);
383
384 ptr += count;
385 remain -= count;
386 host_remain -= count;
387
388 if (remain == 0)
389 break;
390
391 status = readl(base + MMCISTATUS);
392 } while (status & MCI_RXDATAAVLBL);
393
394 return ptr - buffer;
395 }
396
397 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
398 {
399 struct variant_data *variant = host->variant;
400 void __iomem *base = host->base;
401 char *ptr = buffer;
402
403 do {
404 unsigned int count, maxcnt;
405
406 maxcnt = status & MCI_TXFIFOEMPTY ?
407 variant->fifosize : variant->fifohalfsize;
408 count = min(remain, maxcnt);
409
410 /*
411 * The ST Micro variant for SDIO transfer sizes
412 * less then 8 bytes should have clock H/W flow
413 * control disabled.
414 */
415 if (variant->sdio &&
416 mmc_card_sdio(host->mmc->card)) {
417 if (count < 8)
418 writel(readl(host->base + MMCICLOCK) &
419 ~variant->clkreg_enable,
420 host->base + MMCICLOCK);
421 else
422 writel(readl(host->base + MMCICLOCK) |
423 variant->clkreg_enable,
424 host->base + MMCICLOCK);
425 }
426
427 /*
428 * SDIO especially may want to send something that is
429 * not divisible by 4 (as opposed to card sectors
430 * etc), and the FIFO only accept full 32-bit writes.
431 * So compensate by adding +3 on the count, a single
432 * byte become a 32bit write, 7 bytes will be two
433 * 32bit writes etc.
434 */
435 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
436
437 ptr += count;
438 remain -= count;
439
440 if (remain == 0)
441 break;
442
443 status = readl(base + MMCISTATUS);
444 } while (status & MCI_TXFIFOHALFEMPTY);
445
446 return ptr - buffer;
447 }
448
449 /*
450 * PIO data transfer IRQ handler.
451 */
452 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
453 {
454 struct mmci_host *host = dev_id;
455 struct sg_mapping_iter *sg_miter = &host->sg_miter;
456 struct variant_data *variant = host->variant;
457 void __iomem *base = host->base;
458 unsigned long flags;
459 u32 status;
460
461 status = readl(base + MMCISTATUS);
462
463 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
464
465 local_irq_save(flags);
466
467 do {
468 unsigned int remain, len;
469 char *buffer;
470
471 /*
472 * For write, we only need to test the half-empty flag
473 * here - if the FIFO is completely empty, then by
474 * definition it is more than half empty.
475 *
476 * For read, check for data available.
477 */
478 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
479 break;
480
481 if (!sg_miter_next(sg_miter))
482 break;
483
484 buffer = sg_miter->addr;
485 remain = sg_miter->length;
486
487 len = 0;
488 if (status & MCI_RXACTIVE)
489 len = mmci_pio_read(host, buffer, remain);
490 if (status & MCI_TXACTIVE)
491 len = mmci_pio_write(host, buffer, remain, status);
492
493 sg_miter->consumed = len;
494
495 host->size -= len;
496 remain -= len;
497
498 if (remain)
499 break;
500
501 if (status & MCI_RXACTIVE)
502 flush_dcache_page(sg_miter->page);
503
504 status = readl(base + MMCISTATUS);
505 } while (1);
506
507 sg_miter_stop(sg_miter);
508
509 local_irq_restore(flags);
510
511 /*
512 * If we're nearing the end of the read, switch to
513 * "any data available" mode.
514 */
515 if (status & MCI_RXACTIVE && host->size < variant->fifosize)
516 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
517
518 /*
519 * If we run out of data, disable the data IRQs; this
520 * prevents a race where the FIFO becomes empty before
521 * the chip itself has disabled the data path, and
522 * stops us racing with our data end IRQ.
523 */
524 if (host->size == 0) {
525 mmci_set_mask1(host, 0);
526 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
527 }
528
529 return IRQ_HANDLED;
530 }
531
532 /*
533 * Handle completion of command and data transfers.
534 */
535 static irqreturn_t mmci_irq(int irq, void *dev_id)
536 {
537 struct mmci_host *host = dev_id;
538 u32 status;
539 int ret = 0;
540
541 spin_lock(&host->lock);
542
543 do {
544 struct mmc_command *cmd;
545 struct mmc_data *data;
546
547 status = readl(host->base + MMCISTATUS);
548
549 if (host->singleirq) {
550 if (status & readl(host->base + MMCIMASK1))
551 mmci_pio_irq(irq, dev_id);
552
553 status &= ~MCI_IRQ1MASK;
554 }
555
556 status &= readl(host->base + MMCIMASK0);
557 writel(status, host->base + MMCICLEAR);
558
559 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
560
561 data = host->data;
562 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
563 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
564 mmci_data_irq(host, data, status);
565
566 cmd = host->cmd;
567 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
568 mmci_cmd_irq(host, cmd, status);
569
570 ret = 1;
571 } while (status);
572
573 spin_unlock(&host->lock);
574
575 return IRQ_RETVAL(ret);
576 }
577
578 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
579 {
580 struct mmci_host *host = mmc_priv(mmc);
581 unsigned long flags;
582
583 WARN_ON(host->mrq != NULL);
584
585 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
586 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
587 mrq->data->blksz);
588 mrq->cmd->error = -EINVAL;
589 mmc_request_done(mmc, mrq);
590 return;
591 }
592
593 spin_lock_irqsave(&host->lock, flags);
594
595 host->mrq = mrq;
596
597 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
598 mmci_start_data(host, mrq->data);
599
600 mmci_start_command(host, mrq->cmd, 0);
601
602 spin_unlock_irqrestore(&host->lock, flags);
603 }
604
605 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
606 {
607 struct mmci_host *host = mmc_priv(mmc);
608 u32 pwr = 0;
609 unsigned long flags;
610 int ret;
611
612 switch (ios->power_mode) {
613 case MMC_POWER_OFF:
614 if (host->vcc)
615 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
616 break;
617 case MMC_POWER_UP:
618 if (host->vcc) {
619 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
620 if (ret) {
621 dev_err(mmc_dev(mmc), "unable to set OCR\n");
622 /*
623 * The .set_ios() function in the mmc_host_ops
624 * struct return void, and failing to set the
625 * power should be rare so we print an error
626 * and return here.
627 */
628 return;
629 }
630 }
631 if (host->plat->vdd_handler)
632 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
633 ios->power_mode);
634 /* The ST version does not have this, fall through to POWER_ON */
635 if (host->hw_designer != AMBA_VENDOR_ST) {
636 pwr |= MCI_PWR_UP;
637 break;
638 }
639 case MMC_POWER_ON:
640 pwr |= MCI_PWR_ON;
641 break;
642 }
643
644 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
645 if (host->hw_designer != AMBA_VENDOR_ST)
646 pwr |= MCI_ROD;
647 else {
648 /*
649 * The ST Micro variant use the ROD bit for something
650 * else and only has OD (Open Drain).
651 */
652 pwr |= MCI_OD;
653 }
654 }
655
656 spin_lock_irqsave(&host->lock, flags);
657
658 mmci_set_clkreg(host, ios->clock);
659
660 if (host->pwr != pwr) {
661 host->pwr = pwr;
662 writel(pwr, host->base + MMCIPOWER);
663 }
664
665 spin_unlock_irqrestore(&host->lock, flags);
666 }
667
668 static int mmci_get_ro(struct mmc_host *mmc)
669 {
670 struct mmci_host *host = mmc_priv(mmc);
671
672 if (host->gpio_wp == -ENOSYS)
673 return -ENOSYS;
674
675 return gpio_get_value_cansleep(host->gpio_wp);
676 }
677
678 static int mmci_get_cd(struct mmc_host *mmc)
679 {
680 struct mmci_host *host = mmc_priv(mmc);
681 struct mmci_platform_data *plat = host->plat;
682 unsigned int status;
683
684 if (host->gpio_cd == -ENOSYS) {
685 if (!plat->status)
686 return 1; /* Assume always present */
687
688 status = plat->status(mmc_dev(host->mmc));
689 } else
690 status = !!gpio_get_value_cansleep(host->gpio_cd)
691 ^ plat->cd_invert;
692
693 /*
694 * Use positive logic throughout - status is zero for no card,
695 * non-zero for card inserted.
696 */
697 return status;
698 }
699
700 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
701 {
702 struct mmci_host *host = dev_id;
703
704 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
705
706 return IRQ_HANDLED;
707 }
708
709 static const struct mmc_host_ops mmci_ops = {
710 .request = mmci_request,
711 .set_ios = mmci_set_ios,
712 .get_ro = mmci_get_ro,
713 .get_cd = mmci_get_cd,
714 };
715
716 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
717 {
718 struct mmci_platform_data *plat = dev->dev.platform_data;
719 struct variant_data *variant = id->data;
720 struct mmci_host *host;
721 struct mmc_host *mmc;
722 int ret;
723
724 /* must have platform data */
725 if (!plat) {
726 ret = -EINVAL;
727 goto out;
728 }
729
730 ret = amba_request_regions(dev, DRIVER_NAME);
731 if (ret)
732 goto out;
733
734 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
735 if (!mmc) {
736 ret = -ENOMEM;
737 goto rel_regions;
738 }
739
740 host = mmc_priv(mmc);
741 host->mmc = mmc;
742
743 host->gpio_wp = -ENOSYS;
744 host->gpio_cd = -ENOSYS;
745 host->gpio_cd_irq = -1;
746
747 host->hw_designer = amba_manf(dev);
748 host->hw_revision = amba_rev(dev);
749 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
750 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
751
752 host->clk = clk_get(&dev->dev, NULL);
753 if (IS_ERR(host->clk)) {
754 ret = PTR_ERR(host->clk);
755 host->clk = NULL;
756 goto host_free;
757 }
758
759 ret = clk_enable(host->clk);
760 if (ret)
761 goto clk_free;
762
763 host->plat = plat;
764 host->variant = variant;
765 host->mclk = clk_get_rate(host->clk);
766 /*
767 * According to the spec, mclk is max 100 MHz,
768 * so we try to adjust the clock down to this,
769 * (if possible).
770 */
771 if (host->mclk > 100000000) {
772 ret = clk_set_rate(host->clk, 100000000);
773 if (ret < 0)
774 goto clk_disable;
775 host->mclk = clk_get_rate(host->clk);
776 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
777 host->mclk);
778 }
779 host->base = ioremap(dev->res.start, resource_size(&dev->res));
780 if (!host->base) {
781 ret = -ENOMEM;
782 goto clk_disable;
783 }
784
785 mmc->ops = &mmci_ops;
786 mmc->f_min = (host->mclk + 511) / 512;
787 /*
788 * If the platform data supplies a maximum operating
789 * frequency, this takes precedence. Else, we fall back
790 * to using the module parameter, which has a (low)
791 * default value in case it is not specified. Either
792 * value must not exceed the clock rate into the block,
793 * of course.
794 */
795 if (plat->f_max)
796 mmc->f_max = min(host->mclk, plat->f_max);
797 else
798 mmc->f_max = min(host->mclk, fmax);
799 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
800
801 #ifdef CONFIG_REGULATOR
802 /* If we're using the regulator framework, try to fetch a regulator */
803 host->vcc = regulator_get(&dev->dev, "vmmc");
804 if (IS_ERR(host->vcc))
805 host->vcc = NULL;
806 else {
807 int mask = mmc_regulator_get_ocrmask(host->vcc);
808
809 if (mask < 0)
810 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
811 mask);
812 else {
813 host->mmc->ocr_avail = (u32) mask;
814 if (plat->ocr_mask)
815 dev_warn(&dev->dev,
816 "Provided ocr_mask/setpower will not be used "
817 "(using regulator instead)\n");
818 }
819 }
820 #endif
821 /* Fall back to platform data if no regulator is found */
822 if (host->vcc == NULL)
823 mmc->ocr_avail = plat->ocr_mask;
824 mmc->caps = plat->capabilities;
825
826 /*
827 * We can do SGIO
828 */
829 mmc->max_segs = NR_SG;
830
831 /*
832 * Since only a certain number of bits are valid in the data length
833 * register, we must ensure that we don't exceed 2^num-1 bytes in a
834 * single request.
835 */
836 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
837
838 /*
839 * Set the maximum segment size. Since we aren't doing DMA
840 * (yet) we are only limited by the data length register.
841 */
842 mmc->max_seg_size = mmc->max_req_size;
843
844 /*
845 * Block size can be up to 2048 bytes, but must be a power of two.
846 */
847 mmc->max_blk_size = 2048;
848
849 /*
850 * No limit on the number of blocks transferred.
851 */
852 mmc->max_blk_count = mmc->max_req_size;
853
854 spin_lock_init(&host->lock);
855
856 writel(0, host->base + MMCIMASK0);
857 writel(0, host->base + MMCIMASK1);
858 writel(0xfff, host->base + MMCICLEAR);
859
860 if (gpio_is_valid(plat->gpio_cd)) {
861 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
862 if (ret == 0)
863 ret = gpio_direction_input(plat->gpio_cd);
864 if (ret == 0)
865 host->gpio_cd = plat->gpio_cd;
866 else if (ret != -ENOSYS)
867 goto err_gpio_cd;
868
869 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
870 mmci_cd_irq, 0,
871 DRIVER_NAME " (cd)", host);
872 if (ret >= 0)
873 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
874 }
875 if (gpio_is_valid(plat->gpio_wp)) {
876 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
877 if (ret == 0)
878 ret = gpio_direction_input(plat->gpio_wp);
879 if (ret == 0)
880 host->gpio_wp = plat->gpio_wp;
881 else if (ret != -ENOSYS)
882 goto err_gpio_wp;
883 }
884
885 if ((host->plat->status || host->gpio_cd != -ENOSYS)
886 && host->gpio_cd_irq < 0)
887 mmc->caps |= MMC_CAP_NEEDS_POLL;
888
889 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
890 if (ret)
891 goto unmap;
892
893 if (dev->irq[1] == NO_IRQ)
894 host->singleirq = true;
895 else {
896 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
897 DRIVER_NAME " (pio)", host);
898 if (ret)
899 goto irq0_free;
900 }
901
902 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
903
904 amba_set_drvdata(dev, mmc);
905
906 dev_info(&dev->dev, "%s: PL%03x rev%u at 0x%08llx irq %d,%d\n",
907 mmc_hostname(mmc), amba_part(dev), amba_rev(dev),
908 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
909
910 mmc_add_host(mmc);
911
912 return 0;
913
914 irq0_free:
915 free_irq(dev->irq[0], host);
916 unmap:
917 if (host->gpio_wp != -ENOSYS)
918 gpio_free(host->gpio_wp);
919 err_gpio_wp:
920 if (host->gpio_cd_irq >= 0)
921 free_irq(host->gpio_cd_irq, host);
922 if (host->gpio_cd != -ENOSYS)
923 gpio_free(host->gpio_cd);
924 err_gpio_cd:
925 iounmap(host->base);
926 clk_disable:
927 clk_disable(host->clk);
928 clk_free:
929 clk_put(host->clk);
930 host_free:
931 mmc_free_host(mmc);
932 rel_regions:
933 amba_release_regions(dev);
934 out:
935 return ret;
936 }
937
938 static int __devexit mmci_remove(struct amba_device *dev)
939 {
940 struct mmc_host *mmc = amba_get_drvdata(dev);
941
942 amba_set_drvdata(dev, NULL);
943
944 if (mmc) {
945 struct mmci_host *host = mmc_priv(mmc);
946
947 mmc_remove_host(mmc);
948
949 writel(0, host->base + MMCIMASK0);
950 writel(0, host->base + MMCIMASK1);
951
952 writel(0, host->base + MMCICOMMAND);
953 writel(0, host->base + MMCIDATACTRL);
954
955 free_irq(dev->irq[0], host);
956 if (!host->singleirq)
957 free_irq(dev->irq[1], host);
958
959 if (host->gpio_wp != -ENOSYS)
960 gpio_free(host->gpio_wp);
961 if (host->gpio_cd_irq >= 0)
962 free_irq(host->gpio_cd_irq, host);
963 if (host->gpio_cd != -ENOSYS)
964 gpio_free(host->gpio_cd);
965
966 iounmap(host->base);
967 clk_disable(host->clk);
968 clk_put(host->clk);
969
970 if (host->vcc)
971 mmc_regulator_set_ocr(mmc, host->vcc, 0);
972 regulator_put(host->vcc);
973
974 mmc_free_host(mmc);
975
976 amba_release_regions(dev);
977 }
978
979 return 0;
980 }
981
982 #ifdef CONFIG_PM
983 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
984 {
985 struct mmc_host *mmc = amba_get_drvdata(dev);
986 int ret = 0;
987
988 if (mmc) {
989 struct mmci_host *host = mmc_priv(mmc);
990
991 ret = mmc_suspend_host(mmc);
992 if (ret == 0)
993 writel(0, host->base + MMCIMASK0);
994 }
995
996 return ret;
997 }
998
999 static int mmci_resume(struct amba_device *dev)
1000 {
1001 struct mmc_host *mmc = amba_get_drvdata(dev);
1002 int ret = 0;
1003
1004 if (mmc) {
1005 struct mmci_host *host = mmc_priv(mmc);
1006
1007 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1008
1009 ret = mmc_resume_host(mmc);
1010 }
1011
1012 return ret;
1013 }
1014 #else
1015 #define mmci_suspend NULL
1016 #define mmci_resume NULL
1017 #endif
1018
1019 static struct amba_id mmci_ids[] = {
1020 {
1021 .id = 0x00041180,
1022 .mask = 0x000fffff,
1023 .data = &variant_arm,
1024 },
1025 {
1026 .id = 0x00041181,
1027 .mask = 0x000fffff,
1028 .data = &variant_arm,
1029 },
1030 /* ST Micro variants */
1031 {
1032 .id = 0x00180180,
1033 .mask = 0x00ffffff,
1034 .data = &variant_u300,
1035 },
1036 {
1037 .id = 0x00280180,
1038 .mask = 0x00ffffff,
1039 .data = &variant_u300,
1040 },
1041 {
1042 .id = 0x00480180,
1043 .mask = 0x00ffffff,
1044 .data = &variant_ux500,
1045 },
1046 { 0, 0 },
1047 };
1048
1049 static struct amba_driver mmci_driver = {
1050 .drv = {
1051 .name = DRIVER_NAME,
1052 },
1053 .probe = mmci_probe,
1054 .remove = __devexit_p(mmci_remove),
1055 .suspend = mmci_suspend,
1056 .resume = mmci_resume,
1057 .id_table = mmci_ids,
1058 };
1059
1060 static int __init mmci_init(void)
1061 {
1062 return amba_driver_register(&mmci_driver);
1063 }
1064
1065 static void __exit mmci_exit(void)
1066 {
1067 amba_driver_unregister(&mmci_driver);
1068 }
1069
1070 module_init(mmci_init);
1071 module_exit(mmci_exit);
1072 module_param(fmax, uint, 0444);
1073
1074 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1075 MODULE_LICENSE("GPL");
kernel-based virtual machine