include/asm-sh/irq.h

   1 #ifndef __ASM_SH_IRQ_H
   2 #define __ASM_SH_IRQ_H
   3
   4 #include <asm/machvec.h>
   5 #include <asm/ptrace.h>         /* for pt_regs */
   6
   7 /* NR_IRQS is made from three components:
   8  *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
   9  *   2. PINT_NR_IRQS   - number of PINT interrupts
  10  *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
  11  */
  12
  13 /* 1. ONCHIP_NR_IRQS */
  14 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
  15 # define ONCHIP_NR_IRQS 24      // Actually 21
  16 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
  17 # define ONCHIP_NR_IRQS 64
  18 # define PINT_NR_IRQS   16
  19 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
  20 # define ONCHIP_NR_IRQS 32
  21 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  22       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  23       defined(CONFIG_CPU_SUBTYPE_SH7705)
  24 # define ONCHIP_NR_IRQS 64      // Actually 61
  25 # define PINT_NR_IRQS   16
  26 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
  27 # define ONCHIP_NR_IRQS 104
  28 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
  29 # define ONCHIP_NR_IRQS 48      // Actually 44
  30 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
  31 # define ONCHIP_NR_IRQS 72
  32 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  33 # define ONCHIP_NR_IRQS 112     /* XXX */
  34 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
  35 # define ONCHIP_NR_IRQS 72
  36 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
  37 # define ONCHIP_NR_IRQS 144
  38 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
  39       defined(CONFIG_CPU_SUBTYPE_SH73180) || \
  40       defined(CONFIG_CPU_SUBTYPE_SH7343) || \
  41       defined(CONFIG_CPU_SUBTYPE_SH7722)
  42 # define ONCHIP_NR_IRQS 109
  43 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
  44 # define ONCHIP_NR_IRQS 111
  45 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
  46 # define ONCHIP_NR_IRQS 256
  47 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
  48 # define ONCHIP_NR_IRQS 128
  49 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
  50 # define ONCHIP_NR_IRQS 144
  51 #endif
  52
  53 /* 2. PINT_NR_IRQS */
  54 #ifdef CONFIG_SH_UNKNOWN
  55 # define PINT_NR_IRQS 16
  56 #else
  57 # ifndef PINT_NR_IRQS
  58 #  define PINT_NR_IRQS 0
  59 # endif
  60 #endif
  61
  62 #if PINT_NR_IRQS > 0
  63 # define PINT_IRQ_BASE  ONCHIP_NR_IRQS
  64 #endif
  65
  66 /* 3. OFFCHIP_NR_IRQS */
  67 #if defined(CONFIG_HD64461)
  68 # define OFFCHIP_NR_IRQS 18
  69 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
  70 # define OFFCHIP_NR_IRQS 48
  71 #elif defined(CONFIG_HD64465)
  72 # define OFFCHIP_NR_IRQS 16
  73 #elif defined (CONFIG_SH_EC3104)
  74 # define OFFCHIP_NR_IRQS 16
  75 #elif defined (CONFIG_SH_DREAMCAST)
  76 # define OFFCHIP_NR_IRQS 96
  77 #elif defined (CONFIG_SH_TITAN)
  78 # define OFFCHIP_NR_IRQS 4
  79 #elif defined(CONFIG_SH_R7780RP)
  80 # define OFFCHIP_NR_IRQS 16
  81 #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
  82 # define OFFCHIP_NR_IRQS 12
  83 #elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
  84 # define OFFCHIP_NR_IRQS 14
  85 #elif defined(CONFIG_SH_UNKNOWN)
  86 # define OFFCHIP_NR_IRQS 16     /* Must also be last */
  87 #else
  88 # define OFFCHIP_NR_IRQS 0
  89 #endif
  90
  91 #if OFFCHIP_NR_IRQS > 0
  92 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
  93 #endif
  94
  95 /* NR_IRQS. 1+2+3 */
  96 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
  97
  98 /*
  99  * Convert back and forth between INTEVT and IRQ values.
 100  */
 101 #define evt2irq(evt)            (((evt) >> 5) - 16)
 102 #define irq2evt(irq)            (((irq) + 16) << 5)
 103
 104 /*
 105  * Simple Mask Register Support
 106  */
 107 extern void make_maskreg_irq(unsigned int irq);
 108 extern unsigned short *irq_mask_register;
 109
 110 /*
 111  * PINT IRQs
 112  */
 113 void init_IRQ_pint(void);
 114
 115 /*
 116  * The shift value is now the number of bits to shift, not the number of
 117  * bits/4. This is to make it easier to read the value directly from the
 118  * datasheets. The IPR address, addr, will be set from ipr_idx via the
 119  * map_ipridx_to_addr function.
 120  */
 121 struct ipr_data {
 122         unsigned int irq;
 123         int ipr_idx;            /* Index for the IPR registered */
 124         int shift;              /* Number of bits to shift the data */
 125         int priority;           /* The priority */
 126         unsigned int addr;      /* Address of Interrupt Priority Register */
 127 };
 128
 129 /*
 130  * Given an IPR IDX, map the value to an IPR register address.
 131  */
 132 unsigned int map_ipridx_to_addr(int idx);
 133
 134 /*
 135  * Enable individual interrupt mode for external IPR IRQs.
 136  */
 137 void ipr_irq_enable_irlm(void);
 138
 139 /*
 140  * Function for "on chip support modules".
 141  */
 142 void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
 143 void make_imask_irq(unsigned int irq);
 144 void init_IRQ_ipr(void);
 145
 146 struct intc2_data {
 147         unsigned short irq;
 148         unsigned char ipr_offset, ipr_shift;
 149         unsigned char msk_offset, msk_shift;
 150         unsigned char priority;
 151 };
 152
 153 void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
 154 void init_IRQ_intc2(void);
 155
 156 static inline int generic_irq_demux(int irq)
 157 {
 158         return irq;
 159 }
 160
 161 #define irq_canonicalize(irq)   (irq)
 162 #define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
 163
 164 #ifdef CONFIG_4KSTACKS
 165 extern void irq_ctx_init(int cpu);
 166 extern void irq_ctx_exit(int cpu);
 167 # define __ARCH_HAS_DO_SOFTIRQ
 168 #else
 169 # define irq_ctx_init(cpu) do { } while (0)
 170 # define irq_ctx_exit(cpu) do { } while (0)
 171 #endif
 172
 173 #endif /* __ASM_SH_IRQ_H */