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ARM: 6026/1: ARM: Add support for LZMA-compressed kernel images
[linux-2.6/kvm.git] / drivers / i2c / busses / i2c-mpc.c
blob78a15af3294231f1d1403ab593dc704c27ef1f06
1 /*
2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
8 *
9 * Release 0.8
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_i2c.h>
22
23 #include <linux/io.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28
29 #include <asm/mpc52xx.h>
30 #include <sysdev/fsl_soc.h>
31
32 #define DRV_NAME "mpc-i2c"
33
34 #define MPC_I2C_CLOCK_LEGACY 0
35 #define MPC_I2C_CLOCK_PRESERVE (~0U)
36
37 #define MPC_I2C_FDR 0x04
38 #define MPC_I2C_CR 0x08
39 #define MPC_I2C_SR 0x0c
40 #define MPC_I2C_DR 0x10
41 #define MPC_I2C_DFSRR 0x14
42
43 #define CCR_MEN 0x80
44 #define CCR_MIEN 0x40
45 #define CCR_MSTA 0x20
46 #define CCR_MTX 0x10
47 #define CCR_TXAK 0x08
48 #define CCR_RSTA 0x04
49
50 #define CSR_MCF 0x80
51 #define CSR_MAAS 0x40
52 #define CSR_MBB 0x20
53 #define CSR_MAL 0x10
54 #define CSR_SRW 0x04
55 #define CSR_MIF 0x02
56 #define CSR_RXAK 0x01
57
58 struct mpc_i2c {
59 struct device *dev;
60 void __iomem *base;
61 u32 interrupt;
62 wait_queue_head_t queue;
63 struct i2c_adapter adap;
64 int irq;
65 };
66
67 struct mpc_i2c_divider {
68 u16 divider;
69 u16 fdr; /* including dfsrr */
70 };
71
72 struct mpc_i2c_data {
73 void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
74 u32 clock, u32 prescaler);
75 u32 prescaler;
76 };
77
78 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
79 {
80 writeb(x, i2c->base + MPC_I2C_CR);
81 }
82
83 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
84 {
85 struct mpc_i2c *i2c = dev_id;
86 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
87 /* Read again to allow register to stabilise */
88 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
89 writeb(0, i2c->base + MPC_I2C_SR);
90 wake_up(&i2c->queue);
91 }
92 return IRQ_HANDLED;
93 }
94
95 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
96 * the bus, because it wants to send ACK.
97 * Following sequence of enabling/disabling and sending start/stop generates
98 * the pulse, so it's all OK.
99 */
100 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
101 {
102 writeccr(i2c, 0);
103 udelay(30);
104 writeccr(i2c, CCR_MEN);
105 udelay(30);
106 writeccr(i2c, CCR_MSTA | CCR_MTX);
107 udelay(30);
108 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
109 udelay(30);
110 writeccr(i2c, CCR_MEN);
111 udelay(30);
112 }
113
114 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
115 {
116 unsigned long orig_jiffies = jiffies;
117 u32 x;
118 int result = 0;
119
120 if (i2c->irq == NO_IRQ) {
121 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
122 schedule();
123 if (time_after(jiffies, orig_jiffies + timeout)) {
124 dev_dbg(i2c->dev, "timeout\n");
125 writeccr(i2c, 0);
126 result = -EIO;
127 break;
128 }
129 }
130 x = readb(i2c->base + MPC_I2C_SR);
131 writeb(0, i2c->base + MPC_I2C_SR);
132 } else {
133 /* Interrupt mode */
134 result = wait_event_timeout(i2c->queue,
135 (i2c->interrupt & CSR_MIF), timeout);
136
137 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
138 dev_dbg(i2c->dev, "wait timeout\n");
139 writeccr(i2c, 0);
140 result = -ETIMEDOUT;
141 }
142
143 x = i2c->interrupt;
144 i2c->interrupt = 0;
145 }
146
147 if (result < 0)
148 return result;
149
150 if (!(x & CSR_MCF)) {
151 dev_dbg(i2c->dev, "unfinished\n");
152 return -EIO;
153 }
154
155 if (x & CSR_MAL) {
156 dev_dbg(i2c->dev, "MAL\n");
157 return -EIO;
158 }
159
160 if (writing && (x & CSR_RXAK)) {
161 dev_dbg(i2c->dev, "No RXAK\n");
162 /* generate stop */
163 writeccr(i2c, CCR_MEN);
164 return -EIO;
165 }
166 return 0;
167 }
168
169 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
170 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
171 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
172 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
173 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
174 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
175 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
176 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
177 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
178 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
179 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
180 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
181 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
182 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
183 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
184 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
185 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
186 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
187 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
188 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
189 };
190
191 static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
192 int prescaler)
193 {
194 const struct mpc_i2c_divider *div = NULL;
195 unsigned int pvr = mfspr(SPRN_PVR);
196 u32 divider;
197 int i;
198
199 if (clock == MPC_I2C_CLOCK_LEGACY)
200 return -EINVAL;
201
202 /* Determine divider value */
203 divider = mpc5xxx_get_bus_frequency(node) / clock;
204
205 /*
206 * We want to choose an FDR/DFSR that generates an I2C bus speed that
207 * is equal to or lower than the requested speed.
208 */
209 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
210 div = &mpc_i2c_dividers_52xx[i];
211 /* Old MPC5200 rev A CPUs do not support the high bits */
212 if (div->fdr & 0xc0 && pvr == 0x80822011)
213 continue;
214 if (div->divider >= divider)
215 break;
216 }
217
218 return div ? (int)div->fdr : -EINVAL;
219 }
220
221 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
222 struct mpc_i2c *i2c,
223 u32 clock, u32 prescaler)
224 {
225 int ret, fdr;
226
227 if (clock == MPC_I2C_CLOCK_PRESERVE) {
228 dev_dbg(i2c->dev, "using fdr %d\n",
229 readb(i2c->base + MPC_I2C_FDR));
230 return;
231 }
232
233 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
234 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
235
236 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
237
238 if (ret >= 0)
239 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
240 }
241 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
242 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
243 struct mpc_i2c *i2c,
244 u32 clock, u32 prescaler)
245 {
246 }
247 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
248
249 #ifdef CONFIG_PPC_MPC512x
250 static void __devinit mpc_i2c_setup_512x(struct device_node *node,
251 struct mpc_i2c *i2c,
252 u32 clock, u32 prescaler)
253 {
254 struct device_node *node_ctrl;
255 void __iomem *ctrl;
256 const u32 *pval;
257 u32 idx;
258
259 /* Enable I2C interrupts for mpc5121 */
260 node_ctrl = of_find_compatible_node(NULL, NULL,
261 "fsl,mpc5121-i2c-ctrl");
262 if (node_ctrl) {
263 ctrl = of_iomap(node_ctrl, 0);
264 if (ctrl) {
265 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
266 pval = of_get_property(node, "reg", NULL);
267 idx = (*pval & 0xff) / 0x20;
268 setbits32(ctrl, 1 << (24 + idx * 2));
269 iounmap(ctrl);
270 }
271 of_node_put(node_ctrl);
272 }
273
274 /* The clock setup for the 52xx works also fine for the 512x */
275 mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
276 }
277 #else /* CONFIG_PPC_MPC512x */
278 static void __devinit mpc_i2c_setup_512x(struct device_node *node,
279 struct mpc_i2c *i2c,
280 u32 clock, u32 prescaler)
281 {
282 }
283 #endif /* CONFIG_PPC_MPC512x */
284
285 #ifdef CONFIG_FSL_SOC
286 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
287 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
288 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
289 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
290 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
291 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
292 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
293 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
294 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
295 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
296 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
297 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
298 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
299 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
300 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
301 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
302 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
303 {49152, 0x011e}, {61440, 0x011f}
304 };
305
306 static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
307 {
308 struct device_node *node = NULL;
309 u32 __iomem *reg;
310 u32 val = 0;
311
312 node = of_find_node_by_name(NULL, "global-utilities");
313 if (node) {
314 const u32 *prop = of_get_property(node, "reg", NULL);
315 if (prop) {
316 /*
317 * Map and check POR Device Status Register 2
318 * (PORDEVSR2) at 0xE0014
319 */
320 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
321 if (!reg)
322 printk(KERN_ERR
323 "Error: couldn't map PORDEVSR2\n");
324 else
325 val = in_be32(reg) & 0x00000080; /* sec-cfg */
326 iounmap(reg);
327 }
328 }
329 if (node)
330 of_node_put(node);
331
332 return val;
333 }
334
335 static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
336 u32 prescaler)
337 {
338 const struct mpc_i2c_divider *div = NULL;
339 u32 divider;
340 int i;
341
342 if (clock == MPC_I2C_CLOCK_LEGACY)
343 return -EINVAL;
344
345 /* Determine proper divider value */
346 if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
347 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
348 if (!prescaler)
349 prescaler = 1;
350
351 divider = fsl_get_sys_freq() / clock / prescaler;
352
353 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
354 fsl_get_sys_freq(), clock, divider);
355
356 /*
357 * We want to choose an FDR/DFSR that generates an I2C bus speed that
358 * is equal to or lower than the requested speed.
359 */
360 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
361 div = &mpc_i2c_dividers_8xxx[i];
362 if (div->divider >= divider)
363 break;
364 }
365
366 return div ? (int)div->fdr : -EINVAL;
367 }
368
369 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
370 struct mpc_i2c *i2c,
371 u32 clock, u32 prescaler)
372 {
373 int ret, fdr;
374
375 if (clock == MPC_I2C_CLOCK_PRESERVE) {
376 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
377 readb(i2c->base + MPC_I2C_DFSRR),
378 readb(i2c->base + MPC_I2C_FDR));
379 return;
380 }
381
382 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
383 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
384
385 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
386 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
387
388 if (ret >= 0)
389 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
390 clock, fdr >> 8, fdr & 0xff);
391 }
392
393 #else /* !CONFIG_FSL_SOC */
394 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
395 struct mpc_i2c *i2c,
396 u32 clock, u32 prescaler)
397 {
398 }
399 #endif /* CONFIG_FSL_SOC */
400
401 static void mpc_i2c_start(struct mpc_i2c *i2c)
402 {
403 /* Clear arbitration */
404 writeb(0, i2c->base + MPC_I2C_SR);
405 /* Start with MEN */
406 writeccr(i2c, CCR_MEN);
407 }
408
409 static void mpc_i2c_stop(struct mpc_i2c *i2c)
410 {
411 writeccr(i2c, CCR_MEN);
412 }
413
414 static int mpc_write(struct mpc_i2c *i2c, int target,
415 const u8 *data, int length, int restart)
416 {
417 int i, result;
418 unsigned timeout = i2c->adap.timeout;
419 u32 flags = restart ? CCR_RSTA : 0;
420
421 /* Start as master */
422 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
423 /* Write target byte */
424 writeb((target << 1), i2c->base + MPC_I2C_DR);
425
426 result = i2c_wait(i2c, timeout, 1);
427 if (result < 0)
428 return result;
429
430 for (i = 0; i < length; i++) {
431 /* Write data byte */
432 writeb(data[i], i2c->base + MPC_I2C_DR);
433
434 result = i2c_wait(i2c, timeout, 1);
435 if (result < 0)
436 return result;
437 }
438
439 return 0;
440 }
441
442 static int mpc_read(struct mpc_i2c *i2c, int target,
443 u8 *data, int length, int restart)
444 {
445 unsigned timeout = i2c->adap.timeout;
446 int i, result;
447 u32 flags = restart ? CCR_RSTA : 0;
448
449 /* Switch to read - restart */
450 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
451 /* Write target address byte - this time with the read flag set */
452 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
453
454 result = i2c_wait(i2c, timeout, 1);
455 if (result < 0)
456 return result;
457
458 if (length) {
459 if (length == 1)
460 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
461 else
462 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
463 /* Dummy read */
464 readb(i2c->base + MPC_I2C_DR);
465 }
466
467 for (i = 0; i < length; i++) {
468 result = i2c_wait(i2c, timeout, 0);
469 if (result < 0)
470 return result;
471
472 /* Generate txack on next to last byte */
473 if (i == length - 2)
474 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
475 /* Do not generate stop on last byte */
476 if (i == length - 1)
477 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX);
478 data[i] = readb(i2c->base + MPC_I2C_DR);
479 }
480
481 return length;
482 }
483
484 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
485 {
486 struct i2c_msg *pmsg;
487 int i;
488 int ret = 0;
489 unsigned long orig_jiffies = jiffies;
490 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
491
492 mpc_i2c_start(i2c);
493
494 /* Allow bus up to 1s to become not busy */
495 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
496 if (signal_pending(current)) {
497 dev_dbg(i2c->dev, "Interrupted\n");
498 writeccr(i2c, 0);
499 return -EINTR;
500 }
501 if (time_after(jiffies, orig_jiffies + HZ)) {
502 dev_dbg(i2c->dev, "timeout\n");
503 if (readb(i2c->base + MPC_I2C_SR) ==
504 (CSR_MCF | CSR_MBB | CSR_RXAK))
505 mpc_i2c_fixup(i2c);
506 return -EIO;
507 }
508 schedule();
509 }
510
511 for (i = 0; ret >= 0 && i < num; i++) {
512 pmsg = &msgs[i];
513 dev_dbg(i2c->dev,
514 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
515 pmsg->flags & I2C_M_RD ? "read" : "write",
516 pmsg->len, pmsg->addr, i + 1, num);
517 if (pmsg->flags & I2C_M_RD)
518 ret =
519 mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
520 else
521 ret =
522 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
523 }
524 mpc_i2c_stop(i2c);
525 return (ret < 0) ? ret : num;
526 }
527
528 static u32 mpc_functionality(struct i2c_adapter *adap)
529 {
530 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
531 }
532
533 static const struct i2c_algorithm mpc_algo = {
534 .master_xfer = mpc_xfer,
535 .functionality = mpc_functionality,
536 };
537
538 static struct i2c_adapter mpc_ops = {
539 .owner = THIS_MODULE,
540 .name = "MPC adapter",
541 .algo = &mpc_algo,
542 .timeout = HZ,
543 };
544
545 static int __devinit fsl_i2c_probe(struct of_device *op,
546 const struct of_device_id *match)
547 {
548 struct mpc_i2c *i2c;
549 const u32 *prop;
550 u32 clock = MPC_I2C_CLOCK_LEGACY;
551 int result = 0;
552 int plen;
553
554 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
555 if (!i2c)
556 return -ENOMEM;
557
558 i2c->dev = &op->dev; /* for debug and error output */
559
560 init_waitqueue_head(&i2c->queue);
561
562 i2c->base = of_iomap(op->node, 0);
563 if (!i2c->base) {
564 dev_err(i2c->dev, "failed to map controller\n");
565 result = -ENOMEM;
566 goto fail_map;
567 }
568
569 i2c->irq = irq_of_parse_and_map(op->node, 0);
570 if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
571 result = request_irq(i2c->irq, mpc_i2c_isr,
572 IRQF_SHARED, "i2c-mpc", i2c);
573 if (result < 0) {
574 dev_err(i2c->dev, "failed to attach interrupt\n");
575 goto fail_request;
576 }
577 }
578
579 if (of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
580 clock = MPC_I2C_CLOCK_PRESERVE;
581 } else {
582 prop = of_get_property(op->node, "clock-frequency", &plen);
583 if (prop && plen == sizeof(u32))
584 clock = *prop;
585 }
586
587 if (match->data) {
588 struct mpc_i2c_data *data = match->data;
589 data->setup(op->node, i2c, clock, data->prescaler);
590 } else {
591 /* Backwards compatibility */
592 if (of_get_property(op->node, "dfsrr", NULL))
593 mpc_i2c_setup_8xxx(op->node, i2c, clock, 0);
594 }
595
596 dev_set_drvdata(&op->dev, i2c);
597
598 i2c->adap = mpc_ops;
599 i2c_set_adapdata(&i2c->adap, i2c);
600 i2c->adap.dev.parent = &op->dev;
601
602 result = i2c_add_adapter(&i2c->adap);
603 if (result < 0) {
604 dev_err(i2c->dev, "failed to add adapter\n");
605 goto fail_add;
606 }
607 of_register_i2c_devices(&i2c->adap, op->node);
608
609 return result;
610
611 fail_add:
612 dev_set_drvdata(&op->dev, NULL);
613 free_irq(i2c->irq, i2c);
614 fail_request:
615 irq_dispose_mapping(i2c->irq);
616 iounmap(i2c->base);
617 fail_map:
618 kfree(i2c);
619 return result;
620 };
621
622 static int __devexit fsl_i2c_remove(struct of_device *op)
623 {
624 struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
625
626 i2c_del_adapter(&i2c->adap);
627 dev_set_drvdata(&op->dev, NULL);
628
629 if (i2c->irq != NO_IRQ)
630 free_irq(i2c->irq, i2c);
631
632 irq_dispose_mapping(i2c->irq);
633 iounmap(i2c->base);
634 kfree(i2c);
635 return 0;
636 };
637
638 static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = {
639 .setup = mpc_i2c_setup_512x,
640 };
641
642 static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = {
643 .setup = mpc_i2c_setup_52xx,
644 };
645
646 static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = {
647 .setup = mpc_i2c_setup_8xxx,
648 };
649
650 static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = {
651 .setup = mpc_i2c_setup_8xxx,
652 .prescaler = 2,
653 };
654
655 static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = {
656 .setup = mpc_i2c_setup_8xxx,
657 .prescaler = 3,
658 };
659
660 static const struct of_device_id mpc_i2c_of_match[] = {
661 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
662 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
663 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
664 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
665 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
666 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
667 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
668 /* Backward compatibility */
669 {.compatible = "fsl-i2c", },
670 {},
671 };
672 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
673
674 /* Structure for a device driver */
675 static struct of_platform_driver mpc_i2c_driver = {
676 .match_table = mpc_i2c_of_match,
677 .probe = fsl_i2c_probe,
678 .remove = __devexit_p(fsl_i2c_remove),
679 .driver = {
680 .owner = THIS_MODULE,
681 .name = DRV_NAME,
682 },
683 };
684
685 static int __init fsl_i2c_init(void)
686 {
687 int rv;
688
689 rv = of_register_platform_driver(&mpc_i2c_driver);
690 if (rv)
691 printk(KERN_ERR DRV_NAME
692 " of_register_platform_driver failed (%i)\n", rv);
693 return rv;
694 }
695
696 static void __exit fsl_i2c_exit(void)
697 {
698 of_unregister_platform_driver(&mpc_i2c_driver);
699 }
700
701 module_init(fsl_i2c_init);
702 module_exit(fsl_i2c_exit);
703
704 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
705 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
706 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
707 MODULE_LICENSE("GPL");
kernel-based virtual machine