drivers/usb/host/uhci-hcd.h

   1 #ifndef __LINUX_UHCI_HCD_H
   2 #define __LINUX_UHCI_HCD_H
   3
   4 #include <linux/list.h>
   5 #include <linux/usb.h>
   6
   7 #define usb_packetid(pipe)      (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
   8 #define PIPE_DEVEP_MASK         0x0007ff00
   9
  10 /*
  11  * Universal Host Controller Interface data structures and defines
  12  */
  13
  14 /* Command register */
  15 #define USBCMD          0
  16 #define   USBCMD_RS             0x0001  /* Run/Stop */
  17 #define   USBCMD_HCRESET        0x0002  /* Host reset */
  18 #define   USBCMD_GRESET         0x0004  /* Global reset */
  19 #define   USBCMD_EGSM           0x0008  /* Global Suspend Mode */
  20 #define   USBCMD_FGR            0x0010  /* Force Global Resume */
  21 #define   USBCMD_SWDBG          0x0020  /* SW Debug mode */
  22 #define   USBCMD_CF             0x0040  /* Config Flag (sw only) */
  23 #define   USBCMD_MAXP           0x0080  /* Max Packet (0 = 32, 1 = 64) */
  24
  25 /* Status register */
  26 #define USBSTS          2
  27 #define   USBSTS_USBINT         0x0001  /* Interrupt due to IOC */
  28 #define   USBSTS_ERROR          0x0002  /* Interrupt due to error */
  29 #define   USBSTS_RD             0x0004  /* Resume Detect */
  30 #define   USBSTS_HSE            0x0008  /* Host System Error - basically PCI problems */
  31 #define   USBSTS_HCPE           0x0010  /* Host Controller Process Error - the scripts were buggy */
  32 #define   USBSTS_HCH            0x0020  /* HC Halted */
  33
  34 /* Interrupt enable register */
  35 #define USBINTR         4
  36 #define   USBINTR_TIMEOUT       0x0001  /* Timeout/CRC error enable */
  37 #define   USBINTR_RESUME        0x0002  /* Resume interrupt enable */
  38 #define   USBINTR_IOC           0x0004  /* Interrupt On Complete enable */
  39 #define   USBINTR_SP            0x0008  /* Short packet interrupt enable */
  40
  41 #define USBFRNUM        6
  42 #define USBFLBASEADD    8
  43 #define USBSOF          12
  44 #define   USBSOF_DEFAULT        64      /* Frame length is exactly 1 ms */
  45
  46 /* USB port status and control registers */
  47 #define USBPORTSC1      16
  48 #define USBPORTSC2      18
  49 #define   USBPORTSC_CCS         0x0001  /* Current Connect Status ("device present") */
  50 #define   USBPORTSC_CSC         0x0002  /* Connect Status Change */
  51 #define   USBPORTSC_PE          0x0004  /* Port Enable */
  52 #define   USBPORTSC_PEC         0x0008  /* Port Enable Change */
  53 #define   USBPORTSC_DPLUS       0x0010  /* D+ high (line status) */
  54 #define   USBPORTSC_DMINUS      0x0020  /* D- high (line status) */
  55 #define   USBPORTSC_RD          0x0040  /* Resume Detect */
  56 #define   USBPORTSC_RES1        0x0080  /* reserved, always 1 */
  57 #define   USBPORTSC_LSDA        0x0100  /* Low Speed Device Attached */
  58 #define   USBPORTSC_PR          0x0200  /* Port Reset */
  59 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
  60 #define   USBPORTSC_OC          0x0400  /* Over Current condition */
  61 #define   USBPORTSC_OCC         0x0800  /* Over Current Change R/WC */
  62 #define   USBPORTSC_SUSP        0x1000  /* Suspend */
  63 #define   USBPORTSC_RES2        0x2000  /* reserved, write zeroes */
  64 #define   USBPORTSC_RES3        0x4000  /* reserved, write zeroes */
  65 #define   USBPORTSC_RES4        0x8000  /* reserved, write zeroes */
  66
  67 /* Legacy support register */
  68 #define USBLEGSUP               0xc0
  69 #define   USBLEGSUP_DEFAULT     0x2000  /* only PIRQ enable set */
  70 #define   USBLEGSUP_RWC         0x8f00  /* the R/WC bits */
  71 #define   USBLEGSUP_RO          0x5040  /* R/O and reserved bits */
  72
  73 #define UHCI_NULL_DATA_SIZE     0x7FF   /* for UHCI controller TD */
  74
  75 #define UHCI_PTR_BITS           cpu_to_le32(0x000F)
  76 #define UHCI_PTR_TERM           cpu_to_le32(0x0001)
  77 #define UHCI_PTR_QH             cpu_to_le32(0x0002)
  78 #define UHCI_PTR_DEPTH          cpu_to_le32(0x0004)
  79 #define UHCI_PTR_BREADTH        cpu_to_le32(0x0000)
  80
  81 #define UHCI_NUMFRAMES          1024    /* in the frame list [array] */
  82 #define UHCI_MAX_SOF_NUMBER     2047    /* in an SOF packet */
  83 #define CAN_SCHEDULE_FRAMES     1000    /* how far future frames can be scheduled */
  84
  85 struct uhci_frame_list {
  86         __le32 frame[UHCI_NUMFRAMES];
  87
  88         void *frame_cpu[UHCI_NUMFRAMES];
  89
  90         dma_addr_t dma_handle;
  91 };
  92
  93 struct urb_priv;
  94
  95 /*
  96  * One role of a QH is to hold a queue of TDs for some endpoint.  Each QH is
  97  * used with one URB, and qh->element (updated by the HC) is either:
  98  *   - the next unprocessed TD for the URB, or
  99  *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint), or
 100  *   - the QH for the next URB queued to the same endpoint.
 101  *
 102  * The other role of a QH is to serve as a "skeleton" framelist entry, so we
 103  * can easily splice a QH for some endpoint into the schedule at the right
 104  * place.  Then qh->element is UHCI_PTR_TERM.
 105  *
 106  * In the frame list, qh->link maintains a list of QHs seen by the HC:
 107  *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
 108  */
 109 struct uhci_qh {
 110         /* Hardware fields */
 111         __le32 link;                    /* Next queue */
 112         __le32 element;                 /* Queue element pointer */
 113
 114         /* Software fields */
 115         dma_addr_t dma_handle;
 116
 117         struct usb_device *dev;
 118         struct urb_priv *urbp;
 119
 120         struct list_head list;          /* P: uhci->frame_list_lock */
 121         struct list_head remove_list;   /* P: uhci->remove_list_lock */
 122 } __attribute__((aligned(16)));
 123
 124 /*
 125  * We need a special accessor for the element pointer because it is
 126  * subject to asynchronous updates by the controller
 127  */
 128 static __le32 inline qh_element(struct uhci_qh *qh) {
 129         __le32 element = qh->element;
 130
 131         barrier();
 132         return element;
 133 }
 134
 135 /*
 136  * for TD <status>:
 137  */
 138 #define TD_CTRL_SPD             (1 << 29)       /* Short Packet Detect */
 139 #define TD_CTRL_C_ERR_MASK      (3 << 27)       /* Error Counter bits */
 140 #define TD_CTRL_C_ERR_SHIFT     27
 141 #define TD_CTRL_LS              (1 << 26)       /* Low Speed Device */
 142 #define TD_CTRL_IOS             (1 << 25)       /* Isochronous Select */
 143 #define TD_CTRL_IOC             (1 << 24)       /* Interrupt on Complete */
 144 #define TD_CTRL_ACTIVE          (1 << 23)       /* TD Active */
 145 #define TD_CTRL_STALLED         (1 << 22)       /* TD Stalled */
 146 #define TD_CTRL_DBUFERR         (1 << 21)       /* Data Buffer Error */
 147 #define TD_CTRL_BABBLE          (1 << 20)       /* Babble Detected */
 148 #define TD_CTRL_NAK             (1 << 19)       /* NAK Received */
 149 #define TD_CTRL_CRCTIMEO        (1 << 18)       /* CRC/Time Out Error */
 150 #define TD_CTRL_BITSTUFF        (1 << 17)       /* Bit Stuff Error */
 151 #define TD_CTRL_ACTLEN_MASK     0x7FF   /* actual length, encoded as n - 1 */
 152
 153 #define TD_CTRL_ANY_ERROR       (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
 154                                  TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
 155
 156 #define uhci_maxerr(err)                ((err) << TD_CTRL_C_ERR_SHIFT)
 157 #define uhci_status_bits(ctrl_sts)      ((ctrl_sts) & 0xF60000)
 158 #define uhci_actual_length(ctrl_sts)    (((ctrl_sts) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */
 159
 160 /*
 161  * for TD <info>: (a.k.a. Token)
 162  */
 163 #define td_token(td)            le32_to_cpu((td)->token)
 164 #define TD_TOKEN_DEVADDR_SHIFT  8
 165 #define TD_TOKEN_TOGGLE_SHIFT   19
 166 #define TD_TOKEN_TOGGLE         (1 << 19)
 167 #define TD_TOKEN_EXPLEN_SHIFT   21
 168 #define TD_TOKEN_EXPLEN_MASK    0x7FF           /* expected length, encoded as n - 1 */
 169 #define TD_TOKEN_PID_MASK       0xFF
 170
 171 #define uhci_explen(len)        ((len) << TD_TOKEN_EXPLEN_SHIFT)
 172
 173 #define uhci_expected_length(token) ((((token) >> 21) + 1) & TD_TOKEN_EXPLEN_MASK)
 174 #define uhci_toggle(token)      (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
 175 #define uhci_endpoint(token)    (((token) >> 15) & 0xf)
 176 #define uhci_devaddr(token)     (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
 177 #define uhci_devep(token)       (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
 178 #define uhci_packetid(token)    ((token) & TD_TOKEN_PID_MASK)
 179 #define uhci_packetout(token)   (uhci_packetid(token) != USB_PID_IN)
 180 #define uhci_packetin(token)    (uhci_packetid(token) == USB_PID_IN)
 181
 182 /*
 183  * The documentation says "4 words for hardware, 4 words for software".
 184  *
 185  * That's silly, the hardware doesn't care. The hardware only cares that
 186  * the hardware words are 16-byte aligned, and we can have any amount of
 187  * sw space after the TD entry as far as I can tell.
 188  *
 189  * But let's just go with the documentation, at least for 32-bit machines.
 190  * On 64-bit machines we probably want to take advantage of the fact that
 191  * hw doesn't really care about the size of the sw-only area.
 192  *
 193  * Alas, not anymore, we have more than 4 words for software, woops.
 194  * Everything still works tho, surprise! -jerdfelt
 195  *
 196  * td->link points to either another TD (not necessarily for the same urb or
 197  * even the same endpoint), or nothing (PTR_TERM), or a QH (for queued urbs)
 198  */
 199 struct uhci_td {
 200         /* Hardware fields */
 201         __le32 link;
 202         __le32 status;
 203         __le32 token;
 204         __le32 buffer;
 205
 206         /* Software fields */
 207         dma_addr_t dma_handle;
 208
 209         struct usb_device *dev;
 210         struct urb *urb;
 211
 212         struct list_head list;          /* P: urb->lock */
 213         struct list_head remove_list;   /* P: uhci->td_remove_list_lock */
 214
 215         int frame;                      /* for iso: what frame? */
 216         struct list_head fl_list;       /* P: uhci->frame_list_lock */
 217 } __attribute__((aligned(16)));
 218
 219 /*
 220  * We need a special accessor for the control/status word because it is
 221  * subject to asynchronous updates by the controller
 222  */
 223 static u32 inline td_status(struct uhci_td *td) {
 224         __le32 status = td->status;
 225
 226         barrier();
 227         return le32_to_cpu(status);
 228 }
 229
 230
 231 /*
 232  * The UHCI driver places Interrupt, Control and Bulk into QH's both
 233  * to group together TD's for one transfer, and also to faciliate queuing
 234  * of URB's. To make it easy to insert entries into the schedule, we have
 235  * a skeleton of QH's for each predefined Interrupt latency, low-speed
 236  * control, full-speed control and terminating QH (see explanation for
 237  * the terminating QH below).
 238  *
 239  * When we want to add a new QH, we add it to the end of the list for the
 240  * skeleton QH.
 241  *
 242  * For instance, the queue can look like this:
 243  *
 244  * skel int128 QH
 245  * dev 1 interrupt QH
 246  * dev 5 interrupt QH
 247  * skel int64 QH
 248  * skel int32 QH
 249  * ...
 250  * skel int1 QH
 251  * skel low-speed control QH
 252  * dev 5 control QH
 253  * skel full-speed control QH
 254  * skel bulk QH
 255  * dev 1 bulk QH
 256  * dev 2 bulk QH
 257  * skel terminating QH
 258  *
 259  * The terminating QH is used for 2 reasons:
 260  * - To place a terminating TD which is used to workaround a PIIX bug
 261  *   (see Intel errata for explanation)
 262  * - To loop back to the full-speed control queue for full-speed bandwidth
 263  *   reclamation
 264  *
 265  * Isochronous transfers are stored before the start of the skeleton
 266  * schedule and don't use QH's. While the UHCI spec doesn't forbid the
 267  * use of QH's for Isochronous, it doesn't use them either. Since we don't
 268  * need to use them either, we follow the spec diagrams in hope that it'll
 269  * be more compatible with future UHCI implementations.
 270  */
 271
 272 #define UHCI_NUM_SKELQH         12
 273 #define skel_int128_qh          skelqh[0]
 274 #define skel_int64_qh           skelqh[1]
 275 #define skel_int32_qh           skelqh[2]
 276 #define skel_int16_qh           skelqh[3]
 277 #define skel_int8_qh            skelqh[4]
 278 #define skel_int4_qh            skelqh[5]
 279 #define skel_int2_qh            skelqh[6]
 280 #define skel_int1_qh            skelqh[7]
 281 #define skel_ls_control_qh      skelqh[8]
 282 #define skel_fs_control_qh      skelqh[9]
 283 #define skel_bulk_qh            skelqh[10]
 284 #define skel_term_qh            skelqh[11]
 285
 286 /*
 287  * Search tree for determining where <interval> fits in the skelqh[]
 288  * skeleton.
 289  *
 290  * An interrupt request should be placed into the slowest skelqh[]
 291  * which meets the interval/period/frequency requirement.
 292  * An interrupt request is allowed to be faster than <interval> but not slower.
 293  *
 294  * For a given <interval>, this function returns the appropriate/matching
 295  * skelqh[] index value.
 296  */
 297 static inline int __interval_to_skel(int interval)
 298 {
 299         if (interval < 16) {
 300                 if (interval < 4) {
 301                         if (interval < 2)
 302                                 return 7;       /* int1 for 0-1 ms */
 303                         return 6;               /* int2 for 2-3 ms */
 304                 }
 305                 if (interval < 8)
 306                         return 5;               /* int4 for 4-7 ms */
 307                 return 4;                       /* int8 for 8-15 ms */
 308         }
 309         if (interval < 64) {
 310                 if (interval < 32)
 311                         return 3;               /* int16 for 16-31 ms */
 312                 return 2;                       /* int32 for 32-63 ms */
 313         }
 314         if (interval < 128)
 315                 return 1;                       /* int64 for 64-127 ms */
 316         return 0;                               /* int128 for 128-255 ms (Max.) */
 317 }
 318
 319 /*
 320  * States for the root hub.
 321  *
 322  * To prevent "bouncing" in the presence of electrical noise,
 323  * when there are no devices attached we delay for 1 second in the
 324  * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
 325  *
 326  * (Note that the AUTO_STOPPED state won't be necessary once the hub
 327  * driver learns to autosuspend.)
 328  */
 329 enum uhci_rh_state {
 330         /* In the following states the HC must be halted.
 331          * These two must come first */
 332         UHCI_RH_RESET,
 333         UHCI_RH_SUSPENDED,
 334
 335         UHCI_RH_AUTO_STOPPED,
 336         UHCI_RH_RESUMING,
 337
 338         /* In this state the HC changes from running to halted,
 339          * so it can legally appear either way. */
 340         UHCI_RH_SUSPENDING,
 341
 342         /* In the following states it's an error if the HC is halted.
 343          * These two must come last */
 344         UHCI_RH_RUNNING,                /* The normal state */
 345         UHCI_RH_RUNNING_NODEVS,         /* Running with no devices attached */
 346 };
 347
 348 /*
 349  * This describes the full uhci information.
 350  *
 351  * Note how the "proper" USB information is just
 352  * a subset of what the full implementation needs.
 353  */
 354 struct uhci_hcd {
 355
 356         /* debugfs */
 357         struct dentry *dentry;
 358
 359         /* Grabbed from PCI */
 360         unsigned long io_addr;
 361
 362         struct dma_pool *qh_pool;
 363         struct dma_pool *td_pool;
 364
 365         struct usb_bus *bus;
 366
 367         struct uhci_td *term_td;        /* Terminating TD, see UHCI bug */
 368         struct uhci_qh *skelqh[UHCI_NUM_SKELQH];        /* Skeleton QH's */
 369
 370         spinlock_t lock;
 371         struct uhci_frame_list *fl;             /* P: uhci->lock */
 372         int fsbr;                               /* Full-speed bandwidth reclamation */
 373         unsigned long fsbrtimeout;              /* FSBR delay */
 374
 375         enum uhci_rh_state rh_state;
 376         unsigned long auto_stop_time;           /* When to AUTO_STOP */
 377
 378         unsigned int frame_number;              /* As of last check */
 379         unsigned int is_stopped;
 380 #define UHCI_IS_STOPPED         9999            /* Larger than a frame # */
 381
 382         unsigned int scan_in_progress:1;        /* Schedule scan is running */
 383         unsigned int need_rescan:1;             /* Redo the schedule scan */
 384         unsigned int hc_inaccessible:1;         /* HC is suspended or dead */
 385
 386         /* Support for port suspend/resume/reset */
 387         unsigned long port_c_suspend;           /* Bit-arrays of ports */
 388         unsigned long suspended_ports;
 389         unsigned long resuming_ports;
 390         unsigned long ports_timeout;            /* Time to stop signalling */
 391
 392         /* Main list of URB's currently controlled by this HC */
 393         struct list_head urb_list;              /* P: uhci->lock */
 394
 395         /* List of QH's that are done, but waiting to be unlinked (race) */
 396         struct list_head qh_remove_list;        /* P: uhci->lock */
 397         unsigned int qh_remove_age;             /* Age in frames */
 398
 399         /* List of TD's that are done, but waiting to be freed (race) */
 400         struct list_head td_remove_list;        /* P: uhci->lock */
 401         unsigned int td_remove_age;             /* Age in frames */
 402
 403         /* List of asynchronously unlinked URB's */
 404         struct list_head urb_remove_list;       /* P: uhci->lock */
 405         unsigned int urb_remove_age;            /* Age in frames */
 406
 407         /* List of URB's awaiting completion callback */
 408         struct list_head complete_list;         /* P: uhci->lock */
 409
 410         int rh_numports;
 411
 412         struct timer_list stall_timer;
 413
 414         wait_queue_head_t waitqh;               /* endpoint_disable waiters */
 415 };
 416
 417 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
 418 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
 419 {
 420         return (struct uhci_hcd *) (hcd->hcd_priv);
 421 }
 422 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
 423 {
 424         return container_of((void *) uhci, struct usb_hcd, hcd_priv);
 425 }
 426
 427 #define uhci_dev(u)     (uhci_to_hcd(u)->self.controller)
 428
 429 struct urb_priv {
 430         struct list_head urb_list;
 431
 432         struct urb *urb;
 433
 434         struct uhci_qh *qh;             /* QH for this URB */
 435         struct list_head td_list;       /* P: urb->lock */
 436
 437         unsigned fsbr : 1;              /* URB turned on FSBR */
 438         unsigned fsbr_timeout : 1;      /* URB timed out on FSBR */
 439         unsigned queued : 1;            /* QH was queued (not linked in) */
 440         unsigned short_control_packet : 1;      /* If we get a short packet during */
 441                                                 /*  a control transfer, retrigger */
 442                                                 /*  the status phase */
 443
 444         unsigned long inserttime;       /* In jiffies */
 445         unsigned long fsbrtime;         /* In jiffies */
 446
 447         struct list_head queue_list;    /* P: uhci->frame_list_lock */
 448 };
 449
 450 /*
 451  * Locking in uhci.c
 452  *
 453  * Almost everything relating to the hardware schedule and processing
 454  * of URBs is protected by uhci->lock.  urb->status is protected by
 455  * urb->lock; that's the one exception.
 456  *
 457  * To prevent deadlocks, never lock uhci->lock while holding urb->lock.
 458  * The safe order of locking is:
 459  *
 460  * #1 uhci->lock
 461  * #2 urb->lock
 462  */
 463
 464
 465 /* Some special IDs */
 466
 467 #define PCI_VENDOR_ID_GENESYS           0x17a0
 468 #define PCI_DEVICE_ID_GL880S_UHCI       0x8083
 469 #define PCI_DEVICE_ID_GL880S_EHCI       0x8084
 470
 471 #endif