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usbnet cdc_subset: fix issues talking to PXA gadgets
[linux-2.6/kvm.git] / drivers / net / sky2.c
blob7681d28c53d7778a15c1795e786aaf72d875b79a
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.23"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING 128
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
77
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
167 return 0;
168
169 udelay(10);
170 }
171
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
173 return -ETIMEDOUT;
174
175 io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
178 }
179
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 {
182 int i;
183
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
197 udelay(10);
198 }
199
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 return -ETIMEDOUT;
202 io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
205 }
206
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 {
209 u16 v;
210 __gm_phy_read(hw, port, reg, &v);
211 return v;
212 }
213
214
215 static void sky2_power_on(struct sky2_hw *hw)
216 {
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 u32 reg;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
254
255 sky2_read32(hw, B2_GP_IO);
256 }
257 }
258
259 static void sky2_power_aux(struct sky2_hw *hw)
260 {
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
275 }
276
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
278 {
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
283
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292 }
293
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300 };
301
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
308 };
309
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316 };
317
318
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320 {
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
329 PHY_M_EC_MAC_S_MSK);
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
378 }
379
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
385
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401 }
402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
404 }
405
406 ctrl = PHY_CT_RESET;
407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
409 reg = 0;
410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
425
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
432
433 adv |= fiber_fc_adv[sky2->flow_mode];
434 }
435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
453 break;
454 }
455
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
461
462
463 reg |= gm_fc_disable[sky2->flow_mode];
464
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
470 }
471
472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
536
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
539 break;
540
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
566
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
569 }
570
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
584
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
596
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
600 }
601
602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
606
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612 }
613
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
618 {
619 u32 reg1;
620
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
624
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
627
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
636 }
637
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639 {
640 u32 reg1;
641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
670
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
689 }
690
691 /* Force a renegotiation */
692 static void sky2_phy_reinit(struct sky2_port *sky2)
693 {
694 spin_lock_bh(&sky2->phy_lock);
695 sky2_phy_init(sky2->hw, sky2->port);
696 spin_unlock_bh(&sky2->phy_lock);
697 }
698
699 /* Put device in state to listen for Wake On Lan */
700 static void sky2_wol_init(struct sky2_port *sky2)
701 {
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
759 reg1 |= PCI_Y2_PME_LEGACY;
760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765 }
766
767 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768 {
769 struct net_device *dev = hw->dev[port];
770
771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
777
778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
781
782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
792
793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
798 }
799 }
800
801 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802 {
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
805 u32 rx_reg;
806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
827
828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
831 spin_lock_bh(&sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(&sky2->phy_lock);
835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
864
865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
886 rx_reg |= GMF_RX_OVER_ON;
887
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
889
890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
897
898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
909
910 /* On chips without ram buffer, pause is controled by MAC level */
911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
914
915 sky2_set_tx_stfwd(hw, port);
916 }
917
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
925 }
926
927 /* Assign Ram Buffer allocation to queue */
928 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
929 {
930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
936
937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
944 u32 tp = space - space/4;
945
946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
952
953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
965 }
966
967 /* Setup Bus Memory Interface */
968 static void sky2_qset(struct sky2_hw *hw, u16 q)
969 {
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
974 }
975
976 /* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
979 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
980 u64 addr, u32 last)
981 {
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
990 }
991
992 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993 {
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
997 le->ctrl = 0;
998 return le;
999 }
1000
1001 static void tx_init(struct sky2_port *sky2)
1002 {
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1012 }
1013
1014 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016 {
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018 }
1019
1020 /* Update chip's next pointer */
1021 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1022 {
1023 /* Make sure write' to descriptors are complete before we tell hardware */
1024 wmb();
1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
1029 }
1030
1031
1032 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033 {
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1036 le->ctrl = 0;
1037 return le;
1038 }
1039
1040 /* Build description to hardware for one receive segment */
1041 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
1043 {
1044 struct sky2_rx_le *le;
1045
1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32(upper_32_bits(map));
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
1051
1052 le = sky2_next_rx(sky2);
1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
1055 le->opcode = op | HW_OWNER;
1056 }
1057
1058 /* Build description to hardware for one possibly fragmented skb */
1059 static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061 {
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068 }
1069
1070
1071 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1072 unsigned size)
1073 {
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
1089 return 0;
1090 }
1091
1092 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093 {
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104 }
1105
1106 /* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
1110 static void rx_set_checksum(struct sky2_port *sky2)
1111 {
1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
1113
1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
1117
1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1121 }
1122
1123 /*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133 static void sky2_rx_stop(struct sky2_port *sky2)
1134 {
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149 stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1154
1155 /* Reset the RAM Buffer receive queue */
1156 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
1157
1158 /* Reset Rx MAC FIFO */
1159 sky2_write8(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), GMF_RST_SET);
1160
1161 sky2_read8(hw, B0_CTST);
1162 }
1163
1164 /* Clean out receive buffer area, assumes receiver hardware stopped */
1165 static void sky2_rx_clean(struct sky2_port *sky2)
1166 {
1167 unsigned i;
1168
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
1170 for (i = 0; i < sky2->rx_pending; i++) {
1171 struct rx_ring_info *re = sky2->rx_ring + i;
1172
1173 if (re->skb) {
1174 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1175 kfree_skb(re->skb);
1176 re->skb = NULL;
1177 }
1178 }
1179 skb_queue_purge(&sky2->rx_recycle);
1180 }
1181
1182 /* Basic MII support */
1183 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1184 {
1185 struct mii_ioctl_data *data = if_mii(ifr);
1186 struct sky2_port *sky2 = netdev_priv(dev);
1187 struct sky2_hw *hw = sky2->hw;
1188 int err = -EOPNOTSUPP;
1189
1190 if (!netif_running(dev))
1191 return -ENODEV; /* Phy still in reset */
1192
1193 switch (cmd) {
1194 case SIOCGMIIPHY:
1195 data->phy_id = PHY_ADDR_MARV;
1196
1197 /* fallthru */
1198 case SIOCGMIIREG: {
1199 u16 val = 0;
1200
1201 spin_lock_bh(&sky2->phy_lock);
1202 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1203 spin_unlock_bh(&sky2->phy_lock);
1204
1205 data->val_out = val;
1206 break;
1207 }
1208
1209 case SIOCSMIIREG:
1210 if (!capable(CAP_NET_ADMIN))
1211 return -EPERM;
1212
1213 spin_lock_bh(&sky2->phy_lock);
1214 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1215 data->val_in);
1216 spin_unlock_bh(&sky2->phy_lock);
1217 break;
1218 }
1219 return err;
1220 }
1221
1222 #ifdef SKY2_VLAN_TAG_USED
1223 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1224 {
1225 if (onoff) {
1226 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1227 RX_VLAN_STRIP_ON);
1228 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1229 TX_VLAN_TAG_ON);
1230 } else {
1231 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1232 RX_VLAN_STRIP_OFF);
1233 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1234 TX_VLAN_TAG_OFF);
1235 }
1236 }
1237
1238 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1239 {
1240 struct sky2_port *sky2 = netdev_priv(dev);
1241 struct sky2_hw *hw = sky2->hw;
1242 u16 port = sky2->port;
1243
1244 netif_tx_lock_bh(dev);
1245 napi_disable(&hw->napi);
1246
1247 sky2->vlgrp = grp;
1248 sky2_set_vlan_mode(hw, port, grp != NULL);
1249
1250 sky2_read32(hw, B0_Y2_SP_LISR);
1251 napi_enable(&hw->napi);
1252 netif_tx_unlock_bh(dev);
1253 }
1254 #endif
1255
1256 /* Amount of required worst case padding in rx buffer */
1257 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1258 {
1259 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1260 }
1261
1262 /*
1263 * Allocate an skb for receiving. If the MTU is large enough
1264 * make the skb non-linear with a fragment list of pages.
1265 */
1266 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1267 {
1268 struct sk_buff *skb;
1269 int i;
1270
1271 skb = __skb_dequeue(&sky2->rx_recycle);
1272 if (!skb)
1273 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1274 + sky2_rx_pad(sky2->hw));
1275 if (!skb)
1276 goto nomem;
1277
1278 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1279 unsigned char *start;
1280 /*
1281 * Workaround for a bug in FIFO that cause hang
1282 * if the FIFO if the receive buffer is not 64 byte aligned.
1283 * The buffer returned from netdev_alloc_skb is
1284 * aligned except if slab debugging is enabled.
1285 */
1286 start = PTR_ALIGN(skb->data, 8);
1287 skb_reserve(skb, start - skb->data);
1288 } else
1289 skb_reserve(skb, NET_IP_ALIGN);
1290
1291 for (i = 0; i < sky2->rx_nfrags; i++) {
1292 struct page *page = alloc_page(GFP_ATOMIC);
1293
1294 if (!page)
1295 goto free_partial;
1296 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1297 }
1298
1299 return skb;
1300 free_partial:
1301 kfree_skb(skb);
1302 nomem:
1303 return NULL;
1304 }
1305
1306 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1307 {
1308 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1309 }
1310
1311 /*
1312 * Allocate and setup receiver buffer pool.
1313 * Normal case this ends up creating one list element for skb
1314 * in the receive ring. Worst case if using large MTU and each
1315 * allocation falls on a different 64 bit region, that results
1316 * in 6 list elements per ring entry.
1317 * One element is used for checksum enable/disable, and one
1318 * extra to avoid wrap.
1319 */
1320 static int sky2_rx_start(struct sky2_port *sky2)
1321 {
1322 struct sky2_hw *hw = sky2->hw;
1323 struct rx_ring_info *re;
1324 unsigned rxq = rxqaddr[sky2->port];
1325 unsigned i, size, thresh;
1326
1327 sky2->rx_put = sky2->rx_next = 0;
1328 sky2_qset(hw, rxq);
1329
1330 /* On PCI express lowering the watermark gives better performance */
1331 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1332 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1333
1334 /* These chips have no ram buffer?
1335 * MAC Rx RAM Read is controlled by hardware */
1336 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1337 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1338 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1339 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1340
1341 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1342
1343 if (!(hw->flags & SKY2_HW_NEW_LE))
1344 rx_set_checksum(sky2);
1345
1346 /* Space needed for frame data + headers rounded up */
1347 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1348
1349 /* Stopping point for hardware truncation */
1350 thresh = (size - 8) / sizeof(u32);
1351
1352 sky2->rx_nfrags = size >> PAGE_SHIFT;
1353 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1354
1355 /* Compute residue after pages */
1356 size -= sky2->rx_nfrags << PAGE_SHIFT;
1357
1358 /* Optimize to handle small packets and headers */
1359 if (size < copybreak)
1360 size = copybreak;
1361 if (size < ETH_HLEN)
1362 size = ETH_HLEN;
1363
1364 sky2->rx_data_size = size;
1365
1366 skb_queue_head_init(&sky2->rx_recycle);
1367
1368 /* Fill Rx ring */
1369 for (i = 0; i < sky2->rx_pending; i++) {
1370 re = sky2->rx_ring + i;
1371
1372 re->skb = sky2_rx_alloc(sky2);
1373 if (!re->skb)
1374 goto nomem;
1375
1376 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1377 dev_kfree_skb(re->skb);
1378 re->skb = NULL;
1379 goto nomem;
1380 }
1381
1382 sky2_rx_submit(sky2, re);
1383 }
1384
1385 /*
1386 * The receiver hangs if it receives frames larger than the
1387 * packet buffer. As a workaround, truncate oversize frames, but
1388 * the register is limited to 9 bits, so if you do frames > 2052
1389 * you better get the MTU right!
1390 */
1391 if (thresh > 0x1ff)
1392 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1393 else {
1394 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1395 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1396 }
1397
1398 /* Tell chip about available buffers */
1399 sky2_rx_update(sky2, rxq);
1400 return 0;
1401 nomem:
1402 sky2_rx_clean(sky2);
1403 return -ENOMEM;
1404 }
1405
1406 /* Bring up network interface. */
1407 static int sky2_up(struct net_device *dev)
1408 {
1409 struct sky2_port *sky2 = netdev_priv(dev);
1410 struct sky2_hw *hw = sky2->hw;
1411 unsigned port = sky2->port;
1412 u32 imask, ramsize;
1413 int cap, err = -ENOMEM;
1414 struct net_device *otherdev = hw->dev[sky2->port^1];
1415
1416 /*
1417 * On dual port PCI-X card, there is an problem where status
1418 * can be received out of order due to split transactions
1419 */
1420 if (otherdev && netif_running(otherdev) &&
1421 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1422 u16 cmd;
1423
1424 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1425 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1426 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1427
1428 }
1429
1430 netif_carrier_off(dev);
1431
1432 /* must be power of 2 */
1433 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1434 TX_RING_SIZE *
1435 sizeof(struct sky2_tx_le),
1436 &sky2->tx_le_map);
1437 if (!sky2->tx_le)
1438 goto err_out;
1439
1440 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1441 GFP_KERNEL);
1442 if (!sky2->tx_ring)
1443 goto err_out;
1444
1445 tx_init(sky2);
1446
1447 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1448 &sky2->rx_le_map);
1449 if (!sky2->rx_le)
1450 goto err_out;
1451 memset(sky2->rx_le, 0, RX_LE_BYTES);
1452
1453 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1454 GFP_KERNEL);
1455 if (!sky2->rx_ring)
1456 goto err_out;
1457
1458 sky2_mac_init(hw, port);
1459
1460 /* Register is number of 4K blocks on internal RAM buffer. */
1461 ramsize = sky2_read8(hw, B2_E_0) * 4;
1462 if (ramsize > 0) {
1463 u32 rxspace;
1464
1465 hw->flags |= SKY2_HW_RAM_BUFFER;
1466 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1467 if (ramsize < 16)
1468 rxspace = ramsize / 2;
1469 else
1470 rxspace = 8 + (2*(ramsize - 16))/3;
1471
1472 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1473 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1474
1475 /* Make sure SyncQ is disabled */
1476 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1477 RB_RST_SET);
1478 }
1479
1480 sky2_qset(hw, txqaddr[port]);
1481
1482 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1483 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1484 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1485
1486 /* Set almost empty threshold */
1487 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1488 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1489 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1490
1491 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1492 TX_RING_SIZE - 1);
1493
1494 #ifdef SKY2_VLAN_TAG_USED
1495 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1496 #endif
1497
1498 err = sky2_rx_start(sky2);
1499 if (err)
1500 goto err_out;
1501
1502 /* Enable interrupts from phy/mac for port */
1503 imask = sky2_read32(hw, B0_IMSK);
1504 imask |= portirq_msk[port];
1505 sky2_write32(hw, B0_IMSK, imask);
1506 sky2_read32(hw, B0_IMSK);
1507
1508 sky2_set_multicast(dev);
1509
1510 if (netif_msg_ifup(sky2))
1511 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1512 return 0;
1513
1514 err_out:
1515 if (sky2->rx_le) {
1516 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1517 sky2->rx_le, sky2->rx_le_map);
1518 sky2->rx_le = NULL;
1519 }
1520 if (sky2->tx_le) {
1521 pci_free_consistent(hw->pdev,
1522 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1523 sky2->tx_le, sky2->tx_le_map);
1524 sky2->tx_le = NULL;
1525 }
1526 kfree(sky2->tx_ring);
1527 kfree(sky2->rx_ring);
1528
1529 sky2->tx_ring = NULL;
1530 sky2->rx_ring = NULL;
1531 return err;
1532 }
1533
1534 /* Modular subtraction in ring */
1535 static inline int tx_dist(unsigned tail, unsigned head)
1536 {
1537 return (head - tail) & (TX_RING_SIZE - 1);
1538 }
1539
1540 /* Number of list elements available for next tx */
1541 static inline int tx_avail(const struct sky2_port *sky2)
1542 {
1543 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1544 }
1545
1546 /* Estimate of number of transmit list elements required */
1547 static unsigned tx_le_req(const struct sk_buff *skb)
1548 {
1549 unsigned count;
1550
1551 count = sizeof(dma_addr_t) / sizeof(u32);
1552 count += skb_shinfo(skb)->nr_frags * count;
1553
1554 if (skb_is_gso(skb))
1555 ++count;
1556
1557 if (skb->ip_summed == CHECKSUM_PARTIAL)
1558 ++count;
1559
1560 return count;
1561 }
1562
1563 /*
1564 * Put one packet in ring for transmit.
1565 * A single packet can generate multiple list elements, and
1566 * the number of ring elements will probably be less than the number
1567 * of list elements used.
1568 */
1569 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1570 {
1571 struct sky2_port *sky2 = netdev_priv(dev);
1572 struct sky2_hw *hw = sky2->hw;
1573 struct sky2_tx_le *le = NULL;
1574 struct tx_ring_info *re;
1575 unsigned i, len, first_slot;
1576 dma_addr_t mapping;
1577 u16 mss;
1578 u8 ctrl;
1579
1580 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1581 return NETDEV_TX_BUSY;
1582
1583 len = skb_headlen(skb);
1584 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1585
1586 if (pci_dma_mapping_error(hw->pdev, mapping))
1587 goto mapping_error;
1588
1589 first_slot = sky2->tx_prod;
1590 if (unlikely(netif_msg_tx_queued(sky2)))
1591 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1592 dev->name, first_slot, skb->len);
1593
1594 /* Send high bits if needed */
1595 if (sizeof(dma_addr_t) > sizeof(u32)) {
1596 le = get_tx_le(sky2);
1597 le->addr = cpu_to_le32(upper_32_bits(mapping));
1598 le->opcode = OP_ADDR64 | HW_OWNER;
1599 }
1600
1601 /* Check for TCP Segmentation Offload */
1602 mss = skb_shinfo(skb)->gso_size;
1603 if (mss != 0) {
1604
1605 if (!(hw->flags & SKY2_HW_NEW_LE))
1606 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1607
1608 if (mss != sky2->tx_last_mss) {
1609 le = get_tx_le(sky2);
1610 le->addr = cpu_to_le32(mss);
1611
1612 if (hw->flags & SKY2_HW_NEW_LE)
1613 le->opcode = OP_MSS | HW_OWNER;
1614 else
1615 le->opcode = OP_LRGLEN | HW_OWNER;
1616 sky2->tx_last_mss = mss;
1617 }
1618 }
1619
1620 ctrl = 0;
1621 #ifdef SKY2_VLAN_TAG_USED
1622 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1623 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1624 if (!le) {
1625 le = get_tx_le(sky2);
1626 le->addr = 0;
1627 le->opcode = OP_VLAN|HW_OWNER;
1628 } else
1629 le->opcode |= OP_VLAN;
1630 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1631 ctrl |= INS_VLAN;
1632 }
1633 #endif
1634
1635 /* Handle TCP checksum offload */
1636 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1637 /* On Yukon EX (some versions) encoding change. */
1638 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1639 ctrl |= CALSUM; /* auto checksum */
1640 else {
1641 const unsigned offset = skb_transport_offset(skb);
1642 u32 tcpsum;
1643
1644 tcpsum = offset << 16; /* sum start */
1645 tcpsum |= offset + skb->csum_offset; /* sum write */
1646
1647 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1648 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1649 ctrl |= UDPTCP;
1650
1651 if (tcpsum != sky2->tx_tcpsum) {
1652 sky2->tx_tcpsum = tcpsum;
1653
1654 le = get_tx_le(sky2);
1655 le->addr = cpu_to_le32(tcpsum);
1656 le->length = 0; /* initial checksum value */
1657 le->ctrl = 1; /* one packet */
1658 le->opcode = OP_TCPLISW | HW_OWNER;
1659 }
1660 }
1661 }
1662
1663 le = get_tx_le(sky2);
1664 le->addr = cpu_to_le32((u32) mapping);
1665 le->length = cpu_to_le16(len);
1666 le->ctrl = ctrl;
1667 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1668
1669 re = tx_le_re(sky2, le);
1670 re->skb = skb;
1671 pci_unmap_addr_set(re, mapaddr, mapping);
1672 pci_unmap_len_set(re, maplen, len);
1673
1674 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1675 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1676
1677 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1678 frag->size, PCI_DMA_TODEVICE);
1679
1680 if (pci_dma_mapping_error(hw->pdev, mapping))
1681 goto mapping_unwind;
1682
1683 if (sizeof(dma_addr_t) > sizeof(u32)) {
1684 le = get_tx_le(sky2);
1685 le->addr = cpu_to_le32(upper_32_bits(mapping));
1686 le->ctrl = 0;
1687 le->opcode = OP_ADDR64 | HW_OWNER;
1688 }
1689
1690 le = get_tx_le(sky2);
1691 le->addr = cpu_to_le32((u32) mapping);
1692 le->length = cpu_to_le16(frag->size);
1693 le->ctrl = ctrl;
1694 le->opcode = OP_BUFFER | HW_OWNER;
1695
1696 re = tx_le_re(sky2, le);
1697 re->skb = skb;
1698 pci_unmap_addr_set(re, mapaddr, mapping);
1699 pci_unmap_len_set(re, maplen, frag->size);
1700 }
1701
1702 le->ctrl |= EOP;
1703
1704 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1705 netif_stop_queue(dev);
1706
1707 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1708
1709 return NETDEV_TX_OK;
1710
1711 mapping_unwind:
1712 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1713 le = sky2->tx_le + i;
1714 re = sky2->tx_ring + i;
1715
1716 switch(le->opcode & ~HW_OWNER) {
1717 case OP_LARGESEND:
1718 case OP_PACKET:
1719 pci_unmap_single(hw->pdev,
1720 pci_unmap_addr(re, mapaddr),
1721 pci_unmap_len(re, maplen),
1722 PCI_DMA_TODEVICE);
1723 break;
1724 case OP_BUFFER:
1725 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1726 pci_unmap_len(re, maplen),
1727 PCI_DMA_TODEVICE);
1728 break;
1729 }
1730 }
1731
1732 sky2->tx_prod = first_slot;
1733 mapping_error:
1734 if (net_ratelimit())
1735 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1736 dev_kfree_skb(skb);
1737 return NETDEV_TX_OK;
1738 }
1739
1740 /*
1741 * Free ring elements from starting at tx_cons until "done"
1742 *
1743 * NB: the hardware will tell us about partial completion of multi-part
1744 * buffers so make sure not to free skb to early.
1745 */
1746 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1747 {
1748 struct net_device *dev = sky2->netdev;
1749 struct pci_dev *pdev = sky2->hw->pdev;
1750 unsigned idx;
1751
1752 BUG_ON(done >= TX_RING_SIZE);
1753
1754 for (idx = sky2->tx_cons; idx != done;
1755 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1756 struct sky2_tx_le *le = sky2->tx_le + idx;
1757 struct tx_ring_info *re = sky2->tx_ring + idx;
1758
1759 switch(le->opcode & ~HW_OWNER) {
1760 case OP_LARGESEND:
1761 case OP_PACKET:
1762 pci_unmap_single(pdev,
1763 pci_unmap_addr(re, mapaddr),
1764 pci_unmap_len(re, maplen),
1765 PCI_DMA_TODEVICE);
1766 break;
1767 case OP_BUFFER:
1768 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1769 pci_unmap_len(re, maplen),
1770 PCI_DMA_TODEVICE);
1771 break;
1772 }
1773
1774 if (le->ctrl & EOP) {
1775 struct sk_buff *skb = re->skb;
1776
1777 if (unlikely(netif_msg_tx_done(sky2)))
1778 printk(KERN_DEBUG "%s: tx done %u\n",
1779 dev->name, idx);
1780
1781 dev->stats.tx_packets++;
1782 dev->stats.tx_bytes += skb->len;
1783
1784 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1785 && skb_recycle_check(skb, sky2->rx_data_size
1786 + sky2_rx_pad(sky2->hw)))
1787 __skb_queue_head(&sky2->rx_recycle, skb);
1788 else
1789 dev_kfree_skb_any(skb);
1790
1791 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1792 }
1793 }
1794
1795 sky2->tx_cons = idx;
1796 smp_mb();
1797
1798 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1799 netif_wake_queue(dev);
1800 }
1801
1802 /* Cleanup all untransmitted buffers, assume transmitter not running */
1803 static void sky2_tx_clean(struct net_device *dev)
1804 {
1805 struct sky2_port *sky2 = netdev_priv(dev);
1806
1807 netif_tx_lock_bh(dev);
1808 sky2_tx_complete(sky2, sky2->tx_prod);
1809 netif_tx_unlock_bh(dev);
1810 }
1811
1812 /* Network shutdown */
1813 static int sky2_down(struct net_device *dev)
1814 {
1815 struct sky2_port *sky2 = netdev_priv(dev);
1816 struct sky2_hw *hw = sky2->hw;
1817 unsigned port = sky2->port;
1818 u16 ctrl;
1819 u32 imask;
1820
1821 /* Never really got started! */
1822 if (!sky2->tx_le)
1823 return 0;
1824
1825 if (netif_msg_ifdown(sky2))
1826 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1827
1828 /* Disable port IRQ */
1829 imask = sky2_read32(hw, B0_IMSK);
1830 imask &= ~portirq_msk[port];
1831 sky2_write32(hw, B0_IMSK, imask);
1832 sky2_read32(hw, B0_IMSK);
1833
1834 /* Force flow control off */
1835 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1836
1837 /* Stop transmitter */
1838 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1839 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1840
1841 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1842 RB_RST_SET | RB_DIS_OP_MD);
1843
1844 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1845 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1846 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1847
1848 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1849
1850 /* Workaround shared GMAC reset */
1851 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1852 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1853 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1854
1855 /* Disable Force Sync bit and Enable Alloc bit */
1856 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1857 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1858
1859 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1860 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1861 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1862
1863 /* Reset the PCI FIFO of the async Tx queue */
1864 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1865 BMU_RST_SET | BMU_FIFO_RST);
1866
1867 /* Reset the Tx prefetch units */
1868 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1869 PREF_UNIT_RST_SET);
1870
1871 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1872
1873 sky2_rx_stop(sky2);
1874
1875 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1876 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1877
1878 /* Force any delayed status interrrupt and NAPI */
1879 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1880 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1881 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1882 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1883
1884 synchronize_irq(hw->pdev->irq);
1885 napi_synchronize(&hw->napi);
1886
1887 sky2_phy_power_down(hw, port);
1888
1889 /* turn off LED's */
1890 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1891
1892 sky2_tx_clean(dev);
1893 sky2_rx_clean(sky2);
1894
1895 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1896 sky2->rx_le, sky2->rx_le_map);
1897 kfree(sky2->rx_ring);
1898
1899 pci_free_consistent(hw->pdev,
1900 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1901 sky2->tx_le, sky2->tx_le_map);
1902 kfree(sky2->tx_ring);
1903
1904 sky2->tx_le = NULL;
1905 sky2->rx_le = NULL;
1906
1907 sky2->rx_ring = NULL;
1908 sky2->tx_ring = NULL;
1909
1910 return 0;
1911 }
1912
1913 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1914 {
1915 if (hw->flags & SKY2_HW_FIBRE_PHY)
1916 return SPEED_1000;
1917
1918 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1919 if (aux & PHY_M_PS_SPEED_100)
1920 return SPEED_100;
1921 else
1922 return SPEED_10;
1923 }
1924
1925 switch (aux & PHY_M_PS_SPEED_MSK) {
1926 case PHY_M_PS_SPEED_1000:
1927 return SPEED_1000;
1928 case PHY_M_PS_SPEED_100:
1929 return SPEED_100;
1930 default:
1931 return SPEED_10;
1932 }
1933 }
1934
1935 static void sky2_link_up(struct sky2_port *sky2)
1936 {
1937 struct sky2_hw *hw = sky2->hw;
1938 unsigned port = sky2->port;
1939 u16 reg;
1940 static const char *fc_name[] = {
1941 [FC_NONE] = "none",
1942 [FC_TX] = "tx",
1943 [FC_RX] = "rx",
1944 [FC_BOTH] = "both",
1945 };
1946
1947 /* enable Rx/Tx */
1948 reg = gma_read16(hw, port, GM_GP_CTRL);
1949 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1950 gma_write16(hw, port, GM_GP_CTRL, reg);
1951
1952 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1953
1954 netif_carrier_on(sky2->netdev);
1955
1956 mod_timer(&hw->watchdog_timer, jiffies + 1);
1957
1958 /* Turn on link LED */
1959 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1960 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1961
1962 if (netif_msg_link(sky2))
1963 printk(KERN_INFO PFX
1964 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1965 sky2->netdev->name, sky2->speed,
1966 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1967 fc_name[sky2->flow_status]);
1968 }
1969
1970 static void sky2_link_down(struct sky2_port *sky2)
1971 {
1972 struct sky2_hw *hw = sky2->hw;
1973 unsigned port = sky2->port;
1974 u16 reg;
1975
1976 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1977
1978 reg = gma_read16(hw, port, GM_GP_CTRL);
1979 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1980 gma_write16(hw, port, GM_GP_CTRL, reg);
1981
1982 netif_carrier_off(sky2->netdev);
1983
1984 /* Turn on link LED */
1985 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1986
1987 if (netif_msg_link(sky2))
1988 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1989
1990 sky2_phy_init(hw, port);
1991 }
1992
1993 static enum flow_control sky2_flow(int rx, int tx)
1994 {
1995 if (rx)
1996 return tx ? FC_BOTH : FC_RX;
1997 else
1998 return tx ? FC_TX : FC_NONE;
1999 }
2000
2001 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2002 {
2003 struct sky2_hw *hw = sky2->hw;
2004 unsigned port = sky2->port;
2005 u16 advert, lpa;
2006
2007 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2008 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2009 if (lpa & PHY_M_AN_RF) {
2010 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2011 return -1;
2012 }
2013
2014 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2015 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2016 sky2->netdev->name);
2017 return -1;
2018 }
2019
2020 sky2->speed = sky2_phy_speed(hw, aux);
2021 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2022
2023 /* Since the pause result bits seem to in different positions on
2024 * different chips. look at registers.
2025 */
2026 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2027 /* Shift for bits in fiber PHY */
2028 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2029 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2030
2031 if (advert & ADVERTISE_1000XPAUSE)
2032 advert |= ADVERTISE_PAUSE_CAP;
2033 if (advert & ADVERTISE_1000XPSE_ASYM)
2034 advert |= ADVERTISE_PAUSE_ASYM;
2035 if (lpa & LPA_1000XPAUSE)
2036 lpa |= LPA_PAUSE_CAP;
2037 if (lpa & LPA_1000XPAUSE_ASYM)
2038 lpa |= LPA_PAUSE_ASYM;
2039 }
2040
2041 sky2->flow_status = FC_NONE;
2042 if (advert & ADVERTISE_PAUSE_CAP) {
2043 if (lpa & LPA_PAUSE_CAP)
2044 sky2->flow_status = FC_BOTH;
2045 else if (advert & ADVERTISE_PAUSE_ASYM)
2046 sky2->flow_status = FC_RX;
2047 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2048 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2049 sky2->flow_status = FC_TX;
2050 }
2051
2052 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2053 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2054 sky2->flow_status = FC_NONE;
2055
2056 if (sky2->flow_status & FC_TX)
2057 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2058 else
2059 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2060
2061 return 0;
2062 }
2063
2064 /* Interrupt from PHY */
2065 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2066 {
2067 struct net_device *dev = hw->dev[port];
2068 struct sky2_port *sky2 = netdev_priv(dev);
2069 u16 istatus, phystat;
2070
2071 if (!netif_running(dev))
2072 return;
2073
2074 spin_lock(&sky2->phy_lock);
2075 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2076 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2077
2078 if (netif_msg_intr(sky2))
2079 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2080 sky2->netdev->name, istatus, phystat);
2081
2082 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2083 if (sky2_autoneg_done(sky2, phystat) == 0)
2084 sky2_link_up(sky2);
2085 goto out;
2086 }
2087
2088 if (istatus & PHY_M_IS_LSP_CHANGE)
2089 sky2->speed = sky2_phy_speed(hw, phystat);
2090
2091 if (istatus & PHY_M_IS_DUP_CHANGE)
2092 sky2->duplex =
2093 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2094
2095 if (istatus & PHY_M_IS_LST_CHANGE) {
2096 if (phystat & PHY_M_PS_LINK_UP)
2097 sky2_link_up(sky2);
2098 else
2099 sky2_link_down(sky2);
2100 }
2101 out:
2102 spin_unlock(&sky2->phy_lock);
2103 }
2104
2105 /* Transmit timeout is only called if we are running, carrier is up
2106 * and tx queue is full (stopped).
2107 */
2108 static void sky2_tx_timeout(struct net_device *dev)
2109 {
2110 struct sky2_port *sky2 = netdev_priv(dev);
2111 struct sky2_hw *hw = sky2->hw;
2112
2113 if (netif_msg_timer(sky2))
2114 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2115
2116 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2117 dev->name, sky2->tx_cons, sky2->tx_prod,
2118 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2119 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2120
2121 /* can't restart safely under softirq */
2122 schedule_work(&hw->restart_work);
2123 }
2124
2125 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2126 {
2127 struct sky2_port *sky2 = netdev_priv(dev);
2128 struct sky2_hw *hw = sky2->hw;
2129 unsigned port = sky2->port;
2130 int err;
2131 u16 ctl, mode;
2132 u32 imask;
2133
2134 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2135 return -EINVAL;
2136
2137 if (new_mtu > ETH_DATA_LEN &&
2138 (hw->chip_id == CHIP_ID_YUKON_FE ||
2139 hw->chip_id == CHIP_ID_YUKON_FE_P))
2140 return -EINVAL;
2141
2142 if (!netif_running(dev)) {
2143 dev->mtu = new_mtu;
2144 return 0;
2145 }
2146
2147 imask = sky2_read32(hw, B0_IMSK);
2148 sky2_write32(hw, B0_IMSK, 0);
2149
2150 dev->trans_start = jiffies; /* prevent tx timeout */
2151 netif_stop_queue(dev);
2152 napi_disable(&hw->napi);
2153
2154 synchronize_irq(hw->pdev->irq);
2155
2156 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2157 sky2_set_tx_stfwd(hw, port);
2158
2159 ctl = gma_read16(hw, port, GM_GP_CTRL);
2160 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2161 sky2_rx_stop(sky2);
2162 sky2_rx_clean(sky2);
2163
2164 dev->mtu = new_mtu;
2165
2166 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2167 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2168
2169 if (dev->mtu > ETH_DATA_LEN)
2170 mode |= GM_SMOD_JUMBO_ENA;
2171
2172 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2173
2174 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2175
2176 err = sky2_rx_start(sky2);
2177 sky2_write32(hw, B0_IMSK, imask);
2178
2179 sky2_read32(hw, B0_Y2_SP_LISR);
2180 napi_enable(&hw->napi);
2181
2182 if (err)
2183 dev_close(dev);
2184 else {
2185 gma_write16(hw, port, GM_GP_CTRL, ctl);
2186
2187 netif_wake_queue(dev);
2188 }
2189
2190 return err;
2191 }
2192
2193 /* For small just reuse existing skb for next receive */
2194 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2195 const struct rx_ring_info *re,
2196 unsigned length)
2197 {
2198 struct sk_buff *skb;
2199
2200 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2201 if (likely(skb)) {
2202 skb_reserve(skb, 2);
2203 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2204 length, PCI_DMA_FROMDEVICE);
2205 skb_copy_from_linear_data(re->skb, skb->data, length);
2206 skb->ip_summed = re->skb->ip_summed;
2207 skb->csum = re->skb->csum;
2208 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2209 length, PCI_DMA_FROMDEVICE);
2210 re->skb->ip_summed = CHECKSUM_NONE;
2211 skb_put(skb, length);
2212 }
2213 return skb;
2214 }
2215
2216 /* Adjust length of skb with fragments to match received data */
2217 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2218 unsigned int length)
2219 {
2220 int i, num_frags;
2221 unsigned int size;
2222
2223 /* put header into skb */
2224 size = min(length, hdr_space);
2225 skb->tail += size;
2226 skb->len += size;
2227 length -= size;
2228
2229 num_frags = skb_shinfo(skb)->nr_frags;
2230 for (i = 0; i < num_frags; i++) {
2231 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2232
2233 if (length == 0) {
2234 /* don't need this page */
2235 __free_page(frag->page);
2236 --skb_shinfo(skb)->nr_frags;
2237 } else {
2238 size = min(length, (unsigned) PAGE_SIZE);
2239
2240 frag->size = size;
2241 skb->data_len += size;
2242 skb->truesize += size;
2243 skb->len += size;
2244 length -= size;
2245 }
2246 }
2247 }
2248
2249 /* Normal packet - take skb from ring element and put in a new one */
2250 static struct sk_buff *receive_new(struct sky2_port *sky2,
2251 struct rx_ring_info *re,
2252 unsigned int length)
2253 {
2254 struct sk_buff *skb, *nskb;
2255 unsigned hdr_space = sky2->rx_data_size;
2256
2257 /* Don't be tricky about reusing pages (yet) */
2258 nskb = sky2_rx_alloc(sky2);
2259 if (unlikely(!nskb))
2260 return NULL;
2261
2262 skb = re->skb;
2263 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2264
2265 prefetch(skb->data);
2266 re->skb = nskb;
2267 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2268 dev_kfree_skb(nskb);
2269 re->skb = skb;
2270 return NULL;
2271 }
2272
2273 if (skb_shinfo(skb)->nr_frags)
2274 skb_put_frags(skb, hdr_space, length);
2275 else
2276 skb_put(skb, length);
2277 return skb;
2278 }
2279
2280 /*
2281 * Receive one packet.
2282 * For larger packets, get new buffer.
2283 */
2284 static struct sk_buff *sky2_receive(struct net_device *dev,
2285 u16 length, u32 status)
2286 {
2287 struct sky2_port *sky2 = netdev_priv(dev);
2288 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2289 struct sk_buff *skb = NULL;
2290 u16 count = (status & GMR_FS_LEN) >> 16;
2291
2292 #ifdef SKY2_VLAN_TAG_USED
2293 /* Account for vlan tag */
2294 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2295 count -= VLAN_HLEN;
2296 #endif
2297
2298 if (unlikely(netif_msg_rx_status(sky2)))
2299 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2300 dev->name, sky2->rx_next, status, length);
2301
2302 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2303 prefetch(sky2->rx_ring + sky2->rx_next);
2304
2305 /* This chip has hardware problems that generates bogus status.
2306 * So do only marginal checking and expect higher level protocols
2307 * to handle crap frames.
2308 */
2309 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2310 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2311 length != count)
2312 goto okay;
2313
2314 if (status & GMR_FS_ANY_ERR)
2315 goto error;
2316
2317 if (!(status & GMR_FS_RX_OK))
2318 goto resubmit;
2319
2320 /* if length reported by DMA does not match PHY, packet was truncated */
2321 if (length != count)
2322 goto len_error;
2323
2324 okay:
2325 if (length < copybreak)
2326 skb = receive_copy(sky2, re, length);
2327 else
2328 skb = receive_new(sky2, re, length);
2329 resubmit:
2330 sky2_rx_submit(sky2, re);
2331
2332 return skb;
2333
2334 len_error:
2335 /* Truncation of overlength packets
2336 causes PHY length to not match MAC length */
2337 ++dev->stats.rx_length_errors;
2338 if (netif_msg_rx_err(sky2) && net_ratelimit())
2339 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2340 dev->name, status, length);
2341 goto resubmit;
2342
2343 error:
2344 ++dev->stats.rx_errors;
2345 if (status & GMR_FS_RX_FF_OV) {
2346 dev->stats.rx_over_errors++;
2347 goto resubmit;
2348 }
2349
2350 if (netif_msg_rx_err(sky2) && net_ratelimit())
2351 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2352 dev->name, status, length);
2353
2354 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2355 dev->stats.rx_length_errors++;
2356 if (status & GMR_FS_FRAGMENT)
2357 dev->stats.rx_frame_errors++;
2358 if (status & GMR_FS_CRC_ERR)
2359 dev->stats.rx_crc_errors++;
2360
2361 goto resubmit;
2362 }
2363
2364 /* Transmit complete */
2365 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2366 {
2367 struct sky2_port *sky2 = netdev_priv(dev);
2368
2369 if (netif_running(dev)) {
2370 netif_tx_lock(dev);
2371 sky2_tx_complete(sky2, last);
2372 netif_tx_unlock(dev);
2373 }
2374 }
2375
2376 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2377 u32 status, struct sk_buff *skb)
2378 {
2379 #ifdef SKY2_VLAN_TAG_USED
2380 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2381 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2382 if (skb->ip_summed == CHECKSUM_NONE)
2383 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2384 else
2385 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2386 vlan_tag, skb);
2387 return;
2388 }
2389 #endif
2390 if (skb->ip_summed == CHECKSUM_NONE)
2391 netif_receive_skb(skb);
2392 else
2393 napi_gro_receive(&sky2->hw->napi, skb);
2394 }
2395
2396 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2397 unsigned packets, unsigned bytes)
2398 {
2399 if (packets) {
2400 struct net_device *dev = hw->dev[port];
2401
2402 dev->stats.rx_packets += packets;
2403 dev->stats.rx_bytes += bytes;
2404 dev->last_rx = jiffies;
2405 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2406 }
2407 }
2408
2409 /* Process status response ring */
2410 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2411 {
2412 int work_done = 0;
2413 unsigned int total_bytes[2] = { 0 };
2414 unsigned int total_packets[2] = { 0 };
2415
2416 rmb();
2417 do {
2418 struct sky2_port *sky2;
2419 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2420 unsigned port;
2421 struct net_device *dev;
2422 struct sk_buff *skb;
2423 u32 status;
2424 u16 length;
2425 u8 opcode = le->opcode;
2426
2427 if (!(opcode & HW_OWNER))
2428 break;
2429
2430 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2431
2432 port = le->css & CSS_LINK_BIT;
2433 dev = hw->dev[port];
2434 sky2 = netdev_priv(dev);
2435 length = le16_to_cpu(le->length);
2436 status = le32_to_cpu(le->status);
2437
2438 le->opcode = 0;
2439 switch (opcode & ~HW_OWNER) {
2440 case OP_RXSTAT:
2441 total_packets[port]++;
2442 total_bytes[port] += length;
2443 skb = sky2_receive(dev, length, status);
2444 if (unlikely(!skb)) {
2445 dev->stats.rx_dropped++;
2446 break;
2447 }
2448
2449 /* This chip reports checksum status differently */
2450 if (hw->flags & SKY2_HW_NEW_LE) {
2451 if (sky2->rx_csum &&
2452 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2453 (le->css & CSS_TCPUDPCSOK))
2454 skb->ip_summed = CHECKSUM_UNNECESSARY;
2455 else
2456 skb->ip_summed = CHECKSUM_NONE;
2457 }
2458
2459 skb->protocol = eth_type_trans(skb, dev);
2460
2461 sky2_skb_rx(sky2, status, skb);
2462
2463 /* Stop after net poll weight */
2464 if (++work_done >= to_do)
2465 goto exit_loop;
2466 break;
2467
2468 #ifdef SKY2_VLAN_TAG_USED
2469 case OP_RXVLAN:
2470 sky2->rx_tag = length;
2471 break;
2472
2473 case OP_RXCHKSVLAN:
2474 sky2->rx_tag = length;
2475 /* fall through */
2476 #endif
2477 case OP_RXCHKS:
2478 if (!sky2->rx_csum)
2479 break;
2480
2481 /* If this happens then driver assuming wrong format */
2482 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2483 if (net_ratelimit())
2484 printk(KERN_NOTICE "%s: unexpected"
2485 " checksum status\n",
2486 dev->name);
2487 break;
2488 }
2489
2490 /* Both checksum counters are programmed to start at
2491 * the same offset, so unless there is a problem they
2492 * should match. This failure is an early indication that
2493 * hardware receive checksumming won't work.
2494 */
2495 if (likely(status >> 16 == (status & 0xffff))) {
2496 skb = sky2->rx_ring[sky2->rx_next].skb;
2497 skb->ip_summed = CHECKSUM_COMPLETE;
2498 skb->csum = status & 0xffff;
2499 } else {
2500 printk(KERN_NOTICE PFX "%s: hardware receive "
2501 "checksum problem (status = %#x)\n",
2502 dev->name, status);
2503 sky2->rx_csum = 0;
2504 sky2_write32(sky2->hw,
2505 Q_ADDR(rxqaddr[port], Q_CSR),
2506 BMU_DIS_RX_CHKSUM);
2507 }
2508 break;
2509
2510 case OP_TXINDEXLE:
2511 /* TX index reports status for both ports */
2512 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2513 sky2_tx_done(hw->dev[0], status & 0xfff);
2514 if (hw->dev[1])
2515 sky2_tx_done(hw->dev[1],
2516 ((status >> 24) & 0xff)
2517 | (u16)(length & 0xf) << 8);
2518 break;
2519
2520 default:
2521 if (net_ratelimit())
2522 printk(KERN_WARNING PFX
2523 "unknown status opcode 0x%x\n", opcode);
2524 }
2525 } while (hw->st_idx != idx);
2526
2527 /* Fully processed status ring so clear irq */
2528 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2529
2530 exit_loop:
2531 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2532 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2533
2534 return work_done;
2535 }
2536
2537 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2538 {
2539 struct net_device *dev = hw->dev[port];
2540
2541 if (net_ratelimit())
2542 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2543 dev->name, status);
2544
2545 if (status & Y2_IS_PAR_RD1) {
2546 if (net_ratelimit())
2547 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2548 dev->name);
2549 /* Clear IRQ */
2550 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2551 }
2552
2553 if (status & Y2_IS_PAR_WR1) {
2554 if (net_ratelimit())
2555 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2556 dev->name);
2557
2558 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2559 }
2560
2561 if (status & Y2_IS_PAR_MAC1) {
2562 if (net_ratelimit())
2563 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2564 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2565 }
2566
2567 if (status & Y2_IS_PAR_RX1) {
2568 if (net_ratelimit())
2569 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2570 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2571 }
2572
2573 if (status & Y2_IS_TCP_TXA1) {
2574 if (net_ratelimit())
2575 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2576 dev->name);
2577 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2578 }
2579 }
2580
2581 static void sky2_hw_intr(struct sky2_hw *hw)
2582 {
2583 struct pci_dev *pdev = hw->pdev;
2584 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2585 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2586
2587 status &= hwmsk;
2588
2589 if (status & Y2_IS_TIST_OV)
2590 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2591
2592 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2593 u16 pci_err;
2594
2595 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2596 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2597 if (net_ratelimit())
2598 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2599 pci_err);
2600
2601 sky2_pci_write16(hw, PCI_STATUS,
2602 pci_err | PCI_STATUS_ERROR_BITS);
2603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2604 }
2605
2606 if (status & Y2_IS_PCI_EXP) {
2607 /* PCI-Express uncorrectable Error occurred */
2608 u32 err;
2609
2610 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2611 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2612 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2613 0xfffffffful);
2614 if (net_ratelimit())
2615 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2616
2617 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2618 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2619 }
2620
2621 if (status & Y2_HWE_L1_MASK)
2622 sky2_hw_error(hw, 0, status);
2623 status >>= 8;
2624 if (status & Y2_HWE_L1_MASK)
2625 sky2_hw_error(hw, 1, status);
2626 }
2627
2628 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2629 {
2630 struct net_device *dev = hw->dev[port];
2631 struct sky2_port *sky2 = netdev_priv(dev);
2632 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2633
2634 if (netif_msg_intr(sky2))
2635 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2636 dev->name, status);
2637
2638 if (status & GM_IS_RX_CO_OV)
2639 gma_read16(hw, port, GM_RX_IRQ_SRC);
2640
2641 if (status & GM_IS_TX_CO_OV)
2642 gma_read16(hw, port, GM_TX_IRQ_SRC);
2643
2644 if (status & GM_IS_RX_FF_OR) {
2645 ++dev->stats.rx_fifo_errors;
2646 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2647 }
2648
2649 if (status & GM_IS_TX_FF_UR) {
2650 ++dev->stats.tx_fifo_errors;
2651 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2652 }
2653 }
2654
2655 /* This should never happen it is a bug. */
2656 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2657 u16 q, unsigned ring_size)
2658 {
2659 struct net_device *dev = hw->dev[port];
2660 struct sky2_port *sky2 = netdev_priv(dev);
2661 unsigned idx;
2662 const u64 *le = (q == Q_R1 || q == Q_R2)
2663 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2664
2665 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2666 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2667 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2668 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2669
2670 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2671 }
2672
2673 static int sky2_rx_hung(struct net_device *dev)
2674 {
2675 struct sky2_port *sky2 = netdev_priv(dev);
2676 struct sky2_hw *hw = sky2->hw;
2677 unsigned port = sky2->port;
2678 unsigned rxq = rxqaddr[port];
2679 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2680 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2681 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2682 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2683
2684 /* If idle and MAC or PCI is stuck */
2685 if (sky2->check.last == dev->last_rx &&
2686 ((mac_rp == sky2->check.mac_rp &&
2687 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2688 /* Check if the PCI RX hang */
2689 (fifo_rp == sky2->check.fifo_rp &&
2690 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2691 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2692 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2693 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2694 return 1;
2695 } else {
2696 sky2->check.last = dev->last_rx;
2697 sky2->check.mac_rp = mac_rp;
2698 sky2->check.mac_lev = mac_lev;
2699 sky2->check.fifo_rp = fifo_rp;
2700 sky2->check.fifo_lev = fifo_lev;
2701 return 0;
2702 }
2703 }
2704
2705 static void sky2_watchdog(unsigned long arg)
2706 {
2707 struct sky2_hw *hw = (struct sky2_hw *) arg;
2708
2709 /* Check for lost IRQ once a second */
2710 if (sky2_read32(hw, B0_ISRC)) {
2711 napi_schedule(&hw->napi);
2712 } else {
2713 int i, active = 0;
2714
2715 for (i = 0; i < hw->ports; i++) {
2716 struct net_device *dev = hw->dev[i];
2717 if (!netif_running(dev))
2718 continue;
2719 ++active;
2720
2721 /* For chips with Rx FIFO, check if stuck */
2722 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2723 sky2_rx_hung(dev)) {
2724 pr_info(PFX "%s: receiver hang detected\n",
2725 dev->name);
2726 schedule_work(&hw->restart_work);
2727 return;
2728 }
2729 }
2730
2731 if (active == 0)
2732 return;
2733 }
2734
2735 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2736 }
2737
2738 /* Hardware/software error handling */
2739 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2740 {
2741 if (net_ratelimit())
2742 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2743
2744 if (status & Y2_IS_HW_ERR)
2745 sky2_hw_intr(hw);
2746
2747 if (status & Y2_IS_IRQ_MAC1)
2748 sky2_mac_intr(hw, 0);
2749
2750 if (status & Y2_IS_IRQ_MAC2)
2751 sky2_mac_intr(hw, 1);
2752
2753 if (status & Y2_IS_CHK_RX1)
2754 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2755
2756 if (status & Y2_IS_CHK_RX2)
2757 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2758
2759 if (status & Y2_IS_CHK_TXA1)
2760 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2761
2762 if (status & Y2_IS_CHK_TXA2)
2763 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2764 }
2765
2766 static int sky2_poll(struct napi_struct *napi, int work_limit)
2767 {
2768 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2769 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2770 int work_done = 0;
2771 u16 idx;
2772
2773 if (unlikely(status & Y2_IS_ERROR))
2774 sky2_err_intr(hw, status);
2775
2776 if (status & Y2_IS_IRQ_PHY1)
2777 sky2_phy_intr(hw, 0);
2778
2779 if (status & Y2_IS_IRQ_PHY2)
2780 sky2_phy_intr(hw, 1);
2781
2782 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2783 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2784
2785 if (work_done >= work_limit)
2786 goto done;
2787 }
2788
2789 napi_complete(napi);
2790 sky2_read32(hw, B0_Y2_SP_LISR);
2791 done:
2792
2793 return work_done;
2794 }
2795
2796 static irqreturn_t sky2_intr(int irq, void *dev_id)
2797 {
2798 struct sky2_hw *hw = dev_id;
2799 u32 status;
2800
2801 /* Reading this mask interrupts as side effect */
2802 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2803 if (status == 0 || status == ~0)
2804 return IRQ_NONE;
2805
2806 prefetch(&hw->st_le[hw->st_idx]);
2807
2808 napi_schedule(&hw->napi);
2809
2810 return IRQ_HANDLED;
2811 }
2812
2813 #ifdef CONFIG_NET_POLL_CONTROLLER
2814 static void sky2_netpoll(struct net_device *dev)
2815 {
2816 struct sky2_port *sky2 = netdev_priv(dev);
2817
2818 napi_schedule(&sky2->hw->napi);
2819 }
2820 #endif
2821
2822 /* Chip internal frequency for clock calculations */
2823 static u32 sky2_mhz(const struct sky2_hw *hw)
2824 {
2825 switch (hw->chip_id) {
2826 case CHIP_ID_YUKON_EC:
2827 case CHIP_ID_YUKON_EC_U:
2828 case CHIP_ID_YUKON_EX:
2829 case CHIP_ID_YUKON_SUPR:
2830 case CHIP_ID_YUKON_UL_2:
2831 return 125;
2832
2833 case CHIP_ID_YUKON_FE:
2834 return 100;
2835
2836 case CHIP_ID_YUKON_FE_P:
2837 return 50;
2838
2839 case CHIP_ID_YUKON_XL:
2840 return 156;
2841
2842 default:
2843 BUG();
2844 }
2845 }
2846
2847 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2848 {
2849 return sky2_mhz(hw) * us;
2850 }
2851
2852 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2853 {
2854 return clk / sky2_mhz(hw);
2855 }
2856
2857
2858 static int __devinit sky2_init(struct sky2_hw *hw)
2859 {
2860 u8 t8;
2861
2862 /* Enable all clocks and check for bad PCI access */
2863 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2864
2865 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2866
2867 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2868 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2869
2870 switch(hw->chip_id) {
2871 case CHIP_ID_YUKON_XL:
2872 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2873 break;
2874
2875 case CHIP_ID_YUKON_EC_U:
2876 hw->flags = SKY2_HW_GIGABIT
2877 | SKY2_HW_NEWER_PHY
2878 | SKY2_HW_ADV_POWER_CTL;
2879 break;
2880
2881 case CHIP_ID_YUKON_EX:
2882 hw->flags = SKY2_HW_GIGABIT
2883 | SKY2_HW_NEWER_PHY
2884 | SKY2_HW_NEW_LE
2885 | SKY2_HW_ADV_POWER_CTL;
2886
2887 /* New transmit checksum */
2888 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2889 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2890 break;
2891
2892 case CHIP_ID_YUKON_EC:
2893 /* This rev is really old, and requires untested workarounds */
2894 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2895 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2896 return -EOPNOTSUPP;
2897 }
2898 hw->flags = SKY2_HW_GIGABIT;
2899 break;
2900
2901 case CHIP_ID_YUKON_FE:
2902 break;
2903
2904 case CHIP_ID_YUKON_FE_P:
2905 hw->flags = SKY2_HW_NEWER_PHY
2906 | SKY2_HW_NEW_LE
2907 | SKY2_HW_AUTO_TX_SUM
2908 | SKY2_HW_ADV_POWER_CTL;
2909 break;
2910
2911 case CHIP_ID_YUKON_SUPR:
2912 hw->flags = SKY2_HW_GIGABIT
2913 | SKY2_HW_NEWER_PHY
2914 | SKY2_HW_NEW_LE
2915 | SKY2_HW_AUTO_TX_SUM
2916 | SKY2_HW_ADV_POWER_CTL;
2917 break;
2918
2919 case CHIP_ID_YUKON_UL_2:
2920 hw->flags = SKY2_HW_GIGABIT
2921 | SKY2_HW_ADV_POWER_CTL;
2922 break;
2923
2924 default:
2925 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2926 hw->chip_id);
2927 return -EOPNOTSUPP;
2928 }
2929
2930 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2931 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2932 hw->flags |= SKY2_HW_FIBRE_PHY;
2933
2934 hw->ports = 1;
2935 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2936 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2937 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2938 ++hw->ports;
2939 }
2940
2941 return 0;
2942 }
2943
2944 static void sky2_reset(struct sky2_hw *hw)
2945 {
2946 struct pci_dev *pdev = hw->pdev;
2947 u16 status;
2948 int i, cap;
2949 u32 hwe_mask = Y2_HWE_ALL_MASK;
2950
2951 /* disable ASF */
2952 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2953 status = sky2_read16(hw, HCU_CCSR);
2954 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2955 HCU_CCSR_UC_STATE_MSK);
2956 sky2_write16(hw, HCU_CCSR, status);
2957 } else
2958 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2959 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2960
2961 /* do a SW reset */
2962 sky2_write8(hw, B0_CTST, CS_RST_SET);
2963 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2964
2965 /* allow writes to PCI config */
2966 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2967
2968 /* clear PCI errors, if any */
2969 status = sky2_pci_read16(hw, PCI_STATUS);
2970 status |= PCI_STATUS_ERROR_BITS;
2971 sky2_pci_write16(hw, PCI_STATUS, status);
2972
2973 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2974
2975 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2976 if (cap) {
2977 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2978 0xfffffffful);
2979
2980 /* If error bit is stuck on ignore it */
2981 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2982 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2983 else
2984 hwe_mask |= Y2_IS_PCI_EXP;
2985 }
2986
2987 sky2_power_on(hw);
2988 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2989
2990 for (i = 0; i < hw->ports; i++) {
2991 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2992 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2993
2994 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2995 hw->chip_id == CHIP_ID_YUKON_SUPR)
2996 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2997 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2998 | GMC_BYP_RETR_ON);
2999 }
3000
3001 /* Clear I2C IRQ noise */
3002 sky2_write32(hw, B2_I2C_IRQ, 1);
3003
3004 /* turn off hardware timer (unused) */
3005 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3006 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3007
3008 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3009
3010 /* Turn off descriptor polling */
3011 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3012
3013 /* Turn off receive timestamp */
3014 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3015 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3016
3017 /* enable the Tx Arbiters */
3018 for (i = 0; i < hw->ports; i++)
3019 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3020
3021 /* Initialize ram interface */
3022 for (i = 0; i < hw->ports; i++) {
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3024
3025 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3026 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3027 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3028 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3030 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3031 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3032 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3033 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3034 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3035 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3036 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3037 }
3038
3039 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3040
3041 for (i = 0; i < hw->ports; i++)
3042 sky2_gmac_reset(hw, i);
3043
3044 memset(hw->st_le, 0, STATUS_LE_BYTES);
3045 hw->st_idx = 0;
3046
3047 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3048 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3049
3050 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3051 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3052
3053 /* Set the list last index */
3054 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3055
3056 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3057 sky2_write8(hw, STAT_FIFO_WM, 16);
3058
3059 /* set Status-FIFO ISR watermark */
3060 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3061 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3062 else
3063 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3064
3065 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3066 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3067 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3068
3069 /* enable status unit */
3070 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3071
3072 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3073 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3074 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3075 }
3076
3077 static void sky2_restart(struct work_struct *work)
3078 {
3079 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3080 struct net_device *dev;
3081 int i, err;
3082
3083 rtnl_lock();
3084 for (i = 0; i < hw->ports; i++) {
3085 dev = hw->dev[i];
3086 if (netif_running(dev))
3087 sky2_down(dev);
3088 }
3089
3090 napi_disable(&hw->napi);
3091 sky2_write32(hw, B0_IMSK, 0);
3092 sky2_reset(hw);
3093 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3094 napi_enable(&hw->napi);
3095
3096 for (i = 0; i < hw->ports; i++) {
3097 dev = hw->dev[i];
3098 if (netif_running(dev)) {
3099 err = sky2_up(dev);
3100 if (err) {
3101 printk(KERN_INFO PFX "%s: could not restart %d\n",
3102 dev->name, err);
3103 dev_close(dev);
3104 }
3105 }
3106 }
3107
3108 rtnl_unlock();
3109 }
3110
3111 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3112 {
3113 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3114 }
3115
3116 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3117 {
3118 const struct sky2_port *sky2 = netdev_priv(dev);
3119
3120 wol->supported = sky2_wol_supported(sky2->hw);
3121 wol->wolopts = sky2->wol;
3122 }
3123
3124 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3125 {
3126 struct sky2_port *sky2 = netdev_priv(dev);
3127 struct sky2_hw *hw = sky2->hw;
3128
3129 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3130 || !device_can_wakeup(&hw->pdev->dev))
3131 return -EOPNOTSUPP;
3132
3133 sky2->wol = wol->wolopts;
3134
3135 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3136 hw->chip_id == CHIP_ID_YUKON_EX ||
3137 hw->chip_id == CHIP_ID_YUKON_FE_P)
3138 sky2_write32(hw, B0_CTST, sky2->wol
3139 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3140
3141 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3142
3143 if (!netif_running(dev))
3144 sky2_wol_init(sky2);
3145 return 0;
3146 }
3147
3148 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3149 {
3150 if (sky2_is_copper(hw)) {
3151 u32 modes = SUPPORTED_10baseT_Half
3152 | SUPPORTED_10baseT_Full
3153 | SUPPORTED_100baseT_Half
3154 | SUPPORTED_100baseT_Full
3155 | SUPPORTED_Autoneg | SUPPORTED_TP;
3156
3157 if (hw->flags & SKY2_HW_GIGABIT)
3158 modes |= SUPPORTED_1000baseT_Half
3159 | SUPPORTED_1000baseT_Full;
3160 return modes;
3161 } else
3162 return SUPPORTED_1000baseT_Half
3163 | SUPPORTED_1000baseT_Full
3164 | SUPPORTED_Autoneg
3165 | SUPPORTED_FIBRE;
3166 }
3167
3168 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3169 {
3170 struct sky2_port *sky2 = netdev_priv(dev);
3171 struct sky2_hw *hw = sky2->hw;
3172
3173 ecmd->transceiver = XCVR_INTERNAL;
3174 ecmd->supported = sky2_supported_modes(hw);
3175 ecmd->phy_address = PHY_ADDR_MARV;
3176 if (sky2_is_copper(hw)) {
3177 ecmd->port = PORT_TP;
3178 ecmd->speed = sky2->speed;
3179 } else {
3180 ecmd->speed = SPEED_1000;
3181 ecmd->port = PORT_FIBRE;
3182 }
3183
3184 ecmd->advertising = sky2->advertising;
3185 ecmd->autoneg = sky2->autoneg;
3186 ecmd->duplex = sky2->duplex;
3187 return 0;
3188 }
3189
3190 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3191 {
3192 struct sky2_port *sky2 = netdev_priv(dev);
3193 const struct sky2_hw *hw = sky2->hw;
3194 u32 supported = sky2_supported_modes(hw);
3195
3196 if (ecmd->autoneg == AUTONEG_ENABLE) {
3197 ecmd->advertising = supported;
3198 sky2->duplex = -1;
3199 sky2->speed = -1;
3200 } else {
3201 u32 setting;
3202
3203 switch (ecmd->speed) {
3204 case SPEED_1000:
3205 if (ecmd->duplex == DUPLEX_FULL)
3206 setting = SUPPORTED_1000baseT_Full;
3207 else if (ecmd->duplex == DUPLEX_HALF)
3208 setting = SUPPORTED_1000baseT_Half;
3209 else
3210 return -EINVAL;
3211 break;
3212 case SPEED_100:
3213 if (ecmd->duplex == DUPLEX_FULL)
3214 setting = SUPPORTED_100baseT_Full;
3215 else if (ecmd->duplex == DUPLEX_HALF)
3216 setting = SUPPORTED_100baseT_Half;
3217 else
3218 return -EINVAL;
3219 break;
3220
3221 case SPEED_10:
3222 if (ecmd->duplex == DUPLEX_FULL)
3223 setting = SUPPORTED_10baseT_Full;
3224 else if (ecmd->duplex == DUPLEX_HALF)
3225 setting = SUPPORTED_10baseT_Half;
3226 else
3227 return -EINVAL;
3228 break;
3229 default:
3230 return -EINVAL;
3231 }
3232
3233 if ((setting & supported) == 0)
3234 return -EINVAL;
3235
3236 sky2->speed = ecmd->speed;
3237 sky2->duplex = ecmd->duplex;
3238 }
3239
3240 sky2->autoneg = ecmd->autoneg;
3241 sky2->advertising = ecmd->advertising;
3242
3243 if (netif_running(dev)) {
3244 sky2_phy_reinit(sky2);
3245 sky2_set_multicast(dev);
3246 }
3247
3248 return 0;
3249 }
3250
3251 static void sky2_get_drvinfo(struct net_device *dev,
3252 struct ethtool_drvinfo *info)
3253 {
3254 struct sky2_port *sky2 = netdev_priv(dev);
3255
3256 strcpy(info->driver, DRV_NAME);
3257 strcpy(info->version, DRV_VERSION);
3258 strcpy(info->fw_version, "N/A");
3259 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3260 }
3261
3262 static const struct sky2_stat {
3263 char name[ETH_GSTRING_LEN];
3264 u16 offset;
3265 } sky2_stats[] = {
3266 { "tx_bytes", GM_TXO_OK_HI },
3267 { "rx_bytes", GM_RXO_OK_HI },
3268 { "tx_broadcast", GM_TXF_BC_OK },
3269 { "rx_broadcast", GM_RXF_BC_OK },
3270 { "tx_multicast", GM_TXF_MC_OK },
3271 { "rx_multicast", GM_RXF_MC_OK },
3272 { "tx_unicast", GM_TXF_UC_OK },
3273 { "rx_unicast", GM_RXF_UC_OK },
3274 { "tx_mac_pause", GM_TXF_MPAUSE },
3275 { "rx_mac_pause", GM_RXF_MPAUSE },
3276 { "collisions", GM_TXF_COL },
3277 { "late_collision",GM_TXF_LAT_COL },
3278 { "aborted", GM_TXF_ABO_COL },
3279 { "single_collisions", GM_TXF_SNG_COL },
3280 { "multi_collisions", GM_TXF_MUL_COL },
3281
3282 { "rx_short", GM_RXF_SHT },
3283 { "rx_runt", GM_RXE_FRAG },
3284 { "rx_64_byte_packets", GM_RXF_64B },
3285 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3286 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3287 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3288 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3289 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3290 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3291 { "rx_too_long", GM_RXF_LNG_ERR },
3292 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3293 { "rx_jabber", GM_RXF_JAB_PKT },
3294 { "rx_fcs_error", GM_RXF_FCS_ERR },
3295
3296 { "tx_64_byte_packets", GM_TXF_64B },
3297 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3298 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3299 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3300 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3301 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3302 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3303 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3304 };
3305
3306 static u32 sky2_get_rx_csum(struct net_device *dev)
3307 {
3308 struct sky2_port *sky2 = netdev_priv(dev);
3309
3310 return sky2->rx_csum;
3311 }
3312
3313 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3314 {
3315 struct sky2_port *sky2 = netdev_priv(dev);
3316
3317 sky2->rx_csum = data;
3318
3319 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3320 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3321
3322 return 0;
3323 }
3324
3325 static u32 sky2_get_msglevel(struct net_device *netdev)
3326 {
3327 struct sky2_port *sky2 = netdev_priv(netdev);
3328 return sky2->msg_enable;
3329 }
3330
3331 static int sky2_nway_reset(struct net_device *dev)
3332 {
3333 struct sky2_port *sky2 = netdev_priv(dev);
3334
3335 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3336 return -EINVAL;
3337
3338 sky2_phy_reinit(sky2);
3339 sky2_set_multicast(dev);
3340
3341 return 0;
3342 }
3343
3344 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3345 {
3346 struct sky2_hw *hw = sky2->hw;
3347 unsigned port = sky2->port;
3348 int i;
3349
3350 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3351 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3352 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3353 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3354
3355 for (i = 2; i < count; i++)
3356 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3357 }
3358
3359 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3360 {
3361 struct sky2_port *sky2 = netdev_priv(netdev);
3362 sky2->msg_enable = value;
3363 }
3364
3365 static int sky2_get_sset_count(struct net_device *dev, int sset)
3366 {
3367 switch (sset) {
3368 case ETH_SS_STATS:
3369 return ARRAY_SIZE(sky2_stats);
3370 default:
3371 return -EOPNOTSUPP;
3372 }
3373 }
3374
3375 static void sky2_get_ethtool_stats(struct net_device *dev,
3376 struct ethtool_stats *stats, u64 * data)
3377 {
3378 struct sky2_port *sky2 = netdev_priv(dev);
3379
3380 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3381 }
3382
3383 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3384 {
3385 int i;
3386
3387 switch (stringset) {
3388 case ETH_SS_STATS:
3389 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3390 memcpy(data + i * ETH_GSTRING_LEN,
3391 sky2_stats[i].name, ETH_GSTRING_LEN);
3392 break;
3393 }
3394 }
3395
3396 static int sky2_set_mac_address(struct net_device *dev, void *p)
3397 {
3398 struct sky2_port *sky2 = netdev_priv(dev);
3399 struct sky2_hw *hw = sky2->hw;
3400 unsigned port = sky2->port;
3401 const struct sockaddr *addr = p;
3402
3403 if (!is_valid_ether_addr(addr->sa_data))
3404 return -EADDRNOTAVAIL;
3405
3406 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3407 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3408 dev->dev_addr, ETH_ALEN);
3409 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3410 dev->dev_addr, ETH_ALEN);
3411
3412 /* virtual address for data */
3413 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3414
3415 /* physical address: used for pause frames */
3416 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3417
3418 return 0;
3419 }
3420
3421 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3422 {
3423 u32 bit;
3424
3425 bit = ether_crc(ETH_ALEN, addr) & 63;
3426 filter[bit >> 3] |= 1 << (bit & 7);
3427 }
3428
3429 static void sky2_set_multicast(struct net_device *dev)
3430 {
3431 struct sky2_port *sky2 = netdev_priv(dev);
3432 struct sky2_hw *hw = sky2->hw;
3433 unsigned port = sky2->port;
3434 struct dev_mc_list *list = dev->mc_list;
3435 u16 reg;
3436 u8 filter[8];
3437 int rx_pause;
3438 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3439
3440 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3441 memset(filter, 0, sizeof(filter));
3442
3443 reg = gma_read16(hw, port, GM_RX_CTRL);
3444 reg |= GM_RXCR_UCF_ENA;
3445
3446 if (dev->flags & IFF_PROMISC) /* promiscuous */
3447 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3448 else if (dev->flags & IFF_ALLMULTI)
3449 memset(filter, 0xff, sizeof(filter));
3450 else if (dev->mc_count == 0 && !rx_pause)
3451 reg &= ~GM_RXCR_MCF_ENA;
3452 else {
3453 int i;
3454 reg |= GM_RXCR_MCF_ENA;
3455
3456 if (rx_pause)
3457 sky2_add_filter(filter, pause_mc_addr);
3458
3459 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3460 sky2_add_filter(filter, list->dmi_addr);
3461 }
3462
3463 gma_write16(hw, port, GM_MC_ADDR_H1,
3464 (u16) filter[0] | ((u16) filter[1] << 8));
3465 gma_write16(hw, port, GM_MC_ADDR_H2,
3466 (u16) filter[2] | ((u16) filter[3] << 8));
3467 gma_write16(hw, port, GM_MC_ADDR_H3,
3468 (u16) filter[4] | ((u16) filter[5] << 8));
3469 gma_write16(hw, port, GM_MC_ADDR_H4,
3470 (u16) filter[6] | ((u16) filter[7] << 8));
3471
3472 gma_write16(hw, port, GM_RX_CTRL, reg);
3473 }
3474
3475 /* Can have one global because blinking is controlled by
3476 * ethtool and that is always under RTNL mutex
3477 */
3478 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3479 {
3480 struct sky2_hw *hw = sky2->hw;
3481 unsigned port = sky2->port;
3482
3483 spin_lock_bh(&sky2->phy_lock);
3484 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3485 hw->chip_id == CHIP_ID_YUKON_EX ||
3486 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3487 u16 pg;
3488 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3489 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3490
3491 switch (mode) {
3492 case MO_LED_OFF:
3493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3494 PHY_M_LEDC_LOS_CTRL(8) |
3495 PHY_M_LEDC_INIT_CTRL(8) |
3496 PHY_M_LEDC_STA1_CTRL(8) |
3497 PHY_M_LEDC_STA0_CTRL(8));
3498 break;
3499 case MO_LED_ON:
3500 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3501 PHY_M_LEDC_LOS_CTRL(9) |
3502 PHY_M_LEDC_INIT_CTRL(9) |
3503 PHY_M_LEDC_STA1_CTRL(9) |
3504 PHY_M_LEDC_STA0_CTRL(9));
3505 break;
3506 case MO_LED_BLINK:
3507 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3508 PHY_M_LEDC_LOS_CTRL(0xa) |
3509 PHY_M_LEDC_INIT_CTRL(0xa) |
3510 PHY_M_LEDC_STA1_CTRL(0xa) |
3511 PHY_M_LEDC_STA0_CTRL(0xa));
3512 break;
3513 case MO_LED_NORM:
3514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3515 PHY_M_LEDC_LOS_CTRL(1) |
3516 PHY_M_LEDC_INIT_CTRL(8) |
3517 PHY_M_LEDC_STA1_CTRL(7) |
3518 PHY_M_LEDC_STA0_CTRL(7));
3519 }
3520
3521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3522 } else
3523 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3524 PHY_M_LED_MO_DUP(mode) |
3525 PHY_M_LED_MO_10(mode) |
3526 PHY_M_LED_MO_100(mode) |
3527 PHY_M_LED_MO_1000(mode) |
3528 PHY_M_LED_MO_RX(mode) |
3529 PHY_M_LED_MO_TX(mode));
3530
3531 spin_unlock_bh(&sky2->phy_lock);
3532 }
3533
3534 /* blink LED's for finding board */
3535 static int sky2_phys_id(struct net_device *dev, u32 data)
3536 {
3537 struct sky2_port *sky2 = netdev_priv(dev);
3538 unsigned int i;
3539
3540 if (data == 0)
3541 data = UINT_MAX;
3542
3543 for (i = 0; i < data; i++) {
3544 sky2_led(sky2, MO_LED_ON);
3545 if (msleep_interruptible(500))
3546 break;
3547 sky2_led(sky2, MO_LED_OFF);
3548 if (msleep_interruptible(500))
3549 break;
3550 }
3551 sky2_led(sky2, MO_LED_NORM);
3552
3553 return 0;
3554 }
3555
3556 static void sky2_get_pauseparam(struct net_device *dev,
3557 struct ethtool_pauseparam *ecmd)
3558 {
3559 struct sky2_port *sky2 = netdev_priv(dev);
3560
3561 switch (sky2->flow_mode) {
3562 case FC_NONE:
3563 ecmd->tx_pause = ecmd->rx_pause = 0;
3564 break;
3565 case FC_TX:
3566 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3567 break;
3568 case FC_RX:
3569 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3570 break;
3571 case FC_BOTH:
3572 ecmd->tx_pause = ecmd->rx_pause = 1;
3573 }
3574
3575 ecmd->autoneg = sky2->autoneg;
3576 }
3577
3578 static int sky2_set_pauseparam(struct net_device *dev,
3579 struct ethtool_pauseparam *ecmd)
3580 {
3581 struct sky2_port *sky2 = netdev_priv(dev);
3582
3583 sky2->autoneg = ecmd->autoneg;
3584 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3585
3586 if (netif_running(dev))
3587 sky2_phy_reinit(sky2);
3588
3589 return 0;
3590 }
3591
3592 static int sky2_get_coalesce(struct net_device *dev,
3593 struct ethtool_coalesce *ecmd)
3594 {
3595 struct sky2_port *sky2 = netdev_priv(dev);
3596 struct sky2_hw *hw = sky2->hw;
3597
3598 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3599 ecmd->tx_coalesce_usecs = 0;
3600 else {
3601 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3602 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3603 }
3604 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3605
3606 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3607 ecmd->rx_coalesce_usecs = 0;
3608 else {
3609 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3610 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3611 }
3612 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3613
3614 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3615 ecmd->rx_coalesce_usecs_irq = 0;
3616 else {
3617 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3618 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3619 }
3620
3621 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3622
3623 return 0;
3624 }
3625
3626 /* Note: this affect both ports */
3627 static int sky2_set_coalesce(struct net_device *dev,
3628 struct ethtool_coalesce *ecmd)
3629 {
3630 struct sky2_port *sky2 = netdev_priv(dev);
3631 struct sky2_hw *hw = sky2->hw;
3632 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3633
3634 if (ecmd->tx_coalesce_usecs > tmax ||
3635 ecmd->rx_coalesce_usecs > tmax ||
3636 ecmd->rx_coalesce_usecs_irq > tmax)
3637 return -EINVAL;
3638
3639 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3640 return -EINVAL;
3641 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3642 return -EINVAL;
3643 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3644 return -EINVAL;
3645
3646 if (ecmd->tx_coalesce_usecs == 0)
3647 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3648 else {
3649 sky2_write32(hw, STAT_TX_TIMER_INI,
3650 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3651 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3652 }
3653 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3654
3655 if (ecmd->rx_coalesce_usecs == 0)
3656 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3657 else {
3658 sky2_write32(hw, STAT_LEV_TIMER_INI,
3659 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3660 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3661 }
3662 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3663
3664 if (ecmd->rx_coalesce_usecs_irq == 0)
3665 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3666 else {
3667 sky2_write32(hw, STAT_ISR_TIMER_INI,
3668 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3669 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3670 }
3671 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3672 return 0;
3673 }
3674
3675 static void sky2_get_ringparam(struct net_device *dev,
3676 struct ethtool_ringparam *ering)
3677 {
3678 struct sky2_port *sky2 = netdev_priv(dev);
3679
3680 ering->rx_max_pending = RX_MAX_PENDING;
3681 ering->rx_mini_max_pending = 0;
3682 ering->rx_jumbo_max_pending = 0;
3683 ering->tx_max_pending = TX_RING_SIZE - 1;
3684
3685 ering->rx_pending = sky2->rx_pending;
3686 ering->rx_mini_pending = 0;
3687 ering->rx_jumbo_pending = 0;
3688 ering->tx_pending = sky2->tx_pending;
3689 }
3690
3691 static int sky2_set_ringparam(struct net_device *dev,
3692 struct ethtool_ringparam *ering)
3693 {
3694 struct sky2_port *sky2 = netdev_priv(dev);
3695 int err = 0;
3696
3697 if (ering->rx_pending > RX_MAX_PENDING ||
3698 ering->rx_pending < 8 ||
3699 ering->tx_pending < MAX_SKB_TX_LE ||
3700 ering->tx_pending > TX_RING_SIZE - 1)
3701 return -EINVAL;
3702
3703 if (netif_running(dev))
3704 sky2_down(dev);
3705
3706 sky2->rx_pending = ering->rx_pending;
3707 sky2->tx_pending = ering->tx_pending;
3708
3709 if (netif_running(dev)) {
3710 err = sky2_up(dev);
3711 if (err)
3712 dev_close(dev);
3713 }
3714
3715 return err;
3716 }
3717
3718 static int sky2_get_regs_len(struct net_device *dev)
3719 {
3720 return 0x4000;
3721 }
3722
3723 /*
3724 * Returns copy of control register region
3725 * Note: ethtool_get_regs always provides full size (16k) buffer
3726 */
3727 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3728 void *p)
3729 {
3730 const struct sky2_port *sky2 = netdev_priv(dev);
3731 const void __iomem *io = sky2->hw->regs;
3732 unsigned int b;
3733
3734 regs->version = 1;
3735
3736 for (b = 0; b < 128; b++) {
3737 /* This complicated switch statement is to make sure and
3738 * only access regions that are unreserved.
3739 * Some blocks are only valid on dual port cards.
3740 * and block 3 has some special diagnostic registers that
3741 * are poison.
3742 */
3743 switch (b) {
3744 case 3:
3745 /* skip diagnostic ram region */
3746 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3747 break;
3748
3749 /* dual port cards only */
3750 case 5: /* Tx Arbiter 2 */
3751 case 9: /* RX2 */
3752 case 14 ... 15: /* TX2 */
3753 case 17: case 19: /* Ram Buffer 2 */
3754 case 22 ... 23: /* Tx Ram Buffer 2 */
3755 case 25: /* Rx MAC Fifo 1 */
3756 case 27: /* Tx MAC Fifo 2 */
3757 case 31: /* GPHY 2 */
3758 case 40 ... 47: /* Pattern Ram 2 */
3759 case 52: case 54: /* TCP Segmentation 2 */
3760 case 112 ... 116: /* GMAC 2 */
3761 if (sky2->hw->ports == 1)
3762 goto reserved;
3763 /* fall through */
3764 case 0: /* Control */
3765 case 2: /* Mac address */
3766 case 4: /* Tx Arbiter 1 */
3767 case 7: /* PCI express reg */
3768 case 8: /* RX1 */
3769 case 12 ... 13: /* TX1 */
3770 case 16: case 18:/* Rx Ram Buffer 1 */
3771 case 20 ... 21: /* Tx Ram Buffer 1 */
3772 case 24: /* Rx MAC Fifo 1 */
3773 case 26: /* Tx MAC Fifo 1 */
3774 case 28 ... 29: /* Descriptor and status unit */
3775 case 30: /* GPHY 1*/
3776 case 32 ... 39: /* Pattern Ram 1 */
3777 case 48: case 50: /* TCP Segmentation 1 */
3778 case 56 ... 60: /* PCI space */
3779 case 80 ... 84: /* GMAC 1 */
3780 memcpy_fromio(p, io, 128);
3781 break;
3782 default:
3783 reserved:
3784 memset(p, 0, 128);
3785 }
3786
3787 p += 128;
3788 io += 128;
3789 }
3790 }
3791
3792 /* In order to do Jumbo packets on these chips, need to turn off the
3793 * transmit store/forward. Therefore checksum offload won't work.
3794 */
3795 static int no_tx_offload(struct net_device *dev)
3796 {
3797 const struct sky2_port *sky2 = netdev_priv(dev);
3798 const struct sky2_hw *hw = sky2->hw;
3799
3800 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3801 }
3802
3803 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3804 {
3805 if (data && no_tx_offload(dev))
3806 return -EINVAL;
3807
3808 return ethtool_op_set_tx_csum(dev, data);
3809 }
3810
3811
3812 static int sky2_set_tso(struct net_device *dev, u32 data)
3813 {
3814 if (data && no_tx_offload(dev))
3815 return -EINVAL;
3816
3817 return ethtool_op_set_tso(dev, data);
3818 }
3819
3820 static int sky2_get_eeprom_len(struct net_device *dev)
3821 {
3822 struct sky2_port *sky2 = netdev_priv(dev);
3823 struct sky2_hw *hw = sky2->hw;
3824 u16 reg2;
3825
3826 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3827 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3828 }
3829
3830 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3831 {
3832 unsigned long start = jiffies;
3833
3834 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3835 /* Can take up to 10.6 ms for write */
3836 if (time_after(jiffies, start + HZ/4)) {
3837 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3838 return -ETIMEDOUT;
3839 }
3840 mdelay(1);
3841 }
3842
3843 return 0;
3844 }
3845
3846 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3847 u16 offset, size_t length)
3848 {
3849 int rc = 0;
3850
3851 while (length > 0) {
3852 u32 val;
3853
3854 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3855 rc = sky2_vpd_wait(hw, cap, 0);
3856 if (rc)
3857 break;
3858
3859 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3860
3861 memcpy(data, &val, min(sizeof(val), length));
3862 offset += sizeof(u32);
3863 data += sizeof(u32);
3864 length -= sizeof(u32);
3865 }
3866
3867 return rc;
3868 }
3869
3870 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3871 u16 offset, unsigned int length)
3872 {
3873 unsigned int i;
3874 int rc = 0;
3875
3876 for (i = 0; i < length; i += sizeof(u32)) {
3877 u32 val = *(u32 *)(data + i);
3878
3879 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3880 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3881
3882 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3883 if (rc)
3884 break;
3885 }
3886 return rc;
3887 }
3888
3889 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3890 u8 *data)
3891 {
3892 struct sky2_port *sky2 = netdev_priv(dev);
3893 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3894
3895 if (!cap)
3896 return -EINVAL;
3897
3898 eeprom->magic = SKY2_EEPROM_MAGIC;
3899
3900 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3901 }
3902
3903 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3904 u8 *data)
3905 {
3906 struct sky2_port *sky2 = netdev_priv(dev);
3907 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3908
3909 if (!cap)
3910 return -EINVAL;
3911
3912 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3913 return -EINVAL;
3914
3915 /* Partial writes not supported */
3916 if ((eeprom->offset & 3) || (eeprom->len & 3))
3917 return -EINVAL;
3918
3919 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3920 }
3921
3922
3923 static const struct ethtool_ops sky2_ethtool_ops = {
3924 .get_settings = sky2_get_settings,
3925 .set_settings = sky2_set_settings,
3926 .get_drvinfo = sky2_get_drvinfo,
3927 .get_wol = sky2_get_wol,
3928 .set_wol = sky2_set_wol,
3929 .get_msglevel = sky2_get_msglevel,
3930 .set_msglevel = sky2_set_msglevel,
3931 .nway_reset = sky2_nway_reset,
3932 .get_regs_len = sky2_get_regs_len,
3933 .get_regs = sky2_get_regs,
3934 .get_link = ethtool_op_get_link,
3935 .get_eeprom_len = sky2_get_eeprom_len,
3936 .get_eeprom = sky2_get_eeprom,
3937 .set_eeprom = sky2_set_eeprom,
3938 .set_sg = ethtool_op_set_sg,
3939 .set_tx_csum = sky2_set_tx_csum,
3940 .set_tso = sky2_set_tso,
3941 .get_rx_csum = sky2_get_rx_csum,
3942 .set_rx_csum = sky2_set_rx_csum,
3943 .get_strings = sky2_get_strings,
3944 .get_coalesce = sky2_get_coalesce,
3945 .set_coalesce = sky2_set_coalesce,
3946 .get_ringparam = sky2_get_ringparam,
3947 .set_ringparam = sky2_set_ringparam,
3948 .get_pauseparam = sky2_get_pauseparam,
3949 .set_pauseparam = sky2_set_pauseparam,
3950 .phys_id = sky2_phys_id,
3951 .get_sset_count = sky2_get_sset_count,
3952 .get_ethtool_stats = sky2_get_ethtool_stats,
3953 };
3954
3955 #ifdef CONFIG_SKY2_DEBUG
3956
3957 static struct dentry *sky2_debug;
3958
3959
3960 /*
3961 * Read and parse the first part of Vital Product Data
3962 */
3963 #define VPD_SIZE 128
3964 #define VPD_MAGIC 0x82
3965
3966 static const struct vpd_tag {
3967 char tag[2];
3968 char *label;
3969 } vpd_tags[] = {
3970 { "PN", "Part Number" },
3971 { "EC", "Engineering Level" },
3972 { "MN", "Manufacturer" },
3973 { "SN", "Serial Number" },
3974 { "YA", "Asset Tag" },
3975 { "VL", "First Error Log Message" },
3976 { "VF", "Second Error Log Message" },
3977 { "VB", "Boot Agent ROM Configuration" },
3978 { "VE", "EFI UNDI Configuration" },
3979 };
3980
3981 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3982 {
3983 size_t vpd_size;
3984 loff_t offs;
3985 u8 len;
3986 unsigned char *buf;
3987 u16 reg2;
3988
3989 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3990 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3991
3992 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3993 buf = kmalloc(vpd_size, GFP_KERNEL);
3994 if (!buf) {
3995 seq_puts(seq, "no memory!\n");
3996 return;
3997 }
3998
3999 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4000 seq_puts(seq, "VPD read failed\n");
4001 goto out;
4002 }
4003
4004 if (buf[0] != VPD_MAGIC) {
4005 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4006 goto out;
4007 }
4008 len = buf[1];
4009 if (len == 0 || len > vpd_size - 4) {
4010 seq_printf(seq, "Invalid id length: %d\n", len);
4011 goto out;
4012 }
4013
4014 seq_printf(seq, "%.*s\n", len, buf + 3);
4015 offs = len + 3;
4016
4017 while (offs < vpd_size - 4) {
4018 int i;
4019
4020 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4021 break;
4022 len = buf[offs + 2];
4023 if (offs + len + 3 >= vpd_size)
4024 break;
4025
4026 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4027 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4028 seq_printf(seq, " %s: %.*s\n",
4029 vpd_tags[i].label, len, buf + offs + 3);
4030 break;
4031 }
4032 }
4033 offs += len + 3;
4034 }
4035 out:
4036 kfree(buf);
4037 }
4038
4039 static int sky2_debug_show(struct seq_file *seq, void *v)
4040 {
4041 struct net_device *dev = seq->private;
4042 const struct sky2_port *sky2 = netdev_priv(dev);
4043 struct sky2_hw *hw = sky2->hw;
4044 unsigned port = sky2->port;
4045 unsigned idx, last;
4046 int sop;
4047
4048 sky2_show_vpd(seq, hw);
4049
4050 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4051 sky2_read32(hw, B0_ISRC),
4052 sky2_read32(hw, B0_IMSK),
4053 sky2_read32(hw, B0_Y2_SP_ICR));
4054
4055 if (!netif_running(dev)) {
4056 seq_printf(seq, "network not running\n");
4057 return 0;
4058 }
4059
4060 napi_disable(&hw->napi);
4061 last = sky2_read16(hw, STAT_PUT_IDX);
4062
4063 if (hw->st_idx == last)
4064 seq_puts(seq, "Status ring (empty)\n");
4065 else {
4066 seq_puts(seq, "Status ring\n");
4067 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4068 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4069 const struct sky2_status_le *le = hw->st_le + idx;
4070 seq_printf(seq, "[%d] %#x %d %#x\n",
4071 idx, le->opcode, le->length, le->status);
4072 }
4073 seq_puts(seq, "\n");
4074 }
4075
4076 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4077 sky2->tx_cons, sky2->tx_prod,
4078 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4079 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4080
4081 /* Dump contents of tx ring */
4082 sop = 1;
4083 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4084 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4085 const struct sky2_tx_le *le = sky2->tx_le + idx;
4086 u32 a = le32_to_cpu(le->addr);
4087
4088 if (sop)
4089 seq_printf(seq, "%u:", idx);
4090 sop = 0;
4091
4092 switch(le->opcode & ~HW_OWNER) {
4093 case OP_ADDR64:
4094 seq_printf(seq, " %#x:", a);
4095 break;
4096 case OP_LRGLEN:
4097 seq_printf(seq, " mtu=%d", a);
4098 break;
4099 case OP_VLAN:
4100 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4101 break;
4102 case OP_TCPLISW:
4103 seq_printf(seq, " csum=%#x", a);
4104 break;
4105 case OP_LARGESEND:
4106 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4107 break;
4108 case OP_PACKET:
4109 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4110 break;
4111 case OP_BUFFER:
4112 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4113 break;
4114 default:
4115 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4116 a, le16_to_cpu(le->length));
4117 }
4118
4119 if (le->ctrl & EOP) {
4120 seq_putc(seq, '\n');
4121 sop = 1;
4122 }
4123 }
4124
4125 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4126 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4127 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4128 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4129
4130 sky2_read32(hw, B0_Y2_SP_LISR);
4131 napi_enable(&hw->napi);
4132 return 0;
4133 }
4134
4135 static int sky2_debug_open(struct inode *inode, struct file *file)
4136 {
4137 return single_open(file, sky2_debug_show, inode->i_private);
4138 }
4139
4140 static const struct file_operations sky2_debug_fops = {
4141 .owner = THIS_MODULE,
4142 .open = sky2_debug_open,
4143 .read = seq_read,
4144 .llseek = seq_lseek,
4145 .release = single_release,
4146 };
4147
4148 /*
4149 * Use network device events to create/remove/rename
4150 * debugfs file entries
4151 */
4152 static int sky2_device_event(struct notifier_block *unused,
4153 unsigned long event, void *ptr)
4154 {
4155 struct net_device *dev = ptr;
4156 struct sky2_port *sky2 = netdev_priv(dev);
4157
4158 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4159 return NOTIFY_DONE;
4160
4161 switch(event) {
4162 case NETDEV_CHANGENAME:
4163 if (sky2->debugfs) {
4164 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4165 sky2_debug, dev->name);
4166 }
4167 break;
4168
4169 case NETDEV_GOING_DOWN:
4170 if (sky2->debugfs) {
4171 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4172 dev->name);
4173 debugfs_remove(sky2->debugfs);
4174 sky2->debugfs = NULL;
4175 }
4176 break;
4177
4178 case NETDEV_UP:
4179 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4180 sky2_debug, dev,
4181 &sky2_debug_fops);
4182 if (IS_ERR(sky2->debugfs))
4183 sky2->debugfs = NULL;
4184 }
4185
4186 return NOTIFY_DONE;
4187 }
4188
4189 static struct notifier_block sky2_notifier = {
4190 .notifier_call = sky2_device_event,
4191 };
4192
4193
4194 static __init void sky2_debug_init(void)
4195 {
4196 struct dentry *ent;
4197
4198 ent = debugfs_create_dir("sky2", NULL);
4199 if (!ent || IS_ERR(ent))
4200 return;
4201
4202 sky2_debug = ent;
4203 register_netdevice_notifier(&sky2_notifier);
4204 }
4205
4206 static __exit void sky2_debug_cleanup(void)
4207 {
4208 if (sky2_debug) {
4209 unregister_netdevice_notifier(&sky2_notifier);
4210 debugfs_remove(sky2_debug);
4211 sky2_debug = NULL;
4212 }
4213 }
4214
4215 #else
4216 #define sky2_debug_init()
4217 #define sky2_debug_cleanup()
4218 #endif
4219
4220 /* Two copies of network device operations to handle special case of
4221 not allowing netpoll on second port */
4222 static const struct net_device_ops sky2_netdev_ops[2] = {
4223 {
4224 .ndo_open = sky2_up,
4225 .ndo_stop = sky2_down,
4226 .ndo_start_xmit = sky2_xmit_frame,
4227 .ndo_do_ioctl = sky2_ioctl,
4228 .ndo_validate_addr = eth_validate_addr,
4229 .ndo_set_mac_address = sky2_set_mac_address,
4230 .ndo_set_multicast_list = sky2_set_multicast,
4231 .ndo_change_mtu = sky2_change_mtu,
4232 .ndo_tx_timeout = sky2_tx_timeout,
4233 #ifdef SKY2_VLAN_TAG_USED
4234 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4235 #endif
4236 #ifdef CONFIG_NET_POLL_CONTROLLER
4237 .ndo_poll_controller = sky2_netpoll,
4238 #endif
4239 },
4240 {
4241 .ndo_open = sky2_up,
4242 .ndo_stop = sky2_down,
4243 .ndo_start_xmit = sky2_xmit_frame,
4244 .ndo_do_ioctl = sky2_ioctl,
4245 .ndo_validate_addr = eth_validate_addr,
4246 .ndo_set_mac_address = sky2_set_mac_address,
4247 .ndo_set_multicast_list = sky2_set_multicast,
4248 .ndo_change_mtu = sky2_change_mtu,
4249 .ndo_tx_timeout = sky2_tx_timeout,
4250 #ifdef SKY2_VLAN_TAG_USED
4251 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4252 #endif
4253 },
4254 };
4255
4256 /* Initialize network device */
4257 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4258 unsigned port,
4259 int highmem, int wol)
4260 {
4261 struct sky2_port *sky2;
4262 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4263
4264 if (!dev) {
4265 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4266 return NULL;
4267 }
4268
4269 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4270 dev->irq = hw->pdev->irq;
4271 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4272 dev->watchdog_timeo = TX_WATCHDOG;
4273 dev->netdev_ops = &sky2_netdev_ops[port];
4274
4275 sky2 = netdev_priv(dev);
4276 sky2->netdev = dev;
4277 sky2->hw = hw;
4278 sky2->msg_enable = netif_msg_init(debug, default_msg);
4279
4280 /* Auto speed and flow control */
4281 sky2->autoneg = AUTONEG_ENABLE;
4282 sky2->flow_mode = FC_BOTH;
4283
4284 sky2->duplex = -1;
4285 sky2->speed = -1;
4286 sky2->advertising = sky2_supported_modes(hw);
4287 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4288 sky2->wol = wol;
4289
4290 spin_lock_init(&sky2->phy_lock);
4291 sky2->tx_pending = TX_DEF_PENDING;
4292 sky2->rx_pending = RX_DEF_PENDING;
4293
4294 hw->dev[port] = dev;
4295
4296 sky2->port = port;
4297
4298 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4299 if (highmem)
4300 dev->features |= NETIF_F_HIGHDMA;
4301
4302 #ifdef SKY2_VLAN_TAG_USED
4303 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4304 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4305 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4306 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4307 }
4308 #endif
4309
4310 /* read the mac address */
4311 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4312 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4313
4314 return dev;
4315 }
4316
4317 static void __devinit sky2_show_addr(struct net_device *dev)
4318 {
4319 const struct sky2_port *sky2 = netdev_priv(dev);
4320
4321 if (netif_msg_probe(sky2))
4322 printk(KERN_INFO PFX "%s: addr %pM\n",
4323 dev->name, dev->dev_addr);
4324 }
4325
4326 /* Handle software interrupt used during MSI test */
4327 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4328 {
4329 struct sky2_hw *hw = dev_id;
4330 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4331
4332 if (status == 0)
4333 return IRQ_NONE;
4334
4335 if (status & Y2_IS_IRQ_SW) {
4336 hw->flags |= SKY2_HW_USE_MSI;
4337 wake_up(&hw->msi_wait);
4338 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4339 }
4340 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4341
4342 return IRQ_HANDLED;
4343 }
4344
4345 /* Test interrupt path by forcing a a software IRQ */
4346 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4347 {
4348 struct pci_dev *pdev = hw->pdev;
4349 int err;
4350
4351 init_waitqueue_head (&hw->msi_wait);
4352
4353 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4354
4355 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4356 if (err) {
4357 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4358 return err;
4359 }
4360
4361 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4362 sky2_read8(hw, B0_CTST);
4363
4364 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4365
4366 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4367 /* MSI test failed, go back to INTx mode */
4368 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4369 "switching to INTx mode.\n");
4370
4371 err = -EOPNOTSUPP;
4372 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4373 }
4374
4375 sky2_write32(hw, B0_IMSK, 0);
4376 sky2_read32(hw, B0_IMSK);
4377
4378 free_irq(pdev->irq, hw);
4379
4380 return err;
4381 }
4382
4383 /* This driver supports yukon2 chipset only */
4384 static const char *sky2_name(u8 chipid, char *buf, int sz)
4385 {
4386 const char *name[] = {
4387 "XL", /* 0xb3 */
4388 "EC Ultra", /* 0xb4 */
4389 "Extreme", /* 0xb5 */
4390 "EC", /* 0xb6 */
4391 "FE", /* 0xb7 */
4392 "FE+", /* 0xb8 */
4393 "Supreme", /* 0xb9 */
4394 "UL 2", /* 0xba */
4395 };
4396
4397 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4398 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4399 else
4400 snprintf(buf, sz, "(chip %#x)", chipid);
4401 return buf;
4402 }
4403
4404 static int __devinit sky2_probe(struct pci_dev *pdev,
4405 const struct pci_device_id *ent)
4406 {
4407 struct net_device *dev;
4408 struct sky2_hw *hw;
4409 int err, using_dac = 0, wol_default;
4410 u32 reg;
4411 char buf1[16];
4412
4413 err = pci_enable_device(pdev);
4414 if (err) {
4415 dev_err(&pdev->dev, "cannot enable PCI device\n");
4416 goto err_out;
4417 }
4418
4419 /* Get configuration information
4420 * Note: only regular PCI config access once to test for HW issues
4421 * other PCI access through shared memory for speed and to
4422 * avoid MMCONFIG problems.
4423 */
4424 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4425 if (err) {
4426 dev_err(&pdev->dev, "PCI read config failed\n");
4427 goto err_out;
4428 }
4429
4430 if (~reg == 0) {
4431 dev_err(&pdev->dev, "PCI configuration read error\n");
4432 goto err_out;
4433 }
4434
4435 err = pci_request_regions(pdev, DRV_NAME);
4436 if (err) {
4437 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4438 goto err_out_disable;
4439 }
4440
4441 pci_set_master(pdev);
4442
4443 if (sizeof(dma_addr_t) > sizeof(u32) &&
4444 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4445 using_dac = 1;
4446 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4447 if (err < 0) {
4448 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4449 "for consistent allocations\n");
4450 goto err_out_free_regions;
4451 }
4452 } else {
4453 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4454 if (err) {
4455 dev_err(&pdev->dev, "no usable DMA configuration\n");
4456 goto err_out_free_regions;
4457 }
4458 }
4459
4460
4461 #ifdef __BIG_ENDIAN
4462 /* The sk98lin vendor driver uses hardware byte swapping but
4463 * this driver uses software swapping.
4464 */
4465 reg &= ~PCI_REV_DESC;
4466 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4467 if (err) {
4468 dev_err(&pdev->dev, "PCI write config failed\n");
4469 goto err_out_free_regions;
4470 }
4471 #endif
4472
4473 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4474
4475 err = -ENOMEM;
4476 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4477 if (!hw) {
4478 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4479 goto err_out_free_regions;
4480 }
4481
4482 hw->pdev = pdev;
4483
4484 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4485 if (!hw->regs) {
4486 dev_err(&pdev->dev, "cannot map device registers\n");
4487 goto err_out_free_hw;
4488 }
4489
4490 /* ring for status responses */
4491 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4492 if (!hw->st_le)
4493 goto err_out_iounmap;
4494
4495 err = sky2_init(hw);
4496 if (err)
4497 goto err_out_iounmap;
4498
4499 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4500 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4501
4502 sky2_reset(hw);
4503
4504 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4505 if (!dev) {
4506 err = -ENOMEM;
4507 goto err_out_free_pci;
4508 }
4509
4510 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4511 err = sky2_test_msi(hw);
4512 if (err == -EOPNOTSUPP)
4513 pci_disable_msi(pdev);
4514 else if (err)
4515 goto err_out_free_netdev;
4516 }
4517
4518 err = register_netdev(dev);
4519 if (err) {
4520 dev_err(&pdev->dev, "cannot register net device\n");
4521 goto err_out_free_netdev;
4522 }
4523
4524 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4525
4526 err = request_irq(pdev->irq, sky2_intr,
4527 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4528 dev->name, hw);
4529 if (err) {
4530 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4531 goto err_out_unregister;
4532 }
4533 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4534 napi_enable(&hw->napi);
4535
4536 sky2_show_addr(dev);
4537
4538 if (hw->ports > 1) {
4539 struct net_device *dev1;
4540
4541 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4542 if (!dev1)
4543 dev_warn(&pdev->dev, "allocation for second device failed\n");
4544 else if ((err = register_netdev(dev1))) {
4545 dev_warn(&pdev->dev,
4546 "register of second port failed (%d)\n", err);
4547 hw->dev[1] = NULL;
4548 free_netdev(dev1);
4549 } else
4550 sky2_show_addr(dev1);
4551 }
4552
4553 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4554 INIT_WORK(&hw->restart_work, sky2_restart);
4555
4556 pci_set_drvdata(pdev, hw);
4557
4558 return 0;
4559
4560 err_out_unregister:
4561 if (hw->flags & SKY2_HW_USE_MSI)
4562 pci_disable_msi(pdev);
4563 unregister_netdev(dev);
4564 err_out_free_netdev:
4565 free_netdev(dev);
4566 err_out_free_pci:
4567 sky2_write8(hw, B0_CTST, CS_RST_SET);
4568 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4569 err_out_iounmap:
4570 iounmap(hw->regs);
4571 err_out_free_hw:
4572 kfree(hw);
4573 err_out_free_regions:
4574 pci_release_regions(pdev);
4575 err_out_disable:
4576 pci_disable_device(pdev);
4577 err_out:
4578 pci_set_drvdata(pdev, NULL);
4579 return err;
4580 }
4581
4582 static void __devexit sky2_remove(struct pci_dev *pdev)
4583 {
4584 struct sky2_hw *hw = pci_get_drvdata(pdev);
4585 int i;
4586
4587 if (!hw)
4588 return;
4589
4590 del_timer_sync(&hw->watchdog_timer);
4591 cancel_work_sync(&hw->restart_work);
4592
4593 for (i = hw->ports-1; i >= 0; --i)
4594 unregister_netdev(hw->dev[i]);
4595
4596 sky2_write32(hw, B0_IMSK, 0);
4597
4598 sky2_power_aux(hw);
4599
4600 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4601 sky2_write8(hw, B0_CTST, CS_RST_SET);
4602 sky2_read8(hw, B0_CTST);
4603
4604 free_irq(pdev->irq, hw);
4605 if (hw->flags & SKY2_HW_USE_MSI)
4606 pci_disable_msi(pdev);
4607 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4608 pci_release_regions(pdev);
4609 pci_disable_device(pdev);
4610
4611 for (i = hw->ports-1; i >= 0; --i)
4612 free_netdev(hw->dev[i]);
4613
4614 iounmap(hw->regs);
4615 kfree(hw);
4616
4617 pci_set_drvdata(pdev, NULL);
4618 }
4619
4620 #ifdef CONFIG_PM
4621 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4622 {
4623 struct sky2_hw *hw = pci_get_drvdata(pdev);
4624 int i, wol = 0;
4625
4626 if (!hw)
4627 return 0;
4628
4629 del_timer_sync(&hw->watchdog_timer);
4630 cancel_work_sync(&hw->restart_work);
4631
4632 for (i = 0; i < hw->ports; i++) {
4633 struct net_device *dev = hw->dev[i];
4634 struct sky2_port *sky2 = netdev_priv(dev);
4635
4636 netif_device_detach(dev);
4637 if (netif_running(dev))
4638 sky2_down(dev);
4639
4640 if (sky2->wol)
4641 sky2_wol_init(sky2);
4642
4643 wol |= sky2->wol;
4644 }
4645
4646 sky2_write32(hw, B0_IMSK, 0);
4647 napi_disable(&hw->napi);
4648 sky2_power_aux(hw);
4649
4650 pci_save_state(pdev);
4651 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4652 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4653
4654 return 0;
4655 }
4656
4657 static int sky2_resume(struct pci_dev *pdev)
4658 {
4659 struct sky2_hw *hw = pci_get_drvdata(pdev);
4660 int i, err;
4661
4662 if (!hw)
4663 return 0;
4664
4665 err = pci_set_power_state(pdev, PCI_D0);
4666 if (err)
4667 goto out;
4668
4669 err = pci_restore_state(pdev);
4670 if (err)
4671 goto out;
4672
4673 pci_enable_wake(pdev, PCI_D0, 0);
4674
4675 /* Re-enable all clocks */
4676 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4677 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4678 hw->chip_id == CHIP_ID_YUKON_FE_P)
4679 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4680
4681 sky2_reset(hw);
4682 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4683 napi_enable(&hw->napi);
4684
4685 for (i = 0; i < hw->ports; i++) {
4686 struct net_device *dev = hw->dev[i];
4687
4688 netif_device_attach(dev);
4689 if (netif_running(dev)) {
4690 err = sky2_up(dev);
4691 if (err) {
4692 printk(KERN_ERR PFX "%s: could not up: %d\n",
4693 dev->name, err);
4694 rtnl_lock();
4695 dev_close(dev);
4696 rtnl_unlock();
4697 goto out;
4698 }
4699 }
4700 }
4701
4702 return 0;
4703 out:
4704 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4705 pci_disable_device(pdev);
4706 return err;
4707 }
4708 #endif
4709
4710 static void sky2_shutdown(struct pci_dev *pdev)
4711 {
4712 struct sky2_hw *hw = pci_get_drvdata(pdev);
4713 int i, wol = 0;
4714
4715 if (!hw)
4716 return;
4717
4718 del_timer_sync(&hw->watchdog_timer);
4719
4720 for (i = 0; i < hw->ports; i++) {
4721 struct net_device *dev = hw->dev[i];
4722 struct sky2_port *sky2 = netdev_priv(dev);
4723
4724 if (sky2->wol) {
4725 wol = 1;
4726 sky2_wol_init(sky2);
4727 }
4728 }
4729
4730 if (wol)
4731 sky2_power_aux(hw);
4732
4733 pci_enable_wake(pdev, PCI_D3hot, wol);
4734 pci_enable_wake(pdev, PCI_D3cold, wol);
4735
4736 pci_disable_device(pdev);
4737 pci_set_power_state(pdev, PCI_D3hot);
4738 }
4739
4740 static struct pci_driver sky2_driver = {
4741 .name = DRV_NAME,
4742 .id_table = sky2_id_table,
4743 .probe = sky2_probe,
4744 .remove = __devexit_p(sky2_remove),
4745 #ifdef CONFIG_PM
4746 .suspend = sky2_suspend,
4747 .resume = sky2_resume,
4748 #endif
4749 .shutdown = sky2_shutdown,
4750 };
4751
4752 static int __init sky2_init_module(void)
4753 {
4754 pr_info(PFX "driver version " DRV_VERSION "\n");
4755
4756 sky2_debug_init();
4757 return pci_register_driver(&sky2_driver);
4758 }
4759
4760 static void __exit sky2_cleanup_module(void)
4761 {
4762 pci_unregister_driver(&sky2_driver);
4763 sky2_debug_cleanup();
4764 }
4765
4766 module_init(sky2_init_module);
4767 module_exit(sky2_cleanup_module);
4768
4769 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4770 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4771 MODULE_LICENSE("GPL");
4772 MODULE_VERSION(DRV_VERSION);
kernel-based virtual machine