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Merge branch 'fix/hda' into for-linus
[linux-2.6/kvm.git] / drivers / firewire / ohci.c
blob7f03540cabe8b3932021545a6db05aebb3f729b1
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/slab.h>
40 #include <linux/spinlock.h>
41 #include <linux/string.h>
42 #include <linux/time.h>
43
44 #include <asm/byteorder.h>
45 #include <asm/page.h>
46 #include <asm/system.h>
47
48 #ifdef CONFIG_PPC_PMAC
49 #include <asm/pmac_feature.h>
50 #endif
51
52 #include "core.h"
53 #include "ohci.h"
54
55 #define DESCRIPTOR_OUTPUT_MORE 0
56 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
57 #define DESCRIPTOR_INPUT_MORE (2 << 12)
58 #define DESCRIPTOR_INPUT_LAST (3 << 12)
59 #define DESCRIPTOR_STATUS (1 << 11)
60 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
61 #define DESCRIPTOR_PING (1 << 7)
62 #define DESCRIPTOR_YY (1 << 6)
63 #define DESCRIPTOR_NO_IRQ (0 << 4)
64 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
65 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
66 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
67 #define DESCRIPTOR_WAIT (3 << 0)
68
69 struct descriptor {
70 __le16 req_count;
71 __le16 control;
72 __le32 data_address;
73 __le32 branch_address;
74 __le16 res_count;
75 __le16 transfer_status;
76 } __attribute__((aligned(16)));
77
78 #define CONTROL_SET(regs) (regs)
79 #define CONTROL_CLEAR(regs) ((regs) + 4)
80 #define COMMAND_PTR(regs) ((regs) + 12)
81 #define CONTEXT_MATCH(regs) ((regs) + 16)
82
83 struct ar_buffer {
84 struct descriptor descriptor;
85 struct ar_buffer *next;
86 __le32 data[0];
87 };
88
89 struct ar_context {
90 struct fw_ohci *ohci;
91 struct ar_buffer *current_buffer;
92 struct ar_buffer *last_buffer;
93 void *pointer;
94 u32 regs;
95 struct tasklet_struct tasklet;
96 };
97
98 struct context;
99
100 typedef int (*descriptor_callback_t)(struct context *ctx,
101 struct descriptor *d,
102 struct descriptor *last);
103
104 /*
105 * A buffer that contains a block of DMA-able coherent memory used for
106 * storing a portion of a DMA descriptor program.
107 */
108 struct descriptor_buffer {
109 struct list_head list;
110 dma_addr_t buffer_bus;
111 size_t buffer_size;
112 size_t used;
113 struct descriptor buffer[0];
114 };
115
116 struct context {
117 struct fw_ohci *ohci;
118 u32 regs;
119 int total_allocation;
120
121 /*
122 * List of page-sized buffers for storing DMA descriptors.
123 * Head of list contains buffers in use and tail of list contains
124 * free buffers.
125 */
126 struct list_head buffer_list;
127
128 /*
129 * Pointer to a buffer inside buffer_list that contains the tail
130 * end of the current DMA program.
131 */
132 struct descriptor_buffer *buffer_tail;
133
134 /*
135 * The descriptor containing the branch address of the first
136 * descriptor that has not yet been filled by the device.
137 */
138 struct descriptor *last;
139
140 /*
141 * The last descriptor in the DMA program. It contains the branch
142 * address that must be updated upon appending a new descriptor.
143 */
144 struct descriptor *prev;
145
146 descriptor_callback_t callback;
147
148 struct tasklet_struct tasklet;
149 };
150
151 #define IT_HEADER_SY(v) ((v) << 0)
152 #define IT_HEADER_TCODE(v) ((v) << 4)
153 #define IT_HEADER_CHANNEL(v) ((v) << 8)
154 #define IT_HEADER_TAG(v) ((v) << 14)
155 #define IT_HEADER_SPEED(v) ((v) << 16)
156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
157
158 struct iso_context {
159 struct fw_iso_context base;
160 struct context context;
161 int excess_bytes;
162 void *header;
163 size_t header_length;
164 };
165
166 #define CONFIG_ROM_SIZE 1024
167
168 struct fw_ohci {
169 struct fw_card card;
170
171 __iomem char *registers;
172 int node_id;
173 int generation;
174 int request_generation; /* for timestamping incoming requests */
175 unsigned quirks;
176 unsigned int pri_req_max;
177 u32 bus_time;
178 bool is_root;
179 bool csr_state_setclear_abdicate;
180
181 /*
182 * Spinlock for accessing fw_ohci data. Never call out of
183 * this driver with this lock held.
184 */
185 spinlock_t lock;
186
187 struct mutex phy_reg_mutex;
188
189 struct ar_context ar_request_ctx;
190 struct ar_context ar_response_ctx;
191 struct context at_request_ctx;
192 struct context at_response_ctx;
193
194 u32 it_context_mask; /* unoccupied IT contexts */
195 struct iso_context *it_context_list;
196 u64 ir_context_channels; /* unoccupied channels */
197 u32 ir_context_mask; /* unoccupied IR contexts */
198 struct iso_context *ir_context_list;
199 u64 mc_channels; /* channels in use by the multichannel IR context */
200 bool mc_allocated;
201
202 __be32 *config_rom;
203 dma_addr_t config_rom_bus;
204 __be32 *next_config_rom;
205 dma_addr_t next_config_rom_bus;
206 __be32 next_header;
207
208 __le32 *self_id_cpu;
209 dma_addr_t self_id_bus;
210 struct tasklet_struct bus_reset_tasklet;
211
212 u32 self_id_buffer[512];
213 };
214
215 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
216 {
217 return container_of(card, struct fw_ohci, card);
218 }
219
220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
221 #define IR_CONTEXT_BUFFER_FILL 0x80000000
222 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
224 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
225 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
226
227 #define CONTEXT_RUN 0x8000
228 #define CONTEXT_WAKE 0x1000
229 #define CONTEXT_DEAD 0x0800
230 #define CONTEXT_ACTIVE 0x0400
231
232 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
233 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
234 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
235
236 #define OHCI1394_REGISTER_SIZE 0x800
237 #define OHCI_LOOP_COUNT 500
238 #define OHCI1394_PCI_HCI_Control 0x40
239 #define SELF_ID_BUF_SIZE 0x800
240 #define OHCI_TCODE_PHY_PACKET 0x0e
241 #define OHCI_VERSION_1_1 0x010010
242
243 static char ohci_driver_name[] = KBUILD_MODNAME;
244
245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
246 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
247
248 #define QUIRK_CYCLE_TIMER 1
249 #define QUIRK_RESET_PACKET 2
250 #define QUIRK_BE_HEADERS 4
251 #define QUIRK_NO_1394A 8
252 #define QUIRK_NO_MSI 16
253
254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
255 static const struct {
256 unsigned short vendor, device, flags;
257 } ohci_quirks[] = {
258 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
259 QUIRK_RESET_PACKET |
260 QUIRK_NO_1394A},
261 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
262 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
263 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
264 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
265 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
266 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
267 };
268
269 /* This overrides anything that was found in ohci_quirks[]. */
270 static int param_quirks;
271 module_param_named(quirks, param_quirks, int, 0644);
272 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
273 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
274 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
275 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
276 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
277 ", disable MSI = " __stringify(QUIRK_NO_MSI)
278 ")");
279
280 #define OHCI_PARAM_DEBUG_AT_AR 1
281 #define OHCI_PARAM_DEBUG_SELFIDS 2
282 #define OHCI_PARAM_DEBUG_IRQS 4
283 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
284
285 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
286
287 static int param_debug;
288 module_param_named(debug, param_debug, int, 0644);
289 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
290 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
291 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
292 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
293 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
294 ", or a combination, or all = -1)");
295
296 static void log_irqs(u32 evt)
297 {
298 if (likely(!(param_debug &
299 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
300 return;
301
302 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
303 !(evt & OHCI1394_busReset))
304 return;
305
306 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
307 evt & OHCI1394_selfIDComplete ? " selfID" : "",
308 evt & OHCI1394_RQPkt ? " AR_req" : "",
309 evt & OHCI1394_RSPkt ? " AR_resp" : "",
310 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
311 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
312 evt & OHCI1394_isochRx ? " IR" : "",
313 evt & OHCI1394_isochTx ? " IT" : "",
314 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
315 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
316 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
317 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
318 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
319 evt & OHCI1394_busReset ? " busReset" : "",
320 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
321 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
322 OHCI1394_respTxComplete | OHCI1394_isochRx |
323 OHCI1394_isochTx | OHCI1394_postedWriteErr |
324 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
325 OHCI1394_cycleInconsistent |
326 OHCI1394_regAccessFail | OHCI1394_busReset)
327 ? " ?" : "");
328 }
329
330 static const char *speed[] = {
331 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
332 };
333 static const char *power[] = {
334 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
335 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
336 };
337 static const char port[] = { '.', '-', 'p', 'c', };
338
339 static char _p(u32 *s, int shift)
340 {
341 return port[*s >> shift & 3];
342 }
343
344 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
345 {
346 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
347 return;
348
349 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
350 self_id_count, generation, node_id);
351
352 for (; self_id_count--; ++s)
353 if ((*s & 1 << 23) == 0)
354 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
355 "%s gc=%d %s %s%s%s\n",
356 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
357 speed[*s >> 14 & 3], *s >> 16 & 63,
358 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
359 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
360 else
361 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
362 *s, *s >> 24 & 63,
363 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
364 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
365 }
366
367 static const char *evts[] = {
368 [0x00] = "evt_no_status", [0x01] = "-reserved-",
369 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
370 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
371 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
372 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
373 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
374 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
375 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
376 [0x10] = "-reserved-", [0x11] = "ack_complete",
377 [0x12] = "ack_pending ", [0x13] = "-reserved-",
378 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
379 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
380 [0x18] = "-reserved-", [0x19] = "-reserved-",
381 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
382 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
383 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
384 [0x20] = "pending/cancelled",
385 };
386 static const char *tcodes[] = {
387 [0x0] = "QW req", [0x1] = "BW req",
388 [0x2] = "W resp", [0x3] = "-reserved-",
389 [0x4] = "QR req", [0x5] = "BR req",
390 [0x6] = "QR resp", [0x7] = "BR resp",
391 [0x8] = "cycle start", [0x9] = "Lk req",
392 [0xa] = "async stream packet", [0xb] = "Lk resp",
393 [0xc] = "-reserved-", [0xd] = "-reserved-",
394 [0xe] = "link internal", [0xf] = "-reserved-",
395 };
396 static const char *phys[] = {
397 [0x0] = "phy config packet", [0x1] = "link-on packet",
398 [0x2] = "self-id packet", [0x3] = "-reserved-",
399 };
400
401 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
402 {
403 int tcode = header[0] >> 4 & 0xf;
404 char specific[12];
405
406 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
407 return;
408
409 if (unlikely(evt >= ARRAY_SIZE(evts)))
410 evt = 0x1f;
411
412 if (evt == OHCI1394_evt_bus_reset) {
413 fw_notify("A%c evt_bus_reset, generation %d\n",
414 dir, (header[2] >> 16) & 0xff);
415 return;
416 }
417
418 if (header[0] == ~header[1]) {
419 fw_notify("A%c %s, %s, %08x\n",
420 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
421 return;
422 }
423
424 switch (tcode) {
425 case 0x0: case 0x6: case 0x8:
426 snprintf(specific, sizeof(specific), " = %08x",
427 be32_to_cpu((__force __be32)header[3]));
428 break;
429 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
430 snprintf(specific, sizeof(specific), " %x,%x",
431 header[3] >> 16, header[3] & 0xffff);
432 break;
433 default:
434 specific[0] = '\0';
435 }
436
437 switch (tcode) {
438 case 0xe: case 0xa:
439 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
440 break;
441 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
442 fw_notify("A%c spd %x tl %02x, "
443 "%04x -> %04x, %s, "
444 "%s, %04x%08x%s\n",
445 dir, speed, header[0] >> 10 & 0x3f,
446 header[1] >> 16, header[0] >> 16, evts[evt],
447 tcodes[tcode], header[1] & 0xffff, header[2], specific);
448 break;
449 default:
450 fw_notify("A%c spd %x tl %02x, "
451 "%04x -> %04x, %s, "
452 "%s%s\n",
453 dir, speed, header[0] >> 10 & 0x3f,
454 header[1] >> 16, header[0] >> 16, evts[evt],
455 tcodes[tcode], specific);
456 }
457 }
458
459 #else
460
461 #define param_debug 0
462 static inline void log_irqs(u32 evt) {}
463 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
464 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
465
466 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
467
468 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
469 {
470 writel(data, ohci->registers + offset);
471 }
472
473 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
474 {
475 return readl(ohci->registers + offset);
476 }
477
478 static inline void flush_writes(const struct fw_ohci *ohci)
479 {
480 /* Do a dummy read to flush writes. */
481 reg_read(ohci, OHCI1394_Version);
482 }
483
484 static int read_phy_reg(struct fw_ohci *ohci, int addr)
485 {
486 u32 val;
487 int i;
488
489 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
490 for (i = 0; i < 3 + 100; i++) {
491 val = reg_read(ohci, OHCI1394_PhyControl);
492 if (val & OHCI1394_PhyControl_ReadDone)
493 return OHCI1394_PhyControl_ReadData(val);
494
495 /*
496 * Try a few times without waiting. Sleeping is necessary
497 * only when the link/PHY interface is busy.
498 */
499 if (i >= 3)
500 msleep(1);
501 }
502 fw_error("failed to read phy reg\n");
503
504 return -EBUSY;
505 }
506
507 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
508 {
509 int i;
510
511 reg_write(ohci, OHCI1394_PhyControl,
512 OHCI1394_PhyControl_Write(addr, val));
513 for (i = 0; i < 3 + 100; i++) {
514 val = reg_read(ohci, OHCI1394_PhyControl);
515 if (!(val & OHCI1394_PhyControl_WritePending))
516 return 0;
517
518 if (i >= 3)
519 msleep(1);
520 }
521 fw_error("failed to write phy reg\n");
522
523 return -EBUSY;
524 }
525
526 static int update_phy_reg(struct fw_ohci *ohci, int addr,
527 int clear_bits, int set_bits)
528 {
529 int ret = read_phy_reg(ohci, addr);
530 if (ret < 0)
531 return ret;
532
533 /*
534 * The interrupt status bits are cleared by writing a one bit.
535 * Avoid clearing them unless explicitly requested in set_bits.
536 */
537 if (addr == 5)
538 clear_bits |= PHY_INT_STATUS_BITS;
539
540 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
541 }
542
543 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
544 {
545 int ret;
546
547 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
548 if (ret < 0)
549 return ret;
550
551 return read_phy_reg(ohci, addr);
552 }
553
554 static int ohci_read_phy_reg(struct fw_card *card, int addr)
555 {
556 struct fw_ohci *ohci = fw_ohci(card);
557 int ret;
558
559 mutex_lock(&ohci->phy_reg_mutex);
560 ret = read_phy_reg(ohci, addr);
561 mutex_unlock(&ohci->phy_reg_mutex);
562
563 return ret;
564 }
565
566 static int ohci_update_phy_reg(struct fw_card *card, int addr,
567 int clear_bits, int set_bits)
568 {
569 struct fw_ohci *ohci = fw_ohci(card);
570 int ret;
571
572 mutex_lock(&ohci->phy_reg_mutex);
573 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
574 mutex_unlock(&ohci->phy_reg_mutex);
575
576 return ret;
577 }
578
579 static int ar_context_add_page(struct ar_context *ctx)
580 {
581 struct device *dev = ctx->ohci->card.device;
582 struct ar_buffer *ab;
583 dma_addr_t uninitialized_var(ab_bus);
584 size_t offset;
585
586 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
587 if (ab == NULL)
588 return -ENOMEM;
589
590 ab->next = NULL;
591 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
592 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
593 DESCRIPTOR_STATUS |
594 DESCRIPTOR_BRANCH_ALWAYS);
595 offset = offsetof(struct ar_buffer, data);
596 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
597 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
598 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
599 ab->descriptor.branch_address = 0;
600
601 wmb(); /* finish init of new descriptors before branch_address update */
602 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
603 ctx->last_buffer->next = ab;
604 ctx->last_buffer = ab;
605
606 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
607 flush_writes(ctx->ohci);
608
609 return 0;
610 }
611
612 static void ar_context_release(struct ar_context *ctx)
613 {
614 struct ar_buffer *ab, *ab_next;
615 size_t offset;
616 dma_addr_t ab_bus;
617
618 for (ab = ctx->current_buffer; ab; ab = ab_next) {
619 ab_next = ab->next;
620 offset = offsetof(struct ar_buffer, data);
621 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
622 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
623 ab, ab_bus);
624 }
625 }
626
627 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
628 #define cond_le32_to_cpu(v) \
629 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
630 #else
631 #define cond_le32_to_cpu(v) le32_to_cpu(v)
632 #endif
633
634 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
635 {
636 struct fw_ohci *ohci = ctx->ohci;
637 struct fw_packet p;
638 u32 status, length, tcode;
639 int evt;
640
641 p.header[0] = cond_le32_to_cpu(buffer[0]);
642 p.header[1] = cond_le32_to_cpu(buffer[1]);
643 p.header[2] = cond_le32_to_cpu(buffer[2]);
644
645 tcode = (p.header[0] >> 4) & 0x0f;
646 switch (tcode) {
647 case TCODE_WRITE_QUADLET_REQUEST:
648 case TCODE_READ_QUADLET_RESPONSE:
649 p.header[3] = (__force __u32) buffer[3];
650 p.header_length = 16;
651 p.payload_length = 0;
652 break;
653
654 case TCODE_READ_BLOCK_REQUEST :
655 p.header[3] = cond_le32_to_cpu(buffer[3]);
656 p.header_length = 16;
657 p.payload_length = 0;
658 break;
659
660 case TCODE_WRITE_BLOCK_REQUEST:
661 case TCODE_READ_BLOCK_RESPONSE:
662 case TCODE_LOCK_REQUEST:
663 case TCODE_LOCK_RESPONSE:
664 p.header[3] = cond_le32_to_cpu(buffer[3]);
665 p.header_length = 16;
666 p.payload_length = p.header[3] >> 16;
667 break;
668
669 case TCODE_WRITE_RESPONSE:
670 case TCODE_READ_QUADLET_REQUEST:
671 case OHCI_TCODE_PHY_PACKET:
672 p.header_length = 12;
673 p.payload_length = 0;
674 break;
675
676 default:
677 /* FIXME: Stop context, discard everything, and restart? */
678 p.header_length = 0;
679 p.payload_length = 0;
680 }
681
682 p.payload = (void *) buffer + p.header_length;
683
684 /* FIXME: What to do about evt_* errors? */
685 length = (p.header_length + p.payload_length + 3) / 4;
686 status = cond_le32_to_cpu(buffer[length]);
687 evt = (status >> 16) & 0x1f;
688
689 p.ack = evt - 16;
690 p.speed = (status >> 21) & 0x7;
691 p.timestamp = status & 0xffff;
692 p.generation = ohci->request_generation;
693
694 log_ar_at_event('R', p.speed, p.header, evt);
695
696 /*
697 * The OHCI bus reset handler synthesizes a phy packet with
698 * the new generation number when a bus reset happens (see
699 * section 8.4.2.3). This helps us determine when a request
700 * was received and make sure we send the response in the same
701 * generation. We only need this for requests; for responses
702 * we use the unique tlabel for finding the matching
703 * request.
704 *
705 * Alas some chips sometimes emit bus reset packets with a
706 * wrong generation. We set the correct generation for these
707 * at a slightly incorrect time (in bus_reset_tasklet).
708 */
709 if (evt == OHCI1394_evt_bus_reset) {
710 if (!(ohci->quirks & QUIRK_RESET_PACKET))
711 ohci->request_generation = (p.header[2] >> 16) & 0xff;
712 } else if (ctx == &ohci->ar_request_ctx) {
713 fw_core_handle_request(&ohci->card, &p);
714 } else {
715 fw_core_handle_response(&ohci->card, &p);
716 }
717
718 return buffer + length + 1;
719 }
720
721 static void ar_context_tasklet(unsigned long data)
722 {
723 struct ar_context *ctx = (struct ar_context *)data;
724 struct fw_ohci *ohci = ctx->ohci;
725 struct ar_buffer *ab;
726 struct descriptor *d;
727 void *buffer, *end;
728
729 ab = ctx->current_buffer;
730 d = &ab->descriptor;
731
732 if (d->res_count == 0) {
733 size_t size, rest, offset;
734 dma_addr_t start_bus;
735 void *start;
736
737 /*
738 * This descriptor is finished and we may have a
739 * packet split across this and the next buffer. We
740 * reuse the page for reassembling the split packet.
741 */
742
743 offset = offsetof(struct ar_buffer, data);
744 start = buffer = ab;
745 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
746
747 ab = ab->next;
748 d = &ab->descriptor;
749 size = buffer + PAGE_SIZE - ctx->pointer;
750 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
751 memmove(buffer, ctx->pointer, size);
752 memcpy(buffer + size, ab->data, rest);
753 ctx->current_buffer = ab;
754 ctx->pointer = (void *) ab->data + rest;
755 end = buffer + size + rest;
756
757 while (buffer < end)
758 buffer = handle_ar_packet(ctx, buffer);
759
760 dma_free_coherent(ohci->card.device, PAGE_SIZE,
761 start, start_bus);
762 ar_context_add_page(ctx);
763 } else {
764 buffer = ctx->pointer;
765 ctx->pointer = end =
766 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
767
768 while (buffer < end)
769 buffer = handle_ar_packet(ctx, buffer);
770 }
771 }
772
773 static int ar_context_init(struct ar_context *ctx,
774 struct fw_ohci *ohci, u32 regs)
775 {
776 struct ar_buffer ab;
777
778 ctx->regs = regs;
779 ctx->ohci = ohci;
780 ctx->last_buffer = &ab;
781 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
782
783 ar_context_add_page(ctx);
784 ar_context_add_page(ctx);
785 ctx->current_buffer = ab.next;
786 ctx->pointer = ctx->current_buffer->data;
787
788 return 0;
789 }
790
791 static void ar_context_run(struct ar_context *ctx)
792 {
793 struct ar_buffer *ab = ctx->current_buffer;
794 dma_addr_t ab_bus;
795 size_t offset;
796
797 offset = offsetof(struct ar_buffer, data);
798 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
799
800 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
801 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
802 flush_writes(ctx->ohci);
803 }
804
805 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
806 {
807 int b, key;
808
809 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
810 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
811
812 /* figure out which descriptor the branch address goes in */
813 if (z == 2 && (b == 3 || key == 2))
814 return d;
815 else
816 return d + z - 1;
817 }
818
819 static void context_tasklet(unsigned long data)
820 {
821 struct context *ctx = (struct context *) data;
822 struct descriptor *d, *last;
823 u32 address;
824 int z;
825 struct descriptor_buffer *desc;
826
827 desc = list_entry(ctx->buffer_list.next,
828 struct descriptor_buffer, list);
829 last = ctx->last;
830 while (last->branch_address != 0) {
831 struct descriptor_buffer *old_desc = desc;
832 address = le32_to_cpu(last->branch_address);
833 z = address & 0xf;
834 address &= ~0xf;
835
836 /* If the branch address points to a buffer outside of the
837 * current buffer, advance to the next buffer. */
838 if (address < desc->buffer_bus ||
839 address >= desc->buffer_bus + desc->used)
840 desc = list_entry(desc->list.next,
841 struct descriptor_buffer, list);
842 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
843 last = find_branch_descriptor(d, z);
844
845 if (!ctx->callback(ctx, d, last))
846 break;
847
848 if (old_desc != desc) {
849 /* If we've advanced to the next buffer, move the
850 * previous buffer to the free list. */
851 unsigned long flags;
852 old_desc->used = 0;
853 spin_lock_irqsave(&ctx->ohci->lock, flags);
854 list_move_tail(&old_desc->list, &ctx->buffer_list);
855 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
856 }
857 ctx->last = last;
858 }
859 }
860
861 /*
862 * Allocate a new buffer and add it to the list of free buffers for this
863 * context. Must be called with ohci->lock held.
864 */
865 static int context_add_buffer(struct context *ctx)
866 {
867 struct descriptor_buffer *desc;
868 dma_addr_t uninitialized_var(bus_addr);
869 int offset;
870
871 /*
872 * 16MB of descriptors should be far more than enough for any DMA
873 * program. This will catch run-away userspace or DoS attacks.
874 */
875 if (ctx->total_allocation >= 16*1024*1024)
876 return -ENOMEM;
877
878 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
879 &bus_addr, GFP_ATOMIC);
880 if (!desc)
881 return -ENOMEM;
882
883 offset = (void *)&desc->buffer - (void *)desc;
884 desc->buffer_size = PAGE_SIZE - offset;
885 desc->buffer_bus = bus_addr + offset;
886 desc->used = 0;
887
888 list_add_tail(&desc->list, &ctx->buffer_list);
889 ctx->total_allocation += PAGE_SIZE;
890
891 return 0;
892 }
893
894 static int context_init(struct context *ctx, struct fw_ohci *ohci,
895 u32 regs, descriptor_callback_t callback)
896 {
897 ctx->ohci = ohci;
898 ctx->regs = regs;
899 ctx->total_allocation = 0;
900
901 INIT_LIST_HEAD(&ctx->buffer_list);
902 if (context_add_buffer(ctx) < 0)
903 return -ENOMEM;
904
905 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
906 struct descriptor_buffer, list);
907
908 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
909 ctx->callback = callback;
910
911 /*
912 * We put a dummy descriptor in the buffer that has a NULL
913 * branch address and looks like it's been sent. That way we
914 * have a descriptor to append DMA programs to.
915 */
916 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
917 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
918 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
919 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
920 ctx->last = ctx->buffer_tail->buffer;
921 ctx->prev = ctx->buffer_tail->buffer;
922
923 return 0;
924 }
925
926 static void context_release(struct context *ctx)
927 {
928 struct fw_card *card = &ctx->ohci->card;
929 struct descriptor_buffer *desc, *tmp;
930
931 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
932 dma_free_coherent(card->device, PAGE_SIZE, desc,
933 desc->buffer_bus -
934 ((void *)&desc->buffer - (void *)desc));
935 }
936
937 /* Must be called with ohci->lock held */
938 static struct descriptor *context_get_descriptors(struct context *ctx,
939 int z, dma_addr_t *d_bus)
940 {
941 struct descriptor *d = NULL;
942 struct descriptor_buffer *desc = ctx->buffer_tail;
943
944 if (z * sizeof(*d) > desc->buffer_size)
945 return NULL;
946
947 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
948 /* No room for the descriptor in this buffer, so advance to the
949 * next one. */
950
951 if (desc->list.next == &ctx->buffer_list) {
952 /* If there is no free buffer next in the list,
953 * allocate one. */
954 if (context_add_buffer(ctx) < 0)
955 return NULL;
956 }
957 desc = list_entry(desc->list.next,
958 struct descriptor_buffer, list);
959 ctx->buffer_tail = desc;
960 }
961
962 d = desc->buffer + desc->used / sizeof(*d);
963 memset(d, 0, z * sizeof(*d));
964 *d_bus = desc->buffer_bus + desc->used;
965
966 return d;
967 }
968
969 static void context_run(struct context *ctx, u32 extra)
970 {
971 struct fw_ohci *ohci = ctx->ohci;
972
973 reg_write(ohci, COMMAND_PTR(ctx->regs),
974 le32_to_cpu(ctx->last->branch_address));
975 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
976 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
977 flush_writes(ohci);
978 }
979
980 static void context_append(struct context *ctx,
981 struct descriptor *d, int z, int extra)
982 {
983 dma_addr_t d_bus;
984 struct descriptor_buffer *desc = ctx->buffer_tail;
985
986 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
987
988 desc->used += (z + extra) * sizeof(*d);
989
990 wmb(); /* finish init of new descriptors before branch_address update */
991 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
992 ctx->prev = find_branch_descriptor(d, z);
993
994 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
995 flush_writes(ctx->ohci);
996 }
997
998 static void context_stop(struct context *ctx)
999 {
1000 u32 reg;
1001 int i;
1002
1003 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1004 flush_writes(ctx->ohci);
1005
1006 for (i = 0; i < 10; i++) {
1007 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1008 if ((reg & CONTEXT_ACTIVE) == 0)
1009 return;
1010
1011 mdelay(1);
1012 }
1013 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1014 }
1015
1016 struct driver_data {
1017 struct fw_packet *packet;
1018 };
1019
1020 /*
1021 * This function apppends a packet to the DMA queue for transmission.
1022 * Must always be called with the ochi->lock held to ensure proper
1023 * generation handling and locking around packet queue manipulation.
1024 */
1025 static int at_context_queue_packet(struct context *ctx,
1026 struct fw_packet *packet)
1027 {
1028 struct fw_ohci *ohci = ctx->ohci;
1029 dma_addr_t d_bus, uninitialized_var(payload_bus);
1030 struct driver_data *driver_data;
1031 struct descriptor *d, *last;
1032 __le32 *header;
1033 int z, tcode;
1034 u32 reg;
1035
1036 d = context_get_descriptors(ctx, 4, &d_bus);
1037 if (d == NULL) {
1038 packet->ack = RCODE_SEND_ERROR;
1039 return -1;
1040 }
1041
1042 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1043 d[0].res_count = cpu_to_le16(packet->timestamp);
1044
1045 /*
1046 * The DMA format for asyncronous link packets is different
1047 * from the IEEE1394 layout, so shift the fields around
1048 * accordingly. If header_length is 8, it's a PHY packet, to
1049 * which we need to prepend an extra quadlet.
1050 */
1051
1052 header = (__le32 *) &d[1];
1053 switch (packet->header_length) {
1054 case 16:
1055 case 12:
1056 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1057 (packet->speed << 16));
1058 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1059 (packet->header[0] & 0xffff0000));
1060 header[2] = cpu_to_le32(packet->header[2]);
1061
1062 tcode = (packet->header[0] >> 4) & 0x0f;
1063 if (TCODE_IS_BLOCK_PACKET(tcode))
1064 header[3] = cpu_to_le32(packet->header[3]);
1065 else
1066 header[3] = (__force __le32) packet->header[3];
1067
1068 d[0].req_count = cpu_to_le16(packet->header_length);
1069 break;
1070
1071 case 8:
1072 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1073 (packet->speed << 16));
1074 header[1] = cpu_to_le32(packet->header[0]);
1075 header[2] = cpu_to_le32(packet->header[1]);
1076 d[0].req_count = cpu_to_le16(12);
1077
1078 if (is_ping_packet(packet->header))
1079 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1080 break;
1081
1082 case 4:
1083 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1084 (packet->speed << 16));
1085 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1086 d[0].req_count = cpu_to_le16(8);
1087 break;
1088
1089 default:
1090 /* BUG(); */
1091 packet->ack = RCODE_SEND_ERROR;
1092 return -1;
1093 }
1094
1095 driver_data = (struct driver_data *) &d[3];
1096 driver_data->packet = packet;
1097 packet->driver_data = driver_data;
1098
1099 if (packet->payload_length > 0) {
1100 payload_bus =
1101 dma_map_single(ohci->card.device, packet->payload,
1102 packet->payload_length, DMA_TO_DEVICE);
1103 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1104 packet->ack = RCODE_SEND_ERROR;
1105 return -1;
1106 }
1107 packet->payload_bus = payload_bus;
1108 packet->payload_mapped = true;
1109
1110 d[2].req_count = cpu_to_le16(packet->payload_length);
1111 d[2].data_address = cpu_to_le32(payload_bus);
1112 last = &d[2];
1113 z = 3;
1114 } else {
1115 last = &d[0];
1116 z = 2;
1117 }
1118
1119 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1120 DESCRIPTOR_IRQ_ALWAYS |
1121 DESCRIPTOR_BRANCH_ALWAYS);
1122
1123 /*
1124 * If the controller and packet generations don't match, we need to
1125 * bail out and try again. If IntEvent.busReset is set, the AT context
1126 * is halted, so appending to the context and trying to run it is
1127 * futile. Most controllers do the right thing and just flush the AT
1128 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1129 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1130 * up stalling out. So we just bail out in software and try again
1131 * later, and everyone is happy.
1132 * FIXME: Document how the locking works.
1133 */
1134 if (ohci->generation != packet->generation ||
1135 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1136 if (packet->payload_mapped)
1137 dma_unmap_single(ohci->card.device, payload_bus,
1138 packet->payload_length, DMA_TO_DEVICE);
1139 packet->ack = RCODE_GENERATION;
1140 return -1;
1141 }
1142
1143 context_append(ctx, d, z, 4 - z);
1144
1145 /* If the context isn't already running, start it up. */
1146 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1147 if ((reg & CONTEXT_RUN) == 0)
1148 context_run(ctx, 0);
1149
1150 return 0;
1151 }
1152
1153 static int handle_at_packet(struct context *context,
1154 struct descriptor *d,
1155 struct descriptor *last)
1156 {
1157 struct driver_data *driver_data;
1158 struct fw_packet *packet;
1159 struct fw_ohci *ohci = context->ohci;
1160 int evt;
1161
1162 if (last->transfer_status == 0)
1163 /* This descriptor isn't done yet, stop iteration. */
1164 return 0;
1165
1166 driver_data = (struct driver_data *) &d[3];
1167 packet = driver_data->packet;
1168 if (packet == NULL)
1169 /* This packet was cancelled, just continue. */
1170 return 1;
1171
1172 if (packet->payload_mapped)
1173 dma_unmap_single(ohci->card.device, packet->payload_bus,
1174 packet->payload_length, DMA_TO_DEVICE);
1175
1176 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1177 packet->timestamp = le16_to_cpu(last->res_count);
1178
1179 log_ar_at_event('T', packet->speed, packet->header, evt);
1180
1181 switch (evt) {
1182 case OHCI1394_evt_timeout:
1183 /* Async response transmit timed out. */
1184 packet->ack = RCODE_CANCELLED;
1185 break;
1186
1187 case OHCI1394_evt_flushed:
1188 /*
1189 * The packet was flushed should give same error as
1190 * when we try to use a stale generation count.
1191 */
1192 packet->ack = RCODE_GENERATION;
1193 break;
1194
1195 case OHCI1394_evt_missing_ack:
1196 /*
1197 * Using a valid (current) generation count, but the
1198 * node is not on the bus or not sending acks.
1199 */
1200 packet->ack = RCODE_NO_ACK;
1201 break;
1202
1203 case ACK_COMPLETE + 0x10:
1204 case ACK_PENDING + 0x10:
1205 case ACK_BUSY_X + 0x10:
1206 case ACK_BUSY_A + 0x10:
1207 case ACK_BUSY_B + 0x10:
1208 case ACK_DATA_ERROR + 0x10:
1209 case ACK_TYPE_ERROR + 0x10:
1210 packet->ack = evt - 0x10;
1211 break;
1212
1213 default:
1214 packet->ack = RCODE_SEND_ERROR;
1215 break;
1216 }
1217
1218 packet->callback(packet, &ohci->card, packet->ack);
1219
1220 return 1;
1221 }
1222
1223 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1224 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1225 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1226 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1227 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1228
1229 static void handle_local_rom(struct fw_ohci *ohci,
1230 struct fw_packet *packet, u32 csr)
1231 {
1232 struct fw_packet response;
1233 int tcode, length, i;
1234
1235 tcode = HEADER_GET_TCODE(packet->header[0]);
1236 if (TCODE_IS_BLOCK_PACKET(tcode))
1237 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1238 else
1239 length = 4;
1240
1241 i = csr - CSR_CONFIG_ROM;
1242 if (i + length > CONFIG_ROM_SIZE) {
1243 fw_fill_response(&response, packet->header,
1244 RCODE_ADDRESS_ERROR, NULL, 0);
1245 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1246 fw_fill_response(&response, packet->header,
1247 RCODE_TYPE_ERROR, NULL, 0);
1248 } else {
1249 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1250 (void *) ohci->config_rom + i, length);
1251 }
1252
1253 fw_core_handle_response(&ohci->card, &response);
1254 }
1255
1256 static void handle_local_lock(struct fw_ohci *ohci,
1257 struct fw_packet *packet, u32 csr)
1258 {
1259 struct fw_packet response;
1260 int tcode, length, ext_tcode, sel, try;
1261 __be32 *payload, lock_old;
1262 u32 lock_arg, lock_data;
1263
1264 tcode = HEADER_GET_TCODE(packet->header[0]);
1265 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1266 payload = packet->payload;
1267 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1268
1269 if (tcode == TCODE_LOCK_REQUEST &&
1270 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1271 lock_arg = be32_to_cpu(payload[0]);
1272 lock_data = be32_to_cpu(payload[1]);
1273 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1274 lock_arg = 0;
1275 lock_data = 0;
1276 } else {
1277 fw_fill_response(&response, packet->header,
1278 RCODE_TYPE_ERROR, NULL, 0);
1279 goto out;
1280 }
1281
1282 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1283 reg_write(ohci, OHCI1394_CSRData, lock_data);
1284 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1285 reg_write(ohci, OHCI1394_CSRControl, sel);
1286
1287 for (try = 0; try < 20; try++)
1288 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1289 lock_old = cpu_to_be32(reg_read(ohci,
1290 OHCI1394_CSRData));
1291 fw_fill_response(&response, packet->header,
1292 RCODE_COMPLETE,
1293 &lock_old, sizeof(lock_old));
1294 goto out;
1295 }
1296
1297 fw_error("swap not done (CSR lock timeout)\n");
1298 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1299
1300 out:
1301 fw_core_handle_response(&ohci->card, &response);
1302 }
1303
1304 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1305 {
1306 u64 offset, csr;
1307
1308 if (ctx == &ctx->ohci->at_request_ctx) {
1309 packet->ack = ACK_PENDING;
1310 packet->callback(packet, &ctx->ohci->card, packet->ack);
1311 }
1312
1313 offset =
1314 ((unsigned long long)
1315 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1316 packet->header[2];
1317 csr = offset - CSR_REGISTER_BASE;
1318
1319 /* Handle config rom reads. */
1320 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1321 handle_local_rom(ctx->ohci, packet, csr);
1322 else switch (csr) {
1323 case CSR_BUS_MANAGER_ID:
1324 case CSR_BANDWIDTH_AVAILABLE:
1325 case CSR_CHANNELS_AVAILABLE_HI:
1326 case CSR_CHANNELS_AVAILABLE_LO:
1327 handle_local_lock(ctx->ohci, packet, csr);
1328 break;
1329 default:
1330 if (ctx == &ctx->ohci->at_request_ctx)
1331 fw_core_handle_request(&ctx->ohci->card, packet);
1332 else
1333 fw_core_handle_response(&ctx->ohci->card, packet);
1334 break;
1335 }
1336
1337 if (ctx == &ctx->ohci->at_response_ctx) {
1338 packet->ack = ACK_COMPLETE;
1339 packet->callback(packet, &ctx->ohci->card, packet->ack);
1340 }
1341 }
1342
1343 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1344 {
1345 unsigned long flags;
1346 int ret;
1347
1348 spin_lock_irqsave(&ctx->ohci->lock, flags);
1349
1350 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1351 ctx->ohci->generation == packet->generation) {
1352 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1353 handle_local_request(ctx, packet);
1354 return;
1355 }
1356
1357 ret = at_context_queue_packet(ctx, packet);
1358 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1359
1360 if (ret < 0)
1361 packet->callback(packet, &ctx->ohci->card, packet->ack);
1362
1363 }
1364
1365 static u32 cycle_timer_ticks(u32 cycle_timer)
1366 {
1367 u32 ticks;
1368
1369 ticks = cycle_timer & 0xfff;
1370 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1371 ticks += (3072 * 8000) * (cycle_timer >> 25);
1372
1373 return ticks;
1374 }
1375
1376 /*
1377 * Some controllers exhibit one or more of the following bugs when updating the
1378 * iso cycle timer register:
1379 * - When the lowest six bits are wrapping around to zero, a read that happens
1380 * at the same time will return garbage in the lowest ten bits.
1381 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1382 * not incremented for about 60 ns.
1383 * - Occasionally, the entire register reads zero.
1384 *
1385 * To catch these, we read the register three times and ensure that the
1386 * difference between each two consecutive reads is approximately the same, i.e.
1387 * less than twice the other. Furthermore, any negative difference indicates an
1388 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1389 * execute, so we have enough precision to compute the ratio of the differences.)
1390 */
1391 static u32 get_cycle_time(struct fw_ohci *ohci)
1392 {
1393 u32 c0, c1, c2;
1394 u32 t0, t1, t2;
1395 s32 diff01, diff12;
1396 int i;
1397
1398 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1399
1400 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1401 i = 0;
1402 c1 = c2;
1403 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1404 do {
1405 c0 = c1;
1406 c1 = c2;
1407 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1408 t0 = cycle_timer_ticks(c0);
1409 t1 = cycle_timer_ticks(c1);
1410 t2 = cycle_timer_ticks(c2);
1411 diff01 = t1 - t0;
1412 diff12 = t2 - t1;
1413 } while ((diff01 <= 0 || diff12 <= 0 ||
1414 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1415 && i++ < 20);
1416 }
1417
1418 return c2;
1419 }
1420
1421 /*
1422 * This function has to be called at least every 64 seconds. The bus_time
1423 * field stores not only the upper 25 bits of the BUS_TIME register but also
1424 * the most significant bit of the cycle timer in bit 6 so that we can detect
1425 * changes in this bit.
1426 */
1427 static u32 update_bus_time(struct fw_ohci *ohci)
1428 {
1429 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1430
1431 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1432 ohci->bus_time += 0x40;
1433
1434 return ohci->bus_time | cycle_time_seconds;
1435 }
1436
1437 static void bus_reset_tasklet(unsigned long data)
1438 {
1439 struct fw_ohci *ohci = (struct fw_ohci *)data;
1440 int self_id_count, i, j, reg;
1441 int generation, new_generation;
1442 unsigned long flags;
1443 void *free_rom = NULL;
1444 dma_addr_t free_rom_bus = 0;
1445 bool is_new_root;
1446
1447 reg = reg_read(ohci, OHCI1394_NodeID);
1448 if (!(reg & OHCI1394_NodeID_idValid)) {
1449 fw_notify("node ID not valid, new bus reset in progress\n");
1450 return;
1451 }
1452 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1453 fw_notify("malconfigured bus\n");
1454 return;
1455 }
1456 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1457 OHCI1394_NodeID_nodeNumber);
1458
1459 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1460 if (!(ohci->is_root && is_new_root))
1461 reg_write(ohci, OHCI1394_LinkControlSet,
1462 OHCI1394_LinkControl_cycleMaster);
1463 ohci->is_root = is_new_root;
1464
1465 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1466 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1467 fw_notify("inconsistent self IDs\n");
1468 return;
1469 }
1470 /*
1471 * The count in the SelfIDCount register is the number of
1472 * bytes in the self ID receive buffer. Since we also receive
1473 * the inverted quadlets and a header quadlet, we shift one
1474 * bit extra to get the actual number of self IDs.
1475 */
1476 self_id_count = (reg >> 3) & 0xff;
1477 if (self_id_count == 0 || self_id_count > 252) {
1478 fw_notify("inconsistent self IDs\n");
1479 return;
1480 }
1481 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1482 rmb();
1483
1484 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1485 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1486 fw_notify("inconsistent self IDs\n");
1487 return;
1488 }
1489 ohci->self_id_buffer[j] =
1490 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1491 }
1492 rmb();
1493
1494 /*
1495 * Check the consistency of the self IDs we just read. The
1496 * problem we face is that a new bus reset can start while we
1497 * read out the self IDs from the DMA buffer. If this happens,
1498 * the DMA buffer will be overwritten with new self IDs and we
1499 * will read out inconsistent data. The OHCI specification
1500 * (section 11.2) recommends a technique similar to
1501 * linux/seqlock.h, where we remember the generation of the
1502 * self IDs in the buffer before reading them out and compare
1503 * it to the current generation after reading them out. If
1504 * the two generations match we know we have a consistent set
1505 * of self IDs.
1506 */
1507
1508 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1509 if (new_generation != generation) {
1510 fw_notify("recursive bus reset detected, "
1511 "discarding self ids\n");
1512 return;
1513 }
1514
1515 /* FIXME: Document how the locking works. */
1516 spin_lock_irqsave(&ohci->lock, flags);
1517
1518 ohci->generation = generation;
1519 context_stop(&ohci->at_request_ctx);
1520 context_stop(&ohci->at_response_ctx);
1521 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1522
1523 if (ohci->quirks & QUIRK_RESET_PACKET)
1524 ohci->request_generation = generation;
1525
1526 /*
1527 * This next bit is unrelated to the AT context stuff but we
1528 * have to do it under the spinlock also. If a new config rom
1529 * was set up before this reset, the old one is now no longer
1530 * in use and we can free it. Update the config rom pointers
1531 * to point to the current config rom and clear the
1532 * next_config_rom pointer so a new update can take place.
1533 */
1534
1535 if (ohci->next_config_rom != NULL) {
1536 if (ohci->next_config_rom != ohci->config_rom) {
1537 free_rom = ohci->config_rom;
1538 free_rom_bus = ohci->config_rom_bus;
1539 }
1540 ohci->config_rom = ohci->next_config_rom;
1541 ohci->config_rom_bus = ohci->next_config_rom_bus;
1542 ohci->next_config_rom = NULL;
1543
1544 /*
1545 * Restore config_rom image and manually update
1546 * config_rom registers. Writing the header quadlet
1547 * will indicate that the config rom is ready, so we
1548 * do that last.
1549 */
1550 reg_write(ohci, OHCI1394_BusOptions,
1551 be32_to_cpu(ohci->config_rom[2]));
1552 ohci->config_rom[0] = ohci->next_header;
1553 reg_write(ohci, OHCI1394_ConfigROMhdr,
1554 be32_to_cpu(ohci->next_header));
1555 }
1556
1557 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1558 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1559 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1560 #endif
1561
1562 spin_unlock_irqrestore(&ohci->lock, flags);
1563
1564 if (free_rom)
1565 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1566 free_rom, free_rom_bus);
1567
1568 log_selfids(ohci->node_id, generation,
1569 self_id_count, ohci->self_id_buffer);
1570
1571 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1572 self_id_count, ohci->self_id_buffer,
1573 ohci->csr_state_setclear_abdicate);
1574 ohci->csr_state_setclear_abdicate = false;
1575 }
1576
1577 static irqreturn_t irq_handler(int irq, void *data)
1578 {
1579 struct fw_ohci *ohci = data;
1580 u32 event, iso_event;
1581 int i;
1582
1583 event = reg_read(ohci, OHCI1394_IntEventClear);
1584
1585 if (!event || !~event)
1586 return IRQ_NONE;
1587
1588 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1589 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1590 log_irqs(event);
1591
1592 if (event & OHCI1394_selfIDComplete)
1593 tasklet_schedule(&ohci->bus_reset_tasklet);
1594
1595 if (event & OHCI1394_RQPkt)
1596 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1597
1598 if (event & OHCI1394_RSPkt)
1599 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1600
1601 if (event & OHCI1394_reqTxComplete)
1602 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1603
1604 if (event & OHCI1394_respTxComplete)
1605 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1606
1607 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1608 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1609
1610 while (iso_event) {
1611 i = ffs(iso_event) - 1;
1612 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1613 iso_event &= ~(1 << i);
1614 }
1615
1616 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1617 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1618
1619 while (iso_event) {
1620 i = ffs(iso_event) - 1;
1621 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1622 iso_event &= ~(1 << i);
1623 }
1624
1625 if (unlikely(event & OHCI1394_regAccessFail))
1626 fw_error("Register access failure - "
1627 "please notify linux1394-devel@lists.sf.net\n");
1628
1629 if (unlikely(event & OHCI1394_postedWriteErr))
1630 fw_error("PCI posted write error\n");
1631
1632 if (unlikely(event & OHCI1394_cycleTooLong)) {
1633 if (printk_ratelimit())
1634 fw_notify("isochronous cycle too long\n");
1635 reg_write(ohci, OHCI1394_LinkControlSet,
1636 OHCI1394_LinkControl_cycleMaster);
1637 }
1638
1639 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1640 /*
1641 * We need to clear this event bit in order to make
1642 * cycleMatch isochronous I/O work. In theory we should
1643 * stop active cycleMatch iso contexts now and restart
1644 * them at least two cycles later. (FIXME?)
1645 */
1646 if (printk_ratelimit())
1647 fw_notify("isochronous cycle inconsistent\n");
1648 }
1649
1650 if (event & OHCI1394_cycle64Seconds) {
1651 spin_lock(&ohci->lock);
1652 update_bus_time(ohci);
1653 spin_unlock(&ohci->lock);
1654 }
1655
1656 return IRQ_HANDLED;
1657 }
1658
1659 static int software_reset(struct fw_ohci *ohci)
1660 {
1661 int i;
1662
1663 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1664
1665 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1666 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1667 OHCI1394_HCControl_softReset) == 0)
1668 return 0;
1669 msleep(1);
1670 }
1671
1672 return -EBUSY;
1673 }
1674
1675 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1676 {
1677 size_t size = length * 4;
1678
1679 memcpy(dest, src, size);
1680 if (size < CONFIG_ROM_SIZE)
1681 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1682 }
1683
1684 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1685 {
1686 bool enable_1394a;
1687 int ret, clear, set, offset;
1688
1689 /* Check if the driver should configure link and PHY. */
1690 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1691 OHCI1394_HCControl_programPhyEnable))
1692 return 0;
1693
1694 /* Paranoia: check whether the PHY supports 1394a, too. */
1695 enable_1394a = false;
1696 ret = read_phy_reg(ohci, 2);
1697 if (ret < 0)
1698 return ret;
1699 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1700 ret = read_paged_phy_reg(ohci, 1, 8);
1701 if (ret < 0)
1702 return ret;
1703 if (ret >= 1)
1704 enable_1394a = true;
1705 }
1706
1707 if (ohci->quirks & QUIRK_NO_1394A)
1708 enable_1394a = false;
1709
1710 /* Configure PHY and link consistently. */
1711 if (enable_1394a) {
1712 clear = 0;
1713 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1714 } else {
1715 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1716 set = 0;
1717 }
1718 ret = update_phy_reg(ohci, 5, clear, set);
1719 if (ret < 0)
1720 return ret;
1721
1722 if (enable_1394a)
1723 offset = OHCI1394_HCControlSet;
1724 else
1725 offset = OHCI1394_HCControlClear;
1726 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1727
1728 /* Clean up: configuration has been taken care of. */
1729 reg_write(ohci, OHCI1394_HCControlClear,
1730 OHCI1394_HCControl_programPhyEnable);
1731
1732 return 0;
1733 }
1734
1735 static int ohci_enable(struct fw_card *card,
1736 const __be32 *config_rom, size_t length)
1737 {
1738 struct fw_ohci *ohci = fw_ohci(card);
1739 struct pci_dev *dev = to_pci_dev(card->device);
1740 u32 lps, seconds, version, irqs;
1741 int i, ret;
1742
1743 if (software_reset(ohci)) {
1744 fw_error("Failed to reset ohci card.\n");
1745 return -EBUSY;
1746 }
1747
1748 /*
1749 * Now enable LPS, which we need in order to start accessing
1750 * most of the registers. In fact, on some cards (ALI M5251),
1751 * accessing registers in the SClk domain without LPS enabled
1752 * will lock up the machine. Wait 50msec to make sure we have
1753 * full link enabled. However, with some cards (well, at least
1754 * a JMicron PCIe card), we have to try again sometimes.
1755 */
1756 reg_write(ohci, OHCI1394_HCControlSet,
1757 OHCI1394_HCControl_LPS |
1758 OHCI1394_HCControl_postedWriteEnable);
1759 flush_writes(ohci);
1760
1761 for (lps = 0, i = 0; !lps && i < 3; i++) {
1762 msleep(50);
1763 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1764 OHCI1394_HCControl_LPS;
1765 }
1766
1767 if (!lps) {
1768 fw_error("Failed to set Link Power Status\n");
1769 return -EIO;
1770 }
1771
1772 reg_write(ohci, OHCI1394_HCControlClear,
1773 OHCI1394_HCControl_noByteSwapData);
1774
1775 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1776 reg_write(ohci, OHCI1394_LinkControlSet,
1777 OHCI1394_LinkControl_rcvSelfID |
1778 OHCI1394_LinkControl_rcvPhyPkt |
1779 OHCI1394_LinkControl_cycleTimerEnable |
1780 OHCI1394_LinkControl_cycleMaster);
1781
1782 reg_write(ohci, OHCI1394_ATRetries,
1783 OHCI1394_MAX_AT_REQ_RETRIES |
1784 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1785 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1786 (200 << 16));
1787
1788 seconds = lower_32_bits(get_seconds());
1789 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1790 ohci->bus_time = seconds & ~0x3f;
1791
1792 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1793 if (version >= OHCI_VERSION_1_1) {
1794 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1795 0xfffffffe);
1796 card->broadcast_channel_auto_allocated = true;
1797 }
1798
1799 /* Get implemented bits of the priority arbitration request counter. */
1800 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1801 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1802 reg_write(ohci, OHCI1394_FairnessControl, 0);
1803 card->priority_budget_implemented = ohci->pri_req_max != 0;
1804
1805 ar_context_run(&ohci->ar_request_ctx);
1806 ar_context_run(&ohci->ar_response_ctx);
1807
1808 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1809 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1810 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1811
1812 ret = configure_1394a_enhancements(ohci);
1813 if (ret < 0)
1814 return ret;
1815
1816 /* Activate link_on bit and contender bit in our self ID packets.*/
1817 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1818 if (ret < 0)
1819 return ret;
1820
1821 /*
1822 * When the link is not yet enabled, the atomic config rom
1823 * update mechanism described below in ohci_set_config_rom()
1824 * is not active. We have to update ConfigRomHeader and
1825 * BusOptions manually, and the write to ConfigROMmap takes
1826 * effect immediately. We tie this to the enabling of the
1827 * link, so we have a valid config rom before enabling - the
1828 * OHCI requires that ConfigROMhdr and BusOptions have valid
1829 * values before enabling.
1830 *
1831 * However, when the ConfigROMmap is written, some controllers
1832 * always read back quadlets 0 and 2 from the config rom to
1833 * the ConfigRomHeader and BusOptions registers on bus reset.
1834 * They shouldn't do that in this initial case where the link
1835 * isn't enabled. This means we have to use the same
1836 * workaround here, setting the bus header to 0 and then write
1837 * the right values in the bus reset tasklet.
1838 */
1839
1840 if (config_rom) {
1841 ohci->next_config_rom =
1842 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1843 &ohci->next_config_rom_bus,
1844 GFP_KERNEL);
1845 if (ohci->next_config_rom == NULL)
1846 return -ENOMEM;
1847
1848 copy_config_rom(ohci->next_config_rom, config_rom, length);
1849 } else {
1850 /*
1851 * In the suspend case, config_rom is NULL, which
1852 * means that we just reuse the old config rom.
1853 */
1854 ohci->next_config_rom = ohci->config_rom;
1855 ohci->next_config_rom_bus = ohci->config_rom_bus;
1856 }
1857
1858 ohci->next_header = ohci->next_config_rom[0];
1859 ohci->next_config_rom[0] = 0;
1860 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1861 reg_write(ohci, OHCI1394_BusOptions,
1862 be32_to_cpu(ohci->next_config_rom[2]));
1863 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1864
1865 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1866
1867 if (!(ohci->quirks & QUIRK_NO_MSI))
1868 pci_enable_msi(dev);
1869 if (request_irq(dev->irq, irq_handler,
1870 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1871 ohci_driver_name, ohci)) {
1872 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1873 pci_disable_msi(dev);
1874 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1875 ohci->config_rom, ohci->config_rom_bus);
1876 return -EIO;
1877 }
1878
1879 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1880 OHCI1394_RQPkt | OHCI1394_RSPkt |
1881 OHCI1394_isochTx | OHCI1394_isochRx |
1882 OHCI1394_postedWriteErr |
1883 OHCI1394_selfIDComplete |
1884 OHCI1394_regAccessFail |
1885 OHCI1394_cycle64Seconds |
1886 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1887 OHCI1394_masterIntEnable;
1888 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1889 irqs |= OHCI1394_busReset;
1890 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1891
1892 reg_write(ohci, OHCI1394_HCControlSet,
1893 OHCI1394_HCControl_linkEnable |
1894 OHCI1394_HCControl_BIBimageValid);
1895 flush_writes(ohci);
1896
1897 /* We are ready to go, reset bus to finish initialization. */
1898 fw_schedule_bus_reset(&ohci->card, false, true);
1899
1900 return 0;
1901 }
1902
1903 static int ohci_set_config_rom(struct fw_card *card,
1904 const __be32 *config_rom, size_t length)
1905 {
1906 struct fw_ohci *ohci;
1907 unsigned long flags;
1908 int ret = -EBUSY;
1909 __be32 *next_config_rom;
1910 dma_addr_t uninitialized_var(next_config_rom_bus);
1911
1912 ohci = fw_ohci(card);
1913
1914 /*
1915 * When the OHCI controller is enabled, the config rom update
1916 * mechanism is a bit tricky, but easy enough to use. See
1917 * section 5.5.6 in the OHCI specification.
1918 *
1919 * The OHCI controller caches the new config rom address in a
1920 * shadow register (ConfigROMmapNext) and needs a bus reset
1921 * for the changes to take place. When the bus reset is
1922 * detected, the controller loads the new values for the
1923 * ConfigRomHeader and BusOptions registers from the specified
1924 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1925 * shadow register. All automatically and atomically.
1926 *
1927 * Now, there's a twist to this story. The automatic load of
1928 * ConfigRomHeader and BusOptions doesn't honor the
1929 * noByteSwapData bit, so with a be32 config rom, the
1930 * controller will load be32 values in to these registers
1931 * during the atomic update, even on litte endian
1932 * architectures. The workaround we use is to put a 0 in the
1933 * header quadlet; 0 is endian agnostic and means that the
1934 * config rom isn't ready yet. In the bus reset tasklet we
1935 * then set up the real values for the two registers.
1936 *
1937 * We use ohci->lock to avoid racing with the code that sets
1938 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1939 */
1940
1941 next_config_rom =
1942 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1943 &next_config_rom_bus, GFP_KERNEL);
1944 if (next_config_rom == NULL)
1945 return -ENOMEM;
1946
1947 spin_lock_irqsave(&ohci->lock, flags);
1948
1949 if (ohci->next_config_rom == NULL) {
1950 ohci->next_config_rom = next_config_rom;
1951 ohci->next_config_rom_bus = next_config_rom_bus;
1952
1953 copy_config_rom(ohci->next_config_rom, config_rom, length);
1954
1955 ohci->next_header = config_rom[0];
1956 ohci->next_config_rom[0] = 0;
1957
1958 reg_write(ohci, OHCI1394_ConfigROMmap,
1959 ohci->next_config_rom_bus);
1960 ret = 0;
1961 }
1962
1963 spin_unlock_irqrestore(&ohci->lock, flags);
1964
1965 /*
1966 * Now initiate a bus reset to have the changes take
1967 * effect. We clean up the old config rom memory and DMA
1968 * mappings in the bus reset tasklet, since the OHCI
1969 * controller could need to access it before the bus reset
1970 * takes effect.
1971 */
1972 if (ret == 0)
1973 fw_schedule_bus_reset(&ohci->card, true, true);
1974 else
1975 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1976 next_config_rom, next_config_rom_bus);
1977
1978 return ret;
1979 }
1980
1981 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1982 {
1983 struct fw_ohci *ohci = fw_ohci(card);
1984
1985 at_context_transmit(&ohci->at_request_ctx, packet);
1986 }
1987
1988 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1989 {
1990 struct fw_ohci *ohci = fw_ohci(card);
1991
1992 at_context_transmit(&ohci->at_response_ctx, packet);
1993 }
1994
1995 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1996 {
1997 struct fw_ohci *ohci = fw_ohci(card);
1998 struct context *ctx = &ohci->at_request_ctx;
1999 struct driver_data *driver_data = packet->driver_data;
2000 int ret = -ENOENT;
2001
2002 tasklet_disable(&ctx->tasklet);
2003
2004 if (packet->ack != 0)
2005 goto out;
2006
2007 if (packet->payload_mapped)
2008 dma_unmap_single(ohci->card.device, packet->payload_bus,
2009 packet->payload_length, DMA_TO_DEVICE);
2010
2011 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2012 driver_data->packet = NULL;
2013 packet->ack = RCODE_CANCELLED;
2014 packet->callback(packet, &ohci->card, packet->ack);
2015 ret = 0;
2016 out:
2017 tasklet_enable(&ctx->tasklet);
2018
2019 return ret;
2020 }
2021
2022 static int ohci_enable_phys_dma(struct fw_card *card,
2023 int node_id, int generation)
2024 {
2025 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2026 return 0;
2027 #else
2028 struct fw_ohci *ohci = fw_ohci(card);
2029 unsigned long flags;
2030 int n, ret = 0;
2031
2032 /*
2033 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2034 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2035 */
2036
2037 spin_lock_irqsave(&ohci->lock, flags);
2038
2039 if (ohci->generation != generation) {
2040 ret = -ESTALE;
2041 goto out;
2042 }
2043
2044 /*
2045 * Note, if the node ID contains a non-local bus ID, physical DMA is
2046 * enabled for _all_ nodes on remote buses.
2047 */
2048
2049 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2050 if (n < 32)
2051 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2052 else
2053 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2054
2055 flush_writes(ohci);
2056 out:
2057 spin_unlock_irqrestore(&ohci->lock, flags);
2058
2059 return ret;
2060 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2061 }
2062
2063 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2064 {
2065 struct fw_ohci *ohci = fw_ohci(card);
2066 unsigned long flags;
2067 u32 value;
2068
2069 switch (csr_offset) {
2070 case CSR_STATE_CLEAR:
2071 case CSR_STATE_SET:
2072 if (ohci->is_root &&
2073 (reg_read(ohci, OHCI1394_LinkControlSet) &
2074 OHCI1394_LinkControl_cycleMaster))
2075 value = CSR_STATE_BIT_CMSTR;
2076 else
2077 value = 0;
2078 if (ohci->csr_state_setclear_abdicate)
2079 value |= CSR_STATE_BIT_ABDICATE;
2080
2081 return value;
2082
2083 case CSR_NODE_IDS:
2084 return reg_read(ohci, OHCI1394_NodeID) << 16;
2085
2086 case CSR_CYCLE_TIME:
2087 return get_cycle_time(ohci);
2088
2089 case CSR_BUS_TIME:
2090 /*
2091 * We might be called just after the cycle timer has wrapped
2092 * around but just before the cycle64Seconds handler, so we
2093 * better check here, too, if the bus time needs to be updated.
2094 */
2095 spin_lock_irqsave(&ohci->lock, flags);
2096 value = update_bus_time(ohci);
2097 spin_unlock_irqrestore(&ohci->lock, flags);
2098 return value;
2099
2100 case CSR_BUSY_TIMEOUT:
2101 value = reg_read(ohci, OHCI1394_ATRetries);
2102 return (value >> 4) & 0x0ffff00f;
2103
2104 case CSR_PRIORITY_BUDGET:
2105 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2106 (ohci->pri_req_max << 8);
2107
2108 default:
2109 WARN_ON(1);
2110 return 0;
2111 }
2112 }
2113
2114 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2115 {
2116 struct fw_ohci *ohci = fw_ohci(card);
2117 unsigned long flags;
2118
2119 switch (csr_offset) {
2120 case CSR_STATE_CLEAR:
2121 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2122 reg_write(ohci, OHCI1394_LinkControlClear,
2123 OHCI1394_LinkControl_cycleMaster);
2124 flush_writes(ohci);
2125 }
2126 if (value & CSR_STATE_BIT_ABDICATE)
2127 ohci->csr_state_setclear_abdicate = false;
2128 break;
2129
2130 case CSR_STATE_SET:
2131 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2132 reg_write(ohci, OHCI1394_LinkControlSet,
2133 OHCI1394_LinkControl_cycleMaster);
2134 flush_writes(ohci);
2135 }
2136 if (value & CSR_STATE_BIT_ABDICATE)
2137 ohci->csr_state_setclear_abdicate = true;
2138 break;
2139
2140 case CSR_NODE_IDS:
2141 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2142 flush_writes(ohci);
2143 break;
2144
2145 case CSR_CYCLE_TIME:
2146 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2147 reg_write(ohci, OHCI1394_IntEventSet,
2148 OHCI1394_cycleInconsistent);
2149 flush_writes(ohci);
2150 break;
2151
2152 case CSR_BUS_TIME:
2153 spin_lock_irqsave(&ohci->lock, flags);
2154 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2155 spin_unlock_irqrestore(&ohci->lock, flags);
2156 break;
2157
2158 case CSR_BUSY_TIMEOUT:
2159 value = (value & 0xf) | ((value & 0xf) << 4) |
2160 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2161 reg_write(ohci, OHCI1394_ATRetries, value);
2162 flush_writes(ohci);
2163 break;
2164
2165 case CSR_PRIORITY_BUDGET:
2166 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2167 flush_writes(ohci);
2168 break;
2169
2170 default:
2171 WARN_ON(1);
2172 break;
2173 }
2174 }
2175
2176 static void copy_iso_headers(struct iso_context *ctx, void *p)
2177 {
2178 int i = ctx->header_length;
2179
2180 if (i + ctx->base.header_size > PAGE_SIZE)
2181 return;
2182
2183 /*
2184 * The iso header is byteswapped to little endian by
2185 * the controller, but the remaining header quadlets
2186 * are big endian. We want to present all the headers
2187 * as big endian, so we have to swap the first quadlet.
2188 */
2189 if (ctx->base.header_size > 0)
2190 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2191 if (ctx->base.header_size > 4)
2192 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2193 if (ctx->base.header_size > 8)
2194 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2195 ctx->header_length += ctx->base.header_size;
2196 }
2197
2198 static int handle_ir_packet_per_buffer(struct context *context,
2199 struct descriptor *d,
2200 struct descriptor *last)
2201 {
2202 struct iso_context *ctx =
2203 container_of(context, struct iso_context, context);
2204 struct descriptor *pd;
2205 __le32 *ir_header;
2206 void *p;
2207
2208 for (pd = d; pd <= last; pd++)
2209 if (pd->transfer_status)
2210 break;
2211 if (pd > last)
2212 /* Descriptor(s) not done yet, stop iteration */
2213 return 0;
2214
2215 p = last + 1;
2216 copy_iso_headers(ctx, p);
2217
2218 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2219 ir_header = (__le32 *) p;
2220 ctx->base.callback.sc(&ctx->base,
2221 le32_to_cpu(ir_header[0]) & 0xffff,
2222 ctx->header_length, ctx->header,
2223 ctx->base.callback_data);
2224 ctx->header_length = 0;
2225 }
2226
2227 return 1;
2228 }
2229
2230 /* d == last because each descriptor block is only a single descriptor. */
2231 static int handle_ir_buffer_fill(struct context *context,
2232 struct descriptor *d,
2233 struct descriptor *last)
2234 {
2235 struct iso_context *ctx =
2236 container_of(context, struct iso_context, context);
2237
2238 if (!last->transfer_status)
2239 /* Descriptor(s) not done yet, stop iteration */
2240 return 0;
2241
2242 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2243 ctx->base.callback.mc(&ctx->base,
2244 le32_to_cpu(last->data_address) +
2245 le16_to_cpu(last->req_count) -
2246 le16_to_cpu(last->res_count),
2247 ctx->base.callback_data);
2248
2249 return 1;
2250 }
2251
2252 static int handle_it_packet(struct context *context,
2253 struct descriptor *d,
2254 struct descriptor *last)
2255 {
2256 struct iso_context *ctx =
2257 container_of(context, struct iso_context, context);
2258 int i;
2259 struct descriptor *pd;
2260
2261 for (pd = d; pd <= last; pd++)
2262 if (pd->transfer_status)
2263 break;
2264 if (pd > last)
2265 /* Descriptor(s) not done yet, stop iteration */
2266 return 0;
2267
2268 i = ctx->header_length;
2269 if (i + 4 < PAGE_SIZE) {
2270 /* Present this value as big-endian to match the receive code */
2271 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2272 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2273 le16_to_cpu(pd->res_count));
2274 ctx->header_length += 4;
2275 }
2276 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2277 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2278 ctx->header_length, ctx->header,
2279 ctx->base.callback_data);
2280 ctx->header_length = 0;
2281 }
2282 return 1;
2283 }
2284
2285 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2286 {
2287 u32 hi = channels >> 32, lo = channels;
2288
2289 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2290 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2291 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2292 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2293 mmiowb();
2294 ohci->mc_channels = channels;
2295 }
2296
2297 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2298 int type, int channel, size_t header_size)
2299 {
2300 struct fw_ohci *ohci = fw_ohci(card);
2301 struct iso_context *uninitialized_var(ctx);
2302 descriptor_callback_t uninitialized_var(callback);
2303 u64 *uninitialized_var(channels);
2304 u32 *uninitialized_var(mask), uninitialized_var(regs);
2305 unsigned long flags;
2306 int index, ret = -EBUSY;
2307
2308 spin_lock_irqsave(&ohci->lock, flags);
2309
2310 switch (type) {
2311 case FW_ISO_CONTEXT_TRANSMIT:
2312 mask = &ohci->it_context_mask;
2313 callback = handle_it_packet;
2314 index = ffs(*mask) - 1;
2315 if (index >= 0) {
2316 *mask &= ~(1 << index);
2317 regs = OHCI1394_IsoXmitContextBase(index);
2318 ctx = &ohci->it_context_list[index];
2319 }
2320 break;
2321
2322 case FW_ISO_CONTEXT_RECEIVE:
2323 channels = &ohci->ir_context_channels;
2324 mask = &ohci->ir_context_mask;
2325 callback = handle_ir_packet_per_buffer;
2326 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2327 if (index >= 0) {
2328 *channels &= ~(1ULL << channel);
2329 *mask &= ~(1 << index);
2330 regs = OHCI1394_IsoRcvContextBase(index);
2331 ctx = &ohci->ir_context_list[index];
2332 }
2333 break;
2334
2335 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2336 mask = &ohci->ir_context_mask;
2337 callback = handle_ir_buffer_fill;
2338 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2339 if (index >= 0) {
2340 ohci->mc_allocated = true;
2341 *mask &= ~(1 << index);
2342 regs = OHCI1394_IsoRcvContextBase(index);
2343 ctx = &ohci->ir_context_list[index];
2344 }
2345 break;
2346
2347 default:
2348 index = -1;
2349 ret = -ENOSYS;
2350 }
2351
2352 spin_unlock_irqrestore(&ohci->lock, flags);
2353
2354 if (index < 0)
2355 return ERR_PTR(ret);
2356
2357 memset(ctx, 0, sizeof(*ctx));
2358 ctx->header_length = 0;
2359 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2360 if (ctx->header == NULL) {
2361 ret = -ENOMEM;
2362 goto out;
2363 }
2364 ret = context_init(&ctx->context, ohci, regs, callback);
2365 if (ret < 0)
2366 goto out_with_header;
2367
2368 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2369 set_multichannel_mask(ohci, 0);
2370
2371 return &ctx->base;
2372
2373 out_with_header:
2374 free_page((unsigned long)ctx->header);
2375 out:
2376 spin_lock_irqsave(&ohci->lock, flags);
2377
2378 switch (type) {
2379 case FW_ISO_CONTEXT_RECEIVE:
2380 *channels |= 1ULL << channel;
2381 break;
2382
2383 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2384 ohci->mc_allocated = false;
2385 break;
2386 }
2387 *mask |= 1 << index;
2388
2389 spin_unlock_irqrestore(&ohci->lock, flags);
2390
2391 return ERR_PTR(ret);
2392 }
2393
2394 static int ohci_start_iso(struct fw_iso_context *base,
2395 s32 cycle, u32 sync, u32 tags)
2396 {
2397 struct iso_context *ctx = container_of(base, struct iso_context, base);
2398 struct fw_ohci *ohci = ctx->context.ohci;
2399 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2400 int index;
2401
2402 switch (ctx->base.type) {
2403 case FW_ISO_CONTEXT_TRANSMIT:
2404 index = ctx - ohci->it_context_list;
2405 match = 0;
2406 if (cycle >= 0)
2407 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2408 (cycle & 0x7fff) << 16;
2409
2410 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2411 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2412 context_run(&ctx->context, match);
2413 break;
2414
2415 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2416 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2417 /* fall through */
2418 case FW_ISO_CONTEXT_RECEIVE:
2419 index = ctx - ohci->ir_context_list;
2420 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2421 if (cycle >= 0) {
2422 match |= (cycle & 0x07fff) << 12;
2423 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2424 }
2425
2426 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2427 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2428 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2429 context_run(&ctx->context, control);
2430 break;
2431 }
2432
2433 return 0;
2434 }
2435
2436 static int ohci_stop_iso(struct fw_iso_context *base)
2437 {
2438 struct fw_ohci *ohci = fw_ohci(base->card);
2439 struct iso_context *ctx = container_of(base, struct iso_context, base);
2440 int index;
2441
2442 switch (ctx->base.type) {
2443 case FW_ISO_CONTEXT_TRANSMIT:
2444 index = ctx - ohci->it_context_list;
2445 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2446 break;
2447
2448 case FW_ISO_CONTEXT_RECEIVE:
2449 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2450 index = ctx - ohci->ir_context_list;
2451 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2452 break;
2453 }
2454 flush_writes(ohci);
2455 context_stop(&ctx->context);
2456
2457 return 0;
2458 }
2459
2460 static void ohci_free_iso_context(struct fw_iso_context *base)
2461 {
2462 struct fw_ohci *ohci = fw_ohci(base->card);
2463 struct iso_context *ctx = container_of(base, struct iso_context, base);
2464 unsigned long flags;
2465 int index;
2466
2467 ohci_stop_iso(base);
2468 context_release(&ctx->context);
2469 free_page((unsigned long)ctx->header);
2470
2471 spin_lock_irqsave(&ohci->lock, flags);
2472
2473 switch (base->type) {
2474 case FW_ISO_CONTEXT_TRANSMIT:
2475 index = ctx - ohci->it_context_list;
2476 ohci->it_context_mask |= 1 << index;
2477 break;
2478
2479 case FW_ISO_CONTEXT_RECEIVE:
2480 index = ctx - ohci->ir_context_list;
2481 ohci->ir_context_mask |= 1 << index;
2482 ohci->ir_context_channels |= 1ULL << base->channel;
2483 break;
2484
2485 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2486 index = ctx - ohci->ir_context_list;
2487 ohci->ir_context_mask |= 1 << index;
2488 ohci->ir_context_channels |= ohci->mc_channels;
2489 ohci->mc_channels = 0;
2490 ohci->mc_allocated = false;
2491 break;
2492 }
2493
2494 spin_unlock_irqrestore(&ohci->lock, flags);
2495 }
2496
2497 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2498 {
2499 struct fw_ohci *ohci = fw_ohci(base->card);
2500 unsigned long flags;
2501 int ret;
2502
2503 switch (base->type) {
2504 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2505
2506 spin_lock_irqsave(&ohci->lock, flags);
2507
2508 /* Don't allow multichannel to grab other contexts' channels. */
2509 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2510 *channels = ohci->ir_context_channels;
2511 ret = -EBUSY;
2512 } else {
2513 set_multichannel_mask(ohci, *channels);
2514 ret = 0;
2515 }
2516
2517 spin_unlock_irqrestore(&ohci->lock, flags);
2518
2519 break;
2520 default:
2521 ret = -EINVAL;
2522 }
2523
2524 return ret;
2525 }
2526
2527 static int queue_iso_transmit(struct iso_context *ctx,
2528 struct fw_iso_packet *packet,
2529 struct fw_iso_buffer *buffer,
2530 unsigned long payload)
2531 {
2532 struct descriptor *d, *last, *pd;
2533 struct fw_iso_packet *p;
2534 __le32 *header;
2535 dma_addr_t d_bus, page_bus;
2536 u32 z, header_z, payload_z, irq;
2537 u32 payload_index, payload_end_index, next_page_index;
2538 int page, end_page, i, length, offset;
2539
2540 p = packet;
2541 payload_index = payload;
2542
2543 if (p->skip)
2544 z = 1;
2545 else
2546 z = 2;
2547 if (p->header_length > 0)
2548 z++;
2549
2550 /* Determine the first page the payload isn't contained in. */
2551 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2552 if (p->payload_length > 0)
2553 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2554 else
2555 payload_z = 0;
2556
2557 z += payload_z;
2558
2559 /* Get header size in number of descriptors. */
2560 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2561
2562 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2563 if (d == NULL)
2564 return -ENOMEM;
2565
2566 if (!p->skip) {
2567 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2568 d[0].req_count = cpu_to_le16(8);
2569 /*
2570 * Link the skip address to this descriptor itself. This causes
2571 * a context to skip a cycle whenever lost cycles or FIFO
2572 * overruns occur, without dropping the data. The application
2573 * should then decide whether this is an error condition or not.
2574 * FIXME: Make the context's cycle-lost behaviour configurable?
2575 */
2576 d[0].branch_address = cpu_to_le32(d_bus | z);
2577
2578 header = (__le32 *) &d[1];
2579 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2580 IT_HEADER_TAG(p->tag) |
2581 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2582 IT_HEADER_CHANNEL(ctx->base.channel) |
2583 IT_HEADER_SPEED(ctx->base.speed));
2584 header[1] =
2585 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2586 p->payload_length));
2587 }
2588
2589 if (p->header_length > 0) {
2590 d[2].req_count = cpu_to_le16(p->header_length);
2591 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2592 memcpy(&d[z], p->header, p->header_length);
2593 }
2594
2595 pd = d + z - payload_z;
2596 payload_end_index = payload_index + p->payload_length;
2597 for (i = 0; i < payload_z; i++) {
2598 page = payload_index >> PAGE_SHIFT;
2599 offset = payload_index & ~PAGE_MASK;
2600 next_page_index = (page + 1) << PAGE_SHIFT;
2601 length =
2602 min(next_page_index, payload_end_index) - payload_index;
2603 pd[i].req_count = cpu_to_le16(length);
2604
2605 page_bus = page_private(buffer->pages[page]);
2606 pd[i].data_address = cpu_to_le32(page_bus + offset);
2607
2608 payload_index += length;
2609 }
2610
2611 if (p->interrupt)
2612 irq = DESCRIPTOR_IRQ_ALWAYS;
2613 else
2614 irq = DESCRIPTOR_NO_IRQ;
2615
2616 last = z == 2 ? d : d + z - 1;
2617 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2618 DESCRIPTOR_STATUS |
2619 DESCRIPTOR_BRANCH_ALWAYS |
2620 irq);
2621
2622 context_append(&ctx->context, d, z, header_z);
2623
2624 return 0;
2625 }
2626
2627 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2628 struct fw_iso_packet *packet,
2629 struct fw_iso_buffer *buffer,
2630 unsigned long payload)
2631 {
2632 struct descriptor *d, *pd;
2633 dma_addr_t d_bus, page_bus;
2634 u32 z, header_z, rest;
2635 int i, j, length;
2636 int page, offset, packet_count, header_size, payload_per_buffer;
2637
2638 /*
2639 * The OHCI controller puts the isochronous header and trailer in the
2640 * buffer, so we need at least 8 bytes.
2641 */
2642 packet_count = packet->header_length / ctx->base.header_size;
2643 header_size = max(ctx->base.header_size, (size_t)8);
2644
2645 /* Get header size in number of descriptors. */
2646 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2647 page = payload >> PAGE_SHIFT;
2648 offset = payload & ~PAGE_MASK;
2649 payload_per_buffer = packet->payload_length / packet_count;
2650
2651 for (i = 0; i < packet_count; i++) {
2652 /* d points to the header descriptor */
2653 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2654 d = context_get_descriptors(&ctx->context,
2655 z + header_z, &d_bus);
2656 if (d == NULL)
2657 return -ENOMEM;
2658
2659 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2660 DESCRIPTOR_INPUT_MORE);
2661 if (packet->skip && i == 0)
2662 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2663 d->req_count = cpu_to_le16(header_size);
2664 d->res_count = d->req_count;
2665 d->transfer_status = 0;
2666 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2667
2668 rest = payload_per_buffer;
2669 pd = d;
2670 for (j = 1; j < z; j++) {
2671 pd++;
2672 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2673 DESCRIPTOR_INPUT_MORE);
2674
2675 if (offset + rest < PAGE_SIZE)
2676 length = rest;
2677 else
2678 length = PAGE_SIZE - offset;
2679 pd->req_count = cpu_to_le16(length);
2680 pd->res_count = pd->req_count;
2681 pd->transfer_status = 0;
2682
2683 page_bus = page_private(buffer->pages[page]);
2684 pd->data_address = cpu_to_le32(page_bus + offset);
2685
2686 offset = (offset + length) & ~PAGE_MASK;
2687 rest -= length;
2688 if (offset == 0)
2689 page++;
2690 }
2691 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2692 DESCRIPTOR_INPUT_LAST |
2693 DESCRIPTOR_BRANCH_ALWAYS);
2694 if (packet->interrupt && i == packet_count - 1)
2695 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2696
2697 context_append(&ctx->context, d, z, header_z);
2698 }
2699
2700 return 0;
2701 }
2702
2703 static int queue_iso_buffer_fill(struct iso_context *ctx,
2704 struct fw_iso_packet *packet,
2705 struct fw_iso_buffer *buffer,
2706 unsigned long payload)
2707 {
2708 struct descriptor *d;
2709 dma_addr_t d_bus, page_bus;
2710 int page, offset, rest, z, i, length;
2711
2712 page = payload >> PAGE_SHIFT;
2713 offset = payload & ~PAGE_MASK;
2714 rest = packet->payload_length;
2715
2716 /* We need one descriptor for each page in the buffer. */
2717 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2718
2719 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2720 return -EFAULT;
2721
2722 for (i = 0; i < z; i++) {
2723 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2724 if (d == NULL)
2725 return -ENOMEM;
2726
2727 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2728 DESCRIPTOR_BRANCH_ALWAYS);
2729 if (packet->skip && i == 0)
2730 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2731 if (packet->interrupt && i == z - 1)
2732 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2733
2734 if (offset + rest < PAGE_SIZE)
2735 length = rest;
2736 else
2737 length = PAGE_SIZE - offset;
2738 d->req_count = cpu_to_le16(length);
2739 d->res_count = d->req_count;
2740 d->transfer_status = 0;
2741
2742 page_bus = page_private(buffer->pages[page]);
2743 d->data_address = cpu_to_le32(page_bus + offset);
2744
2745 rest -= length;
2746 offset = 0;
2747 page++;
2748
2749 context_append(&ctx->context, d, 1, 0);
2750 }
2751
2752 return 0;
2753 }
2754
2755 static int ohci_queue_iso(struct fw_iso_context *base,
2756 struct fw_iso_packet *packet,
2757 struct fw_iso_buffer *buffer,
2758 unsigned long payload)
2759 {
2760 struct iso_context *ctx = container_of(base, struct iso_context, base);
2761 unsigned long flags;
2762 int ret = -ENOSYS;
2763
2764 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2765 switch (base->type) {
2766 case FW_ISO_CONTEXT_TRANSMIT:
2767 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2768 break;
2769 case FW_ISO_CONTEXT_RECEIVE:
2770 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2771 break;
2772 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2773 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2774 break;
2775 }
2776 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2777
2778 return ret;
2779 }
2780
2781 static const struct fw_card_driver ohci_driver = {
2782 .enable = ohci_enable,
2783 .read_phy_reg = ohci_read_phy_reg,
2784 .update_phy_reg = ohci_update_phy_reg,
2785 .set_config_rom = ohci_set_config_rom,
2786 .send_request = ohci_send_request,
2787 .send_response = ohci_send_response,
2788 .cancel_packet = ohci_cancel_packet,
2789 .enable_phys_dma = ohci_enable_phys_dma,
2790 .read_csr = ohci_read_csr,
2791 .write_csr = ohci_write_csr,
2792
2793 .allocate_iso_context = ohci_allocate_iso_context,
2794 .free_iso_context = ohci_free_iso_context,
2795 .set_iso_channels = ohci_set_iso_channels,
2796 .queue_iso = ohci_queue_iso,
2797 .start_iso = ohci_start_iso,
2798 .stop_iso = ohci_stop_iso,
2799 };
2800
2801 #ifdef CONFIG_PPC_PMAC
2802 static void pmac_ohci_on(struct pci_dev *dev)
2803 {
2804 if (machine_is(powermac)) {
2805 struct device_node *ofn = pci_device_to_OF_node(dev);
2806
2807 if (ofn) {
2808 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2809 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2810 }
2811 }
2812 }
2813
2814 static void pmac_ohci_off(struct pci_dev *dev)
2815 {
2816 if (machine_is(powermac)) {
2817 struct device_node *ofn = pci_device_to_OF_node(dev);
2818
2819 if (ofn) {
2820 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2821 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2822 }
2823 }
2824 }
2825 #else
2826 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2827 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2828 #endif /* CONFIG_PPC_PMAC */
2829
2830 static int __devinit pci_probe(struct pci_dev *dev,
2831 const struct pci_device_id *ent)
2832 {
2833 struct fw_ohci *ohci;
2834 u32 bus_options, max_receive, link_speed, version, link_enh;
2835 u64 guid;
2836 int i, err, n_ir, n_it;
2837 size_t size;
2838
2839 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2840 if (ohci == NULL) {
2841 err = -ENOMEM;
2842 goto fail;
2843 }
2844
2845 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2846
2847 pmac_ohci_on(dev);
2848
2849 err = pci_enable_device(dev);
2850 if (err) {
2851 fw_error("Failed to enable OHCI hardware\n");
2852 goto fail_free;
2853 }
2854
2855 pci_set_master(dev);
2856 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2857 pci_set_drvdata(dev, ohci);
2858
2859 spin_lock_init(&ohci->lock);
2860 mutex_init(&ohci->phy_reg_mutex);
2861
2862 tasklet_init(&ohci->bus_reset_tasklet,
2863 bus_reset_tasklet, (unsigned long)ohci);
2864
2865 err = pci_request_region(dev, 0, ohci_driver_name);
2866 if (err) {
2867 fw_error("MMIO resource unavailable\n");
2868 goto fail_disable;
2869 }
2870
2871 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2872 if (ohci->registers == NULL) {
2873 fw_error("Failed to remap registers\n");
2874 err = -ENXIO;
2875 goto fail_iomem;
2876 }
2877
2878 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2879 if (ohci_quirks[i].vendor == dev->vendor &&
2880 (ohci_quirks[i].device == dev->device ||
2881 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2882 ohci->quirks = ohci_quirks[i].flags;
2883 break;
2884 }
2885 if (param_quirks)
2886 ohci->quirks = param_quirks;
2887
2888 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2889 if (dev->vendor == PCI_VENDOR_ID_TI) {
2890 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2891
2892 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2893 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2894 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2895
2896 /* use priority arbitration for asynchronous responses */
2897 link_enh |= TI_LinkEnh_enab_unfair;
2898
2899 /* required for aPhyEnhanceEnable to work */
2900 link_enh |= TI_LinkEnh_enab_accel;
2901
2902 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2903 }
2904
2905 ar_context_init(&ohci->ar_request_ctx, ohci,
2906 OHCI1394_AsReqRcvContextControlSet);
2907
2908 ar_context_init(&ohci->ar_response_ctx, ohci,
2909 OHCI1394_AsRspRcvContextControlSet);
2910
2911 context_init(&ohci->at_request_ctx, ohci,
2912 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2913
2914 context_init(&ohci->at_response_ctx, ohci,
2915 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2916
2917 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2918 ohci->ir_context_channels = ~0ULL;
2919 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2920 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2921 n_ir = hweight32(ohci->ir_context_mask);
2922 size = sizeof(struct iso_context) * n_ir;
2923 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2924
2925 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2926 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2927 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2928 n_it = hweight32(ohci->it_context_mask);
2929 size = sizeof(struct iso_context) * n_it;
2930 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2931
2932 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2933 err = -ENOMEM;
2934 goto fail_contexts;
2935 }
2936
2937 /* self-id dma buffer allocation */
2938 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2939 SELF_ID_BUF_SIZE,
2940 &ohci->self_id_bus,
2941 GFP_KERNEL);
2942 if (ohci->self_id_cpu == NULL) {
2943 err = -ENOMEM;
2944 goto fail_contexts;
2945 }
2946
2947 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2948 max_receive = (bus_options >> 12) & 0xf;
2949 link_speed = bus_options & 0x7;
2950 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2951 reg_read(ohci, OHCI1394_GUIDLo);
2952
2953 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2954 if (err)
2955 goto fail_self_id;
2956
2957 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2958 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2959 "%d IR + %d IT contexts, quirks 0x%x\n",
2960 dev_name(&dev->dev), version >> 16, version & 0xff,
2961 n_ir, n_it, ohci->quirks);
2962
2963 return 0;
2964
2965 fail_self_id:
2966 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2967 ohci->self_id_cpu, ohci->self_id_bus);
2968 fail_contexts:
2969 kfree(ohci->ir_context_list);
2970 kfree(ohci->it_context_list);
2971 context_release(&ohci->at_response_ctx);
2972 context_release(&ohci->at_request_ctx);
2973 ar_context_release(&ohci->ar_response_ctx);
2974 ar_context_release(&ohci->ar_request_ctx);
2975 pci_iounmap(dev, ohci->registers);
2976 fail_iomem:
2977 pci_release_region(dev, 0);
2978 fail_disable:
2979 pci_disable_device(dev);
2980 fail_free:
2981 kfree(&ohci->card);
2982 pmac_ohci_off(dev);
2983 fail:
2984 if (err == -ENOMEM)
2985 fw_error("Out of memory\n");
2986
2987 return err;
2988 }
2989
2990 static void pci_remove(struct pci_dev *dev)
2991 {
2992 struct fw_ohci *ohci;
2993
2994 ohci = pci_get_drvdata(dev);
2995 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2996 flush_writes(ohci);
2997 fw_core_remove_card(&ohci->card);
2998
2999 /*
3000 * FIXME: Fail all pending packets here, now that the upper
3001 * layers can't queue any more.
3002 */
3003
3004 software_reset(ohci);
3005 free_irq(dev->irq, ohci);
3006
3007 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3008 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3009 ohci->next_config_rom, ohci->next_config_rom_bus);
3010 if (ohci->config_rom)
3011 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3012 ohci->config_rom, ohci->config_rom_bus);
3013 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3014 ohci->self_id_cpu, ohci->self_id_bus);
3015 ar_context_release(&ohci->ar_request_ctx);
3016 ar_context_release(&ohci->ar_response_ctx);
3017 context_release(&ohci->at_request_ctx);
3018 context_release(&ohci->at_response_ctx);
3019 kfree(ohci->it_context_list);
3020 kfree(ohci->ir_context_list);
3021 pci_disable_msi(dev);
3022 pci_iounmap(dev, ohci->registers);
3023 pci_release_region(dev, 0);
3024 pci_disable_device(dev);
3025 kfree(&ohci->card);
3026 pmac_ohci_off(dev);
3027
3028 fw_notify("Removed fw-ohci device.\n");
3029 }
3030
3031 #ifdef CONFIG_PM
3032 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3033 {
3034 struct fw_ohci *ohci = pci_get_drvdata(dev);
3035 int err;
3036
3037 software_reset(ohci);
3038 free_irq(dev->irq, ohci);
3039 pci_disable_msi(dev);
3040 err = pci_save_state(dev);
3041 if (err) {
3042 fw_error("pci_save_state failed\n");
3043 return err;
3044 }
3045 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3046 if (err)
3047 fw_error("pci_set_power_state failed with %d\n", err);
3048 pmac_ohci_off(dev);
3049
3050 return 0;
3051 }
3052
3053 static int pci_resume(struct pci_dev *dev)
3054 {
3055 struct fw_ohci *ohci = pci_get_drvdata(dev);
3056 int err;
3057
3058 pmac_ohci_on(dev);
3059 pci_set_power_state(dev, PCI_D0);
3060 pci_restore_state(dev);
3061 err = pci_enable_device(dev);
3062 if (err) {
3063 fw_error("pci_enable_device failed\n");
3064 return err;
3065 }
3066
3067 return ohci_enable(&ohci->card, NULL, 0);
3068 }
3069 #endif
3070
3071 static const struct pci_device_id pci_table[] = {
3072 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3073 { }
3074 };
3075
3076 MODULE_DEVICE_TABLE(pci, pci_table);
3077
3078 static struct pci_driver fw_ohci_pci_driver = {
3079 .name = ohci_driver_name,
3080 .id_table = pci_table,
3081 .probe = pci_probe,
3082 .remove = pci_remove,
3083 #ifdef CONFIG_PM
3084 .resume = pci_resume,
3085 .suspend = pci_suspend,
3086 #endif
3087 };
3088
3089 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3090 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3091 MODULE_LICENSE("GPL");
3092
3093 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3094 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3095 MODULE_ALIAS("ohci1394");
3096 #endif
3097
3098 static int __init fw_ohci_init(void)
3099 {
3100 return pci_register_driver(&fw_ohci_pci_driver);
3101 }
3102
3103 static void __exit fw_ohci_cleanup(void)
3104 {
3105 pci_unregister_driver(&fw_ohci_pci_driver);
3106 }
3107
3108 module_init(fw_ohci_init);
3109 module_exit(fw_ohci_cleanup);
kernel-based virtual machine