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bfs: fix bitmap size argument to find_first_zero_bit()
[linux-2.6/kvm.git] / drivers / i2c / busses / i2c-i801.c
blobed2e0c5ea37c7b53ee1b67a20881caff26e7797d
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53
54 Features supported by this driver:
55 Software PEC no
56 Hardware PEC yes
57 Block buffer yes
58 Block process call transaction no
59 I2C block read transaction yes (doesn't use the block buffer)
60 Slave mode no
61
62 See the file Documentation/i2c/busses/i2c-i801 for details.
63 */
64
65 #include <linux/module.h>
66 #include <linux/pci.h>
67 #include <linux/kernel.h>
68 #include <linux/stddef.h>
69 #include <linux/delay.h>
70 #include <linux/ioport.h>
71 #include <linux/init.h>
72 #include <linux/i2c.h>
73 #include <linux/acpi.h>
74 #include <linux/io.h>
75 #include <linux/dmi.h>
76 #include <linux/slab.h>
77
78 /* I801 SMBus address offsets */
79 #define SMBHSTSTS(p) (0 + (p)->smba)
80 #define SMBHSTCNT(p) (2 + (p)->smba)
81 #define SMBHSTCMD(p) (3 + (p)->smba)
82 #define SMBHSTADD(p) (4 + (p)->smba)
83 #define SMBHSTDAT0(p) (5 + (p)->smba)
84 #define SMBHSTDAT1(p) (6 + (p)->smba)
85 #define SMBBLKDAT(p) (7 + (p)->smba)
86 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
87 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
88 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
89
90 /* PCI Address Constants */
91 #define SMBBAR 4
92 #define SMBHSTCFG 0x040
93
94 /* Host configuration bits for SMBHSTCFG */
95 #define SMBHSTCFG_HST_EN 1
96 #define SMBHSTCFG_SMB_SMI_EN 2
97 #define SMBHSTCFG_I2C_EN 4
98
99 /* Auxillary control register bits, ICH4+ only */
100 #define SMBAUXCTL_CRC 1
101 #define SMBAUXCTL_E32B 2
102
103 /* kill bit for SMBHSTCNT */
104 #define SMBHSTCNT_KILL 2
105
106 /* Other settings */
107 #define MAX_TIMEOUT 100
108 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
109
110 /* I801 command constants */
111 #define I801_QUICK 0x00
112 #define I801_BYTE 0x04
113 #define I801_BYTE_DATA 0x08
114 #define I801_WORD_DATA 0x0C
115 #define I801_PROC_CALL 0x10 /* unimplemented */
116 #define I801_BLOCK_DATA 0x14
117 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
118 #define I801_BLOCK_LAST 0x34
119 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
120 #define I801_START 0x40
121 #define I801_PEC_EN 0x80 /* ICH3 and later */
122
123 /* I801 Hosts Status register bits */
124 #define SMBHSTSTS_BYTE_DONE 0x80
125 #define SMBHSTSTS_INUSE_STS 0x40
126 #define SMBHSTSTS_SMBALERT_STS 0x20
127 #define SMBHSTSTS_FAILED 0x10
128 #define SMBHSTSTS_BUS_ERR 0x08
129 #define SMBHSTSTS_DEV_ERR 0x04
130 #define SMBHSTSTS_INTR 0x02
131 #define SMBHSTSTS_HOST_BUSY 0x01
132
133 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
134 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
135 SMBHSTSTS_INTR)
136
137 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
138 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
139 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
140 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
141
142 struct i801_priv {
143 struct i2c_adapter adapter;
144 unsigned long smba;
145 unsigned char original_hstcfg;
146 struct pci_dev *pci_dev;
147 unsigned int features;
148 };
149
150 static struct pci_driver i801_driver;
151
152 #define FEATURE_SMBUS_PEC (1 << 0)
153 #define FEATURE_BLOCK_BUFFER (1 << 1)
154 #define FEATURE_BLOCK_PROC (1 << 2)
155 #define FEATURE_I2C_BLOCK_READ (1 << 3)
156
157 static const char *i801_feature_names[] = {
158 "SMBus PEC",
159 "Block buffer",
160 "Block process call",
161 "I2C block read",
162 };
163
164 static unsigned int disable_features;
165 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
166 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
167
168 /* Make sure the SMBus host is ready to start transmitting.
169 Return 0 if it is, -EBUSY if it is not. */
170 static int i801_check_pre(struct i801_priv *priv)
171 {
172 int status;
173
174 status = inb_p(SMBHSTSTS(priv));
175 if (status & SMBHSTSTS_HOST_BUSY) {
176 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
177 return -EBUSY;
178 }
179
180 status &= STATUS_FLAGS;
181 if (status) {
182 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
183 status);
184 outb_p(status, SMBHSTSTS(priv));
185 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
186 if (status) {
187 dev_err(&priv->pci_dev->dev,
188 "Failed clearing status flags (%02x)\n",
189 status);
190 return -EBUSY;
191 }
192 }
193
194 return 0;
195 }
196
197 /* Convert the status register to an error code, and clear it. */
198 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
199 {
200 int result = 0;
201
202 /* If the SMBus is still busy, we give up */
203 if (timeout) {
204 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
205 /* try to stop the current command */
206 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
207 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
208 SMBHSTCNT(priv));
209 msleep(1);
210 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
211 SMBHSTCNT(priv));
212
213 /* Check if it worked */
214 status = inb_p(SMBHSTSTS(priv));
215 if ((status & SMBHSTSTS_HOST_BUSY) ||
216 !(status & SMBHSTSTS_FAILED))
217 dev_err(&priv->pci_dev->dev,
218 "Failed terminating the transaction\n");
219 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
220 return -ETIMEDOUT;
221 }
222
223 if (status & SMBHSTSTS_FAILED) {
224 result = -EIO;
225 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
226 }
227 if (status & SMBHSTSTS_DEV_ERR) {
228 result = -ENXIO;
229 dev_dbg(&priv->pci_dev->dev, "No response\n");
230 }
231 if (status & SMBHSTSTS_BUS_ERR) {
232 result = -EAGAIN;
233 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
234 }
235
236 if (result) {
237 /* Clear error flags */
238 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
239 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
240 if (status) {
241 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
242 "flags at end of transaction (%02x)\n",
243 status);
244 }
245 }
246
247 return result;
248 }
249
250 static int i801_transaction(struct i801_priv *priv, int xact)
251 {
252 int status;
253 int result;
254 int timeout = 0;
255
256 result = i801_check_pre(priv);
257 if (result < 0)
258 return result;
259
260 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
261 * INTREN, SMBSCMD are passed in xact */
262 outb_p(xact | I801_START, SMBHSTCNT(priv));
263
264 /* We will always wait for a fraction of a second! */
265 do {
266 msleep(1);
267 status = inb_p(SMBHSTSTS(priv));
268 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
269
270 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
271 if (result < 0)
272 return result;
273
274 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
275 return 0;
276 }
277
278 /* wait for INTR bit as advised by Intel */
279 static void i801_wait_hwpec(struct i801_priv *priv)
280 {
281 int timeout = 0;
282 int status;
283
284 do {
285 msleep(1);
286 status = inb_p(SMBHSTSTS(priv));
287 } while ((!(status & SMBHSTSTS_INTR))
288 && (timeout++ < MAX_TIMEOUT));
289
290 if (timeout > MAX_TIMEOUT)
291 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
292
293 outb_p(status, SMBHSTSTS(priv));
294 }
295
296 static int i801_block_transaction_by_block(struct i801_priv *priv,
297 union i2c_smbus_data *data,
298 char read_write, int hwpec)
299 {
300 int i, len;
301 int status;
302
303 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
304
305 /* Use 32-byte buffer to process this transaction */
306 if (read_write == I2C_SMBUS_WRITE) {
307 len = data->block[0];
308 outb_p(len, SMBHSTDAT0(priv));
309 for (i = 0; i < len; i++)
310 outb_p(data->block[i+1], SMBBLKDAT(priv));
311 }
312
313 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
314 I801_PEC_EN * hwpec);
315 if (status)
316 return status;
317
318 if (read_write == I2C_SMBUS_READ) {
319 len = inb_p(SMBHSTDAT0(priv));
320 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
321 return -EPROTO;
322
323 data->block[0] = len;
324 for (i = 0; i < len; i++)
325 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
326 }
327 return 0;
328 }
329
330 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
331 union i2c_smbus_data *data,
332 char read_write, int command,
333 int hwpec)
334 {
335 int i, len;
336 int smbcmd;
337 int status;
338 int result;
339 int timeout;
340
341 result = i801_check_pre(priv);
342 if (result < 0)
343 return result;
344
345 len = data->block[0];
346
347 if (read_write == I2C_SMBUS_WRITE) {
348 outb_p(len, SMBHSTDAT0(priv));
349 outb_p(data->block[1], SMBBLKDAT(priv));
350 }
351
352 for (i = 1; i <= len; i++) {
353 if (i == len && read_write == I2C_SMBUS_READ) {
354 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
355 smbcmd = I801_I2C_BLOCK_LAST;
356 else
357 smbcmd = I801_BLOCK_LAST;
358 } else {
359 if (command == I2C_SMBUS_I2C_BLOCK_DATA
360 && read_write == I2C_SMBUS_READ)
361 smbcmd = I801_I2C_BLOCK_DATA;
362 else
363 smbcmd = I801_BLOCK_DATA;
364 }
365 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
366
367 if (i == 1)
368 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
369 SMBHSTCNT(priv));
370
371 /* We will always wait for a fraction of a second! */
372 timeout = 0;
373 do {
374 msleep(1);
375 status = inb_p(SMBHSTSTS(priv));
376 } while ((!(status & SMBHSTSTS_BYTE_DONE))
377 && (timeout++ < MAX_TIMEOUT));
378
379 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
380 if (result < 0)
381 return result;
382
383 if (i == 1 && read_write == I2C_SMBUS_READ
384 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
385 len = inb_p(SMBHSTDAT0(priv));
386 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
387 dev_err(&priv->pci_dev->dev,
388 "Illegal SMBus block read size %d\n",
389 len);
390 /* Recover */
391 while (inb_p(SMBHSTSTS(priv)) &
392 SMBHSTSTS_HOST_BUSY)
393 outb_p(SMBHSTSTS_BYTE_DONE,
394 SMBHSTSTS(priv));
395 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
396 return -EPROTO;
397 }
398 data->block[0] = len;
399 }
400
401 /* Retrieve/store value in SMBBLKDAT */
402 if (read_write == I2C_SMBUS_READ)
403 data->block[i] = inb_p(SMBBLKDAT(priv));
404 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
405 outb_p(data->block[i+1], SMBBLKDAT(priv));
406
407 /* signals SMBBLKDAT ready */
408 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
409 }
410
411 return 0;
412 }
413
414 static int i801_set_block_buffer_mode(struct i801_priv *priv)
415 {
416 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
417 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
418 return -EIO;
419 return 0;
420 }
421
422 /* Block transaction function */
423 static int i801_block_transaction(struct i801_priv *priv,
424 union i2c_smbus_data *data, char read_write,
425 int command, int hwpec)
426 {
427 int result = 0;
428 unsigned char hostc;
429
430 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
431 if (read_write == I2C_SMBUS_WRITE) {
432 /* set I2C_EN bit in configuration register */
433 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
434 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
435 hostc | SMBHSTCFG_I2C_EN);
436 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
437 dev_err(&priv->pci_dev->dev,
438 "I2C block read is unsupported!\n");
439 return -EOPNOTSUPP;
440 }
441 }
442
443 if (read_write == I2C_SMBUS_WRITE
444 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
445 if (data->block[0] < 1)
446 data->block[0] = 1;
447 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
448 data->block[0] = I2C_SMBUS_BLOCK_MAX;
449 } else {
450 data->block[0] = 32; /* max for SMBus block reads */
451 }
452
453 /* Experience has shown that the block buffer can only be used for
454 SMBus (not I2C) block transactions, even though the datasheet
455 doesn't mention this limitation. */
456 if ((priv->features & FEATURE_BLOCK_BUFFER)
457 && command != I2C_SMBUS_I2C_BLOCK_DATA
458 && i801_set_block_buffer_mode(priv) == 0)
459 result = i801_block_transaction_by_block(priv, data,
460 read_write, hwpec);
461 else
462 result = i801_block_transaction_byte_by_byte(priv, data,
463 read_write,
464 command, hwpec);
465
466 if (result == 0 && hwpec)
467 i801_wait_hwpec(priv);
468
469 if (command == I2C_SMBUS_I2C_BLOCK_DATA
470 && read_write == I2C_SMBUS_WRITE) {
471 /* restore saved configuration register value */
472 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
473 }
474 return result;
475 }
476
477 /* Return negative errno on error. */
478 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
479 unsigned short flags, char read_write, u8 command,
480 int size, union i2c_smbus_data *data)
481 {
482 int hwpec;
483 int block = 0;
484 int ret, xact = 0;
485 struct i801_priv *priv = i2c_get_adapdata(adap);
486
487 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
488 && size != I2C_SMBUS_QUICK
489 && size != I2C_SMBUS_I2C_BLOCK_DATA;
490
491 switch (size) {
492 case I2C_SMBUS_QUICK:
493 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
494 SMBHSTADD(priv));
495 xact = I801_QUICK;
496 break;
497 case I2C_SMBUS_BYTE:
498 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
499 SMBHSTADD(priv));
500 if (read_write == I2C_SMBUS_WRITE)
501 outb_p(command, SMBHSTCMD(priv));
502 xact = I801_BYTE;
503 break;
504 case I2C_SMBUS_BYTE_DATA:
505 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
506 SMBHSTADD(priv));
507 outb_p(command, SMBHSTCMD(priv));
508 if (read_write == I2C_SMBUS_WRITE)
509 outb_p(data->byte, SMBHSTDAT0(priv));
510 xact = I801_BYTE_DATA;
511 break;
512 case I2C_SMBUS_WORD_DATA:
513 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
514 SMBHSTADD(priv));
515 outb_p(command, SMBHSTCMD(priv));
516 if (read_write == I2C_SMBUS_WRITE) {
517 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
518 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
519 }
520 xact = I801_WORD_DATA;
521 break;
522 case I2C_SMBUS_BLOCK_DATA:
523 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
524 SMBHSTADD(priv));
525 outb_p(command, SMBHSTCMD(priv));
526 block = 1;
527 break;
528 case I2C_SMBUS_I2C_BLOCK_DATA:
529 /* NB: page 240 of ICH5 datasheet shows that the R/#W
530 * bit should be cleared here, even when reading */
531 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
532 if (read_write == I2C_SMBUS_READ) {
533 /* NB: page 240 of ICH5 datasheet also shows
534 * that DATA1 is the cmd field when reading */
535 outb_p(command, SMBHSTDAT1(priv));
536 } else
537 outb_p(command, SMBHSTCMD(priv));
538 block = 1;
539 break;
540 default:
541 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
542 size);
543 return -EOPNOTSUPP;
544 }
545
546 if (hwpec) /* enable/disable hardware PEC */
547 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
548 else
549 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
550 SMBAUXCTL(priv));
551
552 if (block)
553 ret = i801_block_transaction(priv, data, read_write, size,
554 hwpec);
555 else
556 ret = i801_transaction(priv, xact | ENABLE_INT9);
557
558 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
559 time, so we forcibly disable it after every transaction. Turn off
560 E32B for the same reason. */
561 if (hwpec || block)
562 outb_p(inb_p(SMBAUXCTL(priv)) &
563 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
564
565 if (block)
566 return ret;
567 if (ret)
568 return ret;
569 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
570 return 0;
571
572 switch (xact & 0x7f) {
573 case I801_BYTE: /* Result put in SMBHSTDAT0 */
574 case I801_BYTE_DATA:
575 data->byte = inb_p(SMBHSTDAT0(priv));
576 break;
577 case I801_WORD_DATA:
578 data->word = inb_p(SMBHSTDAT0(priv)) +
579 (inb_p(SMBHSTDAT1(priv)) << 8);
580 break;
581 }
582 return 0;
583 }
584
585
586 static u32 i801_func(struct i2c_adapter *adapter)
587 {
588 struct i801_priv *priv = i2c_get_adapdata(adapter);
589
590 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
591 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
592 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
593 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
594 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
595 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
596 }
597
598 static const struct i2c_algorithm smbus_algorithm = {
599 .smbus_xfer = i801_access,
600 .functionality = i801_func,
601 };
602
603 static const struct pci_device_id i801_ids[] = {
604 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
605 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
606 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
607 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
608 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
609 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
610 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
611 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
612 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
613 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
614 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
626 { 0, }
627 };
628
629 MODULE_DEVICE_TABLE(pci, i801_ids);
630
631 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
632 static unsigned char apanel_addr;
633
634 /* Scan the system ROM for the signature "FJKEYINF" */
635 static __init const void __iomem *bios_signature(const void __iomem *bios)
636 {
637 ssize_t offset;
638 const unsigned char signature[] = "FJKEYINF";
639
640 for (offset = 0; offset < 0x10000; offset += 0x10) {
641 if (check_signature(bios + offset, signature,
642 sizeof(signature)-1))
643 return bios + offset;
644 }
645 return NULL;
646 }
647
648 static void __init input_apanel_init(void)
649 {
650 void __iomem *bios;
651 const void __iomem *p;
652
653 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
654 p = bios_signature(bios);
655 if (p) {
656 /* just use the first address */
657 apanel_addr = readb(p + 8 + 3) >> 1;
658 }
659 iounmap(bios);
660 }
661 #else
662 static void __init input_apanel_init(void) {}
663 #endif
664
665 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
666 struct dmi_onboard_device_info {
667 const char *name;
668 u8 type;
669 unsigned short i2c_addr;
670 const char *i2c_type;
671 };
672
673 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
674 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
675 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
676 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
677 };
678
679 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
680 struct i2c_adapter *adap)
681 {
682 int i;
683 struct i2c_board_info info;
684
685 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
686 /* & ~0x80, ignore enabled/disabled bit */
687 if ((type & ~0x80) != dmi_devices[i].type)
688 continue;
689 if (strcasecmp(name, dmi_devices[i].name))
690 continue;
691
692 memset(&info, 0, sizeof(struct i2c_board_info));
693 info.addr = dmi_devices[i].i2c_addr;
694 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
695 i2c_new_device(adap, &info);
696 break;
697 }
698 }
699
700 /* We use our own function to check for onboard devices instead of
701 dmi_find_device() as some buggy BIOS's have the devices we are interested
702 in marked as disabled */
703 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
704 void *adap)
705 {
706 int i, count;
707
708 if (dm->type != 10)
709 return;
710
711 count = (dm->length - sizeof(struct dmi_header)) / 2;
712 for (i = 0; i < count; i++) {
713 const u8 *d = (char *)(dm + 1) + (i * 2);
714 const char *name = ((char *) dm) + dm->length;
715 u8 type = d[0];
716 u8 s = d[1];
717
718 if (!s)
719 continue;
720 s--;
721 while (s > 0 && name[0]) {
722 name += strlen(name) + 1;
723 s--;
724 }
725 if (name[0] == 0) /* Bogus string reference */
726 continue;
727
728 dmi_check_onboard_device(type, name, adap);
729 }
730 }
731 #endif
732
733 static int __devinit i801_probe(struct pci_dev *dev,
734 const struct pci_device_id *id)
735 {
736 unsigned char temp;
737 int err, i;
738 struct i801_priv *priv;
739
740 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
741 if (!priv)
742 return -ENOMEM;
743
744 i2c_set_adapdata(&priv->adapter, priv);
745 priv->adapter.owner = THIS_MODULE;
746 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
747 priv->adapter.algo = &smbus_algorithm;
748
749 priv->pci_dev = dev;
750 switch (dev->device) {
751 default:
752 priv->features |= FEATURE_I2C_BLOCK_READ;
753 /* fall through */
754 case PCI_DEVICE_ID_INTEL_82801DB_3:
755 priv->features |= FEATURE_SMBUS_PEC;
756 priv->features |= FEATURE_BLOCK_BUFFER;
757 /* fall through */
758 case PCI_DEVICE_ID_INTEL_82801CA_3:
759 case PCI_DEVICE_ID_INTEL_82801BA_2:
760 case PCI_DEVICE_ID_INTEL_82801AB_3:
761 case PCI_DEVICE_ID_INTEL_82801AA_3:
762 break;
763 }
764
765 /* Disable features on user request */
766 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
767 if (priv->features & disable_features & (1 << i))
768 dev_notice(&dev->dev, "%s disabled by user\n",
769 i801_feature_names[i]);
770 }
771 priv->features &= ~disable_features;
772
773 err = pci_enable_device(dev);
774 if (err) {
775 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
776 err);
777 goto exit;
778 }
779
780 /* Determine the address of the SMBus area */
781 priv->smba = pci_resource_start(dev, SMBBAR);
782 if (!priv->smba) {
783 dev_err(&dev->dev, "SMBus base address uninitialized, "
784 "upgrade BIOS\n");
785 err = -ENODEV;
786 goto exit;
787 }
788
789 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
790 if (err) {
791 err = -ENODEV;
792 goto exit;
793 }
794
795 err = pci_request_region(dev, SMBBAR, i801_driver.name);
796 if (err) {
797 dev_err(&dev->dev, "Failed to request SMBus region "
798 "0x%lx-0x%Lx\n", priv->smba,
799 (unsigned long long)pci_resource_end(dev, SMBBAR));
800 goto exit;
801 }
802
803 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
804 priv->original_hstcfg = temp;
805 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
806 if (!(temp & SMBHSTCFG_HST_EN)) {
807 dev_info(&dev->dev, "Enabling SMBus device\n");
808 temp |= SMBHSTCFG_HST_EN;
809 }
810 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
811
812 if (temp & SMBHSTCFG_SMB_SMI_EN)
813 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
814 else
815 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
816
817 /* Clear special mode bits */
818 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
819 outb_p(inb_p(SMBAUXCTL(priv)) &
820 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
821
822 /* set up the sysfs linkage to our parent device */
823 priv->adapter.dev.parent = &dev->dev;
824
825 /* Retry up to 3 times on lost arbitration */
826 priv->adapter.retries = 3;
827
828 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
829 "SMBus I801 adapter at %04lx", priv->smba);
830 err = i2c_add_adapter(&priv->adapter);
831 if (err) {
832 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
833 goto exit_release;
834 }
835
836 /* Register optional slaves */
837 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
838 if (apanel_addr) {
839 struct i2c_board_info info;
840
841 memset(&info, 0, sizeof(struct i2c_board_info));
842 info.addr = apanel_addr;
843 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
844 i2c_new_device(&priv->adapter, &info);
845 }
846 #endif
847 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
848 if (dmi_name_in_vendors("FUJITSU"))
849 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
850 #endif
851
852 pci_set_drvdata(dev, priv);
853 return 0;
854
855 exit_release:
856 pci_release_region(dev, SMBBAR);
857 exit:
858 kfree(priv);
859 return err;
860 }
861
862 static void __devexit i801_remove(struct pci_dev *dev)
863 {
864 struct i801_priv *priv = pci_get_drvdata(dev);
865
866 i2c_del_adapter(&priv->adapter);
867 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
868 pci_release_region(dev, SMBBAR);
869 pci_set_drvdata(dev, NULL);
870 kfree(priv);
871 /*
872 * do not call pci_disable_device(dev) since it can cause hard hangs on
873 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
874 */
875 }
876
877 #ifdef CONFIG_PM
878 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
879 {
880 struct i801_priv *priv = pci_get_drvdata(dev);
881
882 pci_save_state(dev);
883 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
884 pci_set_power_state(dev, pci_choose_state(dev, mesg));
885 return 0;
886 }
887
888 static int i801_resume(struct pci_dev *dev)
889 {
890 pci_set_power_state(dev, PCI_D0);
891 pci_restore_state(dev);
892 return pci_enable_device(dev);
893 }
894 #else
895 #define i801_suspend NULL
896 #define i801_resume NULL
897 #endif
898
899 static struct pci_driver i801_driver = {
900 .name = "i801_smbus",
901 .id_table = i801_ids,
902 .probe = i801_probe,
903 .remove = __devexit_p(i801_remove),
904 .suspend = i801_suspend,
905 .resume = i801_resume,
906 };
907
908 static int __init i2c_i801_init(void)
909 {
910 input_apanel_init();
911 return pci_register_driver(&i801_driver);
912 }
913
914 static void __exit i2c_i801_exit(void)
915 {
916 pci_unregister_driver(&i801_driver);
917 }
918
919 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
920 "Jean Delvare <khali@linux-fr.org>");
921 MODULE_DESCRIPTION("I801 SMBus driver");
922 MODULE_LICENSE("GPL");
923
924 module_init(i2c_i801_init);
925 module_exit(i2c_i801_exit);
kernel-based virtual machine