arch/x86/kernel/setup_64.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  */
   4
   5 /*
   6  * This file handles the architecture-dependent parts of initialization
   7  */
   8
   9 #include <linux/errno.h>
  10 #include <linux/sched.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/stddef.h>
  14 #include <linux/unistd.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/slab.h>
  17 #include <linux/user.h>
  18 #include <linux/screen_info.h>
  19 #include <linux/ioport.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/initrd.h>
  23 #include <linux/highmem.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/module.h>
  26 #include <asm/processor.h>
  27 #include <linux/console.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/crash_dump.h>
  30 #include <linux/root_dev.h>
  31 #include <linux/pci.h>
  32 #include <linux/efi.h>
  33 #include <linux/acpi.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/edd.h>
  36 #include <linux/mmzone.h>
  37 #include <linux/kexec.h>
  38 #include <linux/cpufreq.h>
  39 #include <linux/dmi.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/ctype.h>
  42 #include <linux/uaccess.h>
  43 #include <linux/init_ohci1394_dma.h>
  44
  45 #include <asm/mtrr.h>
  46 #include <asm/uaccess.h>
  47 #include <asm/system.h>
  48 #include <asm/vsyscall.h>
  49 #include <asm/io.h>
  50 #include <asm/smp.h>
  51 #include <asm/msr.h>
  52 #include <asm/desc.h>
  53 #include <video/edid.h>
  54 #include <asm/e820.h>
  55 #include <asm/dma.h>
  56 #include <asm/gart.h>
  57 #include <asm/mpspec.h>
  58 #include <asm/mmu_context.h>
  59 #include <asm/proto.h>
  60 #include <asm/setup.h>
  61 #include <asm/mach_apic.h>
  62 #include <asm/numa.h>
  63 #include <asm/sections.h>
  64 #include <asm/dmi.h>
  65 #include <asm/cacheflush.h>
  66 #include <asm/mce.h>
  67 #include <asm/ds.h>
  68 #include <asm/topology.h>
  69
  70 #ifdef CONFIG_PARAVIRT
  71 #include <asm/paravirt.h>
  72 #else
  73 #define ARCH_SETUP
  74 #endif
  75
  76 /*
  77  * Machine setup..
  78  */
  79
  80 struct cpuinfo_x86 boot_cpu_data __read_mostly;
  81 EXPORT_SYMBOL(boot_cpu_data);
  82
  83 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
  84
  85 unsigned long mmu_cr4_features;
  86
  87 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  88 int bootloader_type;
  89
  90 unsigned long saved_video_mode;
  91
  92 int force_mwait __cpuinitdata;
  93
  94 /*
  95  * Early DMI memory
  96  */
  97 int dmi_alloc_index;
  98 char dmi_alloc_data[DMI_MAX_DATA];
  99
 100 /*
 101  * Setup options
 102  */
 103 struct screen_info screen_info;
 104 EXPORT_SYMBOL(screen_info);
 105 struct sys_desc_table_struct {
 106         unsigned short length;
 107         unsigned char table[0];
 108 };
 109
 110 struct edid_info edid_info;
 111 EXPORT_SYMBOL_GPL(edid_info);
 112
 113 extern int root_mountflags;
 114
 115 char __initdata command_line[COMMAND_LINE_SIZE];
 116
 117 struct resource standard_io_resources[] = {
 118         { .name = "dma1", .start = 0x00, .end = 0x1f,
 119                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 120         { .name = "pic1", .start = 0x20, .end = 0x21,
 121                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 122         { .name = "timer0", .start = 0x40, .end = 0x43,
 123                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 124         { .name = "timer1", .start = 0x50, .end = 0x53,
 125                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 126         { .name = "keyboard", .start = 0x60, .end = 0x6f,
 127                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 128         { .name = "dma page reg", .start = 0x80, .end = 0x8f,
 129                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 130         { .name = "pic2", .start = 0xa0, .end = 0xa1,
 131                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 132         { .name = "dma2", .start = 0xc0, .end = 0xdf,
 133                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 134         { .name = "fpu", .start = 0xf0, .end = 0xff,
 135                 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
 136 };
 137
 138 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
 139
 140 static struct resource data_resource = {
 141         .name = "Kernel data",
 142         .start = 0,
 143         .end = 0,
 144         .flags = IORESOURCE_RAM,
 145 };
 146 static struct resource code_resource = {
 147         .name = "Kernel code",
 148         .start = 0,
 149         .end = 0,
 150         .flags = IORESOURCE_RAM,
 151 };
 152 static struct resource bss_resource = {
 153         .name = "Kernel bss",
 154         .start = 0,
 155         .end = 0,
 156         .flags = IORESOURCE_RAM,
 157 };
 158
 159 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
 160
 161 #ifdef CONFIG_PROC_VMCORE
 162 /* elfcorehdr= specifies the location of elf core header
 163  * stored by the crashed kernel. This option will be passed
 164  * by kexec loader to the capture kernel.
 165  */
 166 static int __init setup_elfcorehdr(char *arg)
 167 {
 168         char *end;
 169         if (!arg)
 170                 return -EINVAL;
 171         elfcorehdr_addr = memparse(arg, &end);
 172         return end > arg ? 0 : -EINVAL;
 173 }
 174 early_param("elfcorehdr", setup_elfcorehdr);
 175 #endif
 176
 177 #ifndef CONFIG_NUMA
 178 static void __init
 179 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 180 {
 181         unsigned long bootmap_size, bootmap;
 182
 183         bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
 184         bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
 185                                  PAGE_SIZE);
 186         if (bootmap == -1L)
 187                 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
 188         bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
 189         e820_register_active_regions(0, start_pfn, end_pfn);
 190         free_bootmem_with_active_regions(0, end_pfn);
 191         reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
 192 }
 193 #endif
 194
 195 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 196 struct edd edd;
 197 #ifdef CONFIG_EDD_MODULE
 198 EXPORT_SYMBOL(edd);
 199 #endif
 200 /**
 201  * copy_edd() - Copy the BIOS EDD information
 202  *              from boot_params into a safe place.
 203  *
 204  */
 205 static inline void copy_edd(void)
 206 {
 207      memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
 208             sizeof(edd.mbr_signature));
 209      memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
 210      edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
 211      edd.edd_info_nr = boot_params.eddbuf_entries;
 212 }
 213 #else
 214 static inline void copy_edd(void)
 215 {
 216 }
 217 #endif
 218
 219 #ifdef CONFIG_KEXEC
 220 static void __init reserve_crashkernel(void)
 221 {
 222         unsigned long long total_mem;
 223         unsigned long long crash_size, crash_base;
 224         int ret;
 225
 226         total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
 227
 228         ret = parse_crashkernel(boot_command_line, total_mem,
 229                         &crash_size, &crash_base);
 230         if (ret == 0 && crash_size) {
 231                 if (crash_base <= 0) {
 232                         printk(KERN_INFO "crashkernel reservation failed - "
 233                                         "you have to specify a base address\n");
 234                         return;
 235                 }
 236
 237                 if (reserve_bootmem(crash_base, crash_size,
 238                                         BOOTMEM_EXCLUSIVE) < 0) {
 239                         printk(KERN_INFO "crashkernel reservation failed - "
 240                                         "memory is in use\n");
 241                         return;
 242                 }
 243
 244                 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
 245                                 "for crashkernel (System RAM: %ldMB)\n",
 246                                 (unsigned long)(crash_size >> 20),
 247                                 (unsigned long)(crash_base >> 20),
 248                                 (unsigned long)(total_mem >> 20));
 249                 crashk_res.start = crash_base;
 250                 crashk_res.end   = crash_base + crash_size - 1;
 251                 insert_resource(&iomem_resource, &crashk_res);
 252         }
 253 }
 254 #else
 255 static inline void __init reserve_crashkernel(void)
 256 {}
 257 #endif
 258
 259 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
 260 void __attribute__((weak)) __init memory_setup(void)
 261 {
 262        machine_specific_memory_setup();
 263 }
 264
 265 /*
 266  * setup_arch - architecture-specific boot-time initializations
 267  *
 268  * Note: On x86_64, fixmaps are ready for use even before this is called.
 269  */
 270 void __init setup_arch(char **cmdline_p)
 271 {
 272         unsigned i;
 273
 274         printk(KERN_INFO "Command line: %s\n", boot_command_line);
 275
 276         ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
 277         screen_info = boot_params.screen_info;
 278         edid_info = boot_params.edid_info;
 279         saved_video_mode = boot_params.hdr.vid_mode;
 280         bootloader_type = boot_params.hdr.type_of_loader;
 281
 282 #ifdef CONFIG_BLK_DEV_RAM
 283         rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
 284         rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
 285         rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
 286 #endif
 287 #ifdef CONFIG_EFI
 288         if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
 289                      "EL64", 4))
 290                 efi_enabled = 1;
 291 #endif
 292
 293         ARCH_SETUP
 294
 295         memory_setup();
 296         copy_edd();
 297
 298         if (!boot_params.hdr.root_flags)
 299                 root_mountflags &= ~MS_RDONLY;
 300         init_mm.start_code = (unsigned long) &_text;
 301         init_mm.end_code = (unsigned long) &_etext;
 302         init_mm.end_data = (unsigned long) &_edata;
 303         init_mm.brk = (unsigned long) &_end;
 304
 305         code_resource.start = virt_to_phys(&_text);
 306         code_resource.end = virt_to_phys(&_etext)-1;
 307         data_resource.start = virt_to_phys(&_etext);
 308         data_resource.end = virt_to_phys(&_edata)-1;
 309         bss_resource.start = virt_to_phys(&__bss_start);
 310         bss_resource.end = virt_to_phys(&__bss_stop)-1;
 311
 312         early_identify_cpu(&boot_cpu_data);
 313
 314         strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 315         *cmdline_p = command_line;
 316
 317         parse_early_param();
 318
 319 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
 320         if (init_ohci1394_dma_early)
 321                 init_ohci1394_dma_on_all_controllers();
 322 #endif
 323
 324         finish_e820_parsing();
 325
 326         /* after parse_early_param, so could debug it */
 327         insert_resource(&iomem_resource, &code_resource);
 328         insert_resource(&iomem_resource, &data_resource);
 329         insert_resource(&iomem_resource, &bss_resource);
 330
 331         early_gart_iommu_check();
 332
 333         e820_register_active_regions(0, 0, -1UL);
 334         /*
 335          * partially used pages are not usable - thus
 336          * we are rounding upwards:
 337          */
 338         end_pfn = e820_end_of_ram();
 339         /* update e820 for memory not covered by WB MTRRs */
 340         mtrr_bp_init();
 341         if (mtrr_trim_uncached_memory(end_pfn)) {
 342                 e820_register_active_regions(0, 0, -1UL);
 343                 end_pfn = e820_end_of_ram();
 344         }
 345
 346         num_physpages = end_pfn;
 347
 348         check_efer();
 349
 350         init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
 351         if (efi_enabled)
 352                 efi_init();
 353
 354         vsmp_init();
 355
 356         dmi_scan_machine();
 357
 358         io_delay_init();
 359
 360 #ifdef CONFIG_SMP
 361         /* setup to use the early static init tables during kernel startup */
 362         x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
 363         x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
 364 #ifdef CONFIG_NUMA
 365         x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
 366 #endif
 367 #endif
 368
 369 #ifdef CONFIG_ACPI
 370         /*
 371          * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
 372          * Call this early for SRAT node setup.
 373          */
 374         acpi_boot_table_init();
 375 #endif
 376
 377         /* How many end-of-memory variables you have, grandma! */
 378         max_low_pfn = end_pfn;
 379         max_pfn = end_pfn;
 380         high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
 381
 382         /* Remove active ranges so rediscovery with NUMA-awareness happens */
 383         remove_all_active_ranges();
 384
 385 #ifdef CONFIG_ACPI_NUMA
 386         /*
 387          * Parse SRAT to discover nodes.
 388          */
 389         acpi_numa_init();
 390 #endif
 391
 392 #ifdef CONFIG_NUMA
 393         numa_initmem_init(0, end_pfn);
 394 #else
 395         contig_initmem_init(0, end_pfn);
 396 #endif
 397
 398         early_res_to_bootmem();
 399
 400 #ifdef CONFIG_ACPI_SLEEP
 401         /*
 402          * Reserve low memory region for sleep support.
 403          */
 404        acpi_reserve_bootmem();
 405 #endif
 406
 407         if (efi_enabled)
 408                 efi_reserve_bootmem();
 409
 410        /*
 411         * Find and reserve possible boot-time SMP configuration:
 412         */
 413         find_smp_config();
 414 #ifdef CONFIG_BLK_DEV_INITRD
 415         if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
 416                 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
 417                 unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
 418                 unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
 419                 unsigned long end_of_mem    = end_pfn << PAGE_SHIFT;
 420
 421                 if (ramdisk_end <= end_of_mem) {
 422                         reserve_bootmem_generic(ramdisk_image, ramdisk_size);
 423                         initrd_start = ramdisk_image + PAGE_OFFSET;
 424                         initrd_end = initrd_start+ramdisk_size;
 425                 } else {
 426                         /* Assumes everything on node 0 */
 427                         free_bootmem(ramdisk_image, ramdisk_size);
 428                         printk(KERN_ERR "initrd extends beyond end of memory "
 429                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 430                                ramdisk_end, end_of_mem);
 431                         initrd_start = 0;
 432                 }
 433         }
 434 #endif
 435         reserve_crashkernel();
 436         paging_init();
 437         map_vsyscall();
 438
 439         early_quirks();
 440
 441 #ifdef CONFIG_ACPI
 442         /*
 443          * Read APIC and some other early information from ACPI tables.
 444          */
 445         acpi_boot_init();
 446 #endif
 447
 448         init_cpu_to_node();
 449
 450         /*
 451          * get boot-time SMP configuration:
 452          */
 453         if (smp_found_config)
 454                 get_smp_config();
 455         init_apic_mappings();
 456         ioapic_init_mappings();
 457
 458         /*
 459          * We trust e820 completely. No explicit ROM probing in memory.
 460          */
 461         e820_reserve_resources();
 462         e820_mark_nosave_regions();
 463
 464         /* request I/O space for devices used on all i[345]86 PCs */
 465         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 466                 request_resource(&ioport_resource, &standard_io_resources[i]);
 467
 468         e820_setup_gap();
 469
 470 #ifdef CONFIG_VT
 471 #if defined(CONFIG_VGA_CONSOLE)
 472         if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
 473                 conswitchp = &vga_con;
 474 #elif defined(CONFIG_DUMMY_CONSOLE)
 475         conswitchp = &dummy_con;
 476 #endif
 477 #endif
 478 }
 479
 480 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 481 {
 482         unsigned int *v;
 483
 484         if (c->extended_cpuid_level < 0x80000004)
 485                 return 0;
 486
 487         v = (unsigned int *) c->x86_model_id;
 488         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 489         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 490         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 491         c->x86_model_id[48] = 0;
 492         return 1;
 493 }
 494
 495
 496 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 497 {
 498         unsigned int n, dummy, eax, ebx, ecx, edx;
 499
 500         n = c->extended_cpuid_level;
 501
 502         if (n >= 0x80000005) {
 503                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 504                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
 505                        "D cache %dK (%d bytes/line)\n",
 506                        edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 507                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 508                 /* On K8 L1 TLB is inclusive, so don't count it */
 509                 c->x86_tlbsize = 0;
 510         }
 511
 512         if (n >= 0x80000006) {
 513                 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 514                 ecx = cpuid_ecx(0x80000006);
 515                 c->x86_cache_size = ecx >> 16;
 516                 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 517
 518                 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 519                 c->x86_cache_size, ecx & 0xFF);
 520         }
 521         if (n >= 0x80000008) {
 522                 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
 523                 c->x86_virt_bits = (eax >> 8) & 0xff;
 524                 c->x86_phys_bits = eax & 0xff;
 525         }
 526 }
 527
 528 #ifdef CONFIG_NUMA
 529 static int __cpuinit nearby_node(int apicid)
 530 {
 531         int i, node;
 532
 533         for (i = apicid - 1; i >= 0; i--) {
 534                 node = apicid_to_node[i];
 535                 if (node != NUMA_NO_NODE && node_online(node))
 536                         return node;
 537         }
 538         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
 539                 node = apicid_to_node[i];
 540                 if (node != NUMA_NO_NODE && node_online(node))
 541                         return node;
 542         }
 543         return first_node(node_online_map); /* Shouldn't happen */
 544 }
 545 #endif
 546
 547 /*
 548  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 549  * Assumes number of cores is a power of two.
 550  */
 551 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 552 {
 553 #ifdef CONFIG_SMP
 554         unsigned bits;
 555 #ifdef CONFIG_NUMA
 556         int cpu = smp_processor_id();
 557         int node = 0;
 558         unsigned apicid = hard_smp_processor_id();
 559 #endif
 560         bits = c->x86_coreid_bits;
 561
 562         /* Low order bits define the core id (index of core in socket) */
 563         c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
 564         /* Convert the initial APIC ID into the socket ID */
 565         c->phys_proc_id = c->initial_apicid >> bits;
 566
 567 #ifdef CONFIG_NUMA
 568         node = c->phys_proc_id;
 569         if (apicid_to_node[apicid] != NUMA_NO_NODE)
 570                 node = apicid_to_node[apicid];
 571         if (!node_online(node)) {
 572                 /* Two possibilities here:
 573                    - The CPU is missing memory and no node was created.
 574                    In that case try picking one from a nearby CPU
 575                    - The APIC IDs differ from the HyperTransport node IDs
 576                    which the K8 northbridge parsing fills in.
 577                    Assume they are all increased by a constant offset,
 578                    but in the same order as the HT nodeids.
 579                    If that doesn't result in a usable node fall back to the
 580                    path for the previous case.  */
 581
 582                 int ht_nodeid = c->initial_apicid;
 583
 584                 if (ht_nodeid >= 0 &&
 585                     apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
 586                         node = apicid_to_node[ht_nodeid];
 587                 /* Pick a nearby node */
 588                 if (!node_online(node))
 589                         node = nearby_node(apicid);
 590         }
 591         numa_set_node(cpu, node);
 592
 593         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 594 #endif
 595 #endif
 596 }
 597
 598 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 599 {
 600 #ifdef CONFIG_SMP
 601         unsigned bits, ecx;
 602
 603         /* Multi core CPU? */
 604         if (c->extended_cpuid_level < 0x80000008)
 605                 return;
 606
 607         ecx = cpuid_ecx(0x80000008);
 608
 609         c->x86_max_cores = (ecx & 0xff) + 1;
 610
 611         /* CPU telling us the core id bits shift? */
 612         bits = (ecx >> 12) & 0xF;
 613
 614         /* Otherwise recompute */
 615         if (bits == 0) {
 616                 while ((1 << bits) < c->x86_max_cores)
 617                         bits++;
 618         }
 619
 620         c->x86_coreid_bits = bits;
 621
 622 #endif
 623 }
 624
 625 #define ENABLE_C1E_MASK         0x18000000
 626 #define CPUID_PROCESSOR_SIGNATURE       1
 627 #define CPUID_XFAM              0x0ff00000
 628 #define CPUID_XFAM_K8           0x00000000
 629 #define CPUID_XFAM_10H          0x00100000
 630 #define CPUID_XFAM_11H          0x00200000
 631 #define CPUID_XMOD              0x000f0000
 632 #define CPUID_XMOD_REV_F        0x00040000
 633
 634 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
 635 static __cpuinit int amd_apic_timer_broken(void)
 636 {
 637         u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
 638
 639         switch (eax & CPUID_XFAM) {
 640         case CPUID_XFAM_K8:
 641                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
 642                         break;
 643         case CPUID_XFAM_10H:
 644         case CPUID_XFAM_11H:
 645                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
 646                 if (lo & ENABLE_C1E_MASK)
 647                         return 1;
 648                 break;
 649         default:
 650                 /* err on the side of caution */
 651                 return 1;
 652         }
 653         return 0;
 654 }
 655
 656 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 657 {
 658         early_init_amd_mc(c);
 659
 660         /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
 661         if (c->x86_power & (1<<8))
 662                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 663 }
 664
 665 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 666 {
 667         unsigned level;
 668
 669 #ifdef CONFIG_SMP
 670         unsigned long value;
 671
 672         /*
 673          * Disable TLB flush filter by setting HWCR.FFDIS on K8
 674          * bit 6 of msr C001_0015
 675          *
 676          * Errata 63 for SH-B3 steppings
 677          * Errata 122 for all steppings (F+ have it disabled by default)
 678          */
 679         if (c->x86 == 15) {
 680                 rdmsrl(MSR_K8_HWCR, value);
 681                 value |= 1 << 6;
 682                 wrmsrl(MSR_K8_HWCR, value);
 683         }
 684 #endif
 685
 686         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 687            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 688         clear_cpu_cap(c, 0*32+31);
 689
 690         /* On C+ stepping K8 rep microcode works well for copy/memset */
 691         level = cpuid_eax(1);
 692         if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
 693                              level >= 0x0f58))
 694                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 695         if (c->x86 == 0x10 || c->x86 == 0x11)
 696                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 697
 698         /* Enable workaround for FXSAVE leak */
 699         if (c->x86 >= 6)
 700                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 701
 702         level = get_model_name(c);
 703         if (!level) {
 704                 switch (c->x86) {
 705                 case 15:
 706                         /* Should distinguish Models here, but this is only
 707                            a fallback anyways. */
 708                         strcpy(c->x86_model_id, "Hammer");
 709                         break;
 710                 }
 711         }
 712         display_cacheinfo(c);
 713
 714         /* Multi core CPU? */
 715         if (c->extended_cpuid_level >= 0x80000008)
 716                 amd_detect_cmp(c);
 717
 718         if (c->extended_cpuid_level >= 0x80000006 &&
 719                 (cpuid_edx(0x80000006) & 0xf000))
 720                 num_cache_leaves = 4;
 721         else
 722                 num_cache_leaves = 3;
 723
 724         if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
 725                 set_cpu_cap(c, X86_FEATURE_K8);
 726
 727         /* MFENCE stops RDTSC speculation */
 728         set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 729
 730         if (amd_apic_timer_broken())
 731                 disable_apic_timer = 1;
 732 }
 733
 734 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 735 {
 736 #ifdef CONFIG_SMP
 737         u32 eax, ebx, ecx, edx;
 738         int index_msb, core_bits;
 739
 740         cpuid(1, &eax, &ebx, &ecx, &edx);
 741
 742
 743         if (!cpu_has(c, X86_FEATURE_HT))
 744                 return;
 745         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 746                 goto out;
 747
 748         smp_num_siblings = (ebx & 0xff0000) >> 16;
 749
 750         if (smp_num_siblings == 1) {
 751                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 752         } else if (smp_num_siblings > 1) {
 753
 754                 if (smp_num_siblings > NR_CPUS) {
 755                         printk(KERN_WARNING "CPU: Unsupported number of "
 756                                "siblings %d", smp_num_siblings);
 757                         smp_num_siblings = 1;
 758                         return;
 759                 }
 760
 761                 index_msb = get_count_order(smp_num_siblings);
 762                 c->phys_proc_id = phys_pkg_id(index_msb);
 763
 764                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 765
 766                 index_msb = get_count_order(smp_num_siblings);
 767
 768                 core_bits = get_count_order(c->x86_max_cores);
 769
 770                 c->cpu_core_id = phys_pkg_id(index_msb) &
 771                                                ((1 << core_bits) - 1);
 772         }
 773 out:
 774         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 775                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 776                        c->phys_proc_id);
 777                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 778                        c->cpu_core_id);
 779         }
 780
 781 #endif
 782 }
 783
 784 /*
 785  * find out the number of processor cores on the die
 786  */
 787 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 788 {
 789         unsigned int eax, t;
 790
 791         if (c->cpuid_level < 4)
 792                 return 1;
 793
 794         cpuid_count(4, 0, &eax, &t, &t, &t);
 795
 796         if (eax & 0x1f)
 797                 return ((eax >> 26) + 1);
 798         else
 799                 return 1;
 800 }
 801
 802 static void __cpuinit srat_detect_node(void)
 803 {
 804 #ifdef CONFIG_NUMA
 805         unsigned node;
 806         int cpu = smp_processor_id();
 807         int apicid = hard_smp_processor_id();
 808
 809         /* Don't do the funky fallback heuristics the AMD version employs
 810            for now. */
 811         node = apicid_to_node[apicid];
 812         if (node == NUMA_NO_NODE || !node_online(node))
 813                 node = first_node(node_online_map);
 814         numa_set_node(cpu, node);
 815
 816         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 817 #endif
 818 }
 819
 820 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 821 {
 822         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
 823             (c->x86 == 0x6 && c->x86_model >= 0x0e))
 824                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 825 }
 826
 827 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 828 {
 829         /* Cache sizes */
 830         unsigned n;
 831
 832         init_intel_cacheinfo(c);
 833         if (c->cpuid_level > 9) {
 834                 unsigned eax = cpuid_eax(10);
 835                 /* Check for version and the number of counters */
 836                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 837                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 838         }
 839
 840         if (cpu_has_ds) {
 841                 unsigned int l1, l2;
 842                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 843                 if (!(l1 & (1<<11)))
 844                         set_cpu_cap(c, X86_FEATURE_BTS);
 845                 if (!(l1 & (1<<12)))
 846                         set_cpu_cap(c, X86_FEATURE_PEBS);
 847         }
 848
 849
 850         if (cpu_has_bts)
 851                 ds_init_intel(c);
 852
 853         n = c->extended_cpuid_level;
 854         if (n >= 0x80000008) {
 855                 unsigned eax = cpuid_eax(0x80000008);
 856                 c->x86_virt_bits = (eax >> 8) & 0xff;
 857                 c->x86_phys_bits = eax & 0xff;
 858                 /* CPUID workaround for Intel 0F34 CPU */
 859                 if (c->x86_vendor == X86_VENDOR_INTEL &&
 860                     c->x86 == 0xF && c->x86_model == 0x3 &&
 861                     c->x86_mask == 0x4)
 862                         c->x86_phys_bits = 36;
 863         }
 864
 865         if (c->x86 == 15)
 866                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 867         if (c->x86 == 6)
 868                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 869         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 870         c->x86_max_cores = intel_num_cpu_cores(c);
 871
 872         srat_detect_node();
 873 }
 874
 875 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 876 {
 877         char *v = c->x86_vendor_id;
 878
 879         if (!strcmp(v, "AuthenticAMD"))
 880                 c->x86_vendor = X86_VENDOR_AMD;
 881         else if (!strcmp(v, "GenuineIntel"))
 882                 c->x86_vendor = X86_VENDOR_INTEL;
 883         else
 884                 c->x86_vendor = X86_VENDOR_UNKNOWN;
 885 }
 886
 887 /* Do some early cpuid on the boot CPU to get some parameter that are
 888    needed before check_bugs. Everything advanced is in identify_cpu
 889    below. */
 890 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
 891 {
 892         u32 tfms, xlvl;
 893
 894         c->loops_per_jiffy = loops_per_jiffy;
 895         c->x86_cache_size = -1;
 896         c->x86_vendor = X86_VENDOR_UNKNOWN;
 897         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 898         c->x86_vendor_id[0] = '\0'; /* Unset */
 899         c->x86_model_id[0] = '\0';  /* Unset */
 900         c->x86_clflush_size = 64;
 901         c->x86_cache_alignment = c->x86_clflush_size;
 902         c->x86_max_cores = 1;
 903         c->x86_coreid_bits = 0;
 904         c->extended_cpuid_level = 0;
 905         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 906
 907         /* Get vendor name */
 908         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 909               (unsigned int *)&c->x86_vendor_id[0],
 910               (unsigned int *)&c->x86_vendor_id[8],
 911               (unsigned int *)&c->x86_vendor_id[4]);
 912
 913         get_cpu_vendor(c);
 914
 915         /* Initialize the standard set of capabilities */
 916         /* Note that the vendor-specific code below might override */
 917
 918         /* Intel-defined flags: level 0x00000001 */
 919         if (c->cpuid_level >= 0x00000001) {
 920                 __u32 misc;
 921                 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
 922                       &c->x86_capability[0]);
 923                 c->x86 = (tfms >> 8) & 0xf;
 924                 c->x86_model = (tfms >> 4) & 0xf;
 925                 c->x86_mask = tfms & 0xf;
 926                 if (c->x86 == 0xf)
 927                         c->x86 += (tfms >> 20) & 0xff;
 928                 if (c->x86 >= 0x6)
 929                         c->x86_model += ((tfms >> 16) & 0xF) << 4;
 930                 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
 931                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 932         } else {
 933                 /* Have CPUID level 0 only - unheard of */
 934                 c->x86 = 4;
 935         }
 936
 937         c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
 938 #ifdef CONFIG_SMP
 939         c->phys_proc_id = c->initial_apicid;
 940 #endif
 941         /* AMD-defined flags: level 0x80000001 */
 942         xlvl = cpuid_eax(0x80000000);
 943         c->extended_cpuid_level = xlvl;
 944         if ((xlvl & 0xffff0000) == 0x80000000) {
 945                 if (xlvl >= 0x80000001) {
 946                         c->x86_capability[1] = cpuid_edx(0x80000001);
 947                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 948                 }
 949                 if (xlvl >= 0x80000004)
 950                         get_model_name(c); /* Default name */
 951         }
 952
 953         /* Transmeta-defined flags: level 0x80860001 */
 954         xlvl = cpuid_eax(0x80860000);
 955         if ((xlvl & 0xffff0000) == 0x80860000) {
 956                 /* Don't set x86_cpuid_level here for now to not confuse. */
 957                 if (xlvl >= 0x80860001)
 958                         c->x86_capability[2] = cpuid_edx(0x80860001);
 959         }
 960
 961         c->extended_cpuid_level = cpuid_eax(0x80000000);
 962         if (c->extended_cpuid_level >= 0x80000007)
 963                 c->x86_power = cpuid_edx(0x80000007);
 964
 965
 966         clear_cpu_cap(c, X86_FEATURE_PAT);
 967
 968         switch (c->x86_vendor) {
 969         case X86_VENDOR_AMD:
 970                 early_init_amd(c);
 971                 if (c->x86 >= 0xf && c->x86 <= 0x11)
 972                         set_cpu_cap(c, X86_FEATURE_PAT);
 973                 break;
 974         case X86_VENDOR_INTEL:
 975                 early_init_intel(c);
 976                 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
 977                         set_cpu_cap(c, X86_FEATURE_PAT);
 978                 break;
 979         }
 980
 981 }
 982
 983 /*
 984  * This does the hard work of actually picking apart the CPU stuff...
 985  */
 986 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 987 {
 988         int i;
 989
 990         early_identify_cpu(c);
 991
 992         init_scattered_cpuid_features(c);
 993
 994         c->apicid = phys_pkg_id(0);
 995
 996         /*
 997          * Vendor-specific initialization.  In this section we
 998          * canonicalize the feature flags, meaning if there are
 999          * features a certain CPU supports which CPUID doesn't
1000          * tell us, CPUID claiming incorrect flags, or other bugs,
1001          * we handle them here.
1002          *
1003          * At the end of this section, c->x86_capability better
1004          * indicate the features this CPU genuinely supports!
1005          */
1006         switch (c->x86_vendor) {
1007         case X86_VENDOR_AMD:
1008                 init_amd(c);
1009                 break;
1010
1011         case X86_VENDOR_INTEL:
1012                 init_intel(c);
1013                 break;
1014
1015         case X86_VENDOR_UNKNOWN:
1016         default:
1017                 display_cacheinfo(c);
1018                 break;
1019         }
1020
1021         detect_ht(c);
1022
1023         /*
1024          * On SMP, boot_cpu_data holds the common feature set between
1025          * all CPUs; so make sure that we indicate which features are
1026          * common between the CPUs.  The first time this routine gets
1027          * executed, c == &boot_cpu_data.
1028          */
1029         if (c != &boot_cpu_data) {
1030                 /* AND the already accumulated flags with these */
1031                 for (i = 0; i < NCAPINTS; i++)
1032                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1033         }
1034
1035         /* Clear all flags overriden by options */
1036         for (i = 0; i < NCAPINTS; i++)
1037                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1038
1039 #ifdef CONFIG_X86_MCE
1040         mcheck_init(c);
1041 #endif
1042         select_idle_routine(c);
1043
1044 #ifdef CONFIG_NUMA
1045         numa_add_cpu(smp_processor_id());
1046 #endif
1047
1048 }
1049
1050 void __cpuinit identify_boot_cpu(void)
1051 {
1052         identify_cpu(&boot_cpu_data);
1053 }
1054
1055 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1056 {
1057         BUG_ON(c == &boot_cpu_data);
1058         identify_cpu(c);
1059         mtrr_ap_init();
1060 }
1061
1062 static __init int setup_noclflush(char *arg)
1063 {
1064         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1065         return 1;
1066 }
1067 __setup("noclflush", setup_noclflush);
1068
1069 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1070 {
1071         if (c->x86_model_id[0])
1072                 printk(KERN_CONT "%s", c->x86_model_id);
1073
1074         if (c->x86_mask || c->cpuid_level >= 0)
1075                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1076         else
1077                 printk(KERN_CONT "\n");
1078 }
1079
1080 static __init int setup_disablecpuid(char *arg)
1081 {
1082         int bit;
1083         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1084                 setup_clear_cpu_cap(bit);
1085         else
1086                 return 0;
1087         return 1;
1088 }
1089 __setup("clearcpuid=", setup_disablecpuid);