2 * Copyright (C) 2007 Lemote Inc.
3 * Author: Fuxin Zhang, zhangfx@lemote.com
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/interrupt.h>
13 #include <asm/irq_cpu.h>
14 #include <asm/i8259.h>
15 #include <asm/mipsregs.h>
20 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
21 #define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
22 #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
23 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
24 #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
26 #define LOONGSON_INT_BIT_INT0 (1 << 11)
27 #define LOONGSON_INT_BIT_INT1 (1 << 12)
30 * The generic i8259_irq() make the kernel hang on booting. Since we cannot
31 * get the irq via the IRR directly, we access the ISR instead.
33 static inline int mach_i8259_irq(void)
39 if ((LOONGSON_INTISR
& LOONGSON_INTEN
) & LOONGSON_INT_BIT_INT0
) {
40 spin_lock(&i8259A_lock
);
41 isr
= inb(PIC_MASTER_CMD
) &
42 ~inb(PIC_MASTER_IMR
) & ~(1 << PIC_CASCADE_IR
);
44 isr
= (inb(PIC_SLAVE_CMD
) & ~inb(PIC_SLAVE_IMR
)) << 8;
46 if (unlikely(irq
== 7)) {
48 * This may be a spurious interrupt.
50 * Read the interrupt status register (ISR). If the most
51 * significant bit is not set then there is no valid
54 outb(0x0B, PIC_MASTER_ISR
); /* ISR register */
55 if (~inb(PIC_MASTER_ISR
) & 0x80)
58 spin_unlock(&i8259A_lock
);
64 static void i8259_irqdispatch(void)
68 irq
= mach_i8259_irq();
75 void mach_irq_dispatch(unsigned int pending
)
77 if (pending
& CAUSEF_IP7
)
78 do_IRQ(LOONGSON_TIMER_IRQ
);
79 else if (pending
& CAUSEF_IP6
) { /* North Bridge, Perf counter */
80 #ifdef CONFIG_OPROFILE
81 do_IRQ(LOONGSON2_PERFCNT_IRQ
);
84 } else if (pending
& CAUSEF_IP3
) /* CPU UART */
85 do_IRQ(LOONGSON_UART_IRQ
);
86 else if (pending
& CAUSEF_IP2
) /* South Bridge */
92 void __init
set_irq_trigger_mode(void)
94 /* setup cs5536 as high level trigger */
95 LOONGSON_INTPOL
= LOONGSON_INT_BIT_INT0
| LOONGSON_INT_BIT_INT1
;
96 LOONGSON_INTEDGE
&= ~(LOONGSON_INT_BIT_INT0
| LOONGSON_INT_BIT_INT1
);
99 static irqreturn_t
ip6_action(int cpl
, void *dev_id
)
104 struct irqaction ip6_irqaction
= {
105 .handler
= ip6_action
,
107 .flags
= IRQF_SHARED
,
110 struct irqaction cascade_irqaction
= {
111 .handler
= no_action
,
115 void __init
mach_init_irq(void)
117 /* init all controller
118 * 0-15 ------> i8259 interrupt
119 * 16-23 ------> mips cpu interrupt
120 * 32-63 ------> bonito irq
123 /* Sets the first-level interrupt dispatcher. */
128 /* setup north bridge irq (bonito) */
129 setup_irq(LOONGSON_NORTH_BRIDGE_IRQ
, &ip6_irqaction
);
130 /* setup source bridge irq (i8259) */
131 setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ
, &cascade_irqaction
);