1 /* Copyright (C) 2004 Mips Technologies, Inc */
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/cpumask.h>
6 #include <linux/interrupt.h>
9 #include <asm/processor.h>
10 #include <asm/atomic.h>
11 #include <asm/system.h>
12 #include <asm/hardirq.h>
13 #include <asm/hazards.h>
14 #include <asm/mmu_context.h>
16 #include <asm/mipsregs.h>
17 #include <asm/cacheflush.h>
19 #include <asm/addrspace.h>
21 #include <asm/smtc_ipi.h>
22 #include <asm/smtc_proc.h>
25 * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
29 * MIPSCPU_INT_BASE is identically defined in both
30 * asm-mips/mips-boards/maltaint.h and asm-mips/mips-boards/simint.h,
31 * but as yet there's no properly organized include structure that
32 * will ensure that the right *int.h file will be included for a
33 * given platform build.
36 #define MIPSCPU_INT_BASE 16
38 #define MIPS_CPU_IPI_IRQ 1
40 #define LOCK_MT_PRA() \
41 local_irq_save(flags); \
44 #define UNLOCK_MT_PRA() \
46 local_irq_restore(flags)
48 #define LOCK_CORE_PRA() \
49 local_irq_save(flags); \
52 #define UNLOCK_CORE_PRA() \
54 local_irq_restore(flags)
57 * Data structures purely associated with SMTC parallelism
62 * Table for tracking ASIDs whose lifetime is prolonged.
65 asiduse smtc_live_asid
[MAX_SMTC_TLBS
][MAX_SMTC_ASIDS
];
68 * Clock interrupt "latch" buffers, per "CPU"
71 unsigned int ipi_timer_latch
[NR_CPUS
];
74 * Number of InterProcessor Interupt (IPI) message buffers to allocate
77 #define IPIBUF_PER_CPU 4
79 struct smtc_ipi_q IPIQ
[NR_CPUS
];
80 struct smtc_ipi_q freeIPIq
;
83 /* Forward declarations */
85 void ipi_decode(struct smtc_ipi
*);
86 void post_direct_ipi(int cpu
, struct smtc_ipi
*pipi
);
87 void setup_cross_vpe_interrupts(void);
88 void init_smtc_stats(void);
90 /* Global SMTC Status */
92 unsigned int smtc_status
= 0;
94 /* Boot command line configuration overrides */
96 static int vpelimit
= 0;
97 static int tclimit
= 0;
98 static int ipibuffers
= 0;
99 static int nostlb
= 0;
100 static int asidmask
= 0;
101 unsigned long smtc_asid_mask
= 0xff;
103 static int __init
maxvpes(char *str
)
105 get_option(&str
, &vpelimit
);
109 static int __init
maxtcs(char *str
)
111 get_option(&str
, &tclimit
);
115 static int __init
ipibufs(char *str
)
117 get_option(&str
, &ipibuffers
);
121 static int __init
stlb_disable(char *s
)
127 static int __init
asidmask_set(char *str
)
129 get_option(&str
, &asidmask
);
139 smtc_asid_mask
= (unsigned long)asidmask
;
142 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask
);
147 __setup("maxvpes=", maxvpes
);
148 __setup("maxtcs=", maxtcs
);
149 __setup("ipibufs=", ipibufs
);
150 __setup("nostlb", stlb_disable
);
151 __setup("asidmask=", asidmask_set
);
153 /* Enable additional debug checks before going into CPU idle loop */
154 #define SMTC_IDLE_HOOK_DEBUG
156 #ifdef SMTC_IDLE_HOOK_DEBUG
158 static int hang_trig
= 0;
160 static int __init
hangtrig_enable(char *s
)
167 __setup("hangtrig", hangtrig_enable
);
169 #define DEFAULT_BLOCKED_IPI_LIMIT 32
171 static int timerq_limit
= DEFAULT_BLOCKED_IPI_LIMIT
;
173 static int __init
tintq(char *str
)
175 get_option(&str
, &timerq_limit
);
179 __setup("tintq=", tintq
);
181 int imstuckcount
[2][8];
182 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
183 int vpemask
[2][8] = {{0,1,1,0,0,0,0,1},{0,1,0,0,0,0,0,1}};
184 int tcnoprog
[NR_CPUS
];
185 static atomic_t idle_hook_initialized
= {0};
186 static int clock_hang_reported
[NR_CPUS
];
188 #endif /* SMTC_IDLE_HOOK_DEBUG */
190 /* Initialize shared TLB - the should probably migrate to smtc_setup_cpus() */
192 void __init
sanitize_tlb_entries(void)
194 printk("Deprecated sanitize_tlb_entries() invoked\n");
199 * Configure shared TLB - VPC configuration bit must be set by caller
202 void smtc_configure_tlb(void)
205 unsigned long mvpconf0
;
206 unsigned long config1val
;
208 /* Set up ASID preservation table */
209 for (vpes
=0; vpes
<MAX_SMTC_TLBS
; vpes
++) {
210 for(i
= 0; i
< MAX_SMTC_ASIDS
; i
++) {
211 smtc_live_asid
[vpes
][i
] = 0;
214 mvpconf0
= read_c0_mvpconf0();
216 if ((vpes
= ((mvpconf0
& MVPCONF0_PVPE
)
217 >> MVPCONF0_PVPE_SHIFT
) + 1) > 1) {
218 /* If we have multiple VPEs, try to share the TLB */
219 if ((mvpconf0
& MVPCONF0_TLBS
) && !nostlb
) {
221 * If TLB sizing is programmable, shared TLB
222 * size is the total available complement.
223 * Otherwise, we have to take the sum of all
224 * static VPE TLB entries.
226 if ((tlbsiz
= ((mvpconf0
& MVPCONF0_PTLBE
)
227 >> MVPCONF0_PTLBE_SHIFT
)) == 0) {
229 * If there's more than one VPE, there had better
230 * be more than one TC, because we need one to bind
231 * to each VPE in turn to be able to read
232 * its configuration state!
235 /* Stop the TC from doing anything foolish */
236 write_tc_c0_tchalt(TCHALT_H
);
238 /* No need to un-Halt - that happens later anyway */
239 for (i
=0; i
< vpes
; i
++) {
240 write_tc_c0_tcbind(i
);
242 * To be 100% sure we're really getting the right
243 * information, we exit the configuration state
244 * and do an IHB after each rebinding.
247 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC
);
250 * Only count if the MMU Type indicated is TLB
252 if (((read_vpe_c0_config() & MIPS_CONF_MT
) >> 7) == 1) {
253 config1val
= read_vpe_c0_config1();
254 tlbsiz
+= ((config1val
>> 25) & 0x3f) + 1;
257 /* Put core back in configuration state */
259 read_c0_mvpcontrol() | MVPCONTROL_VPC
);
263 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB
);
266 * Setup kernel data structures to use software total,
267 * rather than read the per-VPE Config1 value. The values
268 * for "CPU 0" gets copied to all the other CPUs as part
269 * of their initialization in smtc_cpu_setup().
272 tlbsiz
= tlbsiz
& 0x3f; /* MIPS32 limits TLB indices to 64 */
273 cpu_data
[0].tlbsize
= tlbsiz
;
274 smtc_status
|= SMTC_TLB_SHARED
;
276 printk("TLB of %d entry pairs shared by %d VPEs\n",
279 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
286 * Incrementally build the CPU map out of constituent MIPS MT cores,
287 * using the specified available VPEs and TCs. Plaform code needs
288 * to ensure that each MIPS MT core invokes this routine on reset,
291 * This version of the build_cpu_map and prepare_cpus routines assumes
292 * that *all* TCs of a MIPS MT core will be used for Linux, and that
293 * they will be spread across *all* available VPEs (to minimise the
294 * loss of efficiency due to exception service serialization).
295 * An improved version would pick up configuration information and
296 * possibly leave some TCs/VPEs as "slave" processors.
298 * Use c0_MVPConf0 to find out how many TCs are available, setting up
299 * phys_cpu_present_map and the logical/physical mappings.
302 int __init
mipsmt_build_cpu_map(int start_cpu_slot
)
307 * The CPU map isn't actually used for anything at this point,
308 * so it's not clear what else we should do apart from set
309 * everything up so that "logical" = "physical".
311 ntcs
= ((read_c0_mvpconf0() & MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
312 for (i
=start_cpu_slot
; i
<NR_CPUS
&& i
<ntcs
; i
++) {
313 cpu_set(i
, phys_cpu_present_map
);
314 __cpu_number_map
[i
] = i
;
315 __cpu_logical_map
[i
] = i
;
317 /* Initialize map of CPUs with FPUs */
318 cpus_clear(mt_fpu_cpumask
);
320 /* One of those TC's is the one booting, and not a secondary... */
321 printk("%i available secondary CPU TC(s)\n", i
- 1);
327 * Common setup before any secondaries are started
328 * Make sure all CPU's are in a sensible state before we boot any of the
331 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
332 * as possible across the available VPEs.
335 static void smtc_tc_setup(int vpe
, int tc
, int cpu
)
338 write_tc_c0_tchalt(TCHALT_H
);
340 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
341 & ~(TCSTATUS_TKSU
| TCSTATUS_DA
| TCSTATUS_IXMT
))
343 write_tc_c0_tccontext(0);
345 write_tc_c0_tcbind(vpe
);
346 /* In general, all TCs should have the same cpu_data indications */
347 memcpy(&cpu_data
[cpu
], &cpu_data
[0], sizeof(struct cpuinfo_mips
));
348 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
349 if (cpu_data
[0].cputype
== CPU_34K
)
350 cpu_data
[cpu
].options
&= ~MIPS_CPU_FPU
;
351 cpu_data
[cpu
].vpe_id
= vpe
;
352 cpu_data
[cpu
].tc_id
= tc
;
356 void mipsmt_prepare_cpus(void)
358 int i
, vpe
, tc
, ntc
, nvpe
, tcpervpe
, slop
, cpu
;
362 struct smtc_ipi
*pipi
;
364 /* disable interrupts so we can disable MT */
365 local_irq_save(flags
);
366 /* disable MT so we can configure */
370 spin_lock_init(&freeIPIq
.lock
);
373 * We probably don't have as many VPEs as we do SMP "CPUs",
374 * but it's possible - and in any case we'll never use more!
376 for (i
=0; i
<NR_CPUS
; i
++) {
377 IPIQ
[i
].head
= IPIQ
[i
].tail
= NULL
;
378 spin_lock_init(&IPIQ
[i
].lock
);
380 ipi_timer_latch
[i
] = 0;
383 /* cpu_data index starts at zero */
385 cpu_data
[cpu
].vpe_id
= 0;
386 cpu_data
[cpu
].tc_id
= 0;
389 /* Report on boot-time options */
390 mips_mt_set_cpuoptions ();
392 printk("Limit of %d VPEs set\n", vpelimit
);
394 printk("Limit of %d TCs set\n", tclimit
);
396 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
399 printk("ASID mask value override to 0x%x\n", asidmask
);
402 #ifdef SMTC_IDLE_HOOK_DEBUG
404 printk("Logic Analyser Trigger on suspected TC hang\n");
405 #endif /* SMTC_IDLE_HOOK_DEBUG */
407 /* Put MVPE's into 'configuration state' */
408 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC
);
410 val
= read_c0_mvpconf0();
411 nvpe
= ((val
& MVPCONF0_PVPE
) >> MVPCONF0_PVPE_SHIFT
) + 1;
412 if (vpelimit
> 0 && nvpe
> vpelimit
)
414 ntc
= ((val
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
417 if (tclimit
> 0 && ntc
> tclimit
)
419 tcpervpe
= ntc
/ nvpe
;
420 slop
= ntc
% nvpe
; /* Residual TCs, < NVPE */
422 /* Set up shared TLB */
423 smtc_configure_tlb();
425 for (tc
= 0, vpe
= 0 ; (vpe
< nvpe
) && (tc
< ntc
) ; vpe
++) {
430 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP
);
433 printk("VPE %d: TC", vpe
);
434 for (i
= 0; i
< tcpervpe
; i
++) {
436 * TC 0 is bound to VPE 0 at reset,
437 * and is presumably executing this
438 * code. Leave it alone!
441 smtc_tc_setup(vpe
,tc
, cpu
);
449 smtc_tc_setup(vpe
,tc
, cpu
);
458 * Clear any stale software interrupts from VPE's Cause
460 write_vpe_c0_cause(0);
463 * Clear ERL/EXL of VPEs other than 0
464 * and set restricted interrupt enable/mask.
466 write_vpe_c0_status((read_vpe_c0_status()
467 & ~(ST0_BEV
| ST0_ERL
| ST0_EXL
| ST0_IM
))
468 | (STATUSF_IP0
| STATUSF_IP1
| STATUSF_IP7
471 * set config to be the same as vpe0,
472 * particularly kseg0 coherency alg
474 write_vpe_c0_config(read_c0_config());
475 /* Clear any pending timer interrupt */
476 write_vpe_c0_compare(0);
477 /* Propagate Config7 */
478 write_vpe_c0_config7(read_c0_config7());
479 write_vpe_c0_count(read_c0_count());
481 /* enable multi-threading within VPE */
482 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE
);
484 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA
);
488 * Pull any physically present but unused TCs out of circulation.
490 while (tc
< (((val
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1)) {
491 cpu_clear(tc
, phys_cpu_present_map
);
492 cpu_clear(tc
, cpu_present_map
);
496 /* release config state */
497 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC
);
501 /* Set up coprocessor affinity CPU mask(s) */
503 for (tc
= 0; tc
< ntc
; tc
++) {
504 if (cpu_data
[tc
].options
& MIPS_CPU_FPU
)
505 cpu_set(tc
, mt_fpu_cpumask
);
508 /* set up ipi interrupts... */
510 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
513 setup_cross_vpe_interrupts();
515 /* Set up queue of free IPI "messages". */
516 nipi
= NR_CPUS
* IPIBUF_PER_CPU
;
520 pipi
= kmalloc(nipi
*sizeof(struct smtc_ipi
), GFP_KERNEL
);
522 panic("kmalloc of IPI message buffers failed\n");
524 printk("IPI buffer pool of %d buffers\n", nipi
);
525 for (i
= 0; i
< nipi
; i
++) {
526 smtc_ipi_nq(&freeIPIq
, pipi
);
530 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
533 local_irq_restore(flags
);
534 /* Initialize SMTC /proc statistics/diagnostics */
540 * Setup the PC, SP, and GP of a secondary processor and start it
542 * smp_bootstrap is the place to resume from
543 * __KSTK_TOS(idle) is apparently the stack pointer
544 * (unsigned long)idle->thread_info the gp
547 void smtc_boot_secondary(int cpu
, struct task_struct
*idle
)
549 extern u32 kernelsp
[NR_CPUS
];
554 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
557 settc(cpu_data
[cpu
].tc_id
);
560 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap
);
563 kernelsp
[cpu
] = __KSTK_TOS(idle
);
564 write_tc_gpr_sp(__KSTK_TOS(idle
));
567 write_tc_gpr_gp((unsigned long)idle
->thread_info
);
569 smtc_status
|= SMTC_MTC_ACTIVE
;
570 write_tc_c0_tchalt(0);
571 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
577 void smtc_init_secondary(void)
580 * Start timer on secondary VPEs if necessary.
581 * plat_timer_setup has already have been invoked by init/main
582 * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that
583 * SMTC init code assigns TCs consdecutively and in ascending order
584 * to across available VPEs.
586 if (((read_c0_tcbind() & TCBIND_CURTC
) != 0) &&
587 ((read_c0_tcbind() & TCBIND_CURVPE
)
588 != cpu_data
[smp_processor_id() - 1].vpe_id
)){
589 write_c0_compare (read_c0_count() + mips_hpt_frequency
/HZ
);
595 void smtc_smp_finish(void)
597 printk("TC %d going on-line as CPU %d\n",
598 cpu_data
[smp_processor_id()].tc_id
, smp_processor_id());
601 void smtc_cpus_done(void)
606 * Support for SMTC-optimized driver IRQ registration
610 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
611 * in do_IRQ. These are passed in setup_irq_smtc() and stored
615 int setup_irq_smtc(unsigned int irq
, struct irqaction
* new,
616 unsigned long hwmask
)
618 irq_hwmask
[irq
] = hwmask
;
620 return setup_irq(irq
, new);
624 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
625 * Within a VPE one TC can interrupt another by different approaches.
626 * The easiest to get right would probably be to make all TCs except
627 * the target IXMT and set a software interrupt, but an IXMT-based
628 * scheme requires that a handler must run before a new IPI could
629 * be sent, which would break the "broadcast" loops in MIPS MT.
630 * A more gonzo approach within a VPE is to halt the TC, extract
631 * its Restart, Status, and a couple of GPRs, and program the Restart
632 * address to emulate an interrupt.
634 * Within a VPE, one can be confident that the target TC isn't in
635 * a critical EXL state when halted, since the write to the Halt
636 * register could not have issued on the writing thread if the
637 * halting thread had EXL set. So k0 and k1 of the target TC
638 * can be used by the injection code. Across VPEs, one can't
639 * be certain that the target TC isn't in a critical exception
640 * state. So we try a two-step process of sending a software
641 * interrupt to the target VPE, which either handles the event
642 * itself (if it was the target) or injects the event within
646 void smtc_ipi_qdump(void)
650 for (i
= 0; i
< NR_CPUS
;i
++) {
651 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
652 i
, (unsigned)IPIQ
[i
].head
, (unsigned)IPIQ
[i
].tail
,
658 * The standard atomic.h primitives don't quite do what we want
659 * here: We need an atomic add-and-return-previous-value (which
660 * could be done with atomic_add_return and a decrement) and an
661 * atomic set/zero-and-return-previous-value (which can't really
662 * be done with the atomic.h primitives). And since this is
663 * MIPS MT, we can assume that we have LL/SC.
665 static __inline__
int atomic_postincrement(unsigned int *pv
)
667 unsigned long result
;
671 __asm__
__volatile__(
677 : "=&r" (result
), "=&r" (temp
), "=m" (*pv
)
684 /* No longer used in IPI dispatch, but retained for future recycling */
686 static __inline__
int atomic_postclear(unsigned int *pv
)
688 unsigned long result
;
692 __asm__
__volatile__(
698 : "=&r" (result
), "=&r" (temp
), "=m" (*pv
)
706 void smtc_send_ipi(int cpu
, int type
, unsigned int action
)
709 struct smtc_ipi
*pipi
;
713 if (cpu
== smp_processor_id()) {
714 printk("Cannot Send IPI to self!\n");
717 /* Set up a descriptor, to be delivered either promptly or queued */
718 pipi
= smtc_ipi_dq(&freeIPIq
);
721 mips_mt_regdump(dvpe());
722 panic("IPI Msg. Buffers Depleted\n");
725 pipi
->arg
= (void *)action
;
727 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
728 /* If not on same VPE, enqueue and send cross-VPE interupt */
729 smtc_ipi_nq(&IPIQ
[cpu
], pipi
);
731 settc(cpu_data
[cpu
].tc_id
);
732 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1
);
736 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
737 * since ASID shootdown on the other VPE may
738 * collide with this operation.
741 settc(cpu_data
[cpu
].tc_id
);
742 /* Halt the targeted TC */
743 write_tc_c0_tchalt(TCHALT_H
);
747 * Inspect TCStatus - if IXMT is set, we have to queue
748 * a message. Otherwise, we set up the "interrupt"
751 tcstatus
= read_tc_c0_tcstatus();
753 if ((tcstatus
& TCSTATUS_IXMT
) != 0) {
755 * Spin-waiting here can deadlock,
756 * so we queue the message for the target TC.
758 write_tc_c0_tchalt(0);
760 /* Try to reduce redundant timer interrupt messages */
761 if (type
== SMTC_CLOCK_TICK
) {
762 if (atomic_postincrement(&ipi_timer_latch
[cpu
])!=0){
763 smtc_ipi_nq(&freeIPIq
, pipi
);
767 smtc_ipi_nq(&IPIQ
[cpu
], pipi
);
769 post_direct_ipi(cpu
, pipi
);
770 write_tc_c0_tchalt(0);
777 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
779 void post_direct_ipi(int cpu
, struct smtc_ipi
*pipi
)
781 struct pt_regs
*kstack
;
782 unsigned long tcstatus
;
783 unsigned long tcrestart
;
784 extern u32 kernelsp
[NR_CPUS
];
785 extern void __smtc_ipi_vector(void);
787 /* Extract Status, EPC from halted TC */
788 tcstatus
= read_tc_c0_tcstatus();
789 tcrestart
= read_tc_c0_tcrestart();
790 /* If TCRestart indicates a WAIT instruction, advance the PC */
791 if ((tcrestart
& 0x80000000)
792 && ((*(unsigned int *)tcrestart
& 0xfe00003f) == 0x42000020)) {
796 * Save on TC's future kernel stack
798 * CU bit of Status is indicator that TC was
799 * already running on a kernel stack...
801 if (tcstatus
& ST0_CU0
) {
802 /* Note that this "- 1" is pointer arithmetic */
803 kstack
= ((struct pt_regs
*)read_tc_gpr_sp()) - 1;
805 kstack
= ((struct pt_regs
*)kernelsp
[cpu
]) - 1;
808 kstack
->cp0_epc
= (long)tcrestart
;
810 kstack
->cp0_tcstatus
= tcstatus
;
811 /* Pass token of operation to be performed kernel stack pad area */
812 kstack
->pad0
[4] = (unsigned long)pipi
;
813 /* Pass address of function to be called likewise */
814 kstack
->pad0
[5] = (unsigned long)&ipi_decode
;
815 /* Set interrupt exempt and kernel mode */
816 tcstatus
|= TCSTATUS_IXMT
;
817 tcstatus
&= ~TCSTATUS_TKSU
;
818 write_tc_c0_tcstatus(tcstatus
);
820 /* Set TC Restart address to be SMTC IPI vector */
821 write_tc_c0_tcrestart(__smtc_ipi_vector
);
824 static void ipi_resched_interrupt(void)
826 /* Return from interrupt should be enough to cause scheduler check */
830 static void ipi_call_interrupt(void)
832 /* Invoke generic function invocation code in smp.c */
833 smp_call_function_interrupt();
836 void ipi_decode(struct smtc_ipi
*pipi
)
838 void *arg_copy
= pipi
->arg
;
839 int type_copy
= pipi
->type
;
840 int dest_copy
= pipi
->dest
;
842 smtc_ipi_nq(&freeIPIq
, pipi
);
844 case SMTC_CLOCK_TICK
:
845 /* Invoke Clock "Interrupt" */
846 ipi_timer_latch
[dest_copy
] = 0;
847 #ifdef SMTC_IDLE_HOOK_DEBUG
848 clock_hang_reported
[dest_copy
] = 0;
849 #endif /* SMTC_IDLE_HOOK_DEBUG */
850 local_timer_interrupt(0, NULL
);
853 switch ((int)arg_copy
) {
854 case SMP_RESCHEDULE_YOURSELF
:
855 ipi_resched_interrupt();
857 case SMP_CALL_FUNCTION
:
858 ipi_call_interrupt();
861 printk("Impossible SMTC IPI Argument 0x%x\n",
867 printk("Impossible SMTC IPI Type 0x%x\n", type_copy
);
872 void deferred_smtc_ipi(void)
874 struct smtc_ipi
*pipi
;
877 int q
= smp_processor_id();
880 * Test is not atomic, but much faster than a dequeue,
881 * and the vast majority of invocations will have a null queue.
883 if (IPIQ
[q
].head
!= NULL
) {
884 while((pipi
= smtc_ipi_dq(&IPIQ
[q
])) != NULL
) {
885 /* ipi_decode() should be called with interrupts off */
886 local_irq_save(flags
);
888 local_irq_restore(flags
);
894 * Send clock tick to all TCs except the one executing the funtion
897 void smtc_timer_broadcast(int vpe
)
900 int myTC
= cpu_data
[smp_processor_id()].tc_id
;
901 int myVPE
= cpu_data
[smp_processor_id()].vpe_id
;
903 smtc_cpu_stats
[smp_processor_id()].timerints
++;
905 for_each_online_cpu(cpu
) {
906 if (cpu_data
[cpu
].vpe_id
== myVPE
&&
907 cpu_data
[cpu
].tc_id
!= myTC
)
908 smtc_send_ipi(cpu
, SMTC_CLOCK_TICK
, 0);
913 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
914 * set via cross-VPE MTTR manipulation of the Cause register. It would be
915 * in some regards preferable to have external logic for "doorbell" hardware
919 static int cpu_ipi_irq
= MIPSCPU_INT_BASE
+ MIPS_CPU_IPI_IRQ
;
921 static irqreturn_t
ipi_interrupt(int irq
, void *dev_idm
)
923 int my_vpe
= cpu_data
[smp_processor_id()].vpe_id
;
924 int my_tc
= cpu_data
[smp_processor_id()].tc_id
;
926 struct smtc_ipi
*pipi
;
927 unsigned long tcstatus
;
930 unsigned int mtflags
;
931 unsigned int vpflags
;
934 * So long as cross-VPE interrupts are done via
935 * MFTR/MTTR read-modify-writes of Cause, we need
936 * to stop other VPEs whenever the local VPE does
939 local_irq_save(flags
);
941 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ
);
942 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ
);
945 local_irq_restore(flags
);
948 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
949 * queued for TCs on this VPE other than the current one.
950 * Return-from-interrupt should cause us to drain the queue
951 * for the current TC, so we ought not to have to do it explicitly here.
954 for_each_online_cpu(cpu
) {
955 if (cpu_data
[cpu
].vpe_id
!= my_vpe
)
958 pipi
= smtc_ipi_dq(&IPIQ
[cpu
]);
960 if (cpu_data
[cpu
].tc_id
!= my_tc
) {
963 settc(cpu_data
[cpu
].tc_id
);
964 write_tc_c0_tchalt(TCHALT_H
);
966 tcstatus
= read_tc_c0_tcstatus();
967 if ((tcstatus
& TCSTATUS_IXMT
) == 0) {
968 post_direct_ipi(cpu
, pipi
);
971 write_tc_c0_tchalt(0);
974 smtc_ipi_req(&IPIQ
[cpu
], pipi
);
978 * ipi_decode() should be called
979 * with interrupts off
981 local_irq_save(flags
);
983 local_irq_restore(flags
);
991 static void ipi_irq_dispatch(void)
996 static struct irqaction irq_ipi
;
998 void setup_cross_vpe_interrupts(void)
1001 panic("SMTC Kernel requires Vectored Interupt support");
1003 set_vi_handler(MIPS_CPU_IPI_IRQ
, ipi_irq_dispatch
);
1005 irq_ipi
.handler
= ipi_interrupt
;
1006 irq_ipi
.flags
= IRQF_DISABLED
;
1007 irq_ipi
.name
= "SMTC_IPI";
1009 setup_irq_smtc(cpu_ipi_irq
, &irq_ipi
, (0x100 << MIPS_CPU_IPI_IRQ
));
1011 irq_desc
[cpu_ipi_irq
].status
|= IRQ_PER_CPU
;
1015 * SMTC-specific hacks invoked from elsewhere in the kernel.
1018 void smtc_idle_loop_hook(void)
1020 #ifdef SMTC_IDLE_HOOK_DEBUG
1029 * printk within DMT-protected regions can deadlock,
1030 * so buffer diagnostic messages for later output.
1033 char id_ho_db_msg
[768]; /* worst-case use should be less than 700 */
1035 if (atomic_read(&idle_hook_initialized
) == 0) { /* fast test */
1036 if (atomic_add_return(1, &idle_hook_initialized
) == 1) {
1038 /* Tedious stuff to just do once */
1039 mvpconf0
= read_c0_mvpconf0();
1040 hook_ntcs
= ((mvpconf0
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
1041 if (hook_ntcs
> NR_CPUS
)
1042 hook_ntcs
= NR_CPUS
;
1043 for (tc
= 0; tc
< hook_ntcs
; tc
++) {
1045 clock_hang_reported
[tc
] = 0;
1047 for (vpe
= 0; vpe
< 2; vpe
++)
1048 for (im
= 0; im
< 8; im
++)
1049 imstuckcount
[vpe
][im
] = 0;
1050 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs
);
1051 atomic_set(&idle_hook_initialized
, 1000);
1053 /* Someone else is initializing in parallel - let 'em finish */
1054 while (atomic_read(&idle_hook_initialized
) < 1000)
1059 /* Have we stupidly left IXMT set somewhere? */
1060 if (read_c0_tcstatus() & 0x400) {
1061 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1063 printk("Dangling IXMT in cpu_idle()\n");
1066 /* Have we stupidly left an IM bit turned off? */
1067 #define IM_LIMIT 2000
1068 local_irq_save(flags
);
1070 pdb_msg
= &id_ho_db_msg
[0];
1071 im
= read_c0_status();
1072 vpe
= cpu_data
[smp_processor_id()].vpe_id
;
1073 for (bit
= 0; bit
< 8; bit
++) {
1075 * In current prototype, I/O interrupts
1076 * are masked for VPE > 0
1078 if (vpemask
[vpe
][bit
]) {
1079 if (!(im
& (0x100 << bit
)))
1080 imstuckcount
[vpe
][bit
]++;
1082 imstuckcount
[vpe
][bit
] = 0;
1083 if (imstuckcount
[vpe
][bit
] > IM_LIMIT
) {
1084 set_c0_status(0x100 << bit
);
1086 imstuckcount
[vpe
][bit
] = 0;
1087 pdb_msg
+= sprintf(pdb_msg
,
1088 "Dangling IM %d fixed for VPE %d\n", bit
,
1095 * Now that we limit outstanding timer IPIs, check for hung TC
1097 for (tc
= 0; tc
< NR_CPUS
; tc
++) {
1098 /* Don't check ourself - we'll dequeue IPIs just below */
1099 if ((tc
!= smp_processor_id()) &&
1100 ipi_timer_latch
[tc
] > timerq_limit
) {
1101 if (clock_hang_reported
[tc
] == 0) {
1102 pdb_msg
+= sprintf(pdb_msg
,
1103 "TC %d looks hung with timer latch at %d\n",
1104 tc
, ipi_timer_latch
[tc
]);
1105 clock_hang_reported
[tc
]++;
1110 local_irq_restore(flags
);
1111 if (pdb_msg
!= &id_ho_db_msg
[0])
1112 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg
);
1113 #endif /* SMTC_IDLE_HOOK_DEBUG */
1115 * To the extent that we've ever turned interrupts off,
1116 * we may have accumulated deferred IPIs. This is subtle.
1117 * If we use the smtc_ipi_qdepth() macro, we'll get an
1118 * exact number - but we'll also disable interrupts
1119 * and create a window of failure where a new IPI gets
1120 * queued after we test the depth but before we re-enable
1121 * interrupts. So long as IXMT never gets set, however,
1122 * we should be OK: If we pick up something and dispatch
1123 * it here, that's great. If we see nothing, but concurrent
1124 * with this operation, another TC sends us an IPI, IXMT
1125 * is clear, and we'll handle it as a real pseudo-interrupt
1126 * and not a pseudo-pseudo interrupt.
1128 if (IPIQ
[smp_processor_id()].depth
> 0) {
1129 struct smtc_ipi
*pipi
;
1130 extern void self_ipi(struct smtc_ipi
*);
1132 if ((pipi
= smtc_ipi_dq(&IPIQ
[smp_processor_id()])) != NULL
) {
1134 smtc_cpu_stats
[smp_processor_id()].selfipis
++;
1139 void smtc_soft_dump(void)
1143 printk("Counter Interrupts taken per CPU (TC)\n");
1144 for (i
=0; i
< NR_CPUS
; i
++) {
1145 printk("%d: %ld\n", i
, smtc_cpu_stats
[i
].timerints
);
1147 printk("Self-IPI invocations:\n");
1148 for (i
=0; i
< NR_CPUS
; i
++) {
1149 printk("%d: %ld\n", i
, smtc_cpu_stats
[i
].selfipis
);
1152 printk("Timer IPI Backlogs:\n");
1153 for (i
=0; i
< NR_CPUS
; i
++) {
1154 printk("%d: %d\n", i
, ipi_timer_latch
[i
]);
1156 printk("%d Recoveries of \"stolen\" FPU\n",
1157 atomic_read(&smtc_fpu_recoveries
));
1162 * TLB management routines special to SMTC
1165 void smtc_get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
)
1167 unsigned long flags
, mtflags
, tcstat
, prevhalt
, asid
;
1171 * It would be nice to be able to use a spinlock here,
1172 * but this is invoked from within TLB flush routines
1173 * that protect themselves with DVPE, so if a lock is
1174 * held by another TC, it'll never be freed.
1176 * DVPE/DMT must not be done with interrupts enabled,
1177 * so even so most callers will already have disabled
1178 * them, let's be really careful...
1181 local_irq_save(flags
);
1182 if (smtc_status
& SMTC_TLB_SHARED
) {
1187 tlb
= cpu_data
[cpu
].vpe_id
;
1189 asid
= asid_cache(cpu
);
1192 if (!((asid
+= ASID_INC
) & ASID_MASK
) ) {
1193 if (cpu_has_vtag_icache
)
1195 /* Traverse all online CPUs (hack requires contigous range) */
1196 for (i
= 0; i
< num_online_cpus(); i
++) {
1198 * We don't need to worry about our own CPU, nor those of
1199 * CPUs who don't share our TLB.
1201 if ((i
!= smp_processor_id()) &&
1202 ((smtc_status
& SMTC_TLB_SHARED
) ||
1203 (cpu_data
[i
].vpe_id
== cpu_data
[cpu
].vpe_id
))) {
1204 settc(cpu_data
[i
].tc_id
);
1205 prevhalt
= read_tc_c0_tchalt() & TCHALT_H
;
1207 write_tc_c0_tchalt(TCHALT_H
);
1210 tcstat
= read_tc_c0_tcstatus();
1211 smtc_live_asid
[tlb
][(tcstat
& ASID_MASK
)] |= (asiduse
)(0x1 << i
);
1213 write_tc_c0_tchalt(0);
1216 if (!asid
) /* fix version if needed */
1217 asid
= ASID_FIRST_VERSION
;
1218 local_flush_tlb_all(); /* start new asid cycle */
1220 } while (smtc_live_asid
[tlb
][(asid
& ASID_MASK
)]);
1223 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1225 for (i
= 0; i
< num_online_cpus(); i
++) {
1226 if ((smtc_status
& SMTC_TLB_SHARED
) ||
1227 (cpu_data
[i
].vpe_id
== cpu_data
[cpu
].vpe_id
))
1228 cpu_context(i
, mm
) = asid_cache(i
) = asid
;
1231 if (smtc_status
& SMTC_TLB_SHARED
)
1235 local_irq_restore(flags
);
1239 * Invoked from macros defined in mmu_context.h
1240 * which must already have disabled interrupts
1241 * and done a DVPE or DMT as appropriate.
1244 void smtc_flush_tlb_asid(unsigned long asid
)
1249 entry
= read_c0_wired();
1251 /* Traverse all non-wired entries */
1252 while (entry
< current_cpu_data
.tlbsize
) {
1253 write_c0_index(entry
);
1257 ehi
= read_c0_entryhi();
1258 if ((ehi
& ASID_MASK
) == asid
) {
1260 * Invalidate only entries with specified ASID,
1261 * makiing sure all entries differ.
1263 write_c0_entryhi(CKSEG0
+ (entry
<< (PAGE_SHIFT
+ 1)));
1264 write_c0_entrylo0(0);
1265 write_c0_entrylo1(0);
1267 tlb_write_indexed();
1271 write_c0_index(PARKED_INDEX
);
1276 * Support for single-threading cache flush operations.
1279 int halt_state_save
[NR_CPUS
];
1282 * To really, really be sure that nothing is being done
1283 * by other TCs, halt them all. This code assumes that
1284 * a DVPE has already been done, so while their Halted
1285 * state is theoretically architecturally unstable, in
1286 * practice, it's not going to change while we're looking
1290 void smtc_cflush_lockdown(void)
1294 for_each_online_cpu(cpu
) {
1295 if (cpu
!= smp_processor_id()) {
1296 settc(cpu_data
[cpu
].tc_id
);
1297 halt_state_save
[cpu
] = read_tc_c0_tchalt();
1298 write_tc_c0_tchalt(TCHALT_H
);
1304 /* It would be cheating to change the cpu_online states during a flush! */
1306 void smtc_cflush_release(void)
1311 * Start with a hazard barrier to ensure
1312 * that all CACHE ops have played through.
1316 for_each_online_cpu(cpu
) {
1317 if (cpu
!= smp_processor_id()) {
1318 settc(cpu_data
[cpu
].tc_id
);
1319 write_tc_c0_tchalt(halt_state_save
[cpu
]);