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e1000: Add support for new hardware (ESB2)
[linux-2.6/kvm.git] / drivers / net / e1000 / e1000_hw.c
blob63e237084a514158cbd188004ba1e68162468cc5
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33 #include "e1000_hw.h"
34
35 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36 static void e1000_phy_init_script(struct e1000_hw *hw);
37 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
42 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
43 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
45 uint16_t count);
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
49 uint16_t words, uint16_t *data);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
51 uint16_t offset, uint16_t words,
52 uint16_t *data);
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
54 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
55 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
57 uint16_t count);
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
59 uint16_t phy_data);
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
61 uint16_t *phy_data);
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64 static void e1000_release_eeprom(struct e1000_hw *hw);
65 static void e1000_standby_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
68 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
69 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
70 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
71 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
72 static int32_t e1000_check_downshift(struct e1000_hw *hw);
73 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
74 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
75 static void e1000_clear_vfta(struct e1000_hw *hw);
76 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
77 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
78 boolean_t link_up);
79 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
80 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
81 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
82 static int32_t e1000_get_cable_length(struct e1000_hw *hw,
83 uint16_t *min_length,
84 uint16_t *max_length);
85 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
86 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
87 static int32_t e1000_id_led_init(struct e1000_hw * hw);
88 static void e1000_init_rx_addrs(struct e1000_hw *hw);
89 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
90 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
91 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
92 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
93 uint16_t words, uint16_t *data);
94 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
95 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
96 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
97
98 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
99 uint32_t value);
100
101 #define E1000_WRITE_REG_IO(a, reg, val) \
102 e1000_write_reg_io((a), E1000_##reg, val)
103 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw);
104 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
105
106 /* IGP cable length table */
107 static const
108 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
109 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
110 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
111 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
112 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
113 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
114 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
115 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
116 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
117
118 static const
119 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
120 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
121 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
122 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
123 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
124 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
125 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
126 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
127 104, 109, 114, 118, 121, 124};
128
129
130 /******************************************************************************
131 * Set the phy type member in the hw struct.
132 *
133 * hw - Struct containing variables accessed by shared code
134 *****************************************************************************/
135 int32_t
136 e1000_set_phy_type(struct e1000_hw *hw)
137 {
138 DEBUGFUNC("e1000_set_phy_type");
139
140 if(hw->mac_type == e1000_undefined)
141 return -E1000_ERR_PHY_TYPE;
142
143 switch(hw->phy_id) {
144 case M88E1000_E_PHY_ID:
145 case M88E1000_I_PHY_ID:
146 case M88E1011_I_PHY_ID:
147 case M88E1111_I_PHY_ID:
148 hw->phy_type = e1000_phy_m88;
149 break;
150 case IGP01E1000_I_PHY_ID:
151 if(hw->mac_type == e1000_82541 ||
152 hw->mac_type == e1000_82541_rev_2 ||
153 hw->mac_type == e1000_82547 ||
154 hw->mac_type == e1000_82547_rev_2) {
155 hw->phy_type = e1000_phy_igp;
156 break;
157 }
158 case GG82563_E_PHY_ID:
159 if (hw->mac_type == e1000_80003es2lan) {
160 hw->phy_type = e1000_phy_gg82563;
161 break;
162 }
163 /* Fall Through */
164 default:
165 /* Should never have loaded on this device */
166 hw->phy_type = e1000_phy_undefined;
167 return -E1000_ERR_PHY_TYPE;
168 }
169
170 return E1000_SUCCESS;
171 }
172
173 /******************************************************************************
174 * IGP phy init script - initializes the GbE PHY
175 *
176 * hw - Struct containing variables accessed by shared code
177 *****************************************************************************/
178 static void
179 e1000_phy_init_script(struct e1000_hw *hw)
180 {
181 uint32_t ret_val;
182 uint16_t phy_saved_data;
183
184 DEBUGFUNC("e1000_phy_init_script");
185
186 if(hw->phy_init_script) {
187 msec_delay(20);
188
189 /* Save off the current value of register 0x2F5B to be restored at
190 * the end of this routine. */
191 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
192
193 /* Disabled the PHY transmitter */
194 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
195
196 msec_delay(20);
197
198 e1000_write_phy_reg(hw,0x0000,0x0140);
199
200 msec_delay(5);
201
202 switch(hw->mac_type) {
203 case e1000_82541:
204 case e1000_82547:
205 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
206
207 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
208
209 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
210
211 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
212
213 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
214
215 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
216
217 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
218
219 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
220
221 e1000_write_phy_reg(hw, 0x2010, 0x0008);
222 break;
223
224 case e1000_82541_rev_2:
225 case e1000_82547_rev_2:
226 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
227 break;
228 default:
229 break;
230 }
231
232 e1000_write_phy_reg(hw, 0x0000, 0x3300);
233
234 msec_delay(20);
235
236 /* Now enable the transmitter */
237 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
238
239 if(hw->mac_type == e1000_82547) {
240 uint16_t fused, fine, coarse;
241
242 /* Move to analog registers page */
243 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
244
245 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
246 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
247
248 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
249 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
250
251 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
252 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
253 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
254 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
255 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
256
257 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
258 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
259 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
260
261 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
262 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
263 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
264 }
265 }
266 }
267 }
268
269 /******************************************************************************
270 * Set the mac type member in the hw struct.
271 *
272 * hw - Struct containing variables accessed by shared code
273 *****************************************************************************/
274 int32_t
275 e1000_set_mac_type(struct e1000_hw *hw)
276 {
277 DEBUGFUNC("e1000_set_mac_type");
278
279 switch (hw->device_id) {
280 case E1000_DEV_ID_82542:
281 switch (hw->revision_id) {
282 case E1000_82542_2_0_REV_ID:
283 hw->mac_type = e1000_82542_rev2_0;
284 break;
285 case E1000_82542_2_1_REV_ID:
286 hw->mac_type = e1000_82542_rev2_1;
287 break;
288 default:
289 /* Invalid 82542 revision ID */
290 return -E1000_ERR_MAC_TYPE;
291 }
292 break;
293 case E1000_DEV_ID_82543GC_FIBER:
294 case E1000_DEV_ID_82543GC_COPPER:
295 hw->mac_type = e1000_82543;
296 break;
297 case E1000_DEV_ID_82544EI_COPPER:
298 case E1000_DEV_ID_82544EI_FIBER:
299 case E1000_DEV_ID_82544GC_COPPER:
300 case E1000_DEV_ID_82544GC_LOM:
301 hw->mac_type = e1000_82544;
302 break;
303 case E1000_DEV_ID_82540EM:
304 case E1000_DEV_ID_82540EM_LOM:
305 case E1000_DEV_ID_82540EP:
306 case E1000_DEV_ID_82540EP_LOM:
307 case E1000_DEV_ID_82540EP_LP:
308 hw->mac_type = e1000_82540;
309 break;
310 case E1000_DEV_ID_82545EM_COPPER:
311 case E1000_DEV_ID_82545EM_FIBER:
312 hw->mac_type = e1000_82545;
313 break;
314 case E1000_DEV_ID_82545GM_COPPER:
315 case E1000_DEV_ID_82545GM_FIBER:
316 case E1000_DEV_ID_82545GM_SERDES:
317 hw->mac_type = e1000_82545_rev_3;
318 break;
319 case E1000_DEV_ID_82546EB_COPPER:
320 case E1000_DEV_ID_82546EB_FIBER:
321 case E1000_DEV_ID_82546EB_QUAD_COPPER:
322 hw->mac_type = e1000_82546;
323 break;
324 case E1000_DEV_ID_82546GB_COPPER:
325 case E1000_DEV_ID_82546GB_FIBER:
326 case E1000_DEV_ID_82546GB_SERDES:
327 case E1000_DEV_ID_82546GB_PCIE:
328 case E1000_DEV_ID_82546GB_QUAD_COPPER:
329 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
330 hw->mac_type = e1000_82546_rev_3;
331 break;
332 case E1000_DEV_ID_82541EI:
333 case E1000_DEV_ID_82541EI_MOBILE:
334 hw->mac_type = e1000_82541;
335 break;
336 case E1000_DEV_ID_82541ER:
337 case E1000_DEV_ID_82541GI:
338 case E1000_DEV_ID_82541GI_LF:
339 case E1000_DEV_ID_82541GI_MOBILE:
340 hw->mac_type = e1000_82541_rev_2;
341 break;
342 case E1000_DEV_ID_82547EI:
343 hw->mac_type = e1000_82547;
344 break;
345 case E1000_DEV_ID_82547GI:
346 hw->mac_type = e1000_82547_rev_2;
347 break;
348 case E1000_DEV_ID_82571EB_COPPER:
349 case E1000_DEV_ID_82571EB_FIBER:
350 case E1000_DEV_ID_82571EB_SERDES:
351 hw->mac_type = e1000_82571;
352 break;
353 case E1000_DEV_ID_82572EI_COPPER:
354 case E1000_DEV_ID_82572EI_FIBER:
355 case E1000_DEV_ID_82572EI_SERDES:
356 hw->mac_type = e1000_82572;
357 break;
358 case E1000_DEV_ID_82573E:
359 case E1000_DEV_ID_82573E_IAMT:
360 case E1000_DEV_ID_82573L:
361 hw->mac_type = e1000_82573;
362 break;
363 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
364 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
365 hw->mac_type = e1000_80003es2lan;
366 break;
367 default:
368 /* Should never have loaded on this device */
369 return -E1000_ERR_MAC_TYPE;
370 }
371
372 switch(hw->mac_type) {
373 case e1000_80003es2lan:
374 hw->swfw_sync_present = TRUE;
375 /* fall through */
376 case e1000_82571:
377 case e1000_82572:
378 case e1000_82573:
379 hw->eeprom_semaphore_present = TRUE;
380 /* fall through */
381 case e1000_82541:
382 case e1000_82547:
383 case e1000_82541_rev_2:
384 case e1000_82547_rev_2:
385 hw->asf_firmware_present = TRUE;
386 break;
387 default:
388 break;
389 }
390
391 return E1000_SUCCESS;
392 }
393
394 /*****************************************************************************
395 * Set media type and TBI compatibility.
396 *
397 * hw - Struct containing variables accessed by shared code
398 * **************************************************************************/
399 void
400 e1000_set_media_type(struct e1000_hw *hw)
401 {
402 uint32_t status;
403
404 DEBUGFUNC("e1000_set_media_type");
405
406 if(hw->mac_type != e1000_82543) {
407 /* tbi_compatibility is only valid on 82543 */
408 hw->tbi_compatibility_en = FALSE;
409 }
410
411 switch (hw->device_id) {
412 case E1000_DEV_ID_82545GM_SERDES:
413 case E1000_DEV_ID_82546GB_SERDES:
414 case E1000_DEV_ID_82571EB_SERDES:
415 case E1000_DEV_ID_82572EI_SERDES:
416 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
417 hw->media_type = e1000_media_type_internal_serdes;
418 break;
419 default:
420 switch (hw->mac_type) {
421 case e1000_82542_rev2_0:
422 case e1000_82542_rev2_1:
423 hw->media_type = e1000_media_type_fiber;
424 break;
425 case e1000_82573:
426 /* The STATUS_TBIMODE bit is reserved or reused for the this
427 * device.
428 */
429 hw->media_type = e1000_media_type_copper;
430 break;
431 default:
432 status = E1000_READ_REG(hw, STATUS);
433 if (status & E1000_STATUS_TBIMODE) {
434 hw->media_type = e1000_media_type_fiber;
435 /* tbi_compatibility not valid on fiber */
436 hw->tbi_compatibility_en = FALSE;
437 } else {
438 hw->media_type = e1000_media_type_copper;
439 }
440 break;
441 }
442 }
443 }
444
445 /******************************************************************************
446 * Reset the transmit and receive units; mask and clear all interrupts.
447 *
448 * hw - Struct containing variables accessed by shared code
449 *****************************************************************************/
450 int32_t
451 e1000_reset_hw(struct e1000_hw *hw)
452 {
453 uint32_t ctrl;
454 uint32_t ctrl_ext;
455 uint32_t icr;
456 uint32_t manc;
457 uint32_t led_ctrl;
458 uint32_t timeout;
459 uint32_t extcnf_ctrl;
460 int32_t ret_val;
461
462 DEBUGFUNC("e1000_reset_hw");
463
464 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
465 if(hw->mac_type == e1000_82542_rev2_0) {
466 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
467 e1000_pci_clear_mwi(hw);
468 }
469
470 if(hw->bus_type == e1000_bus_type_pci_express) {
471 /* Prevent the PCI-E bus from sticking if there is no TLP connection
472 * on the last TLP read/write transaction when MAC is reset.
473 */
474 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
475 DEBUGOUT("PCI-E Master disable polling has failed.\n");
476 }
477 }
478
479 /* Clear interrupt mask to stop board from generating interrupts */
480 DEBUGOUT("Masking off all interrupts\n");
481 E1000_WRITE_REG(hw, IMC, 0xffffffff);
482
483 /* Disable the Transmit and Receive units. Then delay to allow
484 * any pending transactions to complete before we hit the MAC with
485 * the global reset.
486 */
487 E1000_WRITE_REG(hw, RCTL, 0);
488 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
489 E1000_WRITE_FLUSH(hw);
490
491 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
492 hw->tbi_compatibility_on = FALSE;
493
494 /* Delay to allow any outstanding PCI transactions to complete before
495 * resetting the device
496 */
497 msec_delay(10);
498
499 ctrl = E1000_READ_REG(hw, CTRL);
500
501 /* Must reset the PHY before resetting the MAC */
502 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
503 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
504 msec_delay(5);
505 }
506
507 /* Must acquire the MDIO ownership before MAC reset.
508 * Ownership defaults to firmware after a reset. */
509 if(hw->mac_type == e1000_82573) {
510 timeout = 10;
511
512 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
513 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
514
515 do {
516 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
517 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
518
519 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
520 break;
521 else
522 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
523
524 msec_delay(2);
525 timeout--;
526 } while(timeout);
527 }
528
529 /* Issue a global reset to the MAC. This will reset the chip's
530 * transmit, receive, DMA, and link units. It will not effect
531 * the current PCI configuration. The global reset bit is self-
532 * clearing, and should clear within a microsecond.
533 */
534 DEBUGOUT("Issuing a global reset to MAC\n");
535
536 switch(hw->mac_type) {
537 case e1000_82544:
538 case e1000_82540:
539 case e1000_82545:
540 case e1000_82546:
541 case e1000_82541:
542 case e1000_82541_rev_2:
543 /* These controllers can't ack the 64-bit write when issuing the
544 * reset, so use IO-mapping as a workaround to issue the reset */
545 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
546 break;
547 case e1000_82545_rev_3:
548 case e1000_82546_rev_3:
549 /* Reset is performed on a shadow of the control register */
550 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
551 break;
552 default:
553 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
554 break;
555 }
556
557 /* After MAC reset, force reload of EEPROM to restore power-on settings to
558 * device. Later controllers reload the EEPROM automatically, so just wait
559 * for reload to complete.
560 */
561 switch(hw->mac_type) {
562 case e1000_82542_rev2_0:
563 case e1000_82542_rev2_1:
564 case e1000_82543:
565 case e1000_82544:
566 /* Wait for reset to complete */
567 udelay(10);
568 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
569 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
570 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
571 E1000_WRITE_FLUSH(hw);
572 /* Wait for EEPROM reload */
573 msec_delay(2);
574 break;
575 case e1000_82541:
576 case e1000_82541_rev_2:
577 case e1000_82547:
578 case e1000_82547_rev_2:
579 /* Wait for EEPROM reload */
580 msec_delay(20);
581 break;
582 case e1000_82573:
583 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
584 udelay(10);
585 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
586 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
587 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
588 E1000_WRITE_FLUSH(hw);
589 }
590 /* fall through */
591 case e1000_82571:
592 case e1000_82572:
593 case e1000_80003es2lan:
594 ret_val = e1000_get_auto_rd_done(hw);
595 if(ret_val)
596 /* We don't want to continue accessing MAC registers. */
597 return ret_val;
598 break;
599 default:
600 /* Wait for EEPROM reload (it happens automatically) */
601 msec_delay(5);
602 break;
603 }
604
605 /* Disable HW ARPs on ASF enabled adapters */
606 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
607 manc = E1000_READ_REG(hw, MANC);
608 manc &= ~(E1000_MANC_ARP_EN);
609 E1000_WRITE_REG(hw, MANC, manc);
610 }
611
612 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
613 e1000_phy_init_script(hw);
614
615 /* Configure activity LED after PHY reset */
616 led_ctrl = E1000_READ_REG(hw, LEDCTL);
617 led_ctrl &= IGP_ACTIVITY_LED_MASK;
618 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
619 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
620 }
621
622 /* Clear interrupt mask to stop board from generating interrupts */
623 DEBUGOUT("Masking off all interrupts\n");
624 E1000_WRITE_REG(hw, IMC, 0xffffffff);
625
626 /* Clear any pending interrupt events. */
627 icr = E1000_READ_REG(hw, ICR);
628
629 /* If MWI was previously enabled, reenable it. */
630 if(hw->mac_type == e1000_82542_rev2_0) {
631 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
632 e1000_pci_set_mwi(hw);
633 }
634
635 return E1000_SUCCESS;
636 }
637
638 /******************************************************************************
639 * Performs basic configuration of the adapter.
640 *
641 * hw - Struct containing variables accessed by shared code
642 *
643 * Assumes that the controller has previously been reset and is in a
644 * post-reset uninitialized state. Initializes the receive address registers,
645 * multicast table, and VLAN filter table. Calls routines to setup link
646 * configuration and flow control settings. Clears all on-chip counters. Leaves
647 * the transmit and receive units disabled and uninitialized.
648 *****************************************************************************/
649 int32_t
650 e1000_init_hw(struct e1000_hw *hw)
651 {
652 uint32_t ctrl;
653 uint32_t i;
654 int32_t ret_val;
655 uint16_t pcix_cmd_word;
656 uint16_t pcix_stat_hi_word;
657 uint16_t cmd_mmrbc;
658 uint16_t stat_mmrbc;
659 uint32_t mta_size;
660 uint32_t reg_data;
661 uint32_t ctrl_ext;
662
663 DEBUGFUNC("e1000_init_hw");
664
665 /* Initialize Identification LED */
666 ret_val = e1000_id_led_init(hw);
667 if(ret_val) {
668 DEBUGOUT("Error Initializing Identification LED\n");
669 return ret_val;
670 }
671
672 /* Set the media type and TBI compatibility */
673 e1000_set_media_type(hw);
674
675 /* Disabling VLAN filtering. */
676 DEBUGOUT("Initializing the IEEE VLAN\n");
677 if (hw->mac_type < e1000_82545_rev_3)
678 E1000_WRITE_REG(hw, VET, 0);
679 e1000_clear_vfta(hw);
680
681 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
682 if(hw->mac_type == e1000_82542_rev2_0) {
683 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
684 e1000_pci_clear_mwi(hw);
685 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
686 E1000_WRITE_FLUSH(hw);
687 msec_delay(5);
688 }
689
690 /* Setup the receive address. This involves initializing all of the Receive
691 * Address Registers (RARs 0 - 15).
692 */
693 e1000_init_rx_addrs(hw);
694
695 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
696 if(hw->mac_type == e1000_82542_rev2_0) {
697 E1000_WRITE_REG(hw, RCTL, 0);
698 E1000_WRITE_FLUSH(hw);
699 msec_delay(1);
700 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
701 e1000_pci_set_mwi(hw);
702 }
703
704 /* Zero out the Multicast HASH table */
705 DEBUGOUT("Zeroing the MTA\n");
706 mta_size = E1000_MC_TBL_SIZE;
707 for(i = 0; i < mta_size; i++)
708 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
709
710 /* Set the PCI priority bit correctly in the CTRL register. This
711 * determines if the adapter gives priority to receives, or if it
712 * gives equal priority to transmits and receives. Valid only on
713 * 82542 and 82543 silicon.
714 */
715 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
716 ctrl = E1000_READ_REG(hw, CTRL);
717 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
718 }
719
720 switch(hw->mac_type) {
721 case e1000_82545_rev_3:
722 case e1000_82546_rev_3:
723 break;
724 default:
725 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
726 if(hw->bus_type == e1000_bus_type_pcix) {
727 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
728 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
729 &pcix_stat_hi_word);
730 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
731 PCIX_COMMAND_MMRBC_SHIFT;
732 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
733 PCIX_STATUS_HI_MMRBC_SHIFT;
734 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
735 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
736 if(cmd_mmrbc > stat_mmrbc) {
737 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
738 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
739 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
740 &pcix_cmd_word);
741 }
742 }
743 break;
744 }
745
746 /* Call a subroutine to configure the link and setup flow control. */
747 ret_val = e1000_setup_link(hw);
748
749 /* Set the transmit descriptor write-back policy */
750 if(hw->mac_type > e1000_82544) {
751 ctrl = E1000_READ_REG(hw, TXDCTL);
752 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
753 switch (hw->mac_type) {
754 default:
755 break;
756 case e1000_82571:
757 case e1000_82572:
758 case e1000_82573:
759 case e1000_80003es2lan:
760 ctrl |= E1000_TXDCTL_COUNT_DESC;
761 break;
762 }
763 E1000_WRITE_REG(hw, TXDCTL, ctrl);
764 }
765
766 if (hw->mac_type == e1000_82573) {
767 e1000_enable_tx_pkt_filtering(hw);
768 }
769
770 switch (hw->mac_type) {
771 default:
772 break;
773 case e1000_80003es2lan:
774 /* Enable retransmit on late collisions */
775 reg_data = E1000_READ_REG(hw, TCTL);
776 reg_data |= E1000_TCTL_RTLC;
777 E1000_WRITE_REG(hw, TCTL, reg_data);
778
779 /* Configure Gigabit Carry Extend Padding */
780 reg_data = E1000_READ_REG(hw, TCTL_EXT);
781 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
782 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
783 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
784
785 /* Configure Transmit Inter-Packet Gap */
786 reg_data = E1000_READ_REG(hw, TIPG);
787 reg_data &= ~E1000_TIPG_IPGT_MASK;
788 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
789 E1000_WRITE_REG(hw, TIPG, reg_data);
790
791 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
792 reg_data &= ~0x00100000;
793 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
794 /* Fall through */
795 case e1000_82571:
796 case e1000_82572:
797 ctrl = E1000_READ_REG(hw, TXDCTL1);
798 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
799 if(hw->mac_type >= e1000_82571)
800 ctrl |= E1000_TXDCTL_COUNT_DESC;
801 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
802 break;
803 }
804
805
806
807 if (hw->mac_type == e1000_82573) {
808 uint32_t gcr = E1000_READ_REG(hw, GCR);
809 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
810 E1000_WRITE_REG(hw, GCR, gcr);
811 }
812
813 /* Clear all of the statistics registers (clear on read). It is
814 * important that we do this after we have tried to establish link
815 * because the symbol error count will increment wildly if there
816 * is no link.
817 */
818 e1000_clear_hw_cntrs(hw);
819
820 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
821 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
822 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
823 /* Relaxed ordering must be disabled to avoid a parity
824 * error crash in a PCI slot. */
825 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
826 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
827 }
828
829 return ret_val;
830 }
831
832 /******************************************************************************
833 * Adjust SERDES output amplitude based on EEPROM setting.
834 *
835 * hw - Struct containing variables accessed by shared code.
836 *****************************************************************************/
837 static int32_t
838 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
839 {
840 uint16_t eeprom_data;
841 int32_t ret_val;
842
843 DEBUGFUNC("e1000_adjust_serdes_amplitude");
844
845 if(hw->media_type != e1000_media_type_internal_serdes)
846 return E1000_SUCCESS;
847
848 switch(hw->mac_type) {
849 case e1000_82545_rev_3:
850 case e1000_82546_rev_3:
851 break;
852 default:
853 return E1000_SUCCESS;
854 }
855
856 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
857 if (ret_val) {
858 return ret_val;
859 }
860
861 if(eeprom_data != EEPROM_RESERVED_WORD) {
862 /* Adjust SERDES output amplitude only. */
863 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
864 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
865 if(ret_val)
866 return ret_val;
867 }
868
869 return E1000_SUCCESS;
870 }
871
872 /******************************************************************************
873 * Configures flow control and link settings.
874 *
875 * hw - Struct containing variables accessed by shared code
876 *
877 * Determines which flow control settings to use. Calls the apropriate media-
878 * specific link configuration function. Configures the flow control settings.
879 * Assuming the adapter has a valid link partner, a valid link should be
880 * established. Assumes the hardware has previously been reset and the
881 * transmitter and receiver are not enabled.
882 *****************************************************************************/
883 int32_t
884 e1000_setup_link(struct e1000_hw *hw)
885 {
886 uint32_t ctrl_ext;
887 int32_t ret_val;
888 uint16_t eeprom_data;
889
890 DEBUGFUNC("e1000_setup_link");
891
892 /* In the case of the phy reset being blocked, we already have a link.
893 * We do not have to set it up again. */
894 if (e1000_check_phy_reset_block(hw))
895 return E1000_SUCCESS;
896
897 /* Read and store word 0x0F of the EEPROM. This word contains bits
898 * that determine the hardware's default PAUSE (flow control) mode,
899 * a bit that determines whether the HW defaults to enabling or
900 * disabling auto-negotiation, and the direction of the
901 * SW defined pins. If there is no SW over-ride of the flow
902 * control setting, then the variable hw->fc will
903 * be initialized based on a value in the EEPROM.
904 */
905 if (hw->fc == e1000_fc_default) {
906 switch (hw->mac_type) {
907 case e1000_82573:
908 hw->fc = e1000_fc_full;
909 break;
910 default:
911 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
912 1, &eeprom_data);
913 if (ret_val) {
914 DEBUGOUT("EEPROM Read Error\n");
915 return -E1000_ERR_EEPROM;
916 }
917 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
918 hw->fc = e1000_fc_none;
919 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
920 EEPROM_WORD0F_ASM_DIR)
921 hw->fc = e1000_fc_tx_pause;
922 else
923 hw->fc = e1000_fc_full;
924 break;
925 }
926 }
927
928 /* We want to save off the original Flow Control configuration just
929 * in case we get disconnected and then reconnected into a different
930 * hub or switch with different Flow Control capabilities.
931 */
932 if(hw->mac_type == e1000_82542_rev2_0)
933 hw->fc &= (~e1000_fc_tx_pause);
934
935 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
936 hw->fc &= (~e1000_fc_rx_pause);
937
938 hw->original_fc = hw->fc;
939
940 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
941
942 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
943 * polarity value for the SW controlled pins, and setup the
944 * Extended Device Control reg with that info.
945 * This is needed because one of the SW controlled pins is used for
946 * signal detection. So this should be done before e1000_setup_pcs_link()
947 * or e1000_phy_setup() is called.
948 */
949 if (hw->mac_type == e1000_82543) {
950 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
951 1, &eeprom_data);
952 if (ret_val) {
953 DEBUGOUT("EEPROM Read Error\n");
954 return -E1000_ERR_EEPROM;
955 }
956 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
957 SWDPIO__EXT_SHIFT);
958 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
959 }
960
961 /* Call the necessary subroutine to configure the link. */
962 ret_val = (hw->media_type == e1000_media_type_copper) ?
963 e1000_setup_copper_link(hw) :
964 e1000_setup_fiber_serdes_link(hw);
965
966 /* Initialize the flow control address, type, and PAUSE timer
967 * registers to their default values. This is done even if flow
968 * control is disabled, because it does not hurt anything to
969 * initialize these registers.
970 */
971 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
972
973 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
974 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
975 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
976
977 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
978
979 /* Set the flow control receive threshold registers. Normally,
980 * these registers will be set to a default threshold that may be
981 * adjusted later by the driver's runtime code. However, if the
982 * ability to transmit pause frames in not enabled, then these
983 * registers will be set to 0.
984 */
985 if(!(hw->fc & e1000_fc_tx_pause)) {
986 E1000_WRITE_REG(hw, FCRTL, 0);
987 E1000_WRITE_REG(hw, FCRTH, 0);
988 } else {
989 /* We need to set up the Receive Threshold high and low water marks
990 * as well as (optionally) enabling the transmission of XON frames.
991 */
992 if(hw->fc_send_xon) {
993 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
994 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
995 } else {
996 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
997 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
998 }
999 }
1000 return ret_val;
1001 }
1002
1003 /******************************************************************************
1004 * Sets up link for a fiber based or serdes based adapter
1005 *
1006 * hw - Struct containing variables accessed by shared code
1007 *
1008 * Manipulates Physical Coding Sublayer functions in order to configure
1009 * link. Assumes the hardware has been previously reset and the transmitter
1010 * and receiver are not enabled.
1011 *****************************************************************************/
1012 static int32_t
1013 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1014 {
1015 uint32_t ctrl;
1016 uint32_t status;
1017 uint32_t txcw = 0;
1018 uint32_t i;
1019 uint32_t signal = 0;
1020 int32_t ret_val;
1021
1022 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1023
1024 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1025 * until explicitly turned off or a power cycle is performed. A read to
1026 * the register does not indicate its status. Therefore, we ensure
1027 * loopback mode is disabled during initialization.
1028 */
1029 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1030 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1031
1032 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1033 * set when the optics detect a signal. On older adapters, it will be
1034 * cleared when there is a signal. This applies to fiber media only.
1035 * If we're on serdes media, adjust the output amplitude to value set in
1036 * the EEPROM.
1037 */
1038 ctrl = E1000_READ_REG(hw, CTRL);
1039 if(hw->media_type == e1000_media_type_fiber)
1040 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1041
1042 ret_val = e1000_adjust_serdes_amplitude(hw);
1043 if(ret_val)
1044 return ret_val;
1045
1046 /* Take the link out of reset */
1047 ctrl &= ~(E1000_CTRL_LRST);
1048
1049 /* Adjust VCO speed to improve BER performance */
1050 ret_val = e1000_set_vco_speed(hw);
1051 if(ret_val)
1052 return ret_val;
1053
1054 e1000_config_collision_dist(hw);
1055
1056 /* Check for a software override of the flow control settings, and setup
1057 * the device accordingly. If auto-negotiation is enabled, then software
1058 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1059 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1060 * auto-negotiation is disabled, then software will have to manually
1061 * configure the two flow control enable bits in the CTRL register.
1062 *
1063 * The possible values of the "fc" parameter are:
1064 * 0: Flow control is completely disabled
1065 * 1: Rx flow control is enabled (we can receive pause frames, but
1066 * not send pause frames).
1067 * 2: Tx flow control is enabled (we can send pause frames but we do
1068 * not support receiving pause frames).
1069 * 3: Both Rx and TX flow control (symmetric) are enabled.
1070 */
1071 switch (hw->fc) {
1072 case e1000_fc_none:
1073 /* Flow control is completely disabled by a software over-ride. */
1074 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1075 break;
1076 case e1000_fc_rx_pause:
1077 /* RX Flow control is enabled and TX Flow control is disabled by a
1078 * software over-ride. Since there really isn't a way to advertise
1079 * that we are capable of RX Pause ONLY, we will advertise that we
1080 * support both symmetric and asymmetric RX PAUSE. Later, we will
1081 * disable the adapter's ability to send PAUSE frames.
1082 */
1083 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1084 break;
1085 case e1000_fc_tx_pause:
1086 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1087 * software over-ride.
1088 */
1089 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1090 break;
1091 case e1000_fc_full:
1092 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1093 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1094 break;
1095 default:
1096 DEBUGOUT("Flow control param set incorrectly\n");
1097 return -E1000_ERR_CONFIG;
1098 break;
1099 }
1100
1101 /* Since auto-negotiation is enabled, take the link out of reset (the link
1102 * will be in reset, because we previously reset the chip). This will
1103 * restart auto-negotiation. If auto-neogtiation is successful then the
1104 * link-up status bit will be set and the flow control enable bits (RFCE
1105 * and TFCE) will be set according to their negotiated value.
1106 */
1107 DEBUGOUT("Auto-negotiation enabled\n");
1108
1109 E1000_WRITE_REG(hw, TXCW, txcw);
1110 E1000_WRITE_REG(hw, CTRL, ctrl);
1111 E1000_WRITE_FLUSH(hw);
1112
1113 hw->txcw = txcw;
1114 msec_delay(1);
1115
1116 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1117 * indication in the Device Status Register. Time-out if a link isn't
1118 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1119 * less than 500 milliseconds even if the other end is doing it in SW).
1120 * For internal serdes, we just assume a signal is present, then poll.
1121 */
1122 if(hw->media_type == e1000_media_type_internal_serdes ||
1123 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1124 DEBUGOUT("Looking for Link\n");
1125 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1126 msec_delay(10);
1127 status = E1000_READ_REG(hw, STATUS);
1128 if(status & E1000_STATUS_LU) break;
1129 }
1130 if(i == (LINK_UP_TIMEOUT / 10)) {
1131 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1132 hw->autoneg_failed = 1;
1133 /* AutoNeg failed to achieve a link, so we'll call
1134 * e1000_check_for_link. This routine will force the link up if
1135 * we detect a signal. This will allow us to communicate with
1136 * non-autonegotiating link partners.
1137 */
1138 ret_val = e1000_check_for_link(hw);
1139 if(ret_val) {
1140 DEBUGOUT("Error while checking for link\n");
1141 return ret_val;
1142 }
1143 hw->autoneg_failed = 0;
1144 } else {
1145 hw->autoneg_failed = 0;
1146 DEBUGOUT("Valid Link Found\n");
1147 }
1148 } else {
1149 DEBUGOUT("No Signal Detected\n");
1150 }
1151 return E1000_SUCCESS;
1152 }
1153
1154 /******************************************************************************
1155 * Make sure we have a valid PHY and change PHY mode before link setup.
1156 *
1157 * hw - Struct containing variables accessed by shared code
1158 ******************************************************************************/
1159 static int32_t
1160 e1000_copper_link_preconfig(struct e1000_hw *hw)
1161 {
1162 uint32_t ctrl;
1163 int32_t ret_val;
1164 uint16_t phy_data;
1165
1166 DEBUGFUNC("e1000_copper_link_preconfig");
1167
1168 ctrl = E1000_READ_REG(hw, CTRL);
1169 /* With 82543, we need to force speed and duplex on the MAC equal to what
1170 * the PHY speed and duplex configuration is. In addition, we need to
1171 * perform a hardware reset on the PHY to take it out of reset.
1172 */
1173 if(hw->mac_type > e1000_82543) {
1174 ctrl |= E1000_CTRL_SLU;
1175 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1176 E1000_WRITE_REG(hw, CTRL, ctrl);
1177 } else {
1178 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1179 E1000_WRITE_REG(hw, CTRL, ctrl);
1180 ret_val = e1000_phy_hw_reset(hw);
1181 if(ret_val)
1182 return ret_val;
1183 }
1184
1185 /* Make sure we have a valid PHY */
1186 ret_val = e1000_detect_gig_phy(hw);
1187 if(ret_val) {
1188 DEBUGOUT("Error, did not detect valid phy.\n");
1189 return ret_val;
1190 }
1191 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1192
1193 /* Set PHY to class A mode (if necessary) */
1194 ret_val = e1000_set_phy_mode(hw);
1195 if(ret_val)
1196 return ret_val;
1197
1198 if((hw->mac_type == e1000_82545_rev_3) ||
1199 (hw->mac_type == e1000_82546_rev_3)) {
1200 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1201 phy_data |= 0x00000008;
1202 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1203 }
1204
1205 if(hw->mac_type <= e1000_82543 ||
1206 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1207 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1208 hw->phy_reset_disable = FALSE;
1209
1210 return E1000_SUCCESS;
1211 }
1212
1213
1214 /********************************************************************
1215 * Copper link setup for e1000_phy_igp series.
1216 *
1217 * hw - Struct containing variables accessed by shared code
1218 *********************************************************************/
1219 static int32_t
1220 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1221 {
1222 uint32_t led_ctrl;
1223 int32_t ret_val;
1224 uint16_t phy_data;
1225
1226 DEBUGFUNC("e1000_copper_link_igp_setup");
1227
1228 if (hw->phy_reset_disable)
1229 return E1000_SUCCESS;
1230
1231 ret_val = e1000_phy_reset(hw);
1232 if (ret_val) {
1233 DEBUGOUT("Error Resetting the PHY\n");
1234 return ret_val;
1235 }
1236
1237 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1238 msec_delay(15);
1239
1240 /* Configure activity LED after PHY reset */
1241 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1242 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1243 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1244 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1245
1246 /* disable lplu d3 during driver init */
1247 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1248 if (ret_val) {
1249 DEBUGOUT("Error Disabling LPLU D3\n");
1250 return ret_val;
1251 }
1252
1253 /* disable lplu d0 during driver init */
1254 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1255 if (ret_val) {
1256 DEBUGOUT("Error Disabling LPLU D0\n");
1257 return ret_val;
1258 }
1259 /* Configure mdi-mdix settings */
1260 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1265 hw->dsp_config_state = e1000_dsp_config_disabled;
1266 /* Force MDI for earlier revs of the IGP PHY */
1267 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1268 hw->mdix = 1;
1269
1270 } else {
1271 hw->dsp_config_state = e1000_dsp_config_enabled;
1272 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1273
1274 switch (hw->mdix) {
1275 case 1:
1276 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1277 break;
1278 case 2:
1279 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1280 break;
1281 case 0:
1282 default:
1283 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1284 break;
1285 }
1286 }
1287 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1288 if(ret_val)
1289 return ret_val;
1290
1291 /* set auto-master slave resolution settings */
1292 if(hw->autoneg) {
1293 e1000_ms_type phy_ms_setting = hw->master_slave;
1294
1295 if(hw->ffe_config_state == e1000_ffe_config_active)
1296 hw->ffe_config_state = e1000_ffe_config_enabled;
1297
1298 if(hw->dsp_config_state == e1000_dsp_config_activated)
1299 hw->dsp_config_state = e1000_dsp_config_enabled;
1300
1301 /* when autonegotiation advertisment is only 1000Mbps then we
1302 * should disable SmartSpeed and enable Auto MasterSlave
1303 * resolution as hardware default. */
1304 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1305 /* Disable SmartSpeed */
1306 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1307 if(ret_val)
1308 return ret_val;
1309 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1310 ret_val = e1000_write_phy_reg(hw,
1311 IGP01E1000_PHY_PORT_CONFIG,
1312 phy_data);
1313 if(ret_val)
1314 return ret_val;
1315 /* Set auto Master/Slave resolution process */
1316 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1317 if(ret_val)
1318 return ret_val;
1319 phy_data &= ~CR_1000T_MS_ENABLE;
1320 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1321 if(ret_val)
1322 return ret_val;
1323 }
1324
1325 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1326 if(ret_val)
1327 return ret_val;
1328
1329 /* load defaults for future use */
1330 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1331 ((phy_data & CR_1000T_MS_VALUE) ?
1332 e1000_ms_force_master :
1333 e1000_ms_force_slave) :
1334 e1000_ms_auto;
1335
1336 switch (phy_ms_setting) {
1337 case e1000_ms_force_master:
1338 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1339 break;
1340 case e1000_ms_force_slave:
1341 phy_data |= CR_1000T_MS_ENABLE;
1342 phy_data &= ~(CR_1000T_MS_VALUE);
1343 break;
1344 case e1000_ms_auto:
1345 phy_data &= ~CR_1000T_MS_ENABLE;
1346 default:
1347 break;
1348 }
1349 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1350 if(ret_val)
1351 return ret_val;
1352 }
1353
1354 return E1000_SUCCESS;
1355 }
1356
1357 /********************************************************************
1358 * Copper link setup for e1000_phy_gg82563 series.
1359 *
1360 * hw - Struct containing variables accessed by shared code
1361 *********************************************************************/
1362 static int32_t
1363 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1364 {
1365 int32_t ret_val;
1366 uint16_t phy_data;
1367 uint32_t reg_data;
1368
1369 DEBUGFUNC("e1000_copper_link_ggp_setup");
1370
1371 if(!hw->phy_reset_disable) {
1372
1373 /* Enable CRS on TX for half-duplex operation. */
1374 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1375 &phy_data);
1376 if(ret_val)
1377 return ret_val;
1378
1379 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1380 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1381 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1382
1383 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1384 phy_data);
1385 if(ret_val)
1386 return ret_val;
1387
1388 /* Options:
1389 * MDI/MDI-X = 0 (default)
1390 * 0 - Auto for all speeds
1391 * 1 - MDI mode
1392 * 2 - MDI-X mode
1393 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1394 */
1395 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1396 if(ret_val)
1397 return ret_val;
1398
1399 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1400
1401 switch (hw->mdix) {
1402 case 1:
1403 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1404 break;
1405 case 2:
1406 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1407 break;
1408 case 0:
1409 default:
1410 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1411 break;
1412 }
1413
1414 /* Options:
1415 * disable_polarity_correction = 0 (default)
1416 * Automatic Correction for Reversed Cable Polarity
1417 * 0 - Disabled
1418 * 1 - Enabled
1419 */
1420 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1421 if(hw->disable_polarity_correction == 1)
1422 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1423 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1424
1425 if(ret_val)
1426 return ret_val;
1427
1428 /* SW Reset the PHY so all changes take effect */
1429 ret_val = e1000_phy_reset(hw);
1430 if (ret_val) {
1431 DEBUGOUT("Error Resetting the PHY\n");
1432 return ret_val;
1433 }
1434 } /* phy_reset_disable */
1435
1436 if (hw->mac_type == e1000_80003es2lan) {
1437 /* Bypass RX and TX FIFO's */
1438 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1439 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1440 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1441 if (ret_val)
1442 return ret_val;
1443
1444 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1445 if (ret_val)
1446 return ret_val;
1447
1448 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1449 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1450
1451 if (ret_val)
1452 return ret_val;
1453
1454 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1455 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1456 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1457
1458 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1459 &phy_data);
1460 if (ret_val)
1461 return ret_val;
1462
1463 /* Do not init these registers when the HW is in IAMT mode, since the
1464 * firmware will have already initialized them. We only initialize
1465 * them if the HW is not in IAMT mode.
1466 */
1467 if (e1000_check_mng_mode(hw) == FALSE) {
1468 /* Enable Electrical Idle on the PHY */
1469 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1470 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1471 phy_data);
1472 if (ret_val)
1473 return ret_val;
1474
1475 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1476 &phy_data);
1477 if (ret_val)
1478 return ret_val;
1479
1480 /* Enable Pass False Carrier on the PHY */
1481 phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1482
1483 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1484 phy_data);
1485 if (ret_val)
1486 return ret_val;
1487 }
1488
1489 /* Workaround: Disable padding in Kumeran interface in the MAC
1490 * and in the PHY to avoid CRC errors.
1491 */
1492 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1493 &phy_data);
1494 if (ret_val)
1495 return ret_val;
1496 phy_data |= GG82563_ICR_DIS_PADDING;
1497 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1498 phy_data);
1499 if (ret_val)
1500 return ret_val;
1501 }
1502
1503 return E1000_SUCCESS;
1504 }
1505
1506 /********************************************************************
1507 * Copper link setup for e1000_phy_m88 series.
1508 *
1509 * hw - Struct containing variables accessed by shared code
1510 *********************************************************************/
1511 static int32_t
1512 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1513 {
1514 int32_t ret_val;
1515 uint16_t phy_data;
1516
1517 DEBUGFUNC("e1000_copper_link_mgp_setup");
1518
1519 if(hw->phy_reset_disable)
1520 return E1000_SUCCESS;
1521
1522 /* Enable CRS on TX. This must be set for half-duplex operation. */
1523 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1524 if(ret_val)
1525 return ret_val;
1526
1527 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1528
1529 /* Options:
1530 * MDI/MDI-X = 0 (default)
1531 * 0 - Auto for all speeds
1532 * 1 - MDI mode
1533 * 2 - MDI-X mode
1534 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1535 */
1536 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1537
1538 switch (hw->mdix) {
1539 case 1:
1540 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1541 break;
1542 case 2:
1543 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1544 break;
1545 case 3:
1546 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1547 break;
1548 case 0:
1549 default:
1550 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1551 break;
1552 }
1553
1554 /* Options:
1555 * disable_polarity_correction = 0 (default)
1556 * Automatic Correction for Reversed Cable Polarity
1557 * 0 - Disabled
1558 * 1 - Enabled
1559 */
1560 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1561 if(hw->disable_polarity_correction == 1)
1562 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1563 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1564 if(ret_val)
1565 return ret_val;
1566
1567 /* Force TX_CLK in the Extended PHY Specific Control Register
1568 * to 25MHz clock.
1569 */
1570 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1571 if(ret_val)
1572 return ret_val;
1573
1574 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1575
1576 if (hw->phy_revision < M88E1011_I_REV_4) {
1577 /* Configure Master and Slave downshift values */
1578 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1579 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1580 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1581 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1582 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1583 if(ret_val)
1584 return ret_val;
1585 }
1586
1587 /* SW Reset the PHY so all changes take effect */
1588 ret_val = e1000_phy_reset(hw);
1589 if(ret_val) {
1590 DEBUGOUT("Error Resetting the PHY\n");
1591 return ret_val;
1592 }
1593
1594 return E1000_SUCCESS;
1595 }
1596
1597 /********************************************************************
1598 * Setup auto-negotiation and flow control advertisements,
1599 * and then perform auto-negotiation.
1600 *
1601 * hw - Struct containing variables accessed by shared code
1602 *********************************************************************/
1603 static int32_t
1604 e1000_copper_link_autoneg(struct e1000_hw *hw)
1605 {
1606 int32_t ret_val;
1607 uint16_t phy_data;
1608
1609 DEBUGFUNC("e1000_copper_link_autoneg");
1610
1611 /* Perform some bounds checking on the hw->autoneg_advertised
1612 * parameter. If this variable is zero, then set it to the default.
1613 */
1614 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1615
1616 /* If autoneg_advertised is zero, we assume it was not defaulted
1617 * by the calling code so we set to advertise full capability.
1618 */
1619 if(hw->autoneg_advertised == 0)
1620 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1621
1622 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1623 ret_val = e1000_phy_setup_autoneg(hw);
1624 if(ret_val) {
1625 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1626 return ret_val;
1627 }
1628 DEBUGOUT("Restarting Auto-Neg\n");
1629
1630 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1631 * the Auto Neg Restart bit in the PHY control register.
1632 */
1633 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1634 if(ret_val)
1635 return ret_val;
1636
1637 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1638 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1639 if(ret_val)
1640 return ret_val;
1641
1642 /* Does the user want to wait for Auto-Neg to complete here, or
1643 * check at a later time (for example, callback routine).
1644 */
1645 if(hw->wait_autoneg_complete) {
1646 ret_val = e1000_wait_autoneg(hw);
1647 if(ret_val) {
1648 DEBUGOUT("Error while waiting for autoneg to complete\n");
1649 return ret_val;
1650 }
1651 }
1652
1653 hw->get_link_status = TRUE;
1654
1655 return E1000_SUCCESS;
1656 }
1657
1658
1659 /******************************************************************************
1660 * Config the MAC and the PHY after link is up.
1661 * 1) Set up the MAC to the current PHY speed/duplex
1662 * if we are on 82543. If we
1663 * are on newer silicon, we only need to configure
1664 * collision distance in the Transmit Control Register.
1665 * 2) Set up flow control on the MAC to that established with
1666 * the link partner.
1667 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1668 *
1669 * hw - Struct containing variables accessed by shared code
1670 ******************************************************************************/
1671 static int32_t
1672 e1000_copper_link_postconfig(struct e1000_hw *hw)
1673 {
1674 int32_t ret_val;
1675 DEBUGFUNC("e1000_copper_link_postconfig");
1676
1677 if(hw->mac_type >= e1000_82544) {
1678 e1000_config_collision_dist(hw);
1679 } else {
1680 ret_val = e1000_config_mac_to_phy(hw);
1681 if(ret_val) {
1682 DEBUGOUT("Error configuring MAC to PHY settings\n");
1683 return ret_val;
1684 }
1685 }
1686 ret_val = e1000_config_fc_after_link_up(hw);
1687 if(ret_val) {
1688 DEBUGOUT("Error Configuring Flow Control\n");
1689 return ret_val;
1690 }
1691
1692 /* Config DSP to improve Giga link quality */
1693 if(hw->phy_type == e1000_phy_igp) {
1694 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1695 if(ret_val) {
1696 DEBUGOUT("Error Configuring DSP after link up\n");
1697 return ret_val;
1698 }
1699 }
1700
1701 return E1000_SUCCESS;
1702 }
1703
1704 /******************************************************************************
1705 * Detects which PHY is present and setup the speed and duplex
1706 *
1707 * hw - Struct containing variables accessed by shared code
1708 ******************************************************************************/
1709 static int32_t
1710 e1000_setup_copper_link(struct e1000_hw *hw)
1711 {
1712 int32_t ret_val;
1713 uint16_t i;
1714 uint16_t phy_data;
1715 uint16_t reg_data;
1716
1717 DEBUGFUNC("e1000_setup_copper_link");
1718
1719 /* Check if it is a valid PHY and set PHY mode if necessary. */
1720 ret_val = e1000_copper_link_preconfig(hw);
1721 if(ret_val)
1722 return ret_val;
1723
1724 switch (hw->mac_type) {
1725 case e1000_80003es2lan:
1726 ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1727 &reg_data);
1728 if (ret_val)
1729 return ret_val;
1730 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1731 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1732 reg_data);
1733 if (ret_val)
1734 return ret_val;
1735 break;
1736 default:
1737 break;
1738 }
1739
1740 if (hw->phy_type == e1000_phy_igp ||
1741 hw->phy_type == e1000_phy_igp_2) {
1742 ret_val = e1000_copper_link_igp_setup(hw);
1743 if(ret_val)
1744 return ret_val;
1745 } else if (hw->phy_type == e1000_phy_m88) {
1746 ret_val = e1000_copper_link_mgp_setup(hw);
1747 if(ret_val)
1748 return ret_val;
1749 } else if (hw->phy_type == e1000_phy_gg82563) {
1750 ret_val = e1000_copper_link_ggp_setup(hw);
1751 if(ret_val)
1752 return ret_val;
1753 }
1754
1755 if(hw->autoneg) {
1756 /* Setup autoneg and flow control advertisement
1757 * and perform autonegotiation */
1758 ret_val = e1000_copper_link_autoneg(hw);
1759 if(ret_val)
1760 return ret_val;
1761 } else {
1762 /* PHY will be set to 10H, 10F, 100H,or 100F
1763 * depending on value from forced_speed_duplex. */
1764 DEBUGOUT("Forcing speed and duplex\n");
1765 ret_val = e1000_phy_force_speed_duplex(hw);
1766 if(ret_val) {
1767 DEBUGOUT("Error Forcing Speed and Duplex\n");
1768 return ret_val;
1769 }
1770 }
1771
1772 /* Check link status. Wait up to 100 microseconds for link to become
1773 * valid.
1774 */
1775 for(i = 0; i < 10; i++) {
1776 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1777 if(ret_val)
1778 return ret_val;
1779 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1780 if(ret_val)
1781 return ret_val;
1782
1783 if(phy_data & MII_SR_LINK_STATUS) {
1784 /* Config the MAC and PHY after link is up */
1785 ret_val = e1000_copper_link_postconfig(hw);
1786 if(ret_val)
1787 return ret_val;
1788
1789 DEBUGOUT("Valid link established!!!\n");
1790 return E1000_SUCCESS;
1791 }
1792 udelay(10);
1793 }
1794
1795 DEBUGOUT("Unable to establish link!!!\n");
1796 return E1000_SUCCESS;
1797 }
1798
1799 /******************************************************************************
1800 * Configure the MAC-to-PHY interface for 10/100Mbps
1801 *
1802 * hw - Struct containing variables accessed by shared code
1803 ******************************************************************************/
1804 static int32_t
1805 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw)
1806 {
1807 int32_t ret_val = E1000_SUCCESS;
1808 uint32_t tipg;
1809 uint16_t reg_data;
1810
1811 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1812
1813 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
1814 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1815 reg_data);
1816 if (ret_val)
1817 return ret_val;
1818
1819 /* Configure Transmit Inter-Packet Gap */
1820 tipg = E1000_READ_REG(hw, TIPG);
1821 tipg &= ~E1000_TIPG_IPGT_MASK;
1822 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1823 E1000_WRITE_REG(hw, TIPG, tipg);
1824
1825 return ret_val;
1826 }
1827
1828 static int32_t
1829 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1830 {
1831 int32_t ret_val = E1000_SUCCESS;
1832 uint16_t reg_data;
1833 uint32_t tipg;
1834
1835 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1836
1837 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
1838 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1839 reg_data);
1840 if (ret_val)
1841 return ret_val;
1842
1843 /* Configure Transmit Inter-Packet Gap */
1844 tipg = E1000_READ_REG(hw, TIPG);
1845 tipg &= ~E1000_TIPG_IPGT_MASK;
1846 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1847 E1000_WRITE_REG(hw, TIPG, tipg);
1848
1849 return ret_val;
1850 }
1851
1852 /******************************************************************************
1853 * Configures PHY autoneg and flow control advertisement settings
1854 *
1855 * hw - Struct containing variables accessed by shared code
1856 ******************************************************************************/
1857 int32_t
1858 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1859 {
1860 int32_t ret_val;
1861 uint16_t mii_autoneg_adv_reg;
1862 uint16_t mii_1000t_ctrl_reg;
1863
1864 DEBUGFUNC("e1000_phy_setup_autoneg");
1865
1866 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1867 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1868 if(ret_val)
1869 return ret_val;
1870
1871 /* Read the MII 1000Base-T Control Register (Address 9). */
1872 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1873 if(ret_val)
1874 return ret_val;
1875
1876 /* Need to parse both autoneg_advertised and fc and set up
1877 * the appropriate PHY registers. First we will parse for
1878 * autoneg_advertised software override. Since we can advertise
1879 * a plethora of combinations, we need to check each bit
1880 * individually.
1881 */
1882
1883 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1884 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1885 * the 1000Base-T Control Register (Address 9).
1886 */
1887 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1888 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1889
1890 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1891
1892 /* Do we want to advertise 10 Mb Half Duplex? */
1893 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1894 DEBUGOUT("Advertise 10mb Half duplex\n");
1895 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1896 }
1897
1898 /* Do we want to advertise 10 Mb Full Duplex? */
1899 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1900 DEBUGOUT("Advertise 10mb Full duplex\n");
1901 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1902 }
1903
1904 /* Do we want to advertise 100 Mb Half Duplex? */
1905 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1906 DEBUGOUT("Advertise 100mb Half duplex\n");
1907 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1908 }
1909
1910 /* Do we want to advertise 100 Mb Full Duplex? */
1911 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1912 DEBUGOUT("Advertise 100mb Full duplex\n");
1913 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1914 }
1915
1916 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1917 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1918 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1919 }
1920
1921 /* Do we want to advertise 1000 Mb Full Duplex? */
1922 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1923 DEBUGOUT("Advertise 1000mb Full duplex\n");
1924 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1925 }
1926
1927 /* Check for a software override of the flow control settings, and
1928 * setup the PHY advertisement registers accordingly. If
1929 * auto-negotiation is enabled, then software will have to set the
1930 * "PAUSE" bits to the correct value in the Auto-Negotiation
1931 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1932 *
1933 * The possible values of the "fc" parameter are:
1934 * 0: Flow control is completely disabled
1935 * 1: Rx flow control is enabled (we can receive pause frames
1936 * but not send pause frames).
1937 * 2: Tx flow control is enabled (we can send pause frames
1938 * but we do not support receiving pause frames).
1939 * 3: Both Rx and TX flow control (symmetric) are enabled.
1940 * other: No software override. The flow control configuration
1941 * in the EEPROM is used.
1942 */
1943 switch (hw->fc) {
1944 case e1000_fc_none: /* 0 */
1945 /* Flow control (RX & TX) is completely disabled by a
1946 * software over-ride.
1947 */
1948 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1949 break;
1950 case e1000_fc_rx_pause: /* 1 */
1951 /* RX Flow control is enabled, and TX Flow control is
1952 * disabled, by a software over-ride.
1953 */
1954 /* Since there really isn't a way to advertise that we are
1955 * capable of RX Pause ONLY, we will advertise that we
1956 * support both symmetric and asymmetric RX PAUSE. Later
1957 * (in e1000_config_fc_after_link_up) we will disable the
1958 *hw's ability to send PAUSE frames.
1959 */
1960 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1961 break;
1962 case e1000_fc_tx_pause: /* 2 */
1963 /* TX Flow control is enabled, and RX Flow control is
1964 * disabled, by a software over-ride.
1965 */
1966 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1967 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1968 break;
1969 case e1000_fc_full: /* 3 */
1970 /* Flow control (both RX and TX) is enabled by a software
1971 * over-ride.
1972 */
1973 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1974 break;
1975 default:
1976 DEBUGOUT("Flow control param set incorrectly\n");
1977 return -E1000_ERR_CONFIG;
1978 }
1979
1980 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1981 if(ret_val)
1982 return ret_val;
1983
1984 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1985
1986 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1987 if(ret_val)
1988 return ret_val;
1989
1990 return E1000_SUCCESS;
1991 }
1992
1993 /******************************************************************************
1994 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1995 *
1996 * hw - Struct containing variables accessed by shared code
1997 ******************************************************************************/
1998 static int32_t
1999 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2000 {
2001 uint32_t ctrl;
2002 int32_t ret_val;
2003 uint16_t mii_ctrl_reg;
2004 uint16_t mii_status_reg;
2005 uint16_t phy_data;
2006 uint16_t i;
2007
2008 DEBUGFUNC("e1000_phy_force_speed_duplex");
2009
2010 /* Turn off Flow control if we are forcing speed and duplex. */
2011 hw->fc = e1000_fc_none;
2012
2013 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2014
2015 /* Read the Device Control Register. */
2016 ctrl = E1000_READ_REG(hw, CTRL);
2017
2018 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2019 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2020 ctrl &= ~(DEVICE_SPEED_MASK);
2021
2022 /* Clear the Auto Speed Detect Enable bit. */
2023 ctrl &= ~E1000_CTRL_ASDE;
2024
2025 /* Read the MII Control Register. */
2026 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2027 if(ret_val)
2028 return ret_val;
2029
2030 /* We need to disable autoneg in order to force link and duplex. */
2031
2032 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2033
2034 /* Are we forcing Full or Half Duplex? */
2035 if(hw->forced_speed_duplex == e1000_100_full ||
2036 hw->forced_speed_duplex == e1000_10_full) {
2037 /* We want to force full duplex so we SET the full duplex bits in the
2038 * Device and MII Control Registers.
2039 */
2040 ctrl |= E1000_CTRL_FD;
2041 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2042 DEBUGOUT("Full Duplex\n");
2043 } else {
2044 /* We want to force half duplex so we CLEAR the full duplex bits in
2045 * the Device and MII Control Registers.
2046 */
2047 ctrl &= ~E1000_CTRL_FD;
2048 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2049 DEBUGOUT("Half Duplex\n");
2050 }
2051
2052 /* Are we forcing 100Mbps??? */
2053 if(hw->forced_speed_duplex == e1000_100_full ||
2054 hw->forced_speed_duplex == e1000_100_half) {
2055 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2056 ctrl |= E1000_CTRL_SPD_100;
2057 mii_ctrl_reg |= MII_CR_SPEED_100;
2058 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2059 DEBUGOUT("Forcing 100mb ");
2060 } else {
2061 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2062 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2063 mii_ctrl_reg |= MII_CR_SPEED_10;
2064 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2065 DEBUGOUT("Forcing 10mb ");
2066 }
2067
2068 e1000_config_collision_dist(hw);
2069
2070 /* Write the configured values back to the Device Control Reg. */
2071 E1000_WRITE_REG(hw, CTRL, ctrl);
2072
2073 if ((hw->phy_type == e1000_phy_m88) ||
2074 (hw->phy_type == e1000_phy_gg82563)) {
2075 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2076 if(ret_val)
2077 return ret_val;
2078
2079 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2080 * forced whenever speed are duplex are forced.
2081 */
2082 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2083 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2084 if(ret_val)
2085 return ret_val;
2086
2087 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2088
2089 /* Need to reset the PHY or these changes will be ignored */
2090 mii_ctrl_reg |= MII_CR_RESET;
2091 } else {
2092 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2093 * forced whenever speed or duplex are forced.
2094 */
2095 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2096 if(ret_val)
2097 return ret_val;
2098
2099 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2100 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2101
2102 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2103 if(ret_val)
2104 return ret_val;
2105 }
2106
2107 /* Write back the modified PHY MII control register. */
2108 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2109 if(ret_val)
2110 return ret_val;
2111
2112 udelay(1);
2113
2114 /* The wait_autoneg_complete flag may be a little misleading here.
2115 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2116 * But we do want to delay for a period while forcing only so we
2117 * don't generate false No Link messages. So we will wait here
2118 * only if the user has set wait_autoneg_complete to 1, which is
2119 * the default.
2120 */
2121 if(hw->wait_autoneg_complete) {
2122 /* We will wait for autoneg to complete. */
2123 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2124 mii_status_reg = 0;
2125
2126 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2127 for(i = PHY_FORCE_TIME; i > 0; i--) {
2128 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2129 * to be set.
2130 */
2131 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2132 if(ret_val)
2133 return ret_val;
2134
2135 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2136 if(ret_val)
2137 return ret_val;
2138
2139 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2140 msec_delay(100);
2141 }
2142 if((i == 0) &&
2143 ((hw->phy_type == e1000_phy_m88) ||
2144 (hw->phy_type == e1000_phy_gg82563))) {
2145 /* We didn't get link. Reset the DSP and wait again for link. */
2146 ret_val = e1000_phy_reset_dsp(hw);
2147 if(ret_val) {
2148 DEBUGOUT("Error Resetting PHY DSP\n");
2149 return ret_val;
2150 }
2151 }
2152 /* This loop will early-out if the link condition has been met. */
2153 for(i = PHY_FORCE_TIME; i > 0; i--) {
2154 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2155 msec_delay(100);
2156 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2157 * to be set.
2158 */
2159 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2160 if(ret_val)
2161 return ret_val;
2162
2163 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2164 if(ret_val)
2165 return ret_val;
2166 }
2167 }
2168
2169 if (hw->phy_type == e1000_phy_m88) {
2170 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2171 * Extended PHY Specific Control Register to 25MHz clock. This value
2172 * defaults back to a 2.5MHz clock when the PHY is reset.
2173 */
2174 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2175 if(ret_val)
2176 return ret_val;
2177
2178 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2179 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2180 if(ret_val)
2181 return ret_val;
2182
2183 /* In addition, because of the s/w reset above, we need to enable CRS on
2184 * TX. This must be set for both full and half duplex operation.
2185 */
2186 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2187 if(ret_val)
2188 return ret_val;
2189
2190 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2191 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2192 if(ret_val)
2193 return ret_val;
2194
2195 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2196 (!hw->autoneg) &&
2197 (hw->forced_speed_duplex == e1000_10_full ||
2198 hw->forced_speed_duplex == e1000_10_half)) {
2199 ret_val = e1000_polarity_reversal_workaround(hw);
2200 if(ret_val)
2201 return ret_val;
2202 }
2203 } else if (hw->phy_type == e1000_phy_gg82563) {
2204 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2205 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2206 * we're not in a forced 10/duplex configuration. */
2207 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2208 if (ret_val)
2209 return ret_val;
2210
2211 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2212 if ((hw->forced_speed_duplex == e1000_10_full) ||
2213 (hw->forced_speed_duplex == e1000_10_half))
2214 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2215 else
2216 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2217
2218 /* Also due to the reset, we need to enable CRS on Tx. */
2219 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2220
2221 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2222 if (ret_val)
2223 return ret_val;
2224 }
2225 return E1000_SUCCESS;
2226 }
2227
2228 /******************************************************************************
2229 * Sets the collision distance in the Transmit Control register
2230 *
2231 * hw - Struct containing variables accessed by shared code
2232 *
2233 * Link should have been established previously. Reads the speed and duplex
2234 * information from the Device Status register.
2235 ******************************************************************************/
2236 void
2237 e1000_config_collision_dist(struct e1000_hw *hw)
2238 {
2239 uint32_t tctl, coll_dist;
2240
2241 DEBUGFUNC("e1000_config_collision_dist");
2242
2243 if (hw->mac_type < e1000_82543)
2244 coll_dist = E1000_COLLISION_DISTANCE_82542;
2245 else
2246 coll_dist = E1000_COLLISION_DISTANCE;
2247
2248 tctl = E1000_READ_REG(hw, TCTL);
2249
2250 tctl &= ~E1000_TCTL_COLD;
2251 tctl |= coll_dist << E1000_COLD_SHIFT;
2252
2253 E1000_WRITE_REG(hw, TCTL, tctl);
2254 E1000_WRITE_FLUSH(hw);
2255 }
2256
2257 /******************************************************************************
2258 * Sets MAC speed and duplex settings to reflect the those in the PHY
2259 *
2260 * hw - Struct containing variables accessed by shared code
2261 * mii_reg - data to write to the MII control register
2262 *
2263 * The contents of the PHY register containing the needed information need to
2264 * be passed in.
2265 ******************************************************************************/
2266 static int32_t
2267 e1000_config_mac_to_phy(struct e1000_hw *hw)
2268 {
2269 uint32_t ctrl;
2270 int32_t ret_val;
2271 uint16_t phy_data;
2272
2273 DEBUGFUNC("e1000_config_mac_to_phy");
2274
2275 /* 82544 or newer MAC, Auto Speed Detection takes care of
2276 * MAC speed/duplex configuration.*/
2277 if (hw->mac_type >= e1000_82544)
2278 return E1000_SUCCESS;
2279
2280 /* Read the Device Control Register and set the bits to Force Speed
2281 * and Duplex.
2282 */
2283 ctrl = E1000_READ_REG(hw, CTRL);
2284 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2285 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2286
2287 /* Set up duplex in the Device Control and Transmit Control
2288 * registers depending on negotiated values.
2289 */
2290 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2291 if(ret_val)
2292 return ret_val;
2293
2294 if(phy_data & M88E1000_PSSR_DPLX)
2295 ctrl |= E1000_CTRL_FD;
2296 else
2297 ctrl &= ~E1000_CTRL_FD;
2298
2299 e1000_config_collision_dist(hw);
2300
2301 /* Set up speed in the Device Control register depending on
2302 * negotiated values.
2303 */
2304 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2305 ctrl |= E1000_CTRL_SPD_1000;
2306 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2307 ctrl |= E1000_CTRL_SPD_100;
2308
2309 /* Write the configured values back to the Device Control Reg. */
2310 E1000_WRITE_REG(hw, CTRL, ctrl);
2311 return E1000_SUCCESS;
2312 }
2313
2314 /******************************************************************************
2315 * Forces the MAC's flow control settings.
2316 *
2317 * hw - Struct containing variables accessed by shared code
2318 *
2319 * Sets the TFCE and RFCE bits in the device control register to reflect
2320 * the adapter settings. TFCE and RFCE need to be explicitly set by
2321 * software when a Copper PHY is used because autonegotiation is managed
2322 * by the PHY rather than the MAC. Software must also configure these
2323 * bits when link is forced on a fiber connection.
2324 *****************************************************************************/
2325 int32_t
2326 e1000_force_mac_fc(struct e1000_hw *hw)
2327 {
2328 uint32_t ctrl;
2329
2330 DEBUGFUNC("e1000_force_mac_fc");
2331
2332 /* Get the current configuration of the Device Control Register */
2333 ctrl = E1000_READ_REG(hw, CTRL);
2334
2335 /* Because we didn't get link via the internal auto-negotiation
2336 * mechanism (we either forced link or we got link via PHY
2337 * auto-neg), we have to manually enable/disable transmit an
2338 * receive flow control.
2339 *
2340 * The "Case" statement below enables/disable flow control
2341 * according to the "hw->fc" parameter.
2342 *
2343 * The possible values of the "fc" parameter are:
2344 * 0: Flow control is completely disabled
2345 * 1: Rx flow control is enabled (we can receive pause
2346 * frames but not send pause frames).
2347 * 2: Tx flow control is enabled (we can send pause frames
2348 * frames but we do not receive pause frames).
2349 * 3: Both Rx and TX flow control (symmetric) is enabled.
2350 * other: No other values should be possible at this point.
2351 */
2352
2353 switch (hw->fc) {
2354 case e1000_fc_none:
2355 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2356 break;
2357 case e1000_fc_rx_pause:
2358 ctrl &= (~E1000_CTRL_TFCE);
2359 ctrl |= E1000_CTRL_RFCE;
2360 break;
2361 case e1000_fc_tx_pause:
2362 ctrl &= (~E1000_CTRL_RFCE);
2363 ctrl |= E1000_CTRL_TFCE;
2364 break;
2365 case e1000_fc_full:
2366 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2367 break;
2368 default:
2369 DEBUGOUT("Flow control param set incorrectly\n");
2370 return -E1000_ERR_CONFIG;
2371 }
2372
2373 /* Disable TX Flow Control for 82542 (rev 2.0) */
2374 if(hw->mac_type == e1000_82542_rev2_0)
2375 ctrl &= (~E1000_CTRL_TFCE);
2376
2377 E1000_WRITE_REG(hw, CTRL, ctrl);
2378 return E1000_SUCCESS;
2379 }
2380
2381 /******************************************************************************
2382 * Configures flow control settings after link is established
2383 *
2384 * hw - Struct containing variables accessed by shared code
2385 *
2386 * Should be called immediately after a valid link has been established.
2387 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2388 * and autonegotiation is enabled, the MAC flow control settings will be set
2389 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2390 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2391 *****************************************************************************/
2392 static int32_t
2393 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2394 {
2395 int32_t ret_val;
2396 uint16_t mii_status_reg;
2397 uint16_t mii_nway_adv_reg;
2398 uint16_t mii_nway_lp_ability_reg;
2399 uint16_t speed;
2400 uint16_t duplex;
2401
2402 DEBUGFUNC("e1000_config_fc_after_link_up");
2403
2404 /* Check for the case where we have fiber media and auto-neg failed
2405 * so we had to force link. In this case, we need to force the
2406 * configuration of the MAC to match the "fc" parameter.
2407 */
2408 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2409 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
2410 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2411 ret_val = e1000_force_mac_fc(hw);
2412 if(ret_val) {
2413 DEBUGOUT("Error forcing flow control settings\n");
2414 return ret_val;
2415 }
2416 }
2417
2418 /* Check for the case where we have copper media and auto-neg is
2419 * enabled. In this case, we need to check and see if Auto-Neg
2420 * has completed, and if so, how the PHY and link partner has
2421 * flow control configured.
2422 */
2423 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2424 /* Read the MII Status Register and check to see if AutoNeg
2425 * has completed. We read this twice because this reg has
2426 * some "sticky" (latched) bits.
2427 */
2428 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2429 if(ret_val)
2430 return ret_val;
2431 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2432 if(ret_val)
2433 return ret_val;
2434
2435 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2436 /* The AutoNeg process has completed, so we now need to
2437 * read both the Auto Negotiation Advertisement Register
2438 * (Address 4) and the Auto_Negotiation Base Page Ability
2439 * Register (Address 5) to determine how flow control was
2440 * negotiated.
2441 */
2442 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2443 &mii_nway_adv_reg);
2444 if(ret_val)
2445 return ret_val;
2446 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2447 &mii_nway_lp_ability_reg);
2448 if(ret_val)
2449 return ret_val;
2450
2451 /* Two bits in the Auto Negotiation Advertisement Register
2452 * (Address 4) and two bits in the Auto Negotiation Base
2453 * Page Ability Register (Address 5) determine flow control
2454 * for both the PHY and the link partner. The following
2455 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2456 * 1999, describes these PAUSE resolution bits and how flow
2457 * control is determined based upon these settings.
2458 * NOTE: DC = Don't Care
2459 *
2460 * LOCAL DEVICE | LINK PARTNER
2461 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2462 *-------|---------|-------|---------|--------------------
2463 * 0 | 0 | DC | DC | e1000_fc_none
2464 * 0 | 1 | 0 | DC | e1000_fc_none
2465 * 0 | 1 | 1 | 0 | e1000_fc_none
2466 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2467 * 1 | 0 | 0 | DC | e1000_fc_none
2468 * 1 | DC | 1 | DC | e1000_fc_full
2469 * 1 | 1 | 0 | 0 | e1000_fc_none
2470 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2471 *
2472 */
2473 /* Are both PAUSE bits set to 1? If so, this implies
2474 * Symmetric Flow Control is enabled at both ends. The
2475 * ASM_DIR bits are irrelevant per the spec.
2476 *
2477 * For Symmetric Flow Control:
2478 *
2479 * LOCAL DEVICE | LINK PARTNER
2480 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2481 *-------|---------|-------|---------|--------------------
2482 * 1 | DC | 1 | DC | e1000_fc_full
2483 *
2484 */
2485 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2486 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2487 /* Now we need to check if the user selected RX ONLY
2488 * of pause frames. In this case, we had to advertise
2489 * FULL flow control because we could not advertise RX
2490 * ONLY. Hence, we must now check to see if we need to
2491 * turn OFF the TRANSMISSION of PAUSE frames.
2492 */
2493 if(hw->original_fc == e1000_fc_full) {
2494 hw->fc = e1000_fc_full;
2495 DEBUGOUT("Flow Control = FULL.\r\n");
2496 } else {
2497 hw->fc = e1000_fc_rx_pause;
2498 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2499 }
2500 }
2501 /* For receiving PAUSE frames ONLY.
2502 *
2503 * LOCAL DEVICE | LINK PARTNER
2504 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2505 *-------|---------|-------|---------|--------------------
2506 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2507 *
2508 */
2509 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2510 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2511 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2512 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2513 hw->fc = e1000_fc_tx_pause;
2514 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2515 }
2516 /* For transmitting PAUSE frames ONLY.
2517 *
2518 * LOCAL DEVICE | LINK PARTNER
2519 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2520 *-------|---------|-------|---------|--------------------
2521 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2522 *
2523 */
2524 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2525 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2526 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2527 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2528 hw->fc = e1000_fc_rx_pause;
2529 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2530 }
2531 /* Per the IEEE spec, at this point flow control should be
2532 * disabled. However, we want to consider that we could
2533 * be connected to a legacy switch that doesn't advertise
2534 * desired flow control, but can be forced on the link
2535 * partner. So if we advertised no flow control, that is
2536 * what we will resolve to. If we advertised some kind of
2537 * receive capability (Rx Pause Only or Full Flow Control)
2538 * and the link partner advertised none, we will configure
2539 * ourselves to enable Rx Flow Control only. We can do
2540 * this safely for two reasons: If the link partner really
2541 * didn't want flow control enabled, and we enable Rx, no
2542 * harm done since we won't be receiving any PAUSE frames
2543 * anyway. If the intent on the link partner was to have
2544 * flow control enabled, then by us enabling RX only, we
2545 * can at least receive pause frames and process them.
2546 * This is a good idea because in most cases, since we are
2547 * predominantly a server NIC, more times than not we will
2548 * be asked to delay transmission of packets than asking
2549 * our link partner to pause transmission of frames.
2550 */
2551 else if((hw->original_fc == e1000_fc_none ||
2552 hw->original_fc == e1000_fc_tx_pause) ||
2553 hw->fc_strict_ieee) {
2554 hw->fc = e1000_fc_none;
2555 DEBUGOUT("Flow Control = NONE.\r\n");
2556 } else {
2557 hw->fc = e1000_fc_rx_pause;
2558 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2559 }
2560
2561 /* Now we need to do one last check... If we auto-
2562 * negotiated to HALF DUPLEX, flow control should not be
2563 * enabled per IEEE 802.3 spec.
2564 */
2565 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2566 if(ret_val) {
2567 DEBUGOUT("Error getting link speed and duplex\n");
2568 return ret_val;
2569 }
2570
2571 if(duplex == HALF_DUPLEX)
2572 hw->fc = e1000_fc_none;
2573
2574 /* Now we call a subroutine to actually force the MAC
2575 * controller to use the correct flow control settings.
2576 */
2577 ret_val = e1000_force_mac_fc(hw);
2578 if(ret_val) {
2579 DEBUGOUT("Error forcing flow control settings\n");
2580 return ret_val;
2581 }
2582 } else {
2583 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2584 }
2585 }
2586 return E1000_SUCCESS;
2587 }
2588
2589 /******************************************************************************
2590 * Checks to see if the link status of the hardware has changed.
2591 *
2592 * hw - Struct containing variables accessed by shared code
2593 *
2594 * Called by any function that needs to check the link status of the adapter.
2595 *****************************************************************************/
2596 int32_t
2597 e1000_check_for_link(struct e1000_hw *hw)
2598 {
2599 uint32_t rxcw = 0;
2600 uint32_t ctrl;
2601 uint32_t status;
2602 uint32_t rctl;
2603 uint32_t icr;
2604 uint32_t signal = 0;
2605 int32_t ret_val;
2606 uint16_t phy_data;
2607
2608 DEBUGFUNC("e1000_check_for_link");
2609
2610 ctrl = E1000_READ_REG(hw, CTRL);
2611 status = E1000_READ_REG(hw, STATUS);
2612
2613 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2614 * set when the optics detect a signal. On older adapters, it will be
2615 * cleared when there is a signal. This applies to fiber media only.
2616 */
2617 if((hw->media_type == e1000_media_type_fiber) ||
2618 (hw->media_type == e1000_media_type_internal_serdes)) {
2619 rxcw = E1000_READ_REG(hw, RXCW);
2620
2621 if(hw->media_type == e1000_media_type_fiber) {
2622 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2623 if(status & E1000_STATUS_LU)
2624 hw->get_link_status = FALSE;
2625 }
2626 }
2627
2628 /* If we have a copper PHY then we only want to go out to the PHY
2629 * registers to see if Auto-Neg has completed and/or if our link
2630 * status has changed. The get_link_status flag will be set if we
2631 * receive a Link Status Change interrupt or we have Rx Sequence
2632 * Errors.
2633 */
2634 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2635 /* First we want to see if the MII Status Register reports
2636 * link. If so, then we want to get the current speed/duplex
2637 * of the PHY.
2638 * Read the register twice since the link bit is sticky.
2639 */
2640 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2641 if(ret_val)
2642 return ret_val;
2643 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2644 if(ret_val)
2645 return ret_val;
2646
2647 if(phy_data & MII_SR_LINK_STATUS) {
2648 hw->get_link_status = FALSE;
2649 /* Check if there was DownShift, must be checked immediately after
2650 * link-up */
2651 e1000_check_downshift(hw);
2652
2653 /* If we are on 82544 or 82543 silicon and speed/duplex
2654 * are forced to 10H or 10F, then we will implement the polarity
2655 * reversal workaround. We disable interrupts first, and upon
2656 * returning, place the devices interrupt state to its previous
2657 * value except for the link status change interrupt which will
2658 * happen due to the execution of this workaround.
2659 */
2660
2661 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2662 (!hw->autoneg) &&
2663 (hw->forced_speed_duplex == e1000_10_full ||
2664 hw->forced_speed_duplex == e1000_10_half)) {
2665 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2666 ret_val = e1000_polarity_reversal_workaround(hw);
2667 icr = E1000_READ_REG(hw, ICR);
2668 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2669 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2670 }
2671
2672 } else {
2673 /* No link detected */
2674 e1000_config_dsp_after_link_change(hw, FALSE);
2675 return 0;
2676 }
2677
2678 /* If we are forcing speed/duplex, then we simply return since
2679 * we have already determined whether we have link or not.
2680 */
2681 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2682
2683 /* optimize the dsp settings for the igp phy */
2684 e1000_config_dsp_after_link_change(hw, TRUE);
2685
2686 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2687 * have Si on board that is 82544 or newer, Auto
2688 * Speed Detection takes care of MAC speed/duplex
2689 * configuration. So we only need to configure Collision
2690 * Distance in the MAC. Otherwise, we need to force
2691 * speed/duplex on the MAC to the current PHY speed/duplex
2692 * settings.
2693 */
2694 if(hw->mac_type >= e1000_82544)
2695 e1000_config_collision_dist(hw);
2696 else {
2697 ret_val = e1000_config_mac_to_phy(hw);
2698 if(ret_val) {
2699 DEBUGOUT("Error configuring MAC to PHY settings\n");
2700 return ret_val;
2701 }
2702 }
2703
2704 /* Configure Flow Control now that Auto-Neg has completed. First, we
2705 * need to restore the desired flow control settings because we may
2706 * have had to re-autoneg with a different link partner.
2707 */
2708 ret_val = e1000_config_fc_after_link_up(hw);
2709 if(ret_val) {
2710 DEBUGOUT("Error configuring flow control\n");
2711 return ret_val;
2712 }
2713
2714 /* At this point we know that we are on copper and we have
2715 * auto-negotiated link. These are conditions for checking the link
2716 * partner capability register. We use the link speed to determine if
2717 * TBI compatibility needs to be turned on or off. If the link is not
2718 * at gigabit speed, then TBI compatibility is not needed. If we are
2719 * at gigabit speed, we turn on TBI compatibility.
2720 */
2721 if(hw->tbi_compatibility_en) {
2722 uint16_t speed, duplex;
2723 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2724 if(speed != SPEED_1000) {
2725 /* If link speed is not set to gigabit speed, we do not need
2726 * to enable TBI compatibility.
2727 */
2728 if(hw->tbi_compatibility_on) {
2729 /* If we previously were in the mode, turn it off. */
2730 rctl = E1000_READ_REG(hw, RCTL);
2731 rctl &= ~E1000_RCTL_SBP;
2732 E1000_WRITE_REG(hw, RCTL, rctl);
2733 hw->tbi_compatibility_on = FALSE;
2734 }
2735 } else {
2736 /* If TBI compatibility is was previously off, turn it on. For
2737 * compatibility with a TBI link partner, we will store bad
2738 * packets. Some frames have an additional byte on the end and
2739 * will look like CRC errors to to the hardware.
2740 */
2741 if(!hw->tbi_compatibility_on) {
2742 hw->tbi_compatibility_on = TRUE;
2743 rctl = E1000_READ_REG(hw, RCTL);
2744 rctl |= E1000_RCTL_SBP;
2745 E1000_WRITE_REG(hw, RCTL, rctl);
2746 }
2747 }
2748 }
2749 }
2750 /* If we don't have link (auto-negotiation failed or link partner cannot
2751 * auto-negotiate), the cable is plugged in (we have signal), and our
2752 * link partner is not trying to auto-negotiate with us (we are receiving
2753 * idles or data), we need to force link up. We also need to give
2754 * auto-negotiation time to complete, in case the cable was just plugged
2755 * in. The autoneg_failed flag does this.
2756 */
2757 else if((((hw->media_type == e1000_media_type_fiber) &&
2758 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2759 (hw->media_type == e1000_media_type_internal_serdes)) &&
2760 (!(status & E1000_STATUS_LU)) &&
2761 (!(rxcw & E1000_RXCW_C))) {
2762 if(hw->autoneg_failed == 0) {
2763 hw->autoneg_failed = 1;
2764 return 0;
2765 }
2766 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2767
2768 /* Disable auto-negotiation in the TXCW register */
2769 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2770
2771 /* Force link-up and also force full-duplex. */
2772 ctrl = E1000_READ_REG(hw, CTRL);
2773 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2774 E1000_WRITE_REG(hw, CTRL, ctrl);
2775
2776 /* Configure Flow Control after forcing link up. */
2777 ret_val = e1000_config_fc_after_link_up(hw);
2778 if(ret_val) {
2779 DEBUGOUT("Error configuring flow control\n");
2780 return ret_val;
2781 }
2782 }
2783 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2784 * auto-negotiation in the TXCW register and disable forced link in the
2785 * Device Control register in an attempt to auto-negotiate with our link
2786 * partner.
2787 */
2788 else if(((hw->media_type == e1000_media_type_fiber) ||
2789 (hw->media_type == e1000_media_type_internal_serdes)) &&
2790 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2791 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2792 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2793 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2794
2795 hw->serdes_link_down = FALSE;
2796 }
2797 /* If we force link for non-auto-negotiation switch, check link status
2798 * based on MAC synchronization for internal serdes media type.
2799 */
2800 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2801 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2802 /* SYNCH bit and IV bit are sticky. */
2803 udelay(10);
2804 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2805 if(!(rxcw & E1000_RXCW_IV)) {
2806 hw->serdes_link_down = FALSE;
2807 DEBUGOUT("SERDES: Link is up.\n");
2808 }
2809 } else {
2810 hw->serdes_link_down = TRUE;
2811 DEBUGOUT("SERDES: Link is down.\n");
2812 }
2813 }
2814 if((hw->media_type == e1000_media_type_internal_serdes) &&
2815 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2816 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2817 }
2818 return E1000_SUCCESS;
2819 }
2820
2821 /******************************************************************************
2822 * Detects the current speed and duplex settings of the hardware.
2823 *
2824 * hw - Struct containing variables accessed by shared code
2825 * speed - Speed of the connection
2826 * duplex - Duplex setting of the connection
2827 *****************************************************************************/
2828 int32_t
2829 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2830 uint16_t *speed,
2831 uint16_t *duplex)
2832 {
2833 uint32_t status;
2834 int32_t ret_val;
2835 uint16_t phy_data;
2836
2837 DEBUGFUNC("e1000_get_speed_and_duplex");
2838
2839 if(hw->mac_type >= e1000_82543) {
2840 status = E1000_READ_REG(hw, STATUS);
2841 if(status & E1000_STATUS_SPEED_1000) {
2842 *speed = SPEED_1000;
2843 DEBUGOUT("1000 Mbs, ");
2844 } else if(status & E1000_STATUS_SPEED_100) {
2845 *speed = SPEED_100;
2846 DEBUGOUT("100 Mbs, ");
2847 } else {
2848 *speed = SPEED_10;
2849 DEBUGOUT("10 Mbs, ");
2850 }
2851
2852 if(status & E1000_STATUS_FD) {
2853 *duplex = FULL_DUPLEX;
2854 DEBUGOUT("Full Duplex\r\n");
2855 } else {
2856 *duplex = HALF_DUPLEX;
2857 DEBUGOUT(" Half Duplex\r\n");
2858 }
2859 } else {
2860 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2861 *speed = SPEED_1000;
2862 *duplex = FULL_DUPLEX;
2863 }
2864
2865 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2866 * if it is operating at half duplex. Here we set the duplex settings to
2867 * match the duplex in the link partner's capabilities.
2868 */
2869 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2870 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2871 if(ret_val)
2872 return ret_val;
2873
2874 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2875 *duplex = HALF_DUPLEX;
2876 else {
2877 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2878 if(ret_val)
2879 return ret_val;
2880 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2881 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2882 *duplex = HALF_DUPLEX;
2883 }
2884 }
2885
2886 if ((hw->mac_type == e1000_80003es2lan) &&
2887 (hw->media_type == e1000_media_type_copper)) {
2888 if (*speed == SPEED_1000)
2889 ret_val = e1000_configure_kmrn_for_1000(hw);
2890 else
2891 ret_val = e1000_configure_kmrn_for_10_100(hw);
2892 if (ret_val)
2893 return ret_val;
2894 }
2895
2896 return E1000_SUCCESS;
2897 }
2898
2899 /******************************************************************************
2900 * Blocks until autoneg completes or times out (~4.5 seconds)
2901 *
2902 * hw - Struct containing variables accessed by shared code
2903 ******************************************************************************/
2904 static int32_t
2905 e1000_wait_autoneg(struct e1000_hw *hw)
2906 {
2907 int32_t ret_val;
2908 uint16_t i;
2909 uint16_t phy_data;
2910
2911 DEBUGFUNC("e1000_wait_autoneg");
2912 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2913
2914 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2915 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2916 /* Read the MII Status Register and wait for Auto-Neg
2917 * Complete bit to be set.
2918 */
2919 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2920 if(ret_val)
2921 return ret_val;
2922 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2923 if(ret_val)
2924 return ret_val;
2925 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2926 return E1000_SUCCESS;
2927 }
2928 msec_delay(100);
2929 }
2930 return E1000_SUCCESS;
2931 }
2932
2933 /******************************************************************************
2934 * Raises the Management Data Clock
2935 *
2936 * hw - Struct containing variables accessed by shared code
2937 * ctrl - Device control register's current value
2938 ******************************************************************************/
2939 static void
2940 e1000_raise_mdi_clk(struct e1000_hw *hw,
2941 uint32_t *ctrl)
2942 {
2943 /* Raise the clock input to the Management Data Clock (by setting the MDC
2944 * bit), and then delay 10 microseconds.
2945 */
2946 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2947 E1000_WRITE_FLUSH(hw);
2948 udelay(10);
2949 }
2950
2951 /******************************************************************************
2952 * Lowers the Management Data Clock
2953 *
2954 * hw - Struct containing variables accessed by shared code
2955 * ctrl - Device control register's current value
2956 ******************************************************************************/
2957 static void
2958 e1000_lower_mdi_clk(struct e1000_hw *hw,
2959 uint32_t *ctrl)
2960 {
2961 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2962 * bit), and then delay 10 microseconds.
2963 */
2964 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2965 E1000_WRITE_FLUSH(hw);
2966 udelay(10);
2967 }
2968
2969 /******************************************************************************
2970 * Shifts data bits out to the PHY
2971 *
2972 * hw - Struct containing variables accessed by shared code
2973 * data - Data to send out to the PHY
2974 * count - Number of bits to shift out
2975 *
2976 * Bits are shifted out in MSB to LSB order.
2977 ******************************************************************************/
2978 static void
2979 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2980 uint32_t data,
2981 uint16_t count)
2982 {
2983 uint32_t ctrl;
2984 uint32_t mask;
2985
2986 /* We need to shift "count" number of bits out to the PHY. So, the value
2987 * in the "data" parameter will be shifted out to the PHY one bit at a
2988 * time. In order to do this, "data" must be broken down into bits.
2989 */
2990 mask = 0x01;
2991 mask <<= (count - 1);
2992
2993 ctrl = E1000_READ_REG(hw, CTRL);
2994
2995 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2996 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2997
2998 while(mask) {
2999 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3000 * then raising and lowering the Management Data Clock. A "0" is
3001 * shifted out to the PHY by setting the MDIO bit to "0" and then
3002 * raising and lowering the clock.
3003 */
3004 if(data & mask) ctrl |= E1000_CTRL_MDIO;
3005 else ctrl &= ~E1000_CTRL_MDIO;
3006
3007 E1000_WRITE_REG(hw, CTRL, ctrl);
3008 E1000_WRITE_FLUSH(hw);
3009
3010 udelay(10);
3011
3012 e1000_raise_mdi_clk(hw, &ctrl);
3013 e1000_lower_mdi_clk(hw, &ctrl);
3014
3015 mask = mask >> 1;
3016 }
3017 }
3018
3019 /******************************************************************************
3020 * Shifts data bits in from the PHY
3021 *
3022 * hw - Struct containing variables accessed by shared code
3023 *
3024 * Bits are shifted in in MSB to LSB order.
3025 ******************************************************************************/
3026 static uint16_t
3027 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3028 {
3029 uint32_t ctrl;
3030 uint16_t data = 0;
3031 uint8_t i;
3032
3033 /* In order to read a register from the PHY, we need to shift in a total
3034 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3035 * to avoid contention on the MDIO pin when a read operation is performed.
3036 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3037 * by raising the input to the Management Data Clock (setting the MDC bit),
3038 * and then reading the value of the MDIO bit.
3039 */
3040 ctrl = E1000_READ_REG(hw, CTRL);
3041
3042 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3043 ctrl &= ~E1000_CTRL_MDIO_DIR;
3044 ctrl &= ~E1000_CTRL_MDIO;
3045
3046 E1000_WRITE_REG(hw, CTRL, ctrl);
3047 E1000_WRITE_FLUSH(hw);
3048
3049 /* Raise and Lower the clock before reading in the data. This accounts for
3050 * the turnaround bits. The first clock occurred when we clocked out the
3051 * last bit of the Register Address.
3052 */
3053 e1000_raise_mdi_clk(hw, &ctrl);
3054 e1000_lower_mdi_clk(hw, &ctrl);
3055
3056 for(data = 0, i = 0; i < 16; i++) {
3057 data = data << 1;
3058 e1000_raise_mdi_clk(hw, &ctrl);
3059 ctrl = E1000_READ_REG(hw, CTRL);
3060 /* Check to see if we shifted in a "1". */
3061 if(ctrl & E1000_CTRL_MDIO) data |= 1;
3062 e1000_lower_mdi_clk(hw, &ctrl);
3063 }
3064
3065 e1000_raise_mdi_clk(hw, &ctrl);
3066 e1000_lower_mdi_clk(hw, &ctrl);
3067
3068 return data;
3069 }
3070
3071 int32_t
3072 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3073 {
3074 uint32_t swfw_sync = 0;
3075 uint32_t swmask = mask;
3076 uint32_t fwmask = mask << 16;
3077 int32_t timeout = 200;
3078
3079 DEBUGFUNC("e1000_swfw_sync_acquire");
3080
3081 if (!hw->swfw_sync_present)
3082 return e1000_get_hw_eeprom_semaphore(hw);
3083
3084 while(timeout) {
3085 if (e1000_get_hw_eeprom_semaphore(hw))
3086 return -E1000_ERR_SWFW_SYNC;
3087
3088 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3089 if (!(swfw_sync & (fwmask | swmask))) {
3090 break;
3091 }
3092
3093 /* firmware currently using resource (fwmask) */
3094 /* or other software thread currently using resource (swmask) */
3095 e1000_put_hw_eeprom_semaphore(hw);
3096 msec_delay_irq(5);
3097 timeout--;
3098 }
3099
3100 if (!timeout) {
3101 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3102 return -E1000_ERR_SWFW_SYNC;
3103 }
3104
3105 swfw_sync |= swmask;
3106 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3107
3108 e1000_put_hw_eeprom_semaphore(hw);
3109 return E1000_SUCCESS;
3110 }
3111
3112 void
3113 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3114 {
3115 uint32_t swfw_sync;
3116 uint32_t swmask = mask;
3117
3118 DEBUGFUNC("e1000_swfw_sync_release");
3119
3120 if (!hw->swfw_sync_present) {
3121 e1000_put_hw_eeprom_semaphore(hw);
3122 return;
3123 }
3124
3125 /* if (e1000_get_hw_eeprom_semaphore(hw))
3126 * return -E1000_ERR_SWFW_SYNC; */
3127 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3128 /* empty */
3129
3130 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3131 swfw_sync &= ~swmask;
3132 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3133
3134 e1000_put_hw_eeprom_semaphore(hw);
3135 }
3136
3137 /*****************************************************************************
3138 * Reads the value from a PHY register, if the value is on a specific non zero
3139 * page, sets the page first.
3140 * hw - Struct containing variables accessed by shared code
3141 * reg_addr - address of the PHY register to read
3142 ******************************************************************************/
3143 int32_t
3144 e1000_read_phy_reg(struct e1000_hw *hw,
3145 uint32_t reg_addr,
3146 uint16_t *phy_data)
3147 {
3148 uint32_t ret_val;
3149 uint16_t swfw;
3150
3151 DEBUGFUNC("e1000_read_phy_reg");
3152
3153 if ((hw->mac_type == e1000_80003es2lan) &&
3154 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3155 swfw = E1000_SWFW_PHY1_SM;
3156 } else {
3157 swfw = E1000_SWFW_PHY0_SM;
3158 }
3159 if (e1000_swfw_sync_acquire(hw, swfw))
3160 return -E1000_ERR_SWFW_SYNC;
3161
3162 if((hw->phy_type == e1000_phy_igp ||
3163 hw->phy_type == e1000_phy_igp_2) &&
3164 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3165 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3166 (uint16_t)reg_addr);
3167 if(ret_val) {
3168 e1000_swfw_sync_release(hw, swfw);
3169 return ret_val;
3170 }
3171 } else if (hw->phy_type == e1000_phy_gg82563) {
3172 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3173 (hw->mac_type == e1000_80003es2lan)) {
3174 /* Select Configuration Page */
3175 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3176 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3177 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3178 } else {
3179 /* Use Alternative Page Select register to access
3180 * registers 30 and 31
3181 */
3182 ret_val = e1000_write_phy_reg_ex(hw,
3183 GG82563_PHY_PAGE_SELECT_ALT,
3184 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3185 }
3186
3187 if (ret_val) {
3188 e1000_swfw_sync_release(hw, swfw);
3189 return ret_val;
3190 }
3191 }
3192 }
3193
3194 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3195 phy_data);
3196
3197 e1000_swfw_sync_release(hw, swfw);
3198 return ret_val;
3199 }
3200
3201 int32_t
3202 e1000_read_phy_reg_ex(struct e1000_hw *hw,
3203 uint32_t reg_addr,
3204 uint16_t *phy_data)
3205 {
3206 uint32_t i;
3207 uint32_t mdic = 0;
3208 const uint32_t phy_addr = 1;
3209
3210 DEBUGFUNC("e1000_read_phy_reg_ex");
3211
3212 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3213 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3214 return -E1000_ERR_PARAM;
3215 }
3216
3217 if(hw->mac_type > e1000_82543) {
3218 /* Set up Op-code, Phy Address, and register address in the MDI
3219 * Control register. The MAC will take care of interfacing with the
3220 * PHY to retrieve the desired data.
3221 */
3222 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3223 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3224 (E1000_MDIC_OP_READ));
3225
3226 E1000_WRITE_REG(hw, MDIC, mdic);
3227
3228 /* Poll the ready bit to see if the MDI read completed */
3229 for(i = 0; i < 64; i++) {
3230 udelay(50);
3231 mdic = E1000_READ_REG(hw, MDIC);
3232 if(mdic & E1000_MDIC_READY) break;
3233 }
3234 if(!(mdic & E1000_MDIC_READY)) {
3235 DEBUGOUT("MDI Read did not complete\n");
3236 return -E1000_ERR_PHY;
3237 }
3238 if(mdic & E1000_MDIC_ERROR) {
3239 DEBUGOUT("MDI Error\n");
3240 return -E1000_ERR_PHY;
3241 }
3242 *phy_data = (uint16_t) mdic;
3243 } else {
3244 /* We must first send a preamble through the MDIO pin to signal the
3245 * beginning of an MII instruction. This is done by sending 32
3246 * consecutive "1" bits.
3247 */
3248 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3249
3250 /* Now combine the next few fields that are required for a read
3251 * operation. We use this method instead of calling the
3252 * e1000_shift_out_mdi_bits routine five different times. The format of
3253 * a MII read instruction consists of a shift out of 14 bits and is
3254 * defined as follows:
3255 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3256 * followed by a shift in of 18 bits. This first two bits shifted in
3257 * are TurnAround bits used to avoid contention on the MDIO pin when a
3258 * READ operation is performed. These two bits are thrown away
3259 * followed by a shift in of 16 bits which contains the desired data.
3260 */
3261 mdic = ((reg_addr) | (phy_addr << 5) |
3262 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3263
3264 e1000_shift_out_mdi_bits(hw, mdic, 14);
3265
3266 /* Now that we've shifted out the read command to the MII, we need to
3267 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3268 * register address.
3269 */
3270 *phy_data = e1000_shift_in_mdi_bits(hw);
3271 }
3272 return E1000_SUCCESS;
3273 }
3274
3275 /******************************************************************************
3276 * Writes a value to a PHY register
3277 *
3278 * hw - Struct containing variables accessed by shared code
3279 * reg_addr - address of the PHY register to write
3280 * data - data to write to the PHY
3281 ******************************************************************************/
3282 int32_t
3283 e1000_write_phy_reg(struct e1000_hw *hw,
3284 uint32_t reg_addr,
3285 uint16_t phy_data)
3286 {
3287 uint32_t ret_val;
3288 uint16_t swfw;
3289
3290 DEBUGFUNC("e1000_write_phy_reg");
3291
3292 if ((hw->mac_type == e1000_80003es2lan) &&
3293 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3294 swfw = E1000_SWFW_PHY1_SM;
3295 } else {
3296 swfw = E1000_SWFW_PHY0_SM;
3297 }
3298 if (e1000_swfw_sync_acquire(hw, swfw))
3299 return -E1000_ERR_SWFW_SYNC;
3300
3301 if((hw->phy_type == e1000_phy_igp ||
3302 hw->phy_type == e1000_phy_igp_2) &&
3303 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3304 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3305 (uint16_t)reg_addr);
3306 if(ret_val) {
3307 e1000_swfw_sync_release(hw, swfw);
3308 return ret_val;
3309 }
3310 } else if (hw->phy_type == e1000_phy_gg82563) {
3311 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3312 (hw->mac_type == e1000_80003es2lan)) {
3313 /* Select Configuration Page */
3314 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3315 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3316 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3317 } else {
3318 /* Use Alternative Page Select register to access
3319 * registers 30 and 31
3320 */
3321 ret_val = e1000_write_phy_reg_ex(hw,
3322 GG82563_PHY_PAGE_SELECT_ALT,
3323 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3324 }
3325
3326 if (ret_val) {
3327 e1000_swfw_sync_release(hw, swfw);
3328 return ret_val;
3329 }
3330 }
3331 }
3332
3333 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3334 phy_data);
3335
3336 e1000_swfw_sync_release(hw, swfw);
3337 return ret_val;
3338 }
3339
3340 int32_t
3341 e1000_write_phy_reg_ex(struct e1000_hw *hw,
3342 uint32_t reg_addr,
3343 uint16_t phy_data)
3344 {
3345 uint32_t i;
3346 uint32_t mdic = 0;
3347 const uint32_t phy_addr = 1;
3348
3349 DEBUGFUNC("e1000_write_phy_reg_ex");
3350
3351 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3352 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3353 return -E1000_ERR_PARAM;
3354 }
3355
3356 if(hw->mac_type > e1000_82543) {
3357 /* Set up Op-code, Phy Address, register address, and data intended
3358 * for the PHY register in the MDI Control register. The MAC will take
3359 * care of interfacing with the PHY to send the desired data.
3360 */
3361 mdic = (((uint32_t) phy_data) |
3362 (reg_addr << E1000_MDIC_REG_SHIFT) |
3363 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3364 (E1000_MDIC_OP_WRITE));
3365
3366 E1000_WRITE_REG(hw, MDIC, mdic);
3367
3368 /* Poll the ready bit to see if the MDI read completed */
3369 for(i = 0; i < 640; i++) {
3370 udelay(5);
3371 mdic = E1000_READ_REG(hw, MDIC);
3372 if(mdic & E1000_MDIC_READY) break;
3373 }
3374 if(!(mdic & E1000_MDIC_READY)) {
3375 DEBUGOUT("MDI Write did not complete\n");
3376 return -E1000_ERR_PHY;
3377 }
3378 } else {
3379 /* We'll need to use the SW defined pins to shift the write command
3380 * out to the PHY. We first send a preamble to the PHY to signal the
3381 * beginning of the MII instruction. This is done by sending 32
3382 * consecutive "1" bits.
3383 */
3384 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3385
3386 /* Now combine the remaining required fields that will indicate a
3387 * write operation. We use this method instead of calling the
3388 * e1000_shift_out_mdi_bits routine for each field in the command. The
3389 * format of a MII write instruction is as follows:
3390 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3391 */
3392 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3393 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3394 mdic <<= 16;
3395 mdic |= (uint32_t) phy_data;
3396
3397 e1000_shift_out_mdi_bits(hw, mdic, 32);
3398 }
3399
3400 return E1000_SUCCESS;
3401 }
3402
3403 int32_t
3404 e1000_read_kmrn_reg(struct e1000_hw *hw,
3405 uint32_t reg_addr,
3406 uint16_t *data)
3407 {
3408 uint32_t reg_val;
3409 uint16_t swfw;
3410 DEBUGFUNC("e1000_read_kmrn_reg");
3411
3412 if ((hw->mac_type == e1000_80003es2lan) &&
3413 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3414 swfw = E1000_SWFW_PHY1_SM;
3415 } else {
3416 swfw = E1000_SWFW_PHY0_SM;
3417 }
3418 if (e1000_swfw_sync_acquire(hw, swfw))
3419 return -E1000_ERR_SWFW_SYNC;
3420
3421 /* Write register address */
3422 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3423 E1000_KUMCTRLSTA_OFFSET) |
3424 E1000_KUMCTRLSTA_REN;
3425 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3426 udelay(2);
3427
3428 /* Read the data returned */
3429 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3430 *data = (uint16_t)reg_val;
3431
3432 e1000_swfw_sync_release(hw, swfw);
3433 return E1000_SUCCESS;
3434 }
3435
3436 int32_t
3437 e1000_write_kmrn_reg(struct e1000_hw *hw,
3438 uint32_t reg_addr,
3439 uint16_t data)
3440 {
3441 uint32_t reg_val;
3442 uint16_t swfw;
3443 DEBUGFUNC("e1000_write_kmrn_reg");
3444
3445 if ((hw->mac_type == e1000_80003es2lan) &&
3446 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3447 swfw = E1000_SWFW_PHY1_SM;
3448 } else {
3449 swfw = E1000_SWFW_PHY0_SM;
3450 }
3451 if (e1000_swfw_sync_acquire(hw, swfw))
3452 return -E1000_ERR_SWFW_SYNC;
3453
3454 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3455 E1000_KUMCTRLSTA_OFFSET) | data;
3456 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3457 udelay(2);
3458
3459 e1000_swfw_sync_release(hw, swfw);
3460 return E1000_SUCCESS;
3461 }
3462
3463 /******************************************************************************
3464 * Returns the PHY to the power-on reset state
3465 *
3466 * hw - Struct containing variables accessed by shared code
3467 ******************************************************************************/
3468 int32_t
3469 e1000_phy_hw_reset(struct e1000_hw *hw)
3470 {
3471 uint32_t ctrl, ctrl_ext;
3472 uint32_t led_ctrl;
3473 int32_t ret_val;
3474 uint16_t swfw;
3475
3476 DEBUGFUNC("e1000_phy_hw_reset");
3477
3478 /* In the case of the phy reset being blocked, it's not an error, we
3479 * simply return success without performing the reset. */
3480 ret_val = e1000_check_phy_reset_block(hw);
3481 if (ret_val)
3482 return E1000_SUCCESS;
3483
3484 DEBUGOUT("Resetting Phy...\n");
3485
3486 if(hw->mac_type > e1000_82543) {
3487 if ((hw->mac_type == e1000_80003es2lan) &&
3488 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3489 swfw = E1000_SWFW_PHY1_SM;
3490 } else {
3491 swfw = E1000_SWFW_PHY0_SM;
3492 }
3493 if (e1000_swfw_sync_acquire(hw, swfw)) {
3494 e1000_release_software_semaphore(hw);
3495 return -E1000_ERR_SWFW_SYNC;
3496 }
3497 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3498 * bit. Then, take it out of reset.
3499 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3500 * and deassert. For e1000_82571 hardware and later, we instead delay
3501 * for 10ms after the deassertion.
3502 */
3503 ctrl = E1000_READ_REG(hw, CTRL);
3504 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3505 E1000_WRITE_FLUSH(hw);
3506
3507 if (hw->mac_type < e1000_82571)
3508 msec_delay(10);
3509 else
3510 udelay(100);
3511
3512 E1000_WRITE_REG(hw, CTRL, ctrl);
3513 E1000_WRITE_FLUSH(hw);
3514
3515 if (hw->mac_type >= e1000_82571)
3516 msec_delay(10);
3517 e1000_swfw_sync_release(hw, swfw);
3518 } else {
3519 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3520 * bit to put the PHY into reset. Then, take it out of reset.
3521 */
3522 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3523 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3524 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3525 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3526 E1000_WRITE_FLUSH(hw);
3527 msec_delay(10);
3528 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3529 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3530 E1000_WRITE_FLUSH(hw);
3531 }
3532 udelay(150);
3533
3534 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3535 /* Configure activity LED after PHY reset */
3536 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3537 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3538 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3539 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3540 }
3541
3542 /* Wait for FW to finish PHY configuration. */
3543 ret_val = e1000_get_phy_cfg_done(hw);
3544 e1000_release_software_semaphore(hw);
3545
3546 return ret_val;
3547 }
3548
3549 /******************************************************************************
3550 * Resets the PHY
3551 *
3552 * hw - Struct containing variables accessed by shared code
3553 *
3554 * Sets bit 15 of the MII Control regiser
3555 ******************************************************************************/
3556 int32_t
3557 e1000_phy_reset(struct e1000_hw *hw)
3558 {
3559 int32_t ret_val;
3560 uint16_t phy_data;
3561
3562 DEBUGFUNC("e1000_phy_reset");
3563
3564 /* In the case of the phy reset being blocked, it's not an error, we
3565 * simply return success without performing the reset. */
3566 ret_val = e1000_check_phy_reset_block(hw);
3567 if (ret_val)
3568 return E1000_SUCCESS;
3569
3570 switch (hw->mac_type) {
3571 case e1000_82541_rev_2:
3572 case e1000_82571:
3573 case e1000_82572:
3574 ret_val = e1000_phy_hw_reset(hw);
3575 if(ret_val)
3576 return ret_val;
3577 break;
3578 default:
3579 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3580 if(ret_val)
3581 return ret_val;
3582
3583 phy_data |= MII_CR_RESET;
3584 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3585 if(ret_val)
3586 return ret_val;
3587
3588 udelay(1);
3589 break;
3590 }
3591
3592 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3593 e1000_phy_init_script(hw);
3594
3595 return E1000_SUCCESS;
3596 }
3597
3598 /******************************************************************************
3599 * Probes the expected PHY address for known PHY IDs
3600 *
3601 * hw - Struct containing variables accessed by shared code
3602 ******************************************************************************/
3603 static int32_t
3604 e1000_detect_gig_phy(struct e1000_hw *hw)
3605 {
3606 int32_t phy_init_status, ret_val;
3607 uint16_t phy_id_high, phy_id_low;
3608 boolean_t match = FALSE;
3609
3610 DEBUGFUNC("e1000_detect_gig_phy");
3611
3612 /* The 82571 firmware may still be configuring the PHY. In this
3613 * case, we cannot access the PHY until the configuration is done. So
3614 * we explicitly set the PHY values. */
3615 if(hw->mac_type == e1000_82571 ||
3616 hw->mac_type == e1000_82572) {
3617 hw->phy_id = IGP01E1000_I_PHY_ID;
3618 hw->phy_type = e1000_phy_igp_2;
3619 return E1000_SUCCESS;
3620 }
3621
3622 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
3623 * around that forces PHY page 0 to be set or the reads fail. The rest of
3624 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
3625 * So for ESB-2 we need to have this set so our reads won't fail. If the
3626 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
3627 * this out as well. */
3628 if (hw->mac_type == e1000_80003es2lan)
3629 hw->phy_type = e1000_phy_gg82563;
3630
3631 /* Read the PHY ID Registers to identify which PHY is onboard. */
3632 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3633 if(ret_val)
3634 return ret_val;
3635
3636 hw->phy_id = (uint32_t) (phy_id_high << 16);
3637 udelay(20);
3638 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3639 if(ret_val)
3640 return ret_val;
3641
3642 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3643 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3644
3645 switch(hw->mac_type) {
3646 case e1000_82543:
3647 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3648 break;
3649 case e1000_82544:
3650 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3651 break;
3652 case e1000_82540:
3653 case e1000_82545:
3654 case e1000_82545_rev_3:
3655 case e1000_82546:
3656 case e1000_82546_rev_3:
3657 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3658 break;
3659 case e1000_82541:
3660 case e1000_82541_rev_2:
3661 case e1000_82547:
3662 case e1000_82547_rev_2:
3663 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3664 break;
3665 case e1000_82573:
3666 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3667 break;
3668 case e1000_80003es2lan:
3669 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3670 break;
3671 default:
3672 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3673 return -E1000_ERR_CONFIG;
3674 }
3675 phy_init_status = e1000_set_phy_type(hw);
3676
3677 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3678 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3679 return E1000_SUCCESS;
3680 }
3681 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3682 return -E1000_ERR_PHY;
3683 }
3684
3685 /******************************************************************************
3686 * Resets the PHY's DSP
3687 *
3688 * hw - Struct containing variables accessed by shared code
3689 ******************************************************************************/
3690 static int32_t
3691 e1000_phy_reset_dsp(struct e1000_hw *hw)
3692 {
3693 int32_t ret_val;
3694 DEBUGFUNC("e1000_phy_reset_dsp");
3695
3696 do {
3697 if (hw->phy_type != e1000_phy_gg82563) {
3698 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3699 if(ret_val) break;
3700 }
3701 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3702 if(ret_val) break;
3703 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3704 if(ret_val) break;
3705 ret_val = E1000_SUCCESS;
3706 } while(0);
3707
3708 return ret_val;
3709 }
3710
3711 /******************************************************************************
3712 * Get PHY information from various PHY registers for igp PHY only.
3713 *
3714 * hw - Struct containing variables accessed by shared code
3715 * phy_info - PHY information structure
3716 ******************************************************************************/
3717 static int32_t
3718 e1000_phy_igp_get_info(struct e1000_hw *hw,
3719 struct e1000_phy_info *phy_info)
3720 {
3721 int32_t ret_val;
3722 uint16_t phy_data, polarity, min_length, max_length, average;
3723
3724 DEBUGFUNC("e1000_phy_igp_get_info");
3725
3726 /* The downshift status is checked only once, after link is established,
3727 * and it stored in the hw->speed_downgraded parameter. */
3728 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3729
3730 /* IGP01E1000 does not need to support it. */
3731 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3732
3733 /* IGP01E1000 always correct polarity reversal */
3734 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3735
3736 /* Check polarity status */
3737 ret_val = e1000_check_polarity(hw, &polarity);
3738 if(ret_val)
3739 return ret_val;
3740
3741 phy_info->cable_polarity = polarity;
3742
3743 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3744 if(ret_val)
3745 return ret_val;
3746
3747 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
3748 IGP01E1000_PSSR_MDIX_SHIFT;
3749
3750 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3751 IGP01E1000_PSSR_SPEED_1000MBPS) {
3752 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3753 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3754 if(ret_val)
3755 return ret_val;
3756
3757 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3758 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3759 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3760 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3761
3762 /* Get cable length */
3763 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3764 if(ret_val)
3765 return ret_val;
3766
3767 /* Translate to old method */
3768 average = (max_length + min_length) / 2;
3769
3770 if(average <= e1000_igp_cable_length_50)
3771 phy_info->cable_length = e1000_cable_length_50;
3772 else if(average <= e1000_igp_cable_length_80)
3773 phy_info->cable_length = e1000_cable_length_50_80;
3774 else if(average <= e1000_igp_cable_length_110)
3775 phy_info->cable_length = e1000_cable_length_80_110;
3776 else if(average <= e1000_igp_cable_length_140)
3777 phy_info->cable_length = e1000_cable_length_110_140;
3778 else
3779 phy_info->cable_length = e1000_cable_length_140;
3780 }
3781
3782 return E1000_SUCCESS;
3783 }
3784
3785 /******************************************************************************
3786 * Get PHY information from various PHY registers fot m88 PHY only.
3787 *
3788 * hw - Struct containing variables accessed by shared code
3789 * phy_info - PHY information structure
3790 ******************************************************************************/
3791 static int32_t
3792 e1000_phy_m88_get_info(struct e1000_hw *hw,
3793 struct e1000_phy_info *phy_info)
3794 {
3795 int32_t ret_val;
3796 uint16_t phy_data, polarity;
3797
3798 DEBUGFUNC("e1000_phy_m88_get_info");
3799
3800 /* The downshift status is checked only once, after link is established,
3801 * and it stored in the hw->speed_downgraded parameter. */
3802 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3803
3804 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3805 if(ret_val)
3806 return ret_val;
3807
3808 phy_info->extended_10bt_distance =
3809 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3810 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
3811 phy_info->polarity_correction =
3812 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3813 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
3814
3815 /* Check polarity status */
3816 ret_val = e1000_check_polarity(hw, &polarity);
3817 if(ret_val)
3818 return ret_val;
3819 phy_info->cable_polarity = polarity;
3820
3821 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3822 if(ret_val)
3823 return ret_val;
3824
3825 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
3826 M88E1000_PSSR_MDIX_SHIFT;
3827
3828 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3829 /* Cable Length Estimation and Local/Remote Receiver Information
3830 * are only valid at 1000 Mbps.
3831 */
3832 if (hw->phy_type != e1000_phy_gg82563) {
3833 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
3834 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3835 } else {
3836 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
3837 &phy_data);
3838 if (ret_val)
3839 return ret_val;
3840
3841 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
3842 }
3843
3844 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3845 if(ret_val)
3846 return ret_val;
3847
3848 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3849 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3850
3851 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3852 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3853 }
3854
3855 return E1000_SUCCESS;
3856 }
3857
3858 /******************************************************************************
3859 * Get PHY information from various PHY registers
3860 *
3861 * hw - Struct containing variables accessed by shared code
3862 * phy_info - PHY information structure
3863 ******************************************************************************/
3864 int32_t
3865 e1000_phy_get_info(struct e1000_hw *hw,
3866 struct e1000_phy_info *phy_info)
3867 {
3868 int32_t ret_val;
3869 uint16_t phy_data;
3870
3871 DEBUGFUNC("e1000_phy_get_info");
3872
3873 phy_info->cable_length = e1000_cable_length_undefined;
3874 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3875 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3876 phy_info->downshift = e1000_downshift_undefined;
3877 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3878 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3879 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3880 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3881
3882 if(hw->media_type != e1000_media_type_copper) {
3883 DEBUGOUT("PHY info is only valid for copper media\n");
3884 return -E1000_ERR_CONFIG;
3885 }
3886
3887 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3888 if(ret_val)
3889 return ret_val;
3890
3891 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3892 if(ret_val)
3893 return ret_val;
3894
3895 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3896 DEBUGOUT("PHY info is only valid if link is up\n");
3897 return -E1000_ERR_CONFIG;
3898 }
3899
3900 if(hw->phy_type == e1000_phy_igp ||
3901 hw->phy_type == e1000_phy_igp_2)
3902 return e1000_phy_igp_get_info(hw, phy_info);
3903 else
3904 return e1000_phy_m88_get_info(hw, phy_info);
3905 }
3906
3907 int32_t
3908 e1000_validate_mdi_setting(struct e1000_hw *hw)
3909 {
3910 DEBUGFUNC("e1000_validate_mdi_settings");
3911
3912 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3913 DEBUGOUT("Invalid MDI setting detected\n");
3914 hw->mdix = 1;
3915 return -E1000_ERR_CONFIG;
3916 }
3917 return E1000_SUCCESS;
3918 }
3919
3920
3921 /******************************************************************************
3922 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3923 * is configured.
3924 *
3925 * hw - Struct containing variables accessed by shared code
3926 *****************************************************************************/
3927 int32_t
3928 e1000_init_eeprom_params(struct e1000_hw *hw)
3929 {
3930 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3931 uint32_t eecd = E1000_READ_REG(hw, EECD);
3932 int32_t ret_val = E1000_SUCCESS;
3933 uint16_t eeprom_size;
3934
3935 DEBUGFUNC("e1000_init_eeprom_params");
3936
3937 switch (hw->mac_type) {
3938 case e1000_82542_rev2_0:
3939 case e1000_82542_rev2_1:
3940 case e1000_82543:
3941 case e1000_82544:
3942 eeprom->type = e1000_eeprom_microwire;
3943 eeprom->word_size = 64;
3944 eeprom->opcode_bits = 3;
3945 eeprom->address_bits = 6;
3946 eeprom->delay_usec = 50;
3947 eeprom->use_eerd = FALSE;
3948 eeprom->use_eewr = FALSE;
3949 break;
3950 case e1000_82540:
3951 case e1000_82545:
3952 case e1000_82545_rev_3:
3953 case e1000_82546:
3954 case e1000_82546_rev_3:
3955 eeprom->type = e1000_eeprom_microwire;
3956 eeprom->opcode_bits = 3;
3957 eeprom->delay_usec = 50;
3958 if(eecd & E1000_EECD_SIZE) {
3959 eeprom->word_size = 256;
3960 eeprom->address_bits = 8;
3961 } else {
3962 eeprom->word_size = 64;
3963 eeprom->address_bits = 6;
3964 }
3965 eeprom->use_eerd = FALSE;
3966 eeprom->use_eewr = FALSE;
3967 break;
3968 case e1000_82541:
3969 case e1000_82541_rev_2:
3970 case e1000_82547:
3971 case e1000_82547_rev_2:
3972 if (eecd & E1000_EECD_TYPE) {
3973 eeprom->type = e1000_eeprom_spi;
3974 eeprom->opcode_bits = 8;
3975 eeprom->delay_usec = 1;
3976 if (eecd & E1000_EECD_ADDR_BITS) {
3977 eeprom->page_size = 32;
3978 eeprom->address_bits = 16;
3979 } else {
3980 eeprom->page_size = 8;
3981 eeprom->address_bits = 8;
3982 }
3983 } else {
3984 eeprom->type = e1000_eeprom_microwire;
3985 eeprom->opcode_bits = 3;
3986 eeprom->delay_usec = 50;
3987 if (eecd & E1000_EECD_ADDR_BITS) {
3988 eeprom->word_size = 256;
3989 eeprom->address_bits = 8;
3990 } else {
3991 eeprom->word_size = 64;
3992 eeprom->address_bits = 6;
3993 }
3994 }
3995 eeprom->use_eerd = FALSE;
3996 eeprom->use_eewr = FALSE;
3997 break;
3998 case e1000_82571:
3999 case e1000_82572:
4000 eeprom->type = e1000_eeprom_spi;
4001 eeprom->opcode_bits = 8;
4002 eeprom->delay_usec = 1;
4003 if (eecd & E1000_EECD_ADDR_BITS) {
4004 eeprom->page_size = 32;
4005 eeprom->address_bits = 16;
4006 } else {
4007 eeprom->page_size = 8;
4008 eeprom->address_bits = 8;
4009 }
4010 eeprom->use_eerd = FALSE;
4011 eeprom->use_eewr = FALSE;
4012 break;
4013 case e1000_82573:
4014 eeprom->type = e1000_eeprom_spi;
4015 eeprom->opcode_bits = 8;
4016 eeprom->delay_usec = 1;
4017 if (eecd & E1000_EECD_ADDR_BITS) {
4018 eeprom->page_size = 32;
4019 eeprom->address_bits = 16;
4020 } else {
4021 eeprom->page_size = 8;
4022 eeprom->address_bits = 8;
4023 }
4024 eeprom->use_eerd = TRUE;
4025 eeprom->use_eewr = TRUE;
4026 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4027 eeprom->type = e1000_eeprom_flash;
4028 eeprom->word_size = 2048;
4029
4030 /* Ensure that the Autonomous FLASH update bit is cleared due to
4031 * Flash update issue on parts which use a FLASH for NVM. */
4032 eecd &= ~E1000_EECD_AUPDEN;
4033 E1000_WRITE_REG(hw, EECD, eecd);
4034 }
4035 break;
4036 case e1000_80003es2lan:
4037 eeprom->type = e1000_eeprom_spi;
4038 eeprom->opcode_bits = 8;
4039 eeprom->delay_usec = 1;
4040 if (eecd & E1000_EECD_ADDR_BITS) {
4041 eeprom->page_size = 32;
4042 eeprom->address_bits = 16;
4043 } else {
4044 eeprom->page_size = 8;
4045 eeprom->address_bits = 8;
4046 }
4047 eeprom->use_eerd = TRUE;
4048 eeprom->use_eewr = FALSE;
4049 break;
4050 default:
4051 break;
4052 }
4053
4054 if (eeprom->type == e1000_eeprom_spi) {
4055 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4056 * 32KB (incremented by powers of 2).
4057 */
4058 if(hw->mac_type <= e1000_82547_rev_2) {
4059 /* Set to default value for initial eeprom read. */
4060 eeprom->word_size = 64;
4061 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4062 if(ret_val)
4063 return ret_val;
4064 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4065 /* 256B eeprom size was not supported in earlier hardware, so we
4066 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4067 * is never the result used in the shifting logic below. */
4068 if(eeprom_size)
4069 eeprom_size++;
4070 } else {
4071 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4072 E1000_EECD_SIZE_EX_SHIFT);
4073 }
4074
4075 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4076 }
4077 return ret_val;
4078 }
4079
4080 /******************************************************************************
4081 * Raises the EEPROM's clock input.
4082 *
4083 * hw - Struct containing variables accessed by shared code
4084 * eecd - EECD's current value
4085 *****************************************************************************/
4086 static void
4087 e1000_raise_ee_clk(struct e1000_hw *hw,
4088 uint32_t *eecd)
4089 {
4090 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4091 * wait <delay> microseconds.
4092 */
4093 *eecd = *eecd | E1000_EECD_SK;
4094 E1000_WRITE_REG(hw, EECD, *eecd);
4095 E1000_WRITE_FLUSH(hw);
4096 udelay(hw->eeprom.delay_usec);
4097 }
4098
4099 /******************************************************************************
4100 * Lowers the EEPROM's clock input.
4101 *
4102 * hw - Struct containing variables accessed by shared code
4103 * eecd - EECD's current value
4104 *****************************************************************************/
4105 static void
4106 e1000_lower_ee_clk(struct e1000_hw *hw,
4107 uint32_t *eecd)
4108 {
4109 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4110 * wait 50 microseconds.
4111 */
4112 *eecd = *eecd & ~E1000_EECD_SK;
4113 E1000_WRITE_REG(hw, EECD, *eecd);
4114 E1000_WRITE_FLUSH(hw);
4115 udelay(hw->eeprom.delay_usec);
4116 }
4117
4118 /******************************************************************************
4119 * Shift data bits out to the EEPROM.
4120 *
4121 * hw - Struct containing variables accessed by shared code
4122 * data - data to send to the EEPROM
4123 * count - number of bits to shift out
4124 *****************************************************************************/
4125 static void
4126 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4127 uint16_t data,
4128 uint16_t count)
4129 {
4130 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4131 uint32_t eecd;
4132 uint32_t mask;
4133
4134 /* We need to shift "count" bits out to the EEPROM. So, value in the
4135 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4136 * In order to do this, "data" must be broken down into bits.
4137 */
4138 mask = 0x01 << (count - 1);
4139 eecd = E1000_READ_REG(hw, EECD);
4140 if (eeprom->type == e1000_eeprom_microwire) {
4141 eecd &= ~E1000_EECD_DO;
4142 } else if (eeprom->type == e1000_eeprom_spi) {
4143 eecd |= E1000_EECD_DO;
4144 }
4145 do {
4146 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4147 * and then raising and then lowering the clock (the SK bit controls
4148 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4149 * by setting "DI" to "0" and then raising and then lowering the clock.
4150 */
4151 eecd &= ~E1000_EECD_DI;
4152
4153 if(data & mask)
4154 eecd |= E1000_EECD_DI;
4155
4156 E1000_WRITE_REG(hw, EECD, eecd);
4157 E1000_WRITE_FLUSH(hw);
4158
4159 udelay(eeprom->delay_usec);
4160
4161 e1000_raise_ee_clk(hw, &eecd);
4162 e1000_lower_ee_clk(hw, &eecd);
4163
4164 mask = mask >> 1;
4165
4166 } while(mask);
4167
4168 /* We leave the "DI" bit set to "0" when we leave this routine. */
4169 eecd &= ~E1000_EECD_DI;
4170 E1000_WRITE_REG(hw, EECD, eecd);
4171 }
4172
4173 /******************************************************************************
4174 * Shift data bits in from the EEPROM
4175 *
4176 * hw - Struct containing variables accessed by shared code
4177 *****************************************************************************/
4178 static uint16_t
4179 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4180 uint16_t count)
4181 {
4182 uint32_t eecd;
4183 uint32_t i;
4184 uint16_t data;
4185
4186 /* In order to read a register from the EEPROM, we need to shift 'count'
4187 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4188 * input to the EEPROM (setting the SK bit), and then reading the value of
4189 * the "DO" bit. During this "shifting in" process the "DI" bit should
4190 * always be clear.
4191 */
4192
4193 eecd = E1000_READ_REG(hw, EECD);
4194
4195 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4196 data = 0;
4197
4198 for(i = 0; i < count; i++) {
4199 data = data << 1;
4200 e1000_raise_ee_clk(hw, &eecd);
4201
4202 eecd = E1000_READ_REG(hw, EECD);
4203
4204 eecd &= ~(E1000_EECD_DI);
4205 if(eecd & E1000_EECD_DO)
4206 data |= 1;
4207
4208 e1000_lower_ee_clk(hw, &eecd);
4209 }
4210
4211 return data;
4212 }
4213
4214 /******************************************************************************
4215 * Prepares EEPROM for access
4216 *
4217 * hw - Struct containing variables accessed by shared code
4218 *
4219 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4220 * function should be called before issuing a command to the EEPROM.
4221 *****************************************************************************/
4222 static int32_t
4223 e1000_acquire_eeprom(struct e1000_hw *hw)
4224 {
4225 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4226 uint32_t eecd, i=0;
4227
4228 DEBUGFUNC("e1000_acquire_eeprom");
4229
4230 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4231 return -E1000_ERR_SWFW_SYNC;
4232 eecd = E1000_READ_REG(hw, EECD);
4233
4234 if (hw->mac_type != e1000_82573) {
4235 /* Request EEPROM Access */
4236 if(hw->mac_type > e1000_82544) {
4237 eecd |= E1000_EECD_REQ;
4238 E1000_WRITE_REG(hw, EECD, eecd);
4239 eecd = E1000_READ_REG(hw, EECD);
4240 while((!(eecd & E1000_EECD_GNT)) &&
4241 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4242 i++;
4243 udelay(5);
4244 eecd = E1000_READ_REG(hw, EECD);
4245 }
4246 if(!(eecd & E1000_EECD_GNT)) {
4247 eecd &= ~E1000_EECD_REQ;
4248 E1000_WRITE_REG(hw, EECD, eecd);
4249 DEBUGOUT("Could not acquire EEPROM grant\n");
4250 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4251 return -E1000_ERR_EEPROM;
4252 }
4253 }
4254 }
4255
4256 /* Setup EEPROM for Read/Write */
4257
4258 if (eeprom->type == e1000_eeprom_microwire) {
4259 /* Clear SK and DI */
4260 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4261 E1000_WRITE_REG(hw, EECD, eecd);
4262
4263 /* Set CS */
4264 eecd |= E1000_EECD_CS;
4265 E1000_WRITE_REG(hw, EECD, eecd);
4266 } else if (eeprom->type == e1000_eeprom_spi) {
4267 /* Clear SK and CS */
4268 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4269 E1000_WRITE_REG(hw, EECD, eecd);
4270 udelay(1);
4271 }
4272
4273 return E1000_SUCCESS;
4274 }
4275
4276 /******************************************************************************
4277 * Returns EEPROM to a "standby" state
4278 *
4279 * hw - Struct containing variables accessed by shared code
4280 *****************************************************************************/
4281 static void
4282 e1000_standby_eeprom(struct e1000_hw *hw)
4283 {
4284 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4285 uint32_t eecd;
4286
4287 eecd = E1000_READ_REG(hw, EECD);
4288
4289 if(eeprom->type == e1000_eeprom_microwire) {
4290 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4291 E1000_WRITE_REG(hw, EECD, eecd);
4292 E1000_WRITE_FLUSH(hw);
4293 udelay(eeprom->delay_usec);
4294
4295 /* Clock high */
4296 eecd |= E1000_EECD_SK;
4297 E1000_WRITE_REG(hw, EECD, eecd);
4298 E1000_WRITE_FLUSH(hw);
4299 udelay(eeprom->delay_usec);
4300
4301 /* Select EEPROM */
4302 eecd |= E1000_EECD_CS;
4303 E1000_WRITE_REG(hw, EECD, eecd);
4304 E1000_WRITE_FLUSH(hw);
4305 udelay(eeprom->delay_usec);
4306
4307 /* Clock low */
4308 eecd &= ~E1000_EECD_SK;
4309 E1000_WRITE_REG(hw, EECD, eecd);
4310 E1000_WRITE_FLUSH(hw);
4311 udelay(eeprom->delay_usec);
4312 } else if(eeprom->type == e1000_eeprom_spi) {
4313 /* Toggle CS to flush commands */
4314 eecd |= E1000_EECD_CS;
4315 E1000_WRITE_REG(hw, EECD, eecd);
4316 E1000_WRITE_FLUSH(hw);
4317 udelay(eeprom->delay_usec);
4318 eecd &= ~E1000_EECD_CS;
4319 E1000_WRITE_REG(hw, EECD, eecd);
4320 E1000_WRITE_FLUSH(hw);
4321 udelay(eeprom->delay_usec);
4322 }
4323 }
4324
4325 /******************************************************************************
4326 * Terminates a command by inverting the EEPROM's chip select pin
4327 *
4328 * hw - Struct containing variables accessed by shared code
4329 *****************************************************************************/
4330 static void
4331 e1000_release_eeprom(struct e1000_hw *hw)
4332 {
4333 uint32_t eecd;
4334
4335 DEBUGFUNC("e1000_release_eeprom");
4336
4337 eecd = E1000_READ_REG(hw, EECD);
4338
4339 if (hw->eeprom.type == e1000_eeprom_spi) {
4340 eecd |= E1000_EECD_CS; /* Pull CS high */
4341 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4342
4343 E1000_WRITE_REG(hw, EECD, eecd);
4344
4345 udelay(hw->eeprom.delay_usec);
4346 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
4347 /* cleanup eeprom */
4348
4349 /* CS on Microwire is active-high */
4350 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4351
4352 E1000_WRITE_REG(hw, EECD, eecd);
4353
4354 /* Rising edge of clock */
4355 eecd |= E1000_EECD_SK;
4356 E1000_WRITE_REG(hw, EECD, eecd);
4357 E1000_WRITE_FLUSH(hw);
4358 udelay(hw->eeprom.delay_usec);
4359
4360 /* Falling edge of clock */
4361 eecd &= ~E1000_EECD_SK;
4362 E1000_WRITE_REG(hw, EECD, eecd);
4363 E1000_WRITE_FLUSH(hw);
4364 udelay(hw->eeprom.delay_usec);
4365 }
4366
4367 /* Stop requesting EEPROM access */
4368 if(hw->mac_type > e1000_82544) {
4369 eecd &= ~E1000_EECD_REQ;
4370 E1000_WRITE_REG(hw, EECD, eecd);
4371 }
4372
4373 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4374 }
4375
4376 /******************************************************************************
4377 * Reads a 16 bit word from the EEPROM.
4378 *
4379 * hw - Struct containing variables accessed by shared code
4380 *****************************************************************************/
4381 int32_t
4382 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4383 {
4384 uint16_t retry_count = 0;
4385 uint8_t spi_stat_reg;
4386
4387 DEBUGFUNC("e1000_spi_eeprom_ready");
4388
4389 /* Read "Status Register" repeatedly until the LSB is cleared. The
4390 * EEPROM will signal that the command has been completed by clearing
4391 * bit 0 of the internal status register. If it's not cleared within
4392 * 5 milliseconds, then error out.
4393 */
4394 retry_count = 0;
4395 do {
4396 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4397 hw->eeprom.opcode_bits);
4398 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4399 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4400 break;
4401
4402 udelay(5);
4403 retry_count += 5;
4404
4405 e1000_standby_eeprom(hw);
4406 } while(retry_count < EEPROM_MAX_RETRY_SPI);
4407
4408 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4409 * only 0-5mSec on 5V devices)
4410 */
4411 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
4412 DEBUGOUT("SPI EEPROM Status error\n");
4413 return -E1000_ERR_EEPROM;
4414 }
4415
4416 return E1000_SUCCESS;
4417 }
4418
4419 /******************************************************************************
4420 * Reads a 16 bit word from the EEPROM.
4421 *
4422 * hw - Struct containing variables accessed by shared code
4423 * offset - offset of word in the EEPROM to read
4424 * data - word read from the EEPROM
4425 * words - number of words to read
4426 *****************************************************************************/
4427 int32_t
4428 e1000_read_eeprom(struct e1000_hw *hw,
4429 uint16_t offset,
4430 uint16_t words,
4431 uint16_t *data)
4432 {
4433 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4434 uint32_t i = 0;
4435 int32_t ret_val;
4436
4437 DEBUGFUNC("e1000_read_eeprom");
4438
4439 /* A check for invalid values: offset too large, too many words, and not
4440 * enough words.
4441 */
4442 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4443 (words == 0)) {
4444 DEBUGOUT("\"words\" parameter out of bounds\n");
4445 return -E1000_ERR_EEPROM;
4446 }
4447
4448 /* FLASH reads without acquiring the semaphore are safe */
4449 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4450 hw->eeprom.use_eerd == FALSE) {
4451 switch (hw->mac_type) {
4452 case e1000_80003es2lan:
4453 break;
4454 default:
4455 /* Prepare the EEPROM for reading */
4456 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4457 return -E1000_ERR_EEPROM;
4458 break;
4459 }
4460 }
4461
4462 if (eeprom->use_eerd == TRUE) {
4463 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4464 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4465 (hw->mac_type != e1000_82573))
4466 e1000_release_eeprom(hw);
4467 return ret_val;
4468 }
4469
4470 if(eeprom->type == e1000_eeprom_spi) {
4471 uint16_t word_in;
4472 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4473
4474 if(e1000_spi_eeprom_ready(hw)) {
4475 e1000_release_eeprom(hw);
4476 return -E1000_ERR_EEPROM;
4477 }
4478
4479 e1000_standby_eeprom(hw);
4480
4481 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4482 if((eeprom->address_bits == 8) && (offset >= 128))
4483 read_opcode |= EEPROM_A8_OPCODE_SPI;
4484
4485 /* Send the READ command (opcode + addr) */
4486 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4487 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
4488
4489 /* Read the data. The address of the eeprom internally increments with
4490 * each byte (spi) being read, saving on the overhead of eeprom setup
4491 * and tear-down. The address counter will roll over if reading beyond
4492 * the size of the eeprom, thus allowing the entire memory to be read
4493 * starting from any offset. */
4494 for (i = 0; i < words; i++) {
4495 word_in = e1000_shift_in_ee_bits(hw, 16);
4496 data[i] = (word_in >> 8) | (word_in << 8);
4497 }
4498 } else if(eeprom->type == e1000_eeprom_microwire) {
4499 for (i = 0; i < words; i++) {
4500 /* Send the READ command (opcode + addr) */
4501 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4502 eeprom->opcode_bits);
4503 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
4504 eeprom->address_bits);
4505
4506 /* Read the data. For microwire, each word requires the overhead
4507 * of eeprom setup and tear-down. */
4508 data[i] = e1000_shift_in_ee_bits(hw, 16);
4509 e1000_standby_eeprom(hw);
4510 }
4511 }
4512
4513 /* End this read operation */
4514 e1000_release_eeprom(hw);
4515
4516 return E1000_SUCCESS;
4517 }
4518
4519 /******************************************************************************
4520 * Reads a 16 bit word from the EEPROM using the EERD register.
4521 *
4522 * hw - Struct containing variables accessed by shared code
4523 * offset - offset of word in the EEPROM to read
4524 * data - word read from the EEPROM
4525 * words - number of words to read
4526 *****************************************************************************/
4527 static int32_t
4528 e1000_read_eeprom_eerd(struct e1000_hw *hw,
4529 uint16_t offset,
4530 uint16_t words,
4531 uint16_t *data)
4532 {
4533 uint32_t i, eerd = 0;
4534 int32_t error = 0;
4535
4536 for (i = 0; i < words; i++) {
4537 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4538 E1000_EEPROM_RW_REG_START;
4539
4540 E1000_WRITE_REG(hw, EERD, eerd);
4541 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4542
4543 if(error) {
4544 break;
4545 }
4546 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
4547
4548 }
4549
4550 return error;
4551 }
4552
4553 /******************************************************************************
4554 * Writes a 16 bit word from the EEPROM using the EEWR register.
4555 *
4556 * hw - Struct containing variables accessed by shared code
4557 * offset - offset of word in the EEPROM to read
4558 * data - word read from the EEPROM
4559 * words - number of words to read
4560 *****************************************************************************/
4561 static int32_t
4562 e1000_write_eeprom_eewr(struct e1000_hw *hw,
4563 uint16_t offset,
4564 uint16_t words,
4565 uint16_t *data)
4566 {
4567 uint32_t register_value = 0;
4568 uint32_t i = 0;
4569 int32_t error = 0;
4570
4571 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4572 return -E1000_ERR_SWFW_SYNC;
4573
4574 for (i = 0; i < words; i++) {
4575 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
4576 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
4577 E1000_EEPROM_RW_REG_START;
4578
4579 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4580 if(error) {
4581 break;
4582 }
4583
4584 E1000_WRITE_REG(hw, EEWR, register_value);
4585
4586 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4587
4588 if(error) {
4589 break;
4590 }
4591 }
4592
4593 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4594 return error;
4595 }
4596
4597 /******************************************************************************
4598 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4599 *
4600 * hw - Struct containing variables accessed by shared code
4601 *****************************************************************************/
4602 static int32_t
4603 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
4604 {
4605 uint32_t attempts = 100000;
4606 uint32_t i, reg = 0;
4607 int32_t done = E1000_ERR_EEPROM;
4608
4609 for(i = 0; i < attempts; i++) {
4610 if(eerd == E1000_EEPROM_POLL_READ)
4611 reg = E1000_READ_REG(hw, EERD);
4612 else
4613 reg = E1000_READ_REG(hw, EEWR);
4614
4615 if(reg & E1000_EEPROM_RW_REG_DONE) {
4616 done = E1000_SUCCESS;
4617 break;
4618 }
4619 udelay(5);
4620 }
4621
4622 return done;
4623 }
4624
4625 /***************************************************************************
4626 * Description: Determines if the onboard NVM is FLASH or EEPROM.
4627 *
4628 * hw - Struct containing variables accessed by shared code
4629 ****************************************************************************/
4630 static boolean_t
4631 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4632 {
4633 uint32_t eecd = 0;
4634
4635 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
4636
4637 if(hw->mac_type == e1000_82573) {
4638 eecd = E1000_READ_REG(hw, EECD);
4639
4640 /* Isolate bits 15 & 16 */
4641 eecd = ((eecd >> 15) & 0x03);
4642
4643 /* If both bits are set, device is Flash type */
4644 if(eecd == 0x03) {
4645 return FALSE;
4646 }
4647 }
4648 return TRUE;
4649 }
4650
4651 /******************************************************************************
4652 * Verifies that the EEPROM has a valid checksum
4653 *
4654 * hw - Struct containing variables accessed by shared code
4655 *
4656 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4657 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4658 * valid.
4659 *****************************************************************************/
4660 int32_t
4661 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4662 {
4663 uint16_t checksum = 0;
4664 uint16_t i, eeprom_data;
4665
4666 DEBUGFUNC("e1000_validate_eeprom_checksum");
4667
4668 if ((hw->mac_type == e1000_82573) &&
4669 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
4670 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
4671 * 10h-12h. Checksum may need to be fixed. */
4672 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
4673 if ((eeprom_data & 0x10) == 0) {
4674 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
4675 * has already been fixed. If the checksum is still wrong and this
4676 * bit is a 1, we need to return bad checksum. Otherwise, we need
4677 * to set this bit to a 1 and update the checksum. */
4678 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
4679 if ((eeprom_data & 0x8000) == 0) {
4680 eeprom_data |= 0x8000;
4681 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
4682 e1000_update_eeprom_checksum(hw);
4683 }
4684 }
4685 }
4686
4687 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4688 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4689 DEBUGOUT("EEPROM Read Error\n");
4690 return -E1000_ERR_EEPROM;
4691 }
4692 checksum += eeprom_data;
4693 }
4694
4695 if(checksum == (uint16_t) EEPROM_SUM)
4696 return E1000_SUCCESS;
4697 else {
4698 DEBUGOUT("EEPROM Checksum Invalid\n");
4699 return -E1000_ERR_EEPROM;
4700 }
4701 }
4702
4703 /******************************************************************************
4704 * Calculates the EEPROM checksum and writes it to the EEPROM
4705 *
4706 * hw - Struct containing variables accessed by shared code
4707 *
4708 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4709 * Writes the difference to word offset 63 of the EEPROM.
4710 *****************************************************************************/
4711 int32_t
4712 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4713 {
4714 uint16_t checksum = 0;
4715 uint16_t i, eeprom_data;
4716
4717 DEBUGFUNC("e1000_update_eeprom_checksum");
4718
4719 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4720 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4721 DEBUGOUT("EEPROM Read Error\n");
4722 return -E1000_ERR_EEPROM;
4723 }
4724 checksum += eeprom_data;
4725 }
4726 checksum = (uint16_t) EEPROM_SUM - checksum;
4727 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4728 DEBUGOUT("EEPROM Write Error\n");
4729 return -E1000_ERR_EEPROM;
4730 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4731 e1000_commit_shadow_ram(hw);
4732 }
4733 return E1000_SUCCESS;
4734 }
4735
4736 /******************************************************************************
4737 * Parent function for writing words to the different EEPROM types.
4738 *
4739 * hw - Struct containing variables accessed by shared code
4740 * offset - offset within the EEPROM to be written to
4741 * words - number of words to write
4742 * data - 16 bit word to be written to the EEPROM
4743 *
4744 * If e1000_update_eeprom_checksum is not called after this function, the
4745 * EEPROM will most likely contain an invalid checksum.
4746 *****************************************************************************/
4747 int32_t
4748 e1000_write_eeprom(struct e1000_hw *hw,
4749 uint16_t offset,
4750 uint16_t words,
4751 uint16_t *data)
4752 {
4753 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4754 int32_t status = 0;
4755
4756 DEBUGFUNC("e1000_write_eeprom");
4757
4758 /* A check for invalid values: offset too large, too many words, and not
4759 * enough words.
4760 */
4761 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4762 (words == 0)) {
4763 DEBUGOUT("\"words\" parameter out of bounds\n");
4764 return -E1000_ERR_EEPROM;
4765 }
4766
4767 /* 82573 writes only through eewr */
4768 if(eeprom->use_eewr == TRUE)
4769 return e1000_write_eeprom_eewr(hw, offset, words, data);
4770
4771 /* Prepare the EEPROM for writing */
4772 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4773 return -E1000_ERR_EEPROM;
4774
4775 if(eeprom->type == e1000_eeprom_microwire) {
4776 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4777 } else {
4778 status = e1000_write_eeprom_spi(hw, offset, words, data);
4779 msec_delay(10);
4780 }
4781
4782 /* Done with writing */
4783 e1000_release_eeprom(hw);
4784
4785 return status;
4786 }
4787
4788 /******************************************************************************
4789 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4790 *
4791 * hw - Struct containing variables accessed by shared code
4792 * offset - offset within the EEPROM to be written to
4793 * words - number of words to write
4794 * data - pointer to array of 8 bit words to be written to the EEPROM
4795 *
4796 *****************************************************************************/
4797 int32_t
4798 e1000_write_eeprom_spi(struct e1000_hw *hw,
4799 uint16_t offset,
4800 uint16_t words,
4801 uint16_t *data)
4802 {
4803 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4804 uint16_t widx = 0;
4805
4806 DEBUGFUNC("e1000_write_eeprom_spi");
4807
4808 while (widx < words) {
4809 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
4810
4811 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
4812
4813 e1000_standby_eeprom(hw);
4814
4815 /* Send the WRITE ENABLE command (8 bit opcode ) */
4816 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4817 eeprom->opcode_bits);
4818
4819 e1000_standby_eeprom(hw);
4820
4821 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4822 if((eeprom->address_bits == 8) && (offset >= 128))
4823 write_opcode |= EEPROM_A8_OPCODE_SPI;
4824
4825 /* Send the Write command (8-bit opcode + addr) */
4826 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4827
4828 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
4829 eeprom->address_bits);
4830
4831 /* Send the data */
4832
4833 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4834 while (widx < words) {
4835 uint16_t word_out = data[widx];
4836 word_out = (word_out >> 8) | (word_out << 8);
4837 e1000_shift_out_ee_bits(hw, word_out, 16);
4838 widx++;
4839
4840 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4841 * operation, while the smaller eeproms are capable of an 8-byte
4842 * PAGE WRITE operation. Break the inner loop to pass new address
4843 */
4844 if((((offset + widx)*2) % eeprom->page_size) == 0) {
4845 e1000_standby_eeprom(hw);
4846 break;
4847 }
4848 }
4849 }
4850
4851 return E1000_SUCCESS;
4852 }
4853
4854 /******************************************************************************
4855 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4856 *
4857 * hw - Struct containing variables accessed by shared code
4858 * offset - offset within the EEPROM to be written to
4859 * words - number of words to write
4860 * data - pointer to array of 16 bit words to be written to the EEPROM
4861 *
4862 *****************************************************************************/
4863 int32_t
4864 e1000_write_eeprom_microwire(struct e1000_hw *hw,
4865 uint16_t offset,
4866 uint16_t words,
4867 uint16_t *data)
4868 {
4869 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4870 uint32_t eecd;
4871 uint16_t words_written = 0;
4872 uint16_t i = 0;
4873
4874 DEBUGFUNC("e1000_write_eeprom_microwire");
4875
4876 /* Send the write enable command to the EEPROM (3-bit opcode plus
4877 * 6/8-bit dummy address beginning with 11). It's less work to include
4878 * the 11 of the dummy address as part of the opcode than it is to shift
4879 * it over the correct number of bits for the address. This puts the
4880 * EEPROM into write/erase mode.
4881 */
4882 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4883 (uint16_t)(eeprom->opcode_bits + 2));
4884
4885 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4886
4887 /* Prepare the EEPROM */
4888 e1000_standby_eeprom(hw);
4889
4890 while (words_written < words) {
4891 /* Send the Write command (3-bit opcode + addr) */
4892 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4893 eeprom->opcode_bits);
4894
4895 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
4896 eeprom->address_bits);
4897
4898 /* Send the data */
4899 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4900
4901 /* Toggle the CS line. This in effect tells the EEPROM to execute
4902 * the previous command.
4903 */
4904 e1000_standby_eeprom(hw);
4905
4906 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4907 * signal that the command has been completed by raising the DO signal.
4908 * If DO does not go high in 10 milliseconds, then error out.
4909 */
4910 for(i = 0; i < 200; i++) {
4911 eecd = E1000_READ_REG(hw, EECD);
4912 if(eecd & E1000_EECD_DO) break;
4913 udelay(50);
4914 }
4915 if(i == 200) {
4916 DEBUGOUT("EEPROM Write did not complete\n");
4917 return -E1000_ERR_EEPROM;
4918 }
4919
4920 /* Recover from write */
4921 e1000_standby_eeprom(hw);
4922
4923 words_written++;
4924 }
4925
4926 /* Send the write disable command to the EEPROM (3-bit opcode plus
4927 * 6/8-bit dummy address beginning with 10). It's less work to include
4928 * the 10 of the dummy address as part of the opcode than it is to shift
4929 * it over the correct number of bits for the address. This takes the
4930 * EEPROM out of write/erase mode.
4931 */
4932 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4933 (uint16_t)(eeprom->opcode_bits + 2));
4934
4935 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4936
4937 return E1000_SUCCESS;
4938 }
4939
4940 /******************************************************************************
4941 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4942 * in the eeprom cache and the non modified values in the currently active bank
4943 * to the new bank.
4944 *
4945 * hw - Struct containing variables accessed by shared code
4946 * offset - offset of word in the EEPROM to read
4947 * data - word read from the EEPROM
4948 * words - number of words to read
4949 *****************************************************************************/
4950 static int32_t
4951 e1000_commit_shadow_ram(struct e1000_hw *hw)
4952 {
4953 uint32_t attempts = 100000;
4954 uint32_t eecd = 0;
4955 uint32_t flop = 0;
4956 uint32_t i = 0;
4957 int32_t error = E1000_SUCCESS;
4958
4959 /* The flop register will be used to determine if flash type is STM */
4960 flop = E1000_READ_REG(hw, FLOP);
4961
4962 if (hw->mac_type == e1000_82573) {
4963 for (i=0; i < attempts; i++) {
4964 eecd = E1000_READ_REG(hw, EECD);
4965 if ((eecd & E1000_EECD_FLUPD) == 0) {
4966 break;
4967 }
4968 udelay(5);
4969 }
4970
4971 if (i == attempts) {
4972 return -E1000_ERR_EEPROM;
4973 }
4974
4975 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4976 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4977 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4978 }
4979
4980 /* Perform the flash update */
4981 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4982
4983 for (i=0; i < attempts; i++) {
4984 eecd = E1000_READ_REG(hw, EECD);
4985 if ((eecd & E1000_EECD_FLUPD) == 0) {
4986 break;
4987 }
4988 udelay(5);
4989 }
4990
4991 if (i == attempts) {
4992 return -E1000_ERR_EEPROM;
4993 }
4994 }
4995
4996 return error;
4997 }
4998
4999 /******************************************************************************
5000 * Reads the adapter's part number from the EEPROM
5001 *
5002 * hw - Struct containing variables accessed by shared code
5003 * part_num - Adapter's part number
5004 *****************************************************************************/
5005 int32_t
5006 e1000_read_part_num(struct e1000_hw *hw,
5007 uint32_t *part_num)
5008 {
5009 uint16_t offset = EEPROM_PBA_BYTE_1;
5010 uint16_t eeprom_data;
5011
5012 DEBUGFUNC("e1000_read_part_num");
5013
5014 /* Get word 0 from EEPROM */
5015 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5016 DEBUGOUT("EEPROM Read Error\n");
5017 return -E1000_ERR_EEPROM;
5018 }
5019 /* Save word 0 in upper half of part_num */
5020 *part_num = (uint32_t) (eeprom_data << 16);
5021
5022 /* Get word 1 from EEPROM */
5023 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5024 DEBUGOUT("EEPROM Read Error\n");
5025 return -E1000_ERR_EEPROM;
5026 }
5027 /* Save word 1 in lower half of part_num */
5028 *part_num |= eeprom_data;
5029
5030 return E1000_SUCCESS;
5031 }
5032
5033 /******************************************************************************
5034 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5035 * second function of dual function devices
5036 *
5037 * hw - Struct containing variables accessed by shared code
5038 *****************************************************************************/
5039 int32_t
5040 e1000_read_mac_addr(struct e1000_hw * hw)
5041 {
5042 uint16_t offset;
5043 uint16_t eeprom_data, i;
5044
5045 DEBUGFUNC("e1000_read_mac_addr");
5046
5047 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5048 offset = i >> 1;
5049 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5050 DEBUGOUT("EEPROM Read Error\n");
5051 return -E1000_ERR_EEPROM;
5052 }
5053 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5054 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5055 }
5056
5057 switch (hw->mac_type) {
5058 default:
5059 break;
5060 case e1000_82546:
5061 case e1000_82546_rev_3:
5062 case e1000_82571:
5063 case e1000_80003es2lan:
5064 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5065 hw->perm_mac_addr[5] ^= 0x01;
5066 break;
5067 }
5068
5069 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
5070 hw->mac_addr[i] = hw->perm_mac_addr[i];
5071 return E1000_SUCCESS;
5072 }
5073
5074 /******************************************************************************
5075 * Initializes receive address filters.
5076 *
5077 * hw - Struct containing variables accessed by shared code
5078 *
5079 * Places the MAC address in receive address register 0 and clears the rest
5080 * of the receive addresss registers. Clears the multicast table. Assumes
5081 * the receiver is in reset when the routine is called.
5082 *****************************************************************************/
5083 static void
5084 e1000_init_rx_addrs(struct e1000_hw *hw)
5085 {
5086 uint32_t i;
5087 uint32_t rar_num;
5088
5089 DEBUGFUNC("e1000_init_rx_addrs");
5090
5091 /* Setup the receive address. */
5092 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5093
5094 e1000_rar_set(hw, hw->mac_addr, 0);
5095
5096 rar_num = E1000_RAR_ENTRIES;
5097
5098 /* Reserve a spot for the Locally Administered Address to work around
5099 * an 82571 issue in which a reset on one port will reload the MAC on
5100 * the other port. */
5101 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5102 rar_num -= 1;
5103 /* Zero out the other 15 receive addresses. */
5104 DEBUGOUT("Clearing RAR[1-15]\n");
5105 for(i = 1; i < rar_num; i++) {
5106 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5107 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5108 }
5109 }
5110
5111 #if 0
5112 /******************************************************************************
5113 * Updates the MAC's list of multicast addresses.
5114 *
5115 * hw - Struct containing variables accessed by shared code
5116 * mc_addr_list - the list of new multicast addresses
5117 * mc_addr_count - number of addresses
5118 * pad - number of bytes between addresses in the list
5119 * rar_used_count - offset where to start adding mc addresses into the RAR's
5120 *
5121 * The given list replaces any existing list. Clears the last 15 receive
5122 * address registers and the multicast table. Uses receive address registers
5123 * for the first 15 multicast addresses, and hashes the rest into the
5124 * multicast table.
5125 *****************************************************************************/
5126 void
5127 e1000_mc_addr_list_update(struct e1000_hw *hw,
5128 uint8_t *mc_addr_list,
5129 uint32_t mc_addr_count,
5130 uint32_t pad,
5131 uint32_t rar_used_count)
5132 {
5133 uint32_t hash_value;
5134 uint32_t i;
5135 uint32_t num_rar_entry;
5136 uint32_t num_mta_entry;
5137
5138 DEBUGFUNC("e1000_mc_addr_list_update");
5139
5140 /* Set the new number of MC addresses that we are being requested to use. */
5141 hw->num_mc_addrs = mc_addr_count;
5142
5143 /* Clear RAR[1-15] */
5144 DEBUGOUT(" Clearing RAR[1-15]\n");
5145 num_rar_entry = E1000_RAR_ENTRIES;
5146 /* Reserve a spot for the Locally Administered Address to work around
5147 * an 82571 issue in which a reset on one port will reload the MAC on
5148 * the other port. */
5149 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5150 num_rar_entry -= 1;
5151
5152 for(i = rar_used_count; i < num_rar_entry; i++) {
5153 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5154 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5155 }
5156
5157 /* Clear the MTA */
5158 DEBUGOUT(" Clearing MTA\n");
5159 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5160 for(i = 0; i < num_mta_entry; i++) {
5161 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5162 }
5163
5164 /* Add the new addresses */
5165 for(i = 0; i < mc_addr_count; i++) {
5166 DEBUGOUT(" Adding the multicast addresses:\n");
5167 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5168 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5169 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5170 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5171 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5172 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5173 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5174
5175 hash_value = e1000_hash_mc_addr(hw,
5176 mc_addr_list +
5177 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5178
5179 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5180
5181 /* Place this multicast address in the RAR if there is room, *
5182 * else put it in the MTA
5183 */
5184 if (rar_used_count < num_rar_entry) {
5185 e1000_rar_set(hw,
5186 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5187 rar_used_count);
5188 rar_used_count++;
5189 } else {
5190 e1000_mta_set(hw, hash_value);
5191 }
5192 }
5193 DEBUGOUT("MC Update Complete\n");
5194 }
5195 #endif /* 0 */
5196
5197 /******************************************************************************
5198 * Hashes an address to determine its location in the multicast table
5199 *
5200 * hw - Struct containing variables accessed by shared code
5201 * mc_addr - the multicast address to hash
5202 *****************************************************************************/
5203 uint32_t
5204 e1000_hash_mc_addr(struct e1000_hw *hw,
5205 uint8_t *mc_addr)
5206 {
5207 uint32_t hash_value = 0;
5208
5209 /* The portion of the address that is used for the hash table is
5210 * determined by the mc_filter_type setting.
5211 */
5212 switch (hw->mc_filter_type) {
5213 /* [0] [1] [2] [3] [4] [5]
5214 * 01 AA 00 12 34 56
5215 * LSB MSB
5216 */
5217 case 0:
5218 /* [47:36] i.e. 0x563 for above example address */
5219 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5220 break;
5221 case 1:
5222 /* [46:35] i.e. 0xAC6 for above example address */
5223 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5224 break;
5225 case 2:
5226 /* [45:34] i.e. 0x5D8 for above example address */
5227 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5228 break;
5229 case 3:
5230 /* [43:32] i.e. 0x634 for above example address */
5231 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5232 break;
5233 }
5234
5235 hash_value &= 0xFFF;
5236
5237 return hash_value;
5238 }
5239
5240 /******************************************************************************
5241 * Sets the bit in the multicast table corresponding to the hash value.
5242 *
5243 * hw - Struct containing variables accessed by shared code
5244 * hash_value - Multicast address hash value
5245 *****************************************************************************/
5246 void
5247 e1000_mta_set(struct e1000_hw *hw,
5248 uint32_t hash_value)
5249 {
5250 uint32_t hash_bit, hash_reg;
5251 uint32_t mta;
5252 uint32_t temp;
5253
5254 /* The MTA is a register array of 128 32-bit registers.
5255 * It is treated like an array of 4096 bits. We want to set
5256 * bit BitArray[hash_value]. So we figure out what register
5257 * the bit is in, read it, OR in the new bit, then write
5258 * back the new value. The register is determined by the
5259 * upper 7 bits of the hash value and the bit within that
5260 * register are determined by the lower 5 bits of the value.
5261 */
5262 hash_reg = (hash_value >> 5) & 0x7F;
5263 hash_bit = hash_value & 0x1F;
5264
5265 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5266
5267 mta |= (1 << hash_bit);
5268
5269 /* If we are on an 82544 and we are trying to write an odd offset
5270 * in the MTA, save off the previous entry before writing and
5271 * restore the old value after writing.
5272 */
5273 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5274 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5275 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5276 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5277 } else {
5278 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5279 }
5280 }
5281
5282 /******************************************************************************
5283 * Puts an ethernet address into a receive address register.
5284 *
5285 * hw - Struct containing variables accessed by shared code
5286 * addr - Address to put into receive address register
5287 * index - Receive address register to write
5288 *****************************************************************************/
5289 void
5290 e1000_rar_set(struct e1000_hw *hw,
5291 uint8_t *addr,
5292 uint32_t index)
5293 {
5294 uint32_t rar_low, rar_high;
5295
5296 /* HW expects these in little endian so we reverse the byte order
5297 * from network order (big endian) to little endian
5298 */
5299 rar_low = ((uint32_t) addr[0] |
5300 ((uint32_t) addr[1] << 8) |
5301 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5302 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5303
5304 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5305 * unit hang.
5306 *
5307 * Description:
5308 * If there are any Rx frames queued up or otherwise present in the HW
5309 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5310 * hang. To work around this issue, we have to disable receives and
5311 * flush out all Rx frames before we enable RSS. To do so, we modify we
5312 * redirect all Rx traffic to manageability and then reset the HW.
5313 * This flushes away Rx frames, and (since the redirections to
5314 * manageability persists across resets) keeps new ones from coming in
5315 * while we work. Then, we clear the Address Valid AV bit for all MAC
5316 * addresses and undo the re-direction to manageability.
5317 * Now, frames are coming in again, but the MAC won't accept them, so
5318 * far so good. We now proceed to initialize RSS (if necessary) and
5319 * configure the Rx unit. Last, we re-enable the AV bits and continue
5320 * on our merry way.
5321 */
5322 switch (hw->mac_type) {
5323 case e1000_82571:
5324 case e1000_82572:
5325 case e1000_80003es2lan:
5326 if (hw->leave_av_bit_off == TRUE)
5327 break;
5328 default:
5329 /* Indicate to hardware the Address is Valid. */
5330 rar_high |= E1000_RAH_AV;
5331 break;
5332 }
5333
5334 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5335 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5336 }
5337
5338 /******************************************************************************
5339 * Writes a value to the specified offset in the VLAN filter table.
5340 *
5341 * hw - Struct containing variables accessed by shared code
5342 * offset - Offset in VLAN filer table to write
5343 * value - Value to write into VLAN filter table
5344 *****************************************************************************/
5345 void
5346 e1000_write_vfta(struct e1000_hw *hw,
5347 uint32_t offset,
5348 uint32_t value)
5349 {
5350 uint32_t temp;
5351
5352 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5353 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5354 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5355 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5356 } else {
5357 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5358 }
5359 }
5360
5361 /******************************************************************************
5362 * Clears the VLAN filer table
5363 *
5364 * hw - Struct containing variables accessed by shared code
5365 *****************************************************************************/
5366 static void
5367 e1000_clear_vfta(struct e1000_hw *hw)
5368 {
5369 uint32_t offset;
5370 uint32_t vfta_value = 0;
5371 uint32_t vfta_offset = 0;
5372 uint32_t vfta_bit_in_reg = 0;
5373
5374 if (hw->mac_type == e1000_82573) {
5375 if (hw->mng_cookie.vlan_id != 0) {
5376 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5377 * ID. The following operations determine which 32b entry
5378 * (i.e. offset) into the array we want to set the VLAN ID
5379 * (i.e. bit) of the manageability unit. */
5380 vfta_offset = (hw->mng_cookie.vlan_id >>
5381 E1000_VFTA_ENTRY_SHIFT) &
5382 E1000_VFTA_ENTRY_MASK;
5383 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5384 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5385 }
5386 }
5387 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5388 /* If the offset we want to clear is the same offset of the
5389 * manageability VLAN ID, then clear all bits except that of the
5390 * manageability unit */
5391 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5392 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5393 }
5394 }
5395
5396 static int32_t
5397 e1000_id_led_init(struct e1000_hw * hw)
5398 {
5399 uint32_t ledctl;
5400 const uint32_t ledctl_mask = 0x000000FF;
5401 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5402 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5403 uint16_t eeprom_data, i, temp;
5404 const uint16_t led_mask = 0x0F;
5405
5406 DEBUGFUNC("e1000_id_led_init");
5407
5408 if(hw->mac_type < e1000_82540) {
5409 /* Nothing to do */
5410 return E1000_SUCCESS;
5411 }
5412
5413 ledctl = E1000_READ_REG(hw, LEDCTL);
5414 hw->ledctl_default = ledctl;
5415 hw->ledctl_mode1 = hw->ledctl_default;
5416 hw->ledctl_mode2 = hw->ledctl_default;
5417
5418 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5419 DEBUGOUT("EEPROM Read Error\n");
5420 return -E1000_ERR_EEPROM;
5421 }
5422 if((eeprom_data== ID_LED_RESERVED_0000) ||
5423 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
5424 for(i = 0; i < 4; i++) {
5425 temp = (eeprom_data >> (i << 2)) & led_mask;
5426 switch(temp) {
5427 case ID_LED_ON1_DEF2:
5428 case ID_LED_ON1_ON2:
5429 case ID_LED_ON1_OFF2:
5430 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5431 hw->ledctl_mode1 |= ledctl_on << (i << 3);
5432 break;
5433 case ID_LED_OFF1_DEF2:
5434 case ID_LED_OFF1_ON2:
5435 case ID_LED_OFF1_OFF2:
5436 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5437 hw->ledctl_mode1 |= ledctl_off << (i << 3);
5438 break;
5439 default:
5440 /* Do nothing */
5441 break;
5442 }
5443 switch(temp) {
5444 case ID_LED_DEF1_ON2:
5445 case ID_LED_ON1_ON2:
5446 case ID_LED_OFF1_ON2:
5447 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5448 hw->ledctl_mode2 |= ledctl_on << (i << 3);
5449 break;
5450 case ID_LED_DEF1_OFF2:
5451 case ID_LED_ON1_OFF2:
5452 case ID_LED_OFF1_OFF2:
5453 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5454 hw->ledctl_mode2 |= ledctl_off << (i << 3);
5455 break;
5456 default:
5457 /* Do nothing */
5458 break;
5459 }
5460 }
5461 return E1000_SUCCESS;
5462 }
5463
5464 /******************************************************************************
5465 * Prepares SW controlable LED for use and saves the current state of the LED.
5466 *
5467 * hw - Struct containing variables accessed by shared code
5468 *****************************************************************************/
5469 int32_t
5470 e1000_setup_led(struct e1000_hw *hw)
5471 {
5472 uint32_t ledctl;
5473 int32_t ret_val = E1000_SUCCESS;
5474
5475 DEBUGFUNC("e1000_setup_led");
5476
5477 switch(hw->mac_type) {
5478 case e1000_82542_rev2_0:
5479 case e1000_82542_rev2_1:
5480 case e1000_82543:
5481 case e1000_82544:
5482 /* No setup necessary */
5483 break;
5484 case e1000_82541:
5485 case e1000_82547:
5486 case e1000_82541_rev_2:
5487 case e1000_82547_rev_2:
5488 /* Turn off PHY Smart Power Down (if enabled) */
5489 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
5490 &hw->phy_spd_default);
5491 if(ret_val)
5492 return ret_val;
5493 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5494 (uint16_t)(hw->phy_spd_default &
5495 ~IGP01E1000_GMII_SPD));
5496 if(ret_val)
5497 return ret_val;
5498 /* Fall Through */
5499 default:
5500 if(hw->media_type == e1000_media_type_fiber) {
5501 ledctl = E1000_READ_REG(hw, LEDCTL);
5502 /* Save current LEDCTL settings */
5503 hw->ledctl_default = ledctl;
5504 /* Turn off LED0 */
5505 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
5506 E1000_LEDCTL_LED0_BLINK |
5507 E1000_LEDCTL_LED0_MODE_MASK);
5508 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
5509 E1000_LEDCTL_LED0_MODE_SHIFT);
5510 E1000_WRITE_REG(hw, LEDCTL, ledctl);
5511 } else if(hw->media_type == e1000_media_type_copper)
5512 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5513 break;
5514 }
5515
5516 return E1000_SUCCESS;
5517 }
5518
5519 /******************************************************************************
5520 * Restores the saved state of the SW controlable LED.
5521 *
5522 * hw - Struct containing variables accessed by shared code
5523 *****************************************************************************/
5524 int32_t
5525 e1000_cleanup_led(struct e1000_hw *hw)
5526 {
5527 int32_t ret_val = E1000_SUCCESS;
5528
5529 DEBUGFUNC("e1000_cleanup_led");
5530
5531 switch(hw->mac_type) {
5532 case e1000_82542_rev2_0:
5533 case e1000_82542_rev2_1:
5534 case e1000_82543:
5535 case e1000_82544:
5536 /* No cleanup necessary */
5537 break;
5538 case e1000_82541:
5539 case e1000_82547:
5540 case e1000_82541_rev_2:
5541 case e1000_82547_rev_2:
5542 /* Turn on PHY Smart Power Down (if previously enabled) */
5543 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5544 hw->phy_spd_default);
5545 if(ret_val)
5546 return ret_val;
5547 /* Fall Through */
5548 default:
5549 /* Restore LEDCTL settings */
5550 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
5551 break;
5552 }
5553
5554 return E1000_SUCCESS;
5555 }
5556
5557 /******************************************************************************
5558 * Turns on the software controllable LED
5559 *
5560 * hw - Struct containing variables accessed by shared code
5561 *****************************************************************************/
5562 int32_t
5563 e1000_led_on(struct e1000_hw *hw)
5564 {
5565 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
5566
5567 DEBUGFUNC("e1000_led_on");
5568
5569 switch(hw->mac_type) {
5570 case e1000_82542_rev2_0:
5571 case e1000_82542_rev2_1:
5572 case e1000_82543:
5573 /* Set SW Defineable Pin 0 to turn on the LED */
5574 ctrl |= E1000_CTRL_SWDPIN0;
5575 ctrl |= E1000_CTRL_SWDPIO0;
5576 break;
5577 case e1000_82544:
5578 if(hw->media_type == e1000_media_type_fiber) {
5579 /* Set SW Defineable Pin 0 to turn on the LED */
5580 ctrl |= E1000_CTRL_SWDPIN0;
5581 ctrl |= E1000_CTRL_SWDPIO0;
5582 } else {
5583 /* Clear SW Defineable Pin 0 to turn on the LED */
5584 ctrl &= ~E1000_CTRL_SWDPIN0;
5585 ctrl |= E1000_CTRL_SWDPIO0;
5586 }
5587 break;
5588 default:
5589 if(hw->media_type == e1000_media_type_fiber) {
5590 /* Clear SW Defineable Pin 0 to turn on the LED */
5591 ctrl &= ~E1000_CTRL_SWDPIN0;
5592 ctrl |= E1000_CTRL_SWDPIO0;
5593 } else if(hw->media_type == e1000_media_type_copper) {
5594 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5595 return E1000_SUCCESS;
5596 }
5597 break;
5598 }
5599
5600 E1000_WRITE_REG(hw, CTRL, ctrl);
5601
5602 return E1000_SUCCESS;
5603 }
5604
5605 /******************************************************************************
5606 * Turns off the software controllable LED
5607 *
5608 * hw - Struct containing variables accessed by shared code
5609 *****************************************************************************/
5610 int32_t
5611 e1000_led_off(struct e1000_hw *hw)
5612 {
5613 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
5614
5615 DEBUGFUNC("e1000_led_off");
5616
5617 switch(hw->mac_type) {
5618 case e1000_82542_rev2_0:
5619 case e1000_82542_rev2_1:
5620 case e1000_82543:
5621 /* Clear SW Defineable Pin 0 to turn off the LED */
5622 ctrl &= ~E1000_CTRL_SWDPIN0;
5623 ctrl |= E1000_CTRL_SWDPIO0;
5624 break;
5625 case e1000_82544:
5626 if(hw->media_type == e1000_media_type_fiber) {
5627 /* Clear SW Defineable Pin 0 to turn off the LED */
5628 ctrl &= ~E1000_CTRL_SWDPIN0;
5629 ctrl |= E1000_CTRL_SWDPIO0;
5630 } else {
5631 /* Set SW Defineable Pin 0 to turn off the LED */
5632 ctrl |= E1000_CTRL_SWDPIN0;
5633 ctrl |= E1000_CTRL_SWDPIO0;
5634 }
5635 break;
5636 default:
5637 if(hw->media_type == e1000_media_type_fiber) {
5638 /* Set SW Defineable Pin 0 to turn off the LED */
5639 ctrl |= E1000_CTRL_SWDPIN0;
5640 ctrl |= E1000_CTRL_SWDPIO0;
5641 } else if(hw->media_type == e1000_media_type_copper) {
5642 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5643 return E1000_SUCCESS;
5644 }
5645 break;
5646 }
5647
5648 E1000_WRITE_REG(hw, CTRL, ctrl);
5649
5650 return E1000_SUCCESS;
5651 }
5652
5653 /******************************************************************************
5654 * Clears all hardware statistics counters.
5655 *
5656 * hw - Struct containing variables accessed by shared code
5657 *****************************************************************************/
5658 static void
5659 e1000_clear_hw_cntrs(struct e1000_hw *hw)
5660 {
5661 volatile uint32_t temp;
5662
5663 temp = E1000_READ_REG(hw, CRCERRS);
5664 temp = E1000_READ_REG(hw, SYMERRS);
5665 temp = E1000_READ_REG(hw, MPC);
5666 temp = E1000_READ_REG(hw, SCC);
5667 temp = E1000_READ_REG(hw, ECOL);
5668 temp = E1000_READ_REG(hw, MCC);
5669 temp = E1000_READ_REG(hw, LATECOL);
5670 temp = E1000_READ_REG(hw, COLC);
5671 temp = E1000_READ_REG(hw, DC);
5672 temp = E1000_READ_REG(hw, SEC);
5673 temp = E1000_READ_REG(hw, RLEC);
5674 temp = E1000_READ_REG(hw, XONRXC);
5675 temp = E1000_READ_REG(hw, XONTXC);
5676 temp = E1000_READ_REG(hw, XOFFRXC);
5677 temp = E1000_READ_REG(hw, XOFFTXC);
5678 temp = E1000_READ_REG(hw, FCRUC);
5679 temp = E1000_READ_REG(hw, PRC64);
5680 temp = E1000_READ_REG(hw, PRC127);
5681 temp = E1000_READ_REG(hw, PRC255);
5682 temp = E1000_READ_REG(hw, PRC511);
5683 temp = E1000_READ_REG(hw, PRC1023);
5684 temp = E1000_READ_REG(hw, PRC1522);
5685 temp = E1000_READ_REG(hw, GPRC);
5686 temp = E1000_READ_REG(hw, BPRC);
5687 temp = E1000_READ_REG(hw, MPRC);
5688 temp = E1000_READ_REG(hw, GPTC);
5689 temp = E1000_READ_REG(hw, GORCL);
5690 temp = E1000_READ_REG(hw, GORCH);
5691 temp = E1000_READ_REG(hw, GOTCL);
5692 temp = E1000_READ_REG(hw, GOTCH);
5693 temp = E1000_READ_REG(hw, RNBC);
5694 temp = E1000_READ_REG(hw, RUC);
5695 temp = E1000_READ_REG(hw, RFC);
5696 temp = E1000_READ_REG(hw, ROC);
5697 temp = E1000_READ_REG(hw, RJC);
5698 temp = E1000_READ_REG(hw, TORL);
5699 temp = E1000_READ_REG(hw, TORH);
5700 temp = E1000_READ_REG(hw, TOTL);
5701 temp = E1000_READ_REG(hw, TOTH);
5702 temp = E1000_READ_REG(hw, TPR);
5703 temp = E1000_READ_REG(hw, TPT);
5704 temp = E1000_READ_REG(hw, PTC64);
5705 temp = E1000_READ_REG(hw, PTC127);
5706 temp = E1000_READ_REG(hw, PTC255);
5707 temp = E1000_READ_REG(hw, PTC511);
5708 temp = E1000_READ_REG(hw, PTC1023);
5709 temp = E1000_READ_REG(hw, PTC1522);
5710 temp = E1000_READ_REG(hw, MPTC);
5711 temp = E1000_READ_REG(hw, BPTC);
5712
5713 if(hw->mac_type < e1000_82543) return;
5714
5715 temp = E1000_READ_REG(hw, ALGNERRC);
5716 temp = E1000_READ_REG(hw, RXERRC);
5717 temp = E1000_READ_REG(hw, TNCRS);
5718 temp = E1000_READ_REG(hw, CEXTERR);
5719 temp = E1000_READ_REG(hw, TSCTC);
5720 temp = E1000_READ_REG(hw, TSCTFC);
5721
5722 if(hw->mac_type <= e1000_82544) return;
5723
5724 temp = E1000_READ_REG(hw, MGTPRC);
5725 temp = E1000_READ_REG(hw, MGTPDC);
5726 temp = E1000_READ_REG(hw, MGTPTC);
5727
5728 if(hw->mac_type <= e1000_82547_rev_2) return;
5729
5730 temp = E1000_READ_REG(hw, IAC);
5731 temp = E1000_READ_REG(hw, ICRXOC);
5732 temp = E1000_READ_REG(hw, ICRXPTC);
5733 temp = E1000_READ_REG(hw, ICRXATC);
5734 temp = E1000_READ_REG(hw, ICTXPTC);
5735 temp = E1000_READ_REG(hw, ICTXATC);
5736 temp = E1000_READ_REG(hw, ICTXQEC);
5737 temp = E1000_READ_REG(hw, ICTXQMTC);
5738 temp = E1000_READ_REG(hw, ICRXDMTC);
5739 }
5740
5741 /******************************************************************************
5742 * Resets Adaptive IFS to its default state.
5743 *
5744 * hw - Struct containing variables accessed by shared code
5745 *
5746 * Call this after e1000_init_hw. You may override the IFS defaults by setting
5747 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
5748 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
5749 * before calling this function.
5750 *****************************************************************************/
5751 void
5752 e1000_reset_adaptive(struct e1000_hw *hw)
5753 {
5754 DEBUGFUNC("e1000_reset_adaptive");
5755
5756 if(hw->adaptive_ifs) {
5757 if(!hw->ifs_params_forced) {
5758 hw->current_ifs_val = 0;
5759 hw->ifs_min_val = IFS_MIN;
5760 hw->ifs_max_val = IFS_MAX;
5761 hw->ifs_step_size = IFS_STEP;
5762 hw->ifs_ratio = IFS_RATIO;
5763 }
5764 hw->in_ifs_mode = FALSE;
5765 E1000_WRITE_REG(hw, AIT, 0);
5766 } else {
5767 DEBUGOUT("Not in Adaptive IFS mode!\n");
5768 }
5769 }
5770
5771 /******************************************************************************
5772 * Called during the callback/watchdog routine to update IFS value based on
5773 * the ratio of transmits to collisions.
5774 *
5775 * hw - Struct containing variables accessed by shared code
5776 * tx_packets - Number of transmits since last callback
5777 * total_collisions - Number of collisions since last callback
5778 *****************************************************************************/
5779 void
5780 e1000_update_adaptive(struct e1000_hw *hw)
5781 {
5782 DEBUGFUNC("e1000_update_adaptive");
5783
5784 if(hw->adaptive_ifs) {
5785 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
5786 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
5787 hw->in_ifs_mode = TRUE;
5788 if(hw->current_ifs_val < hw->ifs_max_val) {
5789 if(hw->current_ifs_val == 0)
5790 hw->current_ifs_val = hw->ifs_min_val;
5791 else
5792 hw->current_ifs_val += hw->ifs_step_size;
5793 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
5794 }
5795 }
5796 } else {
5797 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
5798 hw->current_ifs_val = 0;
5799 hw->in_ifs_mode = FALSE;
5800 E1000_WRITE_REG(hw, AIT, 0);
5801 }
5802 }
5803 } else {
5804 DEBUGOUT("Not in Adaptive IFS mode!\n");
5805 }
5806 }
5807
5808 /******************************************************************************
5809 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5810 *
5811 * hw - Struct containing variables accessed by shared code
5812 * frame_len - The length of the frame in question
5813 * mac_addr - The Ethernet destination address of the frame in question
5814 *****************************************************************************/
5815 void
5816 e1000_tbi_adjust_stats(struct e1000_hw *hw,
5817 struct e1000_hw_stats *stats,
5818 uint32_t frame_len,
5819 uint8_t *mac_addr)
5820 {
5821 uint64_t carry_bit;
5822
5823 /* First adjust the frame length. */
5824 frame_len--;
5825 /* We need to adjust the statistics counters, since the hardware
5826 * counters overcount this packet as a CRC error and undercount
5827 * the packet as a good packet
5828 */
5829 /* This packet should not be counted as a CRC error. */
5830 stats->crcerrs--;
5831 /* This packet does count as a Good Packet Received. */
5832 stats->gprc++;
5833
5834 /* Adjust the Good Octets received counters */
5835 carry_bit = 0x80000000 & stats->gorcl;
5836 stats->gorcl += frame_len;
5837 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5838 * Received Count) was one before the addition,
5839 * AND it is zero after, then we lost the carry out,
5840 * need to add one to Gorch (Good Octets Received Count High).
5841 * This could be simplified if all environments supported
5842 * 64-bit integers.
5843 */
5844 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
5845 stats->gorch++;
5846 /* Is this a broadcast or multicast? Check broadcast first,
5847 * since the test for a multicast frame will test positive on
5848 * a broadcast frame.
5849 */
5850 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
5851 /* Broadcast packet */
5852 stats->bprc++;
5853 else if(*mac_addr & 0x01)
5854 /* Multicast packet */
5855 stats->mprc++;
5856
5857 if(frame_len == hw->max_frame_size) {
5858 /* In this case, the hardware has overcounted the number of
5859 * oversize frames.
5860 */
5861 if(stats->roc > 0)
5862 stats->roc--;
5863 }
5864
5865 /* Adjust the bin counters when the extra byte put the frame in the
5866 * wrong bin. Remember that the frame_len was adjusted above.
5867 */
5868 if(frame_len == 64) {
5869 stats->prc64++;
5870 stats->prc127--;
5871 } else if(frame_len == 127) {
5872 stats->prc127++;
5873 stats->prc255--;
5874 } else if(frame_len == 255) {
5875 stats->prc255++;
5876 stats->prc511--;
5877 } else if(frame_len == 511) {
5878 stats->prc511++;
5879 stats->prc1023--;
5880 } else if(frame_len == 1023) {
5881 stats->prc1023++;
5882 stats->prc1522--;
5883 } else if(frame_len == 1522) {
5884 stats->prc1522++;
5885 }
5886 }
5887
5888 /******************************************************************************
5889 * Gets the current PCI bus type, speed, and width of the hardware
5890 *
5891 * hw - Struct containing variables accessed by shared code
5892 *****************************************************************************/
5893 void
5894 e1000_get_bus_info(struct e1000_hw *hw)
5895 {
5896 uint32_t status;
5897
5898 switch (hw->mac_type) {
5899 case e1000_82542_rev2_0:
5900 case e1000_82542_rev2_1:
5901 hw->bus_type = e1000_bus_type_unknown;
5902 hw->bus_speed = e1000_bus_speed_unknown;
5903 hw->bus_width = e1000_bus_width_unknown;
5904 break;
5905 case e1000_82572:
5906 case e1000_82573:
5907 hw->bus_type = e1000_bus_type_pci_express;
5908 hw->bus_speed = e1000_bus_speed_2500;
5909 hw->bus_width = e1000_bus_width_pciex_1;
5910 break;
5911 case e1000_82571:
5912 case e1000_80003es2lan:
5913 hw->bus_type = e1000_bus_type_pci_express;
5914 hw->bus_speed = e1000_bus_speed_2500;
5915 hw->bus_width = e1000_bus_width_pciex_4;
5916 break;
5917 default:
5918 status = E1000_READ_REG(hw, STATUS);
5919 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5920 e1000_bus_type_pcix : e1000_bus_type_pci;
5921
5922 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
5923 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
5924 e1000_bus_speed_66 : e1000_bus_speed_120;
5925 } else if(hw->bus_type == e1000_bus_type_pci) {
5926 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
5927 e1000_bus_speed_66 : e1000_bus_speed_33;
5928 } else {
5929 switch (status & E1000_STATUS_PCIX_SPEED) {
5930 case E1000_STATUS_PCIX_SPEED_66:
5931 hw->bus_speed = e1000_bus_speed_66;
5932 break;
5933 case E1000_STATUS_PCIX_SPEED_100:
5934 hw->bus_speed = e1000_bus_speed_100;
5935 break;
5936 case E1000_STATUS_PCIX_SPEED_133:
5937 hw->bus_speed = e1000_bus_speed_133;
5938 break;
5939 default:
5940 hw->bus_speed = e1000_bus_speed_reserved;
5941 break;
5942 }
5943 }
5944 hw->bus_width = (status & E1000_STATUS_BUS64) ?
5945 e1000_bus_width_64 : e1000_bus_width_32;
5946 break;
5947 }
5948 }
5949
5950 #if 0
5951 /******************************************************************************
5952 * Reads a value from one of the devices registers using port I/O (as opposed
5953 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5954 *
5955 * hw - Struct containing variables accessed by shared code
5956 * offset - offset to read from
5957 *****************************************************************************/
5958 uint32_t
5959 e1000_read_reg_io(struct e1000_hw *hw,
5960 uint32_t offset)
5961 {
5962 unsigned long io_addr = hw->io_base;
5963 unsigned long io_data = hw->io_base + 4;
5964
5965 e1000_io_write(hw, io_addr, offset);
5966 return e1000_io_read(hw, io_data);
5967 }
5968 #endif /* 0 */
5969
5970 /******************************************************************************
5971 * Writes a value to one of the devices registers using port I/O (as opposed to
5972 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5973 *
5974 * hw - Struct containing variables accessed by shared code
5975 * offset - offset to write to
5976 * value - value to write
5977 *****************************************************************************/
5978 static void
5979 e1000_write_reg_io(struct e1000_hw *hw,
5980 uint32_t offset,
5981 uint32_t value)
5982 {
5983 unsigned long io_addr = hw->io_base;
5984 unsigned long io_data = hw->io_base + 4;
5985
5986 e1000_io_write(hw, io_addr, offset);
5987 e1000_io_write(hw, io_data, value);
5988 }
5989
5990
5991 /******************************************************************************
5992 * Estimates the cable length.
5993 *
5994 * hw - Struct containing variables accessed by shared code
5995 * min_length - The estimated minimum length
5996 * max_length - The estimated maximum length
5997 *
5998 * returns: - E1000_ERR_XXX
5999 * E1000_SUCCESS
6000 *
6001 * This function always returns a ranged length (minimum & maximum).
6002 * So for M88 phy's, this function interprets the one value returned from the
6003 * register to the minimum and maximum range.
6004 * For IGP phy's, the function calculates the range by the AGC registers.
6005 *****************************************************************************/
6006 static int32_t
6007 e1000_get_cable_length(struct e1000_hw *hw,
6008 uint16_t *min_length,
6009 uint16_t *max_length)
6010 {
6011 int32_t ret_val;
6012 uint16_t agc_value = 0;
6013 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6014 uint16_t max_agc = 0;
6015 uint16_t i, phy_data;
6016 uint16_t cable_length;
6017
6018 DEBUGFUNC("e1000_get_cable_length");
6019
6020 *min_length = *max_length = 0;
6021
6022 /* Use old method for Phy older than IGP */
6023 if(hw->phy_type == e1000_phy_m88) {
6024
6025 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6026 &phy_data);
6027 if(ret_val)
6028 return ret_val;
6029 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6030 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6031
6032 /* Convert the enum value to ranged values */
6033 switch (cable_length) {
6034 case e1000_cable_length_50:
6035 *min_length = 0;
6036 *max_length = e1000_igp_cable_length_50;
6037 break;
6038 case e1000_cable_length_50_80:
6039 *min_length = e1000_igp_cable_length_50;
6040 *max_length = e1000_igp_cable_length_80;
6041 break;
6042 case e1000_cable_length_80_110:
6043 *min_length = e1000_igp_cable_length_80;
6044 *max_length = e1000_igp_cable_length_110;
6045 break;
6046 case e1000_cable_length_110_140:
6047 *min_length = e1000_igp_cable_length_110;
6048 *max_length = e1000_igp_cable_length_140;
6049 break;
6050 case e1000_cable_length_140:
6051 *min_length = e1000_igp_cable_length_140;
6052 *max_length = e1000_igp_cable_length_170;
6053 break;
6054 default:
6055 return -E1000_ERR_PHY;
6056 break;
6057 }
6058 } else if (hw->phy_type == e1000_phy_gg82563) {
6059 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6060 &phy_data);
6061 if (ret_val)
6062 return ret_val;
6063 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6064
6065 switch (cable_length) {
6066 case e1000_gg_cable_length_60:
6067 *min_length = 0;
6068 *max_length = e1000_igp_cable_length_60;
6069 break;
6070 case e1000_gg_cable_length_60_115:
6071 *min_length = e1000_igp_cable_length_60;
6072 *max_length = e1000_igp_cable_length_115;
6073 break;
6074 case e1000_gg_cable_length_115_150:
6075 *min_length = e1000_igp_cable_length_115;
6076 *max_length = e1000_igp_cable_length_150;
6077 break;
6078 case e1000_gg_cable_length_150:
6079 *min_length = e1000_igp_cable_length_150;
6080 *max_length = e1000_igp_cable_length_180;
6081 break;
6082 default:
6083 return -E1000_ERR_PHY;
6084 break;
6085 }
6086 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6087 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6088 {IGP01E1000_PHY_AGC_A,
6089 IGP01E1000_PHY_AGC_B,
6090 IGP01E1000_PHY_AGC_C,
6091 IGP01E1000_PHY_AGC_D};
6092 /* Read the AGC registers for all channels */
6093 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6094
6095 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6096 if(ret_val)
6097 return ret_val;
6098
6099 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6100
6101 /* Array bound check. */
6102 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6103 (cur_agc == 0))
6104 return -E1000_ERR_PHY;
6105
6106 agc_value += cur_agc;
6107
6108 /* Update minimal AGC value. */
6109 if(min_agc > cur_agc)
6110 min_agc = cur_agc;
6111 }
6112
6113 /* Remove the minimal AGC result for length < 50m */
6114 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6115 agc_value -= min_agc;
6116
6117 /* Get the average length of the remaining 3 channels */
6118 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6119 } else {
6120 /* Get the average length of all the 4 channels. */
6121 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6122 }
6123
6124 /* Set the range of the calculated length. */
6125 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6126 IGP01E1000_AGC_RANGE) > 0) ?
6127 (e1000_igp_cable_length_table[agc_value] -
6128 IGP01E1000_AGC_RANGE) : 0;
6129 *max_length = e1000_igp_cable_length_table[agc_value] +
6130 IGP01E1000_AGC_RANGE;
6131 } else if (hw->phy_type == e1000_phy_igp_2) {
6132 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6133 {IGP02E1000_PHY_AGC_A,
6134 IGP02E1000_PHY_AGC_B,
6135 IGP02E1000_PHY_AGC_C,
6136 IGP02E1000_PHY_AGC_D};
6137 /* Read the AGC registers for all channels */
6138 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6139 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6140 if (ret_val)
6141 return ret_val;
6142
6143 /* Getting bits 15:9, which represent the combination of course and
6144 * fine gain values. The result is a number that can be put into
6145 * the lookup table to obtain the approximate cable length. */
6146 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6147 IGP02E1000_AGC_LENGTH_MASK;
6148
6149 /* Remove min & max AGC values from calculation. */
6150 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc])
6151 min_agc = cur_agc;
6152 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc])
6153 max_agc = cur_agc;
6154
6155 agc_value += e1000_igp_2_cable_length_table[cur_agc];
6156 }
6157
6158 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]);
6159 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6160
6161 /* Calculate cable length with the error range of +/- 10 meters. */
6162 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6163 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6164 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6165 }
6166
6167 return E1000_SUCCESS;
6168 }
6169
6170 /******************************************************************************
6171 * Check the cable polarity
6172 *
6173 * hw - Struct containing variables accessed by shared code
6174 * polarity - output parameter : 0 - Polarity is not reversed
6175 * 1 - Polarity is reversed.
6176 *
6177 * returns: - E1000_ERR_XXX
6178 * E1000_SUCCESS
6179 *
6180 * For phy's older then IGP, this function simply reads the polarity bit in the
6181 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6182 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6183 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6184 * IGP01E1000_PHY_PCS_INIT_REG.
6185 *****************************************************************************/
6186 static int32_t
6187 e1000_check_polarity(struct e1000_hw *hw,
6188 uint16_t *polarity)
6189 {
6190 int32_t ret_val;
6191 uint16_t phy_data;
6192
6193 DEBUGFUNC("e1000_check_polarity");
6194
6195 if ((hw->phy_type == e1000_phy_m88) ||
6196 (hw->phy_type == e1000_phy_gg82563)) {
6197 /* return the Polarity bit in the Status register. */
6198 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6199 &phy_data);
6200 if(ret_val)
6201 return ret_val;
6202 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6203 M88E1000_PSSR_REV_POLARITY_SHIFT;
6204 } else if(hw->phy_type == e1000_phy_igp ||
6205 hw->phy_type == e1000_phy_igp_2) {
6206 /* Read the Status register to check the speed */
6207 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6208 &phy_data);
6209 if(ret_val)
6210 return ret_val;
6211
6212 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6213 * find the polarity status */
6214 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6215 IGP01E1000_PSSR_SPEED_1000MBPS) {
6216
6217 /* Read the GIG initialization PCS register (0x00B4) */
6218 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6219 &phy_data);
6220 if(ret_val)
6221 return ret_val;
6222
6223 /* Check the polarity bits */
6224 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
6225 } else {
6226 /* For 10 Mbps, read the polarity bit in the status register. (for
6227 * 100 Mbps this bit is always 0) */
6228 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6229 }
6230 }
6231 return E1000_SUCCESS;
6232 }
6233
6234 /******************************************************************************
6235 * Check if Downshift occured
6236 *
6237 * hw - Struct containing variables accessed by shared code
6238 * downshift - output parameter : 0 - No Downshift ocured.
6239 * 1 - Downshift ocured.
6240 *
6241 * returns: - E1000_ERR_XXX
6242 * E1000_SUCCESS
6243 *
6244 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6245 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6246 * Link Health register. In IGP this bit is latched high, so the driver must
6247 * read it immediately after link is established.
6248 *****************************************************************************/
6249 static int32_t
6250 e1000_check_downshift(struct e1000_hw *hw)
6251 {
6252 int32_t ret_val;
6253 uint16_t phy_data;
6254
6255 DEBUGFUNC("e1000_check_downshift");
6256
6257 if(hw->phy_type == e1000_phy_igp ||
6258 hw->phy_type == e1000_phy_igp_2) {
6259 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6260 &phy_data);
6261 if(ret_val)
6262 return ret_val;
6263
6264 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6265 } else if ((hw->phy_type == e1000_phy_m88) ||
6266 (hw->phy_type == e1000_phy_gg82563)) {
6267 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6268 &phy_data);
6269 if(ret_val)
6270 return ret_val;
6271
6272 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6273 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6274 }
6275
6276 return E1000_SUCCESS;
6277 }
6278
6279 /*****************************************************************************
6280 *
6281 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6282 * gigabit link is achieved to improve link quality.
6283 *
6284 * hw: Struct containing variables accessed by shared code
6285 *
6286 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6287 * E1000_SUCCESS at any other case.
6288 *
6289 ****************************************************************************/
6290
6291 static int32_t
6292 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6293 boolean_t link_up)
6294 {
6295 int32_t ret_val;
6296 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6297 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6298 {IGP01E1000_PHY_AGC_PARAM_A,
6299 IGP01E1000_PHY_AGC_PARAM_B,
6300 IGP01E1000_PHY_AGC_PARAM_C,
6301 IGP01E1000_PHY_AGC_PARAM_D};
6302 uint16_t min_length, max_length;
6303
6304 DEBUGFUNC("e1000_config_dsp_after_link_change");
6305
6306 if(hw->phy_type != e1000_phy_igp)
6307 return E1000_SUCCESS;
6308
6309 if(link_up) {
6310 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6311 if(ret_val) {
6312 DEBUGOUT("Error getting link speed and duplex\n");
6313 return ret_val;
6314 }
6315
6316 if(speed == SPEED_1000) {
6317
6318 e1000_get_cable_length(hw, &min_length, &max_length);
6319
6320 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6321 min_length >= e1000_igp_cable_length_50) {
6322
6323 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6324 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6325 &phy_data);
6326 if(ret_val)
6327 return ret_val;
6328
6329 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6330
6331 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6332 phy_data);
6333 if(ret_val)
6334 return ret_val;
6335 }
6336 hw->dsp_config_state = e1000_dsp_config_activated;
6337 }
6338
6339 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6340 (min_length < e1000_igp_cable_length_50)) {
6341
6342 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
6343 uint32_t idle_errs = 0;
6344
6345 /* clear previous idle error counts */
6346 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6347 &phy_data);
6348 if(ret_val)
6349 return ret_val;
6350
6351 for(i = 0; i < ffe_idle_err_timeout; i++) {
6352 udelay(1000);
6353 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6354 &phy_data);
6355 if(ret_val)
6356 return ret_val;
6357
6358 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
6359 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
6360 hw->ffe_config_state = e1000_ffe_config_active;
6361
6362 ret_val = e1000_write_phy_reg(hw,
6363 IGP01E1000_PHY_DSP_FFE,
6364 IGP01E1000_PHY_DSP_FFE_CM_CP);
6365 if(ret_val)
6366 return ret_val;
6367 break;
6368 }
6369
6370 if(idle_errs)
6371 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
6372 }
6373 }
6374 }
6375 } else {
6376 if(hw->dsp_config_state == e1000_dsp_config_activated) {
6377 /* Save off the current value of register 0x2F5B to be restored at
6378 * the end of the routines. */
6379 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6380
6381 if(ret_val)
6382 return ret_val;
6383
6384 /* Disable the PHY transmitter */
6385 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6386
6387 if(ret_val)
6388 return ret_val;
6389
6390 msec_delay_irq(20);
6391
6392 ret_val = e1000_write_phy_reg(hw, 0x0000,
6393 IGP01E1000_IEEE_FORCE_GIGA);
6394 if(ret_val)
6395 return ret_val;
6396 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6397 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
6398 if(ret_val)
6399 return ret_val;
6400
6401 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6402 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
6403
6404 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
6405 if(ret_val)
6406 return ret_val;
6407 }
6408
6409 ret_val = e1000_write_phy_reg(hw, 0x0000,
6410 IGP01E1000_IEEE_RESTART_AUTONEG);
6411 if(ret_val)
6412 return ret_val;
6413
6414 msec_delay_irq(20);
6415
6416 /* Now enable the transmitter */
6417 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
6418
6419 if(ret_val)
6420 return ret_val;
6421
6422 hw->dsp_config_state = e1000_dsp_config_enabled;
6423 }
6424
6425 if(hw->ffe_config_state == e1000_ffe_config_active) {
6426 /* Save off the current value of register 0x2F5B to be restored at
6427 * the end of the routines. */
6428 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6429
6430 if(ret_val)
6431 return ret_val;
6432
6433 /* Disable the PHY transmitter */
6434 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6435
6436 if(ret_val)
6437 return ret_val;
6438
6439 msec_delay_irq(20);
6440
6441 ret_val = e1000_write_phy_reg(hw, 0x0000,
6442 IGP01E1000_IEEE_FORCE_GIGA);
6443 if(ret_val)
6444 return ret_val;
6445 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
6446 IGP01E1000_PHY_DSP_FFE_DEFAULT);
6447 if(ret_val)
6448 return ret_val;
6449
6450 ret_val = e1000_write_phy_reg(hw, 0x0000,
6451 IGP01E1000_IEEE_RESTART_AUTONEG);
6452 if(ret_val)
6453 return ret_val;
6454
6455 msec_delay_irq(20);
6456
6457 /* Now enable the transmitter */
6458 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
6459
6460 if(ret_val)
6461 return ret_val;
6462
6463 hw->ffe_config_state = e1000_ffe_config_enabled;
6464 }
6465 }
6466 return E1000_SUCCESS;
6467 }
6468
6469 /*****************************************************************************
6470 * Set PHY to class A mode
6471 * Assumes the following operations will follow to enable the new class mode.
6472 * 1. Do a PHY soft reset
6473 * 2. Restart auto-negotiation or force link.
6474 *
6475 * hw - Struct containing variables accessed by shared code
6476 ****************************************************************************/
6477 static int32_t
6478 e1000_set_phy_mode(struct e1000_hw *hw)
6479 {
6480 int32_t ret_val;
6481 uint16_t eeprom_data;
6482
6483 DEBUGFUNC("e1000_set_phy_mode");
6484
6485 if((hw->mac_type == e1000_82545_rev_3) &&
6486 (hw->media_type == e1000_media_type_copper)) {
6487 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
6488 if(ret_val) {
6489 return ret_val;
6490 }
6491
6492 if((eeprom_data != EEPROM_RESERVED_WORD) &&
6493 (eeprom_data & EEPROM_PHY_CLASS_A)) {
6494 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
6495 if(ret_val)
6496 return ret_val;
6497 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
6498 if(ret_val)
6499 return ret_val;
6500
6501 hw->phy_reset_disable = FALSE;
6502 }
6503 }
6504
6505 return E1000_SUCCESS;
6506 }
6507
6508 /*****************************************************************************
6509 *
6510 * This function sets the lplu state according to the active flag. When
6511 * activating lplu this function also disables smart speed and vise versa.
6512 * lplu will not be activated unless the device autonegotiation advertisment
6513 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
6514 * hw: Struct containing variables accessed by shared code
6515 * active - true to enable lplu false to disable lplu.
6516 *
6517 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6518 * E1000_SUCCESS at any other case.
6519 *
6520 ****************************************************************************/
6521
6522 static int32_t
6523 e1000_set_d3_lplu_state(struct e1000_hw *hw,
6524 boolean_t active)
6525 {
6526 int32_t ret_val;
6527 uint16_t phy_data;
6528 DEBUGFUNC("e1000_set_d3_lplu_state");
6529
6530 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
6531 return E1000_SUCCESS;
6532
6533 /* During driver activity LPLU should not be used or it will attain link
6534 * from the lowest speeds starting from 10Mbps. The capability is used for
6535 * Dx transitions and states */
6536 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
6537 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
6538 if(ret_val)
6539 return ret_val;
6540 } else {
6541 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6542 if(ret_val)
6543 return ret_val;
6544 }
6545
6546 if(!active) {
6547 if(hw->mac_type == e1000_82541_rev_2 ||
6548 hw->mac_type == e1000_82547_rev_2) {
6549 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
6550 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6551 if(ret_val)
6552 return ret_val;
6553 } else {
6554 phy_data &= ~IGP02E1000_PM_D3_LPLU;
6555 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6556 phy_data);
6557 if (ret_val)
6558 return ret_val;
6559 }
6560
6561 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6562 * Dx states where the power conservation is most important. During
6563 * driver activity we should enable SmartSpeed, so performance is
6564 * maintained. */
6565 if (hw->smart_speed == e1000_smart_speed_on) {
6566 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6567 &phy_data);
6568 if(ret_val)
6569 return ret_val;
6570
6571 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
6572 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6573 phy_data);
6574 if(ret_val)
6575 return ret_val;
6576 } else if (hw->smart_speed == e1000_smart_speed_off) {
6577 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6578 &phy_data);
6579 if (ret_val)
6580 return ret_val;
6581
6582 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6583 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6584 phy_data);
6585 if(ret_val)
6586 return ret_val;
6587 }
6588
6589 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
6590 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
6591 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
6592
6593 if(hw->mac_type == e1000_82541_rev_2 ||
6594 hw->mac_type == e1000_82547_rev_2) {
6595 phy_data |= IGP01E1000_GMII_FLEX_SPD;
6596 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6597 if(ret_val)
6598 return ret_val;
6599 } else {
6600 phy_data |= IGP02E1000_PM_D3_LPLU;
6601 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6602 phy_data);
6603 if (ret_val)
6604 return ret_val;
6605 }
6606
6607 /* When LPLU is enabled we should disable SmartSpeed */
6608 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
6609 if(ret_val)
6610 return ret_val;
6611
6612 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6613 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
6614 if(ret_val)
6615 return ret_val;
6616
6617 }
6618 return E1000_SUCCESS;
6619 }
6620
6621 /*****************************************************************************
6622 *
6623 * This function sets the lplu d0 state according to the active flag. When
6624 * activating lplu this function also disables smart speed and vise versa.
6625 * lplu will not be activated unless the device autonegotiation advertisment
6626 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
6627 * hw: Struct containing variables accessed by shared code
6628 * active - true to enable lplu false to disable lplu.
6629 *
6630 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6631 * E1000_SUCCESS at any other case.
6632 *
6633 ****************************************************************************/
6634
6635 static int32_t
6636 e1000_set_d0_lplu_state(struct e1000_hw *hw,
6637 boolean_t active)
6638 {
6639 int32_t ret_val;
6640 uint16_t phy_data;
6641 DEBUGFUNC("e1000_set_d0_lplu_state");
6642
6643 if(hw->mac_type <= e1000_82547_rev_2)
6644 return E1000_SUCCESS;
6645
6646 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6647 if(ret_val)
6648 return ret_val;
6649
6650 if (!active) {
6651 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6652 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6653 if (ret_val)
6654 return ret_val;
6655
6656 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6657 * Dx states where the power conservation is most important. During
6658 * driver activity we should enable SmartSpeed, so performance is
6659 * maintained. */
6660 if (hw->smart_speed == e1000_smart_speed_on) {
6661 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6662 &phy_data);
6663 if(ret_val)
6664 return ret_val;
6665
6666 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
6667 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6668 phy_data);
6669 if(ret_val)
6670 return ret_val;
6671 } else if (hw->smart_speed == e1000_smart_speed_off) {
6672 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6673 &phy_data);
6674 if (ret_val)
6675 return ret_val;
6676
6677 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6678 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6679 phy_data);
6680 if(ret_val)
6681 return ret_val;
6682 }
6683
6684
6685 } else {
6686
6687 phy_data |= IGP02E1000_PM_D0_LPLU;
6688 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6689 if (ret_val)
6690 return ret_val;
6691
6692 /* When LPLU is enabled we should disable SmartSpeed */
6693 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
6694 if(ret_val)
6695 return ret_val;
6696
6697 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6698 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
6699 if(ret_val)
6700 return ret_val;
6701
6702 }
6703 return E1000_SUCCESS;
6704 }
6705
6706 /******************************************************************************
6707 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
6708 *
6709 * hw - Struct containing variables accessed by shared code
6710 *****************************************************************************/
6711 static int32_t
6712 e1000_set_vco_speed(struct e1000_hw *hw)
6713 {
6714 int32_t ret_val;
6715 uint16_t default_page = 0;
6716 uint16_t phy_data;
6717
6718 DEBUGFUNC("e1000_set_vco_speed");
6719
6720 switch(hw->mac_type) {
6721 case e1000_82545_rev_3:
6722 case e1000_82546_rev_3:
6723 break;
6724 default:
6725 return E1000_SUCCESS;
6726 }
6727
6728 /* Set PHY register 30, page 5, bit 8 to 0 */
6729
6730 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
6731 if(ret_val)
6732 return ret_val;
6733
6734 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
6735 if(ret_val)
6736 return ret_val;
6737
6738 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6739 if(ret_val)
6740 return ret_val;
6741
6742 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
6743 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6744 if(ret_val)
6745 return ret_val;
6746
6747 /* Set PHY register 30, page 4, bit 11 to 1 */
6748
6749 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
6750 if(ret_val)
6751 return ret_val;
6752
6753 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6754 if(ret_val)
6755 return ret_val;
6756
6757 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
6758 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6759 if(ret_val)
6760 return ret_val;
6761
6762 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
6763 if(ret_val)
6764 return ret_val;
6765
6766 return E1000_SUCCESS;
6767 }
6768
6769
6770 /*****************************************************************************
6771 * This function reads the cookie from ARC ram.
6772 *
6773 * returns: - E1000_SUCCESS .
6774 ****************************************************************************/
6775 int32_t
6776 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
6777 {
6778 uint8_t i;
6779 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
6780 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
6781
6782 length = (length >> 2);
6783 offset = (offset >> 2);
6784
6785 for (i = 0; i < length; i++) {
6786 *((uint32_t *) buffer + i) =
6787 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
6788 }
6789 return E1000_SUCCESS;
6790 }
6791
6792
6793 /*****************************************************************************
6794 * This function checks whether the HOST IF is enabled for command operaton
6795 * and also checks whether the previous command is completed.
6796 * It busy waits in case of previous command is not completed.
6797 *
6798 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
6799 * timeout
6800 * - E1000_SUCCESS for success.
6801 ****************************************************************************/
6802 static int32_t
6803 e1000_mng_enable_host_if(struct e1000_hw * hw)
6804 {
6805 uint32_t hicr;
6806 uint8_t i;
6807
6808 /* Check that the host interface is enabled. */
6809 hicr = E1000_READ_REG(hw, HICR);
6810 if ((hicr & E1000_HICR_EN) == 0) {
6811 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
6812 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6813 }
6814 /* check the previous command is completed */
6815 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
6816 hicr = E1000_READ_REG(hw, HICR);
6817 if (!(hicr & E1000_HICR_C))
6818 break;
6819 msec_delay_irq(1);
6820 }
6821
6822 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
6823 DEBUGOUT("Previous command timeout failed .\n");
6824 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6825 }
6826 return E1000_SUCCESS;
6827 }
6828
6829 /*****************************************************************************
6830 * This function writes the buffer content at the offset given on the host if.
6831 * It also does alignment considerations to do the writes in most efficient way.
6832 * Also fills up the sum of the buffer in *buffer parameter.
6833 *
6834 * returns - E1000_SUCCESS for success.
6835 ****************************************************************************/
6836 static int32_t
6837 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6838 uint16_t length, uint16_t offset, uint8_t *sum)
6839 {
6840 uint8_t *tmp;
6841 uint8_t *bufptr = buffer;
6842 uint32_t data;
6843 uint16_t remaining, i, j, prev_bytes;
6844
6845 /* sum = only sum of the data and it is not checksum */
6846
6847 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6848 return -E1000_ERR_PARAM;
6849 }
6850
6851 tmp = (uint8_t *)&data;
6852 prev_bytes = offset & 0x3;
6853 offset &= 0xFFFC;
6854 offset >>= 2;
6855
6856 if (prev_bytes) {
6857 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6858 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6859 *(tmp + j) = *bufptr++;
6860 *sum += *(tmp + j);
6861 }
6862 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6863 length -= j - prev_bytes;
6864 offset++;
6865 }
6866
6867 remaining = length & 0x3;
6868 length -= remaining;
6869
6870 /* Calculate length in DWORDs */
6871 length >>= 2;
6872
6873 /* The device driver writes the relevant command block into the
6874 * ram area. */
6875 for (i = 0; i < length; i++) {
6876 for (j = 0; j < sizeof(uint32_t); j++) {
6877 *(tmp + j) = *bufptr++;
6878 *sum += *(tmp + j);
6879 }
6880
6881 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6882 }
6883 if (remaining) {
6884 for (j = 0; j < sizeof(uint32_t); j++) {
6885 if (j < remaining)
6886 *(tmp + j) = *bufptr++;
6887 else
6888 *(tmp + j) = 0;
6889
6890 *sum += *(tmp + j);
6891 }
6892 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6893 }
6894
6895 return E1000_SUCCESS;
6896 }
6897
6898
6899 /*****************************************************************************
6900 * This function writes the command header after does the checksum calculation.
6901 *
6902 * returns - E1000_SUCCESS for success.
6903 ****************************************************************************/
6904 static int32_t
6905 e1000_mng_write_cmd_header(struct e1000_hw * hw,
6906 struct e1000_host_mng_command_header * hdr)
6907 {
6908 uint16_t i;
6909 uint8_t sum;
6910 uint8_t *buffer;
6911
6912 /* Write the whole command header structure which includes sum of
6913 * the buffer */
6914
6915 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6916
6917 sum = hdr->checksum;
6918 hdr->checksum = 0;
6919
6920 buffer = (uint8_t *) hdr;
6921 i = length;
6922 while(i--)
6923 sum += buffer[i];
6924
6925 hdr->checksum = 0 - sum;
6926
6927 length >>= 2;
6928 /* The device driver writes the relevant command block into the ram area. */
6929 for (i = 0; i < length; i++)
6930 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6931
6932 return E1000_SUCCESS;
6933 }
6934
6935
6936 /*****************************************************************************
6937 * This function indicates to ARC that a new command is pending which completes
6938 * one write operation by the driver.
6939 *
6940 * returns - E1000_SUCCESS for success.
6941 ****************************************************************************/
6942 static int32_t
6943 e1000_mng_write_commit(
6944 struct e1000_hw * hw)
6945 {
6946 uint32_t hicr;
6947
6948 hicr = E1000_READ_REG(hw, HICR);
6949 /* Setting this bit tells the ARC that a new command is pending. */
6950 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6951
6952 return E1000_SUCCESS;
6953 }
6954
6955
6956 /*****************************************************************************
6957 * This function checks the mode of the firmware.
6958 *
6959 * returns - TRUE when the mode is IAMT or FALSE.
6960 ****************************************************************************/
6961 boolean_t
6962 e1000_check_mng_mode(
6963 struct e1000_hw *hw)
6964 {
6965 uint32_t fwsm;
6966
6967 fwsm = E1000_READ_REG(hw, FWSM);
6968
6969 if((fwsm & E1000_FWSM_MODE_MASK) ==
6970 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6971 return TRUE;
6972
6973 return FALSE;
6974 }
6975
6976
6977 /*****************************************************************************
6978 * This function writes the dhcp info .
6979 ****************************************************************************/
6980 int32_t
6981 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
6982 uint16_t length)
6983 {
6984 int32_t ret_val;
6985 struct e1000_host_mng_command_header hdr;
6986
6987 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6988 hdr.command_length = length;
6989 hdr.reserved1 = 0;
6990 hdr.reserved2 = 0;
6991 hdr.checksum = 0;
6992
6993 ret_val = e1000_mng_enable_host_if(hw);
6994 if (ret_val == E1000_SUCCESS) {
6995 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6996 &(hdr.checksum));
6997 if (ret_val == E1000_SUCCESS) {
6998 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
6999 if (ret_val == E1000_SUCCESS)
7000 ret_val = e1000_mng_write_commit(hw);
7001 }
7002 }
7003 return ret_val;
7004 }
7005
7006
7007 /*****************************************************************************
7008 * This function calculates the checksum.
7009 *
7010 * returns - checksum of buffer contents.
7011 ****************************************************************************/
7012 uint8_t
7013 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7014 {
7015 uint8_t sum = 0;
7016 uint32_t i;
7017
7018 if (!buffer)
7019 return 0;
7020
7021 for (i=0; i < length; i++)
7022 sum += buffer[i];
7023
7024 return (uint8_t) (0 - sum);
7025 }
7026
7027 /*****************************************************************************
7028 * This function checks whether tx pkt filtering needs to be enabled or not.
7029 *
7030 * returns - TRUE for packet filtering or FALSE.
7031 ****************************************************************************/
7032 boolean_t
7033 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7034 {
7035 /* called in init as well as watchdog timer functions */
7036
7037 int32_t ret_val, checksum;
7038 boolean_t tx_filter = FALSE;
7039 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7040 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7041
7042 if (e1000_check_mng_mode(hw)) {
7043 ret_val = e1000_mng_enable_host_if(hw);
7044 if (ret_val == E1000_SUCCESS) {
7045 ret_val = e1000_host_if_read_cookie(hw, buffer);
7046 if (ret_val == E1000_SUCCESS) {
7047 checksum = hdr->checksum;
7048 hdr->checksum = 0;
7049 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7050 checksum == e1000_calculate_mng_checksum((char *)buffer,
7051 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7052 if (hdr->status &
7053 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7054 tx_filter = TRUE;
7055 } else
7056 tx_filter = TRUE;
7057 } else
7058 tx_filter = TRUE;
7059 }
7060 }
7061
7062 hw->tx_pkt_filtering = tx_filter;
7063 return tx_filter;
7064 }
7065
7066 /******************************************************************************
7067 * Verifies the hardware needs to allow ARPs to be processed by the host
7068 *
7069 * hw - Struct containing variables accessed by shared code
7070 *
7071 * returns: - TRUE/FALSE
7072 *
7073 *****************************************************************************/
7074 uint32_t
7075 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7076 {
7077 uint32_t manc;
7078 uint32_t fwsm, factps;
7079
7080 if (hw->asf_firmware_present) {
7081 manc = E1000_READ_REG(hw, MANC);
7082
7083 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7084 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7085 return FALSE;
7086 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7087 fwsm = E1000_READ_REG(hw, FWSM);
7088 factps = E1000_READ_REG(hw, FACTPS);
7089
7090 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7091 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7092 (factps & E1000_FACTPS_MNGCG))
7093 return TRUE;
7094 } else
7095 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7096 return TRUE;
7097 }
7098 return FALSE;
7099 }
7100
7101 static int32_t
7102 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7103 {
7104 int32_t ret_val;
7105 uint16_t mii_status_reg;
7106 uint16_t i;
7107
7108 /* Polarity reversal workaround for forced 10F/10H links. */
7109
7110 /* Disable the transmitter on the PHY */
7111
7112 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7113 if(ret_val)
7114 return ret_val;
7115 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7116 if(ret_val)
7117 return ret_val;
7118
7119 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7120 if(ret_val)
7121 return ret_val;
7122
7123 /* This loop will early-out if the NO link condition has been met. */
7124 for(i = PHY_FORCE_TIME; i > 0; i--) {
7125 /* Read the MII Status Register and wait for Link Status bit
7126 * to be clear.
7127 */
7128
7129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7130 if(ret_val)
7131 return ret_val;
7132
7133 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7134 if(ret_val)
7135 return ret_val;
7136
7137 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7138 msec_delay_irq(100);
7139 }
7140
7141 /* Recommended delay time after link has been lost */
7142 msec_delay_irq(1000);
7143
7144 /* Now we will re-enable th transmitter on the PHY */
7145
7146 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7147 if(ret_val)
7148 return ret_val;
7149 msec_delay_irq(50);
7150 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7151 if(ret_val)
7152 return ret_val;
7153 msec_delay_irq(50);
7154 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7155 if(ret_val)
7156 return ret_val;
7157 msec_delay_irq(50);
7158 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7159 if(ret_val)
7160 return ret_val;
7161
7162 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7163 if(ret_val)
7164 return ret_val;
7165
7166 /* This loop will early-out if the link condition has been met. */
7167 for(i = PHY_FORCE_TIME; i > 0; i--) {
7168 /* Read the MII Status Register and wait for Link Status bit
7169 * to be set.
7170 */
7171
7172 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7173 if(ret_val)
7174 return ret_val;
7175
7176 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7177 if(ret_val)
7178 return ret_val;
7179
7180 if(mii_status_reg & MII_SR_LINK_STATUS) break;
7181 msec_delay_irq(100);
7182 }
7183 return E1000_SUCCESS;
7184 }
7185
7186 /***************************************************************************
7187 *
7188 * Disables PCI-Express master access.
7189 *
7190 * hw: Struct containing variables accessed by shared code
7191 *
7192 * returns: - none.
7193 *
7194 ***************************************************************************/
7195 static void
7196 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7197 {
7198 uint32_t ctrl;
7199
7200 DEBUGFUNC("e1000_set_pci_express_master_disable");
7201
7202 if (hw->bus_type != e1000_bus_type_pci_express)
7203 return;
7204
7205 ctrl = E1000_READ_REG(hw, CTRL);
7206 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7207 E1000_WRITE_REG(hw, CTRL, ctrl);
7208 }
7209
7210 #if 0
7211 /***************************************************************************
7212 *
7213 * Enables PCI-Express master access.
7214 *
7215 * hw: Struct containing variables accessed by shared code
7216 *
7217 * returns: - none.
7218 *
7219 ***************************************************************************/
7220 void
7221 e1000_enable_pciex_master(struct e1000_hw *hw)
7222 {
7223 uint32_t ctrl;
7224
7225 DEBUGFUNC("e1000_enable_pciex_master");
7226
7227 if (hw->bus_type != e1000_bus_type_pci_express)
7228 return;
7229
7230 ctrl = E1000_READ_REG(hw, CTRL);
7231 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7232 E1000_WRITE_REG(hw, CTRL, ctrl);
7233 }
7234 #endif /* 0 */
7235
7236 /*******************************************************************************
7237 *
7238 * Disables PCI-Express master access and verifies there are no pending requests
7239 *
7240 * hw: Struct containing variables accessed by shared code
7241 *
7242 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7243 * caused the master requests to be disabled.
7244 * E1000_SUCCESS master requests disabled.
7245 *
7246 ******************************************************************************/
7247 int32_t
7248 e1000_disable_pciex_master(struct e1000_hw *hw)
7249 {
7250 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7251
7252 DEBUGFUNC("e1000_disable_pciex_master");
7253
7254 if (hw->bus_type != e1000_bus_type_pci_express)
7255 return E1000_SUCCESS;
7256
7257 e1000_set_pci_express_master_disable(hw);
7258
7259 while(timeout) {
7260 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7261 break;
7262 else
7263 udelay(100);
7264 timeout--;
7265 }
7266
7267 if(!timeout) {
7268 DEBUGOUT("Master requests are pending.\n");
7269 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7270 }
7271
7272 return E1000_SUCCESS;
7273 }
7274
7275 /*******************************************************************************
7276 *
7277 * Check for EEPROM Auto Read bit done.
7278 *
7279 * hw: Struct containing variables accessed by shared code
7280 *
7281 * returns: - E1000_ERR_RESET if fail to reset MAC
7282 * E1000_SUCCESS at any other case.
7283 *
7284 ******************************************************************************/
7285 static int32_t
7286 e1000_get_auto_rd_done(struct e1000_hw *hw)
7287 {
7288 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7289
7290 DEBUGFUNC("e1000_get_auto_rd_done");
7291
7292 switch (hw->mac_type) {
7293 default:
7294 msec_delay(5);
7295 break;
7296 case e1000_82571:
7297 case e1000_82572:
7298 case e1000_82573:
7299 case e1000_80003es2lan:
7300 while(timeout) {
7301 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
7302 else msec_delay(1);
7303 timeout--;
7304 }
7305
7306 if(!timeout) {
7307 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7308 return -E1000_ERR_RESET;
7309 }
7310 break;
7311 }
7312
7313 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
7314 * Need to wait for PHY configuration completion before accessing NVM
7315 * and PHY. */
7316 if (hw->mac_type == e1000_82573)
7317 msec_delay(25);
7318
7319 return E1000_SUCCESS;
7320 }
7321
7322 /***************************************************************************
7323 * Checks if the PHY configuration is done
7324 *
7325 * hw: Struct containing variables accessed by shared code
7326 *
7327 * returns: - E1000_ERR_RESET if fail to reset MAC
7328 * E1000_SUCCESS at any other case.
7329 *
7330 ***************************************************************************/
7331 static int32_t
7332 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7333 {
7334 int32_t timeout = PHY_CFG_TIMEOUT;
7335 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
7336
7337 DEBUGFUNC("e1000_get_phy_cfg_done");
7338
7339 switch (hw->mac_type) {
7340 default:
7341 msec_delay(10);
7342 break;
7343 case e1000_80003es2lan:
7344 /* Separate *_CFG_DONE_* bit for each port */
7345 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
7346 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7347 /* Fall Through */
7348 case e1000_82571:
7349 case e1000_82572:
7350 while (timeout) {
7351 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
7352 break;
7353 else
7354 msec_delay(1);
7355 timeout--;
7356 }
7357
7358 if (!timeout) {
7359 DEBUGOUT("MNG configuration cycle has not completed.\n");
7360 return -E1000_ERR_RESET;
7361 }
7362 break;
7363 }
7364
7365 return E1000_SUCCESS;
7366 }
7367
7368 /***************************************************************************
7369 *
7370 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
7371 * adapter or Eeprom access.
7372 *
7373 * hw: Struct containing variables accessed by shared code
7374 *
7375 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
7376 * E1000_SUCCESS at any other case.
7377 *
7378 ***************************************************************************/
7379 static int32_t
7380 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7381 {
7382 int32_t timeout;
7383 uint32_t swsm;
7384
7385 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
7386
7387 if(!hw->eeprom_semaphore_present)
7388 return E1000_SUCCESS;
7389
7390 if (hw->mac_type == e1000_80003es2lan) {
7391 /* Get the SW semaphore. */
7392 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
7393 return -E1000_ERR_EEPROM;
7394 }
7395
7396 /* Get the FW semaphore. */
7397 timeout = hw->eeprom.word_size + 1;
7398 while(timeout) {
7399 swsm = E1000_READ_REG(hw, SWSM);
7400 swsm |= E1000_SWSM_SWESMBI;
7401 E1000_WRITE_REG(hw, SWSM, swsm);
7402 /* if we managed to set the bit we got the semaphore. */
7403 swsm = E1000_READ_REG(hw, SWSM);
7404 if(swsm & E1000_SWSM_SWESMBI)
7405 break;
7406
7407 udelay(50);
7408 timeout--;
7409 }
7410
7411 if(!timeout) {
7412 /* Release semaphores */
7413 e1000_put_hw_eeprom_semaphore(hw);
7414 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
7415 return -E1000_ERR_EEPROM;
7416 }
7417
7418 return E1000_SUCCESS;
7419 }
7420
7421 /***************************************************************************
7422 * This function clears HW semaphore bits.
7423 *
7424 * hw: Struct containing variables accessed by shared code
7425 *
7426 * returns: - None.
7427 *
7428 ***************************************************************************/
7429 static void
7430 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7431 {
7432 uint32_t swsm;
7433
7434 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
7435
7436 if(!hw->eeprom_semaphore_present)
7437 return;
7438
7439 swsm = E1000_READ_REG(hw, SWSM);
7440 if (hw->mac_type == e1000_80003es2lan) {
7441 /* Release both semaphores. */
7442 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
7443 } else
7444 swsm &= ~(E1000_SWSM_SWESMBI);
7445 E1000_WRITE_REG(hw, SWSM, swsm);
7446 }
7447
7448 /***************************************************************************
7449 *
7450 * Obtaining software semaphore bit (SMBI) before resetting PHY.
7451 *
7452 * hw: Struct containing variables accessed by shared code
7453 *
7454 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
7455 * E1000_SUCCESS at any other case.
7456 *
7457 ***************************************************************************/
7458 int32_t
7459 e1000_get_software_semaphore(struct e1000_hw *hw)
7460 {
7461 int32_t timeout = hw->eeprom.word_size + 1;
7462 uint32_t swsm;
7463
7464 DEBUGFUNC("e1000_get_software_semaphore");
7465
7466 if (hw->mac_type != e1000_80003es2lan)
7467 return E1000_SUCCESS;
7468
7469 while(timeout) {
7470 swsm = E1000_READ_REG(hw, SWSM);
7471 /* If SMBI bit cleared, it is now set and we hold the semaphore */
7472 if(!(swsm & E1000_SWSM_SMBI))
7473 break;
7474 msec_delay_irq(1);
7475 timeout--;
7476 }
7477
7478 if(!timeout) {
7479 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
7480 return -E1000_ERR_RESET;
7481 }
7482
7483 return E1000_SUCCESS;
7484 }
7485
7486 /***************************************************************************
7487 *
7488 * Release semaphore bit (SMBI).
7489 *
7490 * hw: Struct containing variables accessed by shared code
7491 *
7492 ***************************************************************************/
7493 void
7494 e1000_release_software_semaphore(struct e1000_hw *hw)
7495 {
7496 uint32_t swsm;
7497
7498 DEBUGFUNC("e1000_release_software_semaphore");
7499
7500 if (hw->mac_type != e1000_80003es2lan)
7501 return;
7502
7503 swsm = E1000_READ_REG(hw, SWSM);
7504 /* Release the SW semaphores.*/
7505 swsm &= ~E1000_SWSM_SMBI;
7506 E1000_WRITE_REG(hw, SWSM, swsm);
7507 }
7508
7509 /******************************************************************************
7510 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
7511 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
7512 * the caller to figure out how to deal with it.
7513 *
7514 * hw - Struct containing variables accessed by shared code
7515 *
7516 * returns: - E1000_BLK_PHY_RESET
7517 * E1000_SUCCESS
7518 *
7519 *****************************************************************************/
7520 int32_t
7521 e1000_check_phy_reset_block(struct e1000_hw *hw)
7522 {
7523 uint32_t manc = 0;
7524
7525 if (hw->mac_type > e1000_82547_rev_2)
7526 manc = E1000_READ_REG(hw, MANC);
7527 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
7528 E1000_BLK_PHY_RESET : E1000_SUCCESS;
7529 }
7530
7531 static uint8_t
7532 e1000_arc_subsystem_valid(struct e1000_hw *hw)
7533 {
7534 uint32_t fwsm;
7535
7536 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
7537 * may not be provided a DMA clock when no manageability features are
7538 * enabled. We do not want to perform any reads/writes to these registers
7539 * if this is the case. We read FWSM to determine the manageability mode.
7540 */
7541 switch (hw->mac_type) {
7542 case e1000_82571:
7543 case e1000_82572:
7544 case e1000_82573:
7545 case e1000_80003es2lan:
7546 fwsm = E1000_READ_REG(hw, FWSM);
7547 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
7548 return TRUE;
7549 break;
7550 default:
7551 break;
7552 }
7553 return FALSE;
7554 }
7555
7556
7557
kernel-based virtual machine