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rt2x00: uncomment get_tsf
[linux-2.6/kvm.git] / drivers / net / wireless / rt2x00 / rt73usb.c
blob8f522342b16d314b589715475306800cea3240fa
1 /*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00usb.h"
37 #include "rt73usb.h"
38
39 /*
40 * Allow hardware encryption to be disabled.
41 */
42 static int modparam_nohwcrypt = 0;
43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64
65 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
66 const unsigned int word, const u8 value)
67 {
68 u32 reg;
69
70 mutex_lock(&rt2x00dev->csr_mutex);
71
72 /*
73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
75 */
76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
84 }
85
86 mutex_unlock(&rt2x00dev->csr_mutex);
87 }
88
89 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
90 const unsigned int word, u8 *value)
91 {
92 u32 reg;
93
94 mutex_lock(&rt2x00dev->csr_mutex);
95
96 /*
97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
103 */
104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
109
110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
111
112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
116
117 mutex_unlock(&rt2x00dev->csr_mutex);
118 }
119
120 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
121 const unsigned int word, const u32 value)
122 {
123 u32 reg;
124
125 if (!word)
126 return;
127
128 mutex_lock(&rt2x00dev->csr_mutex);
129
130 /*
131 * Wait until the RF becomes available, afterwards we
132 * can safely write the new data into the register.
133 */
134 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
135 reg = 0;
136 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
137 /*
138 * RF5225 and RF2527 contain 21 bits per RF register value,
139 * all others contain 20 bits.
140 */
141 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
142 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
143 rt2x00_rf(&rt2x00dev->chip, RF2527)));
144 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
145 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
146
147 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
148 rt2x00_rf_write(rt2x00dev, word, value);
149 }
150
151 mutex_unlock(&rt2x00dev->csr_mutex);
152 }
153
154 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
155 static const struct rt2x00debug rt73usb_rt2x00debug = {
156 .owner = THIS_MODULE,
157 .csr = {
158 .read = rt2x00usb_register_read,
159 .write = rt2x00usb_register_write,
160 .flags = RT2X00DEBUGFS_OFFSET,
161 .word_base = CSR_REG_BASE,
162 .word_size = sizeof(u32),
163 .word_count = CSR_REG_SIZE / sizeof(u32),
164 },
165 .eeprom = {
166 .read = rt2x00_eeprom_read,
167 .write = rt2x00_eeprom_write,
168 .word_base = EEPROM_BASE,
169 .word_size = sizeof(u16),
170 .word_count = EEPROM_SIZE / sizeof(u16),
171 },
172 .bbp = {
173 .read = rt73usb_bbp_read,
174 .write = rt73usb_bbp_write,
175 .word_base = BBP_BASE,
176 .word_size = sizeof(u8),
177 .word_count = BBP_SIZE / sizeof(u8),
178 },
179 .rf = {
180 .read = rt2x00_rf_read,
181 .write = rt73usb_rf_write,
182 .word_base = RF_BASE,
183 .word_size = sizeof(u32),
184 .word_count = RF_SIZE / sizeof(u32),
185 },
186 };
187 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
188
189 #ifdef CONFIG_RT2X00_LIB_RFKILL
190 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
191 {
192 u32 reg;
193
194 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
195 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
196 }
197 #else
198 #define rt73usb_rfkill_poll NULL
199 #endif /* CONFIG_RT2X00_LIB_RFKILL */
200
201 #ifdef CONFIG_RT2X00_LIB_LEDS
202 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
203 enum led_brightness brightness)
204 {
205 struct rt2x00_led *led =
206 container_of(led_cdev, struct rt2x00_led, led_dev);
207 unsigned int enabled = brightness != LED_OFF;
208 unsigned int a_mode =
209 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
210 unsigned int bg_mode =
211 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
212
213 if (led->type == LED_TYPE_RADIO) {
214 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
215 MCU_LEDCS_RADIO_STATUS, enabled);
216
217 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
218 0, led->rt2x00dev->led_mcu_reg,
219 REGISTER_TIMEOUT);
220 } else if (led->type == LED_TYPE_ASSOC) {
221 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
222 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
223 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
224 MCU_LEDCS_LINK_A_STATUS, a_mode);
225
226 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
227 0, led->rt2x00dev->led_mcu_reg,
228 REGISTER_TIMEOUT);
229 } else if (led->type == LED_TYPE_QUALITY) {
230 /*
231 * The brightness is divided into 6 levels (0 - 5),
232 * this means we need to convert the brightness
233 * argument into the matching level within that range.
234 */
235 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
236 brightness / (LED_FULL / 6),
237 led->rt2x00dev->led_mcu_reg,
238 REGISTER_TIMEOUT);
239 }
240 }
241
242 static int rt73usb_blink_set(struct led_classdev *led_cdev,
243 unsigned long *delay_on,
244 unsigned long *delay_off)
245 {
246 struct rt2x00_led *led =
247 container_of(led_cdev, struct rt2x00_led, led_dev);
248 u32 reg;
249
250 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
251 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
252 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
253 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
254
255 return 0;
256 }
257
258 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
259 struct rt2x00_led *led,
260 enum led_type type)
261 {
262 led->rt2x00dev = rt2x00dev;
263 led->type = type;
264 led->led_dev.brightness_set = rt73usb_brightness_set;
265 led->led_dev.blink_set = rt73usb_blink_set;
266 led->flags = LED_INITIALIZED;
267 }
268 #endif /* CONFIG_RT2X00_LIB_LEDS */
269
270 /*
271 * Configuration handlers.
272 */
273 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00lib_crypto *crypto,
275 struct ieee80211_key_conf *key)
276 {
277 struct hw_key_entry key_entry;
278 struct rt2x00_field32 field;
279 int timeout;
280 u32 mask;
281 u32 reg;
282
283 if (crypto->cmd == SET_KEY) {
284 /*
285 * rt2x00lib can't determine the correct free
286 * key_idx for shared keys. We have 1 register
287 * with key valid bits. The goal is simple, read
288 * the register, if that is full we have no slots
289 * left.
290 * Note that each BSS is allowed to have up to 4
291 * shared keys, so put a mask over the allowed
292 * entries.
293 */
294 mask = (0xf << crypto->bssidx);
295
296 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
297 reg &= mask;
298
299 if (reg && reg == mask)
300 return -ENOSPC;
301
302 key->hw_key_idx += reg ? ffz(reg) : 0;
303
304 /*
305 * Upload key to hardware
306 */
307 memcpy(key_entry.key, crypto->key,
308 sizeof(key_entry.key));
309 memcpy(key_entry.tx_mic, crypto->tx_mic,
310 sizeof(key_entry.tx_mic));
311 memcpy(key_entry.rx_mic, crypto->rx_mic,
312 sizeof(key_entry.rx_mic));
313
314 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
315 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
316 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
317 USB_VENDOR_REQUEST_OUT, reg,
318 &key_entry,
319 sizeof(key_entry),
320 timeout);
321
322 /*
323 * The cipher types are stored over 2 registers.
324 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
325 * bssidx 1 and 2 keys are stored in SEC_CSR5.
326 * Using the correct defines correctly will cause overhead,
327 * so just calculate the correct offset.
328 */
329 if (key->hw_key_idx < 8) {
330 field.bit_offset = (3 * key->hw_key_idx);
331 field.bit_mask = 0x7 << field.bit_offset;
332
333 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
334 rt2x00_set_field32(&reg, field, crypto->cipher);
335 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
336 } else {
337 field.bit_offset = (3 * (key->hw_key_idx - 8));
338 field.bit_mask = 0x7 << field.bit_offset;
339
340 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
341 rt2x00_set_field32(&reg, field, crypto->cipher);
342 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
343 }
344
345 /*
346 * The driver does not support the IV/EIV generation
347 * in hardware. However it doesn't support the IV/EIV
348 * inside the ieee80211 frame either, but requires it
349 * to be provided seperately for the descriptor.
350 * rt2x00lib will cut the IV/EIV data out of all frames
351 * given to us by mac80211, but we must tell mac80211
352 * to generate the IV/EIV data.
353 */
354 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
355 }
356
357 /*
358 * SEC_CSR0 contains only single-bit fields to indicate
359 * a particular key is valid. Because using the FIELD32()
360 * defines directly will cause a lot of overhead we use
361 * a calculation to determine the correct bit directly.
362 */
363 mask = 1 << key->hw_key_idx;
364
365 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
366 if (crypto->cmd == SET_KEY)
367 reg |= mask;
368 else if (crypto->cmd == DISABLE_KEY)
369 reg &= ~mask;
370 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
371
372 return 0;
373 }
374
375 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
376 struct rt2x00lib_crypto *crypto,
377 struct ieee80211_key_conf *key)
378 {
379 struct hw_pairwise_ta_entry addr_entry;
380 struct hw_key_entry key_entry;
381 int timeout;
382 u32 mask;
383 u32 reg;
384
385 if (crypto->cmd == SET_KEY) {
386 /*
387 * rt2x00lib can't determine the correct free
388 * key_idx for pairwise keys. We have 2 registers
389 * with key valid bits. The goal is simple, read
390 * the first register, if that is full move to
391 * the next register.
392 * When both registers are full, we drop the key,
393 * otherwise we use the first invalid entry.
394 */
395 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
396 if (reg && reg == ~0) {
397 key->hw_key_idx = 32;
398 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
399 if (reg && reg == ~0)
400 return -ENOSPC;
401 }
402
403 key->hw_key_idx += reg ? ffz(reg) : 0;
404
405 /*
406 * Upload key to hardware
407 */
408 memcpy(key_entry.key, crypto->key,
409 sizeof(key_entry.key));
410 memcpy(key_entry.tx_mic, crypto->tx_mic,
411 sizeof(key_entry.tx_mic));
412 memcpy(key_entry.rx_mic, crypto->rx_mic,
413 sizeof(key_entry.rx_mic));
414
415 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
416 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
417 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
418 USB_VENDOR_REQUEST_OUT, reg,
419 &key_entry,
420 sizeof(key_entry),
421 timeout);
422
423 /*
424 * Send the address and cipher type to the hardware register.
425 * This data fits within the CSR cache size, so we can use
426 * rt2x00usb_register_multiwrite() directly.
427 */
428 memset(&addr_entry, 0, sizeof(addr_entry));
429 memcpy(&addr_entry, crypto->address, ETH_ALEN);
430 addr_entry.cipher = crypto->cipher;
431
432 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
433 rt2x00usb_register_multiwrite(rt2x00dev, reg,
434 &addr_entry, sizeof(addr_entry));
435
436 /*
437 * Enable pairwise lookup table for given BSS idx,
438 * without this received frames will not be decrypted
439 * by the hardware.
440 */
441 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
442 reg |= (1 << crypto->bssidx);
443 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
444
445 /*
446 * The driver does not support the IV/EIV generation
447 * in hardware. However it doesn't support the IV/EIV
448 * inside the ieee80211 frame either, but requires it
449 * to be provided seperately for the descriptor.
450 * rt2x00lib will cut the IV/EIV data out of all frames
451 * given to us by mac80211, but we must tell mac80211
452 * to generate the IV/EIV data.
453 */
454 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
455 }
456
457 /*
458 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
459 * a particular key is valid. Because using the FIELD32()
460 * defines directly will cause a lot of overhead we use
461 * a calculation to determine the correct bit directly.
462 */
463 if (key->hw_key_idx < 32) {
464 mask = 1 << key->hw_key_idx;
465
466 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
467 if (crypto->cmd == SET_KEY)
468 reg |= mask;
469 else if (crypto->cmd == DISABLE_KEY)
470 reg &= ~mask;
471 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
472 } else {
473 mask = 1 << (key->hw_key_idx - 32);
474
475 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
476 if (crypto->cmd == SET_KEY)
477 reg |= mask;
478 else if (crypto->cmd == DISABLE_KEY)
479 reg &= ~mask;
480 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
481 }
482
483 return 0;
484 }
485
486 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
487 const unsigned int filter_flags)
488 {
489 u32 reg;
490
491 /*
492 * Start configuration steps.
493 * Note that the version error will always be dropped
494 * and broadcast frames will always be accepted since
495 * there is no filter for it at this time.
496 */
497 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
498 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
499 !(filter_flags & FIF_FCSFAIL));
500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
501 !(filter_flags & FIF_PLCPFAIL));
502 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
503 !(filter_flags & FIF_CONTROL));
504 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
505 !(filter_flags & FIF_PROMISC_IN_BSS));
506 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
507 !(filter_flags & FIF_PROMISC_IN_BSS) &&
508 !rt2x00dev->intf_ap_count);
509 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
510 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
511 !(filter_flags & FIF_ALLMULTI));
512 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
513 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
514 !(filter_flags & FIF_CONTROL));
515 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
516 }
517
518 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
519 struct rt2x00_intf *intf,
520 struct rt2x00intf_conf *conf,
521 const unsigned int flags)
522 {
523 unsigned int beacon_base;
524 u32 reg;
525
526 if (flags & CONFIG_UPDATE_TYPE) {
527 /*
528 * Clear current synchronisation setup.
529 * For the Beacon base registers we only need to clear
530 * the first byte since that byte contains the VALID and OWNER
531 * bits which (when set to 0) will invalidate the entire beacon.
532 */
533 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
534 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
535
536 /*
537 * Enable synchronisation.
538 */
539 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
540 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
541 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
542 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
543 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
544 }
545
546 if (flags & CONFIG_UPDATE_MAC) {
547 reg = le32_to_cpu(conf->mac[1]);
548 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
549 conf->mac[1] = cpu_to_le32(reg);
550
551 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
552 conf->mac, sizeof(conf->mac));
553 }
554
555 if (flags & CONFIG_UPDATE_BSSID) {
556 reg = le32_to_cpu(conf->bssid[1]);
557 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
558 conf->bssid[1] = cpu_to_le32(reg);
559
560 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
561 conf->bssid, sizeof(conf->bssid));
562 }
563 }
564
565 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
566 struct rt2x00lib_erp *erp)
567 {
568 u32 reg;
569
570 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
571 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
572 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
573
574 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
575 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
576 !!erp->short_preamble);
577 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
578
579 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
580
581 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
582 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
583 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
584
585 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
586 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
587 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
588 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
589 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
590 }
591
592 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
593 struct antenna_setup *ant)
594 {
595 u8 r3;
596 u8 r4;
597 u8 r77;
598 u8 temp;
599
600 rt73usb_bbp_read(rt2x00dev, 3, &r3);
601 rt73usb_bbp_read(rt2x00dev, 4, &r4);
602 rt73usb_bbp_read(rt2x00dev, 77, &r77);
603
604 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
605
606 /*
607 * Configure the RX antenna.
608 */
609 switch (ant->rx) {
610 case ANTENNA_HW_DIVERSITY:
611 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
612 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
613 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
614 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
615 break;
616 case ANTENNA_A:
617 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
618 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
619 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
620 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
621 else
622 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
623 break;
624 case ANTENNA_B:
625 default:
626 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
627 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
628 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
629 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
630 else
631 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
632 break;
633 }
634
635 rt73usb_bbp_write(rt2x00dev, 77, r77);
636 rt73usb_bbp_write(rt2x00dev, 3, r3);
637 rt73usb_bbp_write(rt2x00dev, 4, r4);
638 }
639
640 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
641 struct antenna_setup *ant)
642 {
643 u8 r3;
644 u8 r4;
645 u8 r77;
646
647 rt73usb_bbp_read(rt2x00dev, 3, &r3);
648 rt73usb_bbp_read(rt2x00dev, 4, &r4);
649 rt73usb_bbp_read(rt2x00dev, 77, &r77);
650
651 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
652 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
653 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
654
655 /*
656 * Configure the RX antenna.
657 */
658 switch (ant->rx) {
659 case ANTENNA_HW_DIVERSITY:
660 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
661 break;
662 case ANTENNA_A:
663 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
664 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
665 break;
666 case ANTENNA_B:
667 default:
668 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
669 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
670 break;
671 }
672
673 rt73usb_bbp_write(rt2x00dev, 77, r77);
674 rt73usb_bbp_write(rt2x00dev, 3, r3);
675 rt73usb_bbp_write(rt2x00dev, 4, r4);
676 }
677
678 struct antenna_sel {
679 u8 word;
680 /*
681 * value[0] -> non-LNA
682 * value[1] -> LNA
683 */
684 u8 value[2];
685 };
686
687 static const struct antenna_sel antenna_sel_a[] = {
688 { 96, { 0x58, 0x78 } },
689 { 104, { 0x38, 0x48 } },
690 { 75, { 0xfe, 0x80 } },
691 { 86, { 0xfe, 0x80 } },
692 { 88, { 0xfe, 0x80 } },
693 { 35, { 0x60, 0x60 } },
694 { 97, { 0x58, 0x58 } },
695 { 98, { 0x58, 0x58 } },
696 };
697
698 static const struct antenna_sel antenna_sel_bg[] = {
699 { 96, { 0x48, 0x68 } },
700 { 104, { 0x2c, 0x3c } },
701 { 75, { 0xfe, 0x80 } },
702 { 86, { 0xfe, 0x80 } },
703 { 88, { 0xfe, 0x80 } },
704 { 35, { 0x50, 0x50 } },
705 { 97, { 0x48, 0x48 } },
706 { 98, { 0x48, 0x48 } },
707 };
708
709 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
710 struct antenna_setup *ant)
711 {
712 const struct antenna_sel *sel;
713 unsigned int lna;
714 unsigned int i;
715 u32 reg;
716
717 /*
718 * We should never come here because rt2x00lib is supposed
719 * to catch this and send us the correct antenna explicitely.
720 */
721 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
722 ant->tx == ANTENNA_SW_DIVERSITY);
723
724 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
725 sel = antenna_sel_a;
726 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
727 } else {
728 sel = antenna_sel_bg;
729 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
730 }
731
732 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
733 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
734
735 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
736
737 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
738 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
739 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
740 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
741
742 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
743
744 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
745 rt2x00_rf(&rt2x00dev->chip, RF5225))
746 rt73usb_config_antenna_5x(rt2x00dev, ant);
747 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
748 rt2x00_rf(&rt2x00dev->chip, RF2527))
749 rt73usb_config_antenna_2x(rt2x00dev, ant);
750 }
751
752 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
753 struct rt2x00lib_conf *libconf)
754 {
755 u16 eeprom;
756 short lna_gain = 0;
757
758 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
759 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
760 lna_gain += 14;
761
762 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
763 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
764 } else {
765 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
766 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
767 }
768
769 rt2x00dev->lna_gain = lna_gain;
770 }
771
772 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
773 struct rf_channel *rf, const int txpower)
774 {
775 u8 r3;
776 u8 r94;
777 u8 smart;
778
779 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
780 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
781
782 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
783 rt2x00_rf(&rt2x00dev->chip, RF2527));
784
785 rt73usb_bbp_read(rt2x00dev, 3, &r3);
786 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
787 rt73usb_bbp_write(rt2x00dev, 3, r3);
788
789 r94 = 6;
790 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
791 r94 += txpower - MAX_TXPOWER;
792 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
793 r94 += txpower;
794 rt73usb_bbp_write(rt2x00dev, 94, r94);
795
796 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
797 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
798 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
799 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
800
801 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
802 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
803 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
804 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
805
806 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
807 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
808 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
809 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
810
811 udelay(10);
812 }
813
814 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
815 const int txpower)
816 {
817 struct rf_channel rf;
818
819 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
820 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
821 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
822 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
823
824 rt73usb_config_channel(rt2x00dev, &rf, txpower);
825 }
826
827 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
828 struct rt2x00lib_conf *libconf)
829 {
830 u32 reg;
831
832 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
833 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
834 libconf->conf->long_frame_max_tx_count);
835 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
836 libconf->conf->short_frame_max_tx_count);
837 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
838 }
839
840 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
841 struct rt2x00lib_conf *libconf)
842 {
843 u32 reg;
844
845 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
846 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
847 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
848
849 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
850 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
851 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
852
853 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
854 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
855 libconf->conf->beacon_int * 16);
856 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
857 }
858
859 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
860 struct rt2x00lib_conf *libconf)
861 {
862 enum dev_state state =
863 (libconf->conf->flags & IEEE80211_CONF_PS) ?
864 STATE_SLEEP : STATE_AWAKE;
865 u32 reg;
866
867 if (state == STATE_SLEEP) {
868 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
869 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
870 libconf->conf->beacon_int - 10);
871 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
872 libconf->conf->listen_interval - 1);
873 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
874
875 /* We must first disable autowake before it can be enabled */
876 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
877 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
878
879 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
880 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
881
882 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
883 USB_MODE_SLEEP, REGISTER_TIMEOUT);
884 } else {
885 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
886 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
887
888 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
889 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
890 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
891 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
892 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
893 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
894 }
895 }
896
897 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
898 struct rt2x00lib_conf *libconf,
899 const unsigned int flags)
900 {
901 /* Always recalculate LNA gain before changing configuration */
902 rt73usb_config_lna_gain(rt2x00dev, libconf);
903
904 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
905 rt73usb_config_channel(rt2x00dev, &libconf->rf,
906 libconf->conf->power_level);
907 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
908 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
909 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
910 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
911 rt73usb_config_retry_limit(rt2x00dev, libconf);
912 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
913 rt73usb_config_duration(rt2x00dev, libconf);
914 if (flags & IEEE80211_CONF_CHANGE_PS)
915 rt73usb_config_ps(rt2x00dev, libconf);
916 }
917
918 /*
919 * Link tuning
920 */
921 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
922 struct link_qual *qual)
923 {
924 u32 reg;
925
926 /*
927 * Update FCS error count from register.
928 */
929 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
930 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
931
932 /*
933 * Update False CCA count from register.
934 */
935 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
936 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
937 }
938
939 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
940 struct link_qual *qual, u8 vgc_level)
941 {
942 if (qual->vgc_level != vgc_level) {
943 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
944 qual->vgc_level = vgc_level;
945 qual->vgc_level_reg = vgc_level;
946 }
947 }
948
949 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
950 struct link_qual *qual)
951 {
952 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
953 }
954
955 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
956 struct link_qual *qual, const u32 count)
957 {
958 u8 up_bound;
959 u8 low_bound;
960
961 /*
962 * Determine r17 bounds.
963 */
964 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
965 low_bound = 0x28;
966 up_bound = 0x48;
967
968 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
969 low_bound += 0x10;
970 up_bound += 0x10;
971 }
972 } else {
973 if (qual->rssi > -82) {
974 low_bound = 0x1c;
975 up_bound = 0x40;
976 } else if (qual->rssi > -84) {
977 low_bound = 0x1c;
978 up_bound = 0x20;
979 } else {
980 low_bound = 0x1c;
981 up_bound = 0x1c;
982 }
983
984 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
985 low_bound += 0x14;
986 up_bound += 0x10;
987 }
988 }
989
990 /*
991 * If we are not associated, we should go straight to the
992 * dynamic CCA tuning.
993 */
994 if (!rt2x00dev->intf_associated)
995 goto dynamic_cca_tune;
996
997 /*
998 * Special big-R17 for very short distance
999 */
1000 if (qual->rssi > -35) {
1001 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
1002 return;
1003 }
1004
1005 /*
1006 * Special big-R17 for short distance
1007 */
1008 if (qual->rssi >= -58) {
1009 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1010 return;
1011 }
1012
1013 /*
1014 * Special big-R17 for middle-short distance
1015 */
1016 if (qual->rssi >= -66) {
1017 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1018 return;
1019 }
1020
1021 /*
1022 * Special mid-R17 for middle distance
1023 */
1024 if (qual->rssi >= -74) {
1025 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1026 return;
1027 }
1028
1029 /*
1030 * Special case: Change up_bound based on the rssi.
1031 * Lower up_bound when rssi is weaker then -74 dBm.
1032 */
1033 up_bound -= 2 * (-74 - qual->rssi);
1034 if (low_bound > up_bound)
1035 up_bound = low_bound;
1036
1037 if (qual->vgc_level > up_bound) {
1038 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1039 return;
1040 }
1041
1042 dynamic_cca_tune:
1043
1044 /*
1045 * r17 does not yet exceed upper limit, continue and base
1046 * the r17 tuning on the false CCA count.
1047 */
1048 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1049 rt73usb_set_vgc(rt2x00dev, qual,
1050 min_t(u8, qual->vgc_level + 4, up_bound));
1051 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1052 rt73usb_set_vgc(rt2x00dev, qual,
1053 max_t(u8, qual->vgc_level - 4, low_bound));
1054 }
1055
1056 /*
1057 * Firmware functions
1058 */
1059 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1060 {
1061 return FIRMWARE_RT2571;
1062 }
1063
1064 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1065 const u8 *data, const size_t len)
1066 {
1067 u16 fw_crc;
1068 u16 crc;
1069
1070 /*
1071 * Only support 2kb firmware files.
1072 */
1073 if (len != 2048)
1074 return FW_BAD_LENGTH;
1075
1076 /*
1077 * The last 2 bytes in the firmware array are the crc checksum itself,
1078 * this means that we should never pass those 2 bytes to the crc
1079 * algorithm.
1080 */
1081 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1082
1083 /*
1084 * Use the crc itu-t algorithm.
1085 */
1086 crc = crc_itu_t(0, data, len - 2);
1087 crc = crc_itu_t_byte(crc, 0);
1088 crc = crc_itu_t_byte(crc, 0);
1089
1090 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1091 }
1092
1093 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1094 const u8 *data, const size_t len)
1095 {
1096 unsigned int i;
1097 int status;
1098 u32 reg;
1099
1100 /*
1101 * Wait for stable hardware.
1102 */
1103 for (i = 0; i < 100; i++) {
1104 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1105 if (reg)
1106 break;
1107 msleep(1);
1108 }
1109
1110 if (!reg) {
1111 ERROR(rt2x00dev, "Unstable hardware.\n");
1112 return -EBUSY;
1113 }
1114
1115 /*
1116 * Write firmware to device.
1117 */
1118 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1119 USB_VENDOR_REQUEST_OUT,
1120 FIRMWARE_IMAGE_BASE,
1121 data, len,
1122 REGISTER_TIMEOUT32(len));
1123
1124 /*
1125 * Send firmware request to device to load firmware,
1126 * we need to specify a long timeout time.
1127 */
1128 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1129 0, USB_MODE_FIRMWARE,
1130 REGISTER_TIMEOUT_FIRMWARE);
1131 if (status < 0) {
1132 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1133 return status;
1134 }
1135
1136 return 0;
1137 }
1138
1139 /*
1140 * Initialization functions.
1141 */
1142 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1143 {
1144 u32 reg;
1145
1146 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1147 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1148 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1149 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1150 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1151
1152 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1153 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1154 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1155 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1156 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1157 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1158 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1159 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1160 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1161 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1162
1163 /*
1164 * CCK TXD BBP registers
1165 */
1166 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1167 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1168 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1169 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1170 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1171 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1172 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1173 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1174 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1175 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1176
1177 /*
1178 * OFDM TXD BBP registers
1179 */
1180 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1181 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1182 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1183 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1184 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1185 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1186 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1187 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1188
1189 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1190 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1191 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1192 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1193 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1194 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1195
1196 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1197 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1198 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1199 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1200 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1201 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1202
1203 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1204 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1205 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1206 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1207 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1208 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1209 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1210 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1211
1212 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1213
1214 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1215 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1216 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1217
1218 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1219
1220 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1221 return -EBUSY;
1222
1223 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1224
1225 /*
1226 * Invalidate all Shared Keys (SEC_CSR0),
1227 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1228 */
1229 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1230 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1231 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1232
1233 reg = 0x000023b0;
1234 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1235 rt2x00_rf(&rt2x00dev->chip, RF2527))
1236 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1237 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1238
1239 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1240 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1241 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1242
1243 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1244 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1245 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1246
1247 /*
1248 * Clear all beacons
1249 * For the Beacon base registers we only need to clear
1250 * the first byte since that byte contains the VALID and OWNER
1251 * bits which (when set to 0) will invalidate the entire beacon.
1252 */
1253 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1254 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1255 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1256 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1257
1258 /*
1259 * We must clear the error counters.
1260 * These registers are cleared on read,
1261 * so we may pass a useless variable to store the value.
1262 */
1263 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1264 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1265 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1266
1267 /*
1268 * Reset MAC and BBP registers.
1269 */
1270 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1271 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1272 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1273 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1274
1275 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1276 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1277 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1278 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1279
1280 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1281 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1282 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1283
1284 return 0;
1285 }
1286
1287 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1288 {
1289 unsigned int i;
1290 u8 value;
1291
1292 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1293 rt73usb_bbp_read(rt2x00dev, 0, &value);
1294 if ((value != 0xff) && (value != 0x00))
1295 return 0;
1296 udelay(REGISTER_BUSY_DELAY);
1297 }
1298
1299 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1300 return -EACCES;
1301 }
1302
1303 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1304 {
1305 unsigned int i;
1306 u16 eeprom;
1307 u8 reg_id;
1308 u8 value;
1309
1310 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1311 return -EACCES;
1312
1313 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1314 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1315 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1316 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1317 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1318 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1319 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1320 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1321 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1322 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1323 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1324 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1325 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1326 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1327 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1328 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1329 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1330 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1331 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1332 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1333 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1334 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1335 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1336 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1337 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1338
1339 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1340 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1341
1342 if (eeprom != 0xffff && eeprom != 0x0000) {
1343 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1344 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1345 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1346 }
1347 }
1348
1349 return 0;
1350 }
1351
1352 /*
1353 * Device state switch handlers.
1354 */
1355 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1356 enum dev_state state)
1357 {
1358 u32 reg;
1359
1360 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1361 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1362 (state == STATE_RADIO_RX_OFF) ||
1363 (state == STATE_RADIO_RX_OFF_LINK));
1364 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1365 }
1366
1367 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1368 {
1369 /*
1370 * Initialize all registers.
1371 */
1372 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1373 rt73usb_init_bbp(rt2x00dev)))
1374 return -EIO;
1375
1376 return 0;
1377 }
1378
1379 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1380 {
1381 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1382
1383 /*
1384 * Disable synchronisation.
1385 */
1386 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1387
1388 rt2x00usb_disable_radio(rt2x00dev);
1389 }
1390
1391 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1392 {
1393 u32 reg;
1394 unsigned int i;
1395 char put_to_sleep;
1396
1397 put_to_sleep = (state != STATE_AWAKE);
1398
1399 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1400 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1401 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1402 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1403
1404 /*
1405 * Device is not guaranteed to be in the requested state yet.
1406 * We must wait until the register indicates that the
1407 * device has entered the correct state.
1408 */
1409 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1410 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1411 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1412 if (state == !put_to_sleep)
1413 return 0;
1414 msleep(10);
1415 }
1416
1417 return -EBUSY;
1418 }
1419
1420 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1421 enum dev_state state)
1422 {
1423 int retval = 0;
1424
1425 switch (state) {
1426 case STATE_RADIO_ON:
1427 retval = rt73usb_enable_radio(rt2x00dev);
1428 break;
1429 case STATE_RADIO_OFF:
1430 rt73usb_disable_radio(rt2x00dev);
1431 break;
1432 case STATE_RADIO_RX_ON:
1433 case STATE_RADIO_RX_ON_LINK:
1434 case STATE_RADIO_RX_OFF:
1435 case STATE_RADIO_RX_OFF_LINK:
1436 rt73usb_toggle_rx(rt2x00dev, state);
1437 break;
1438 case STATE_RADIO_IRQ_ON:
1439 case STATE_RADIO_IRQ_OFF:
1440 /* No support, but no error either */
1441 break;
1442 case STATE_DEEP_SLEEP:
1443 case STATE_SLEEP:
1444 case STATE_STANDBY:
1445 case STATE_AWAKE:
1446 retval = rt73usb_set_state(rt2x00dev, state);
1447 break;
1448 default:
1449 retval = -ENOTSUPP;
1450 break;
1451 }
1452
1453 if (unlikely(retval))
1454 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1455 state, retval);
1456
1457 return retval;
1458 }
1459
1460 /*
1461 * TX descriptor initialization
1462 */
1463 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1464 struct sk_buff *skb,
1465 struct txentry_desc *txdesc)
1466 {
1467 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1468 __le32 *txd = skbdesc->desc;
1469 u32 word;
1470
1471 /*
1472 * Start writing the descriptor words.
1473 */
1474 rt2x00_desc_read(txd, 1, &word);
1475 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1476 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1477 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1478 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1479 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1480 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1481 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1482 rt2x00_desc_write(txd, 1, word);
1483
1484 rt2x00_desc_read(txd, 2, &word);
1485 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1486 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1487 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1488 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1489 rt2x00_desc_write(txd, 2, word);
1490
1491 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1492 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1493 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1494 }
1495
1496 rt2x00_desc_read(txd, 5, &word);
1497 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1498 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1499 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1500 rt2x00_desc_write(txd, 5, word);
1501
1502 rt2x00_desc_read(txd, 0, &word);
1503 rt2x00_set_field32(&word, TXD_W0_BURST,
1504 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1505 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1506 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1507 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1508 rt2x00_set_field32(&word, TXD_W0_ACK,
1509 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1510 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1511 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1512 rt2x00_set_field32(&word, TXD_W0_OFDM,
1513 (txdesc->rate_mode == RATE_MODE_OFDM));
1514 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1515 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1516 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1517 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1518 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1519 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1520 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1521 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1522 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1523 rt2x00_set_field32(&word, TXD_W0_BURST2,
1524 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1525 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1526 rt2x00_desc_write(txd, 0, word);
1527 }
1528
1529 /*
1530 * TX data initialization
1531 */
1532 static void rt73usb_write_beacon(struct queue_entry *entry)
1533 {
1534 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1535 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1536 unsigned int beacon_base;
1537 u32 reg;
1538
1539 /*
1540 * Add the descriptor in front of the skb.
1541 */
1542 skb_push(entry->skb, entry->queue->desc_size);
1543 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1544 skbdesc->desc = entry->skb->data;
1545
1546 /*
1547 * Disable beaconing while we are reloading the beacon data,
1548 * otherwise we might be sending out invalid data.
1549 */
1550 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1551 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1552 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1553 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1554 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1555
1556 /*
1557 * Write entire beacon with descriptor to register.
1558 */
1559 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1560 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1561 USB_VENDOR_REQUEST_OUT, beacon_base,
1562 entry->skb->data, entry->skb->len,
1563 REGISTER_TIMEOUT32(entry->skb->len));
1564
1565 /*
1566 * Clean up the beacon skb.
1567 */
1568 dev_kfree_skb(entry->skb);
1569 entry->skb = NULL;
1570 }
1571
1572 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1573 {
1574 int length;
1575
1576 /*
1577 * The length _must_ be a multiple of 4,
1578 * but it must _not_ be a multiple of the USB packet size.
1579 */
1580 length = roundup(entry->skb->len, 4);
1581 length += (4 * !(length % entry->queue->usb_maxpacket));
1582
1583 return length;
1584 }
1585
1586 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1587 const enum data_queue_qid queue)
1588 {
1589 u32 reg;
1590
1591 if (queue != QID_BEACON) {
1592 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1593 return;
1594 }
1595
1596 /*
1597 * For Wi-Fi faily generated beacons between participating stations.
1598 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1599 */
1600 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1601
1602 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1603 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1604 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1605 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1606 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1607 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1608 }
1609 }
1610
1611 /*
1612 * RX control handlers
1613 */
1614 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1615 {
1616 u8 offset = rt2x00dev->lna_gain;
1617 u8 lna;
1618
1619 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1620 switch (lna) {
1621 case 3:
1622 offset += 90;
1623 break;
1624 case 2:
1625 offset += 74;
1626 break;
1627 case 1:
1628 offset += 64;
1629 break;
1630 default:
1631 return 0;
1632 }
1633
1634 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1635 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1636 if (lna == 3 || lna == 2)
1637 offset += 10;
1638 } else {
1639 if (lna == 3)
1640 offset += 6;
1641 else if (lna == 2)
1642 offset += 8;
1643 }
1644 }
1645
1646 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1647 }
1648
1649 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1650 struct rxdone_entry_desc *rxdesc)
1651 {
1652 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1653 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1654 __le32 *rxd = (__le32 *)entry->skb->data;
1655 u32 word0;
1656 u32 word1;
1657
1658 /*
1659 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1660 * frame data in rt2x00usb.
1661 */
1662 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1663 rxd = (__le32 *)skbdesc->desc;
1664
1665 /*
1666 * It is now safe to read the descriptor on all architectures.
1667 */
1668 rt2x00_desc_read(rxd, 0, &word0);
1669 rt2x00_desc_read(rxd, 1, &word1);
1670
1671 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1672 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1673
1674 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1675 rxdesc->cipher =
1676 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1677 rxdesc->cipher_status =
1678 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1679 }
1680
1681 if (rxdesc->cipher != CIPHER_NONE) {
1682 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1683 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1684 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1685
1686 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1687 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1688
1689 /*
1690 * Hardware has stripped IV/EIV data from 802.11 frame during
1691 * decryption. It has provided the data seperately but rt2x00lib
1692 * should decide if it should be reinserted.
1693 */
1694 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1695
1696 /*
1697 * FIXME: Legacy driver indicates that the frame does
1698 * contain the Michael Mic. Unfortunately, in rt2x00
1699 * the MIC seems to be missing completely...
1700 */
1701 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1702
1703 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1704 rxdesc->flags |= RX_FLAG_DECRYPTED;
1705 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1706 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1707 }
1708
1709 /*
1710 * Obtain the status about this packet.
1711 * When frame was received with an OFDM bitrate,
1712 * the signal is the PLCP value. If it was received with
1713 * a CCK bitrate the signal is the rate in 100kbit/s.
1714 */
1715 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1716 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1717 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1718
1719 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1720 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1721 else
1722 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1723 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1724 rxdesc->dev_flags |= RXDONE_MY_BSS;
1725
1726 /*
1727 * Set skb pointers, and update frame information.
1728 */
1729 skb_pull(entry->skb, entry->queue->desc_size);
1730 skb_trim(entry->skb, rxdesc->size);
1731 }
1732
1733 /*
1734 * Device probe functions.
1735 */
1736 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1737 {
1738 u16 word;
1739 u8 *mac;
1740 s8 value;
1741
1742 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1743
1744 /*
1745 * Start validation of the data that has been read.
1746 */
1747 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1748 if (!is_valid_ether_addr(mac)) {
1749 random_ether_addr(mac);
1750 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1751 }
1752
1753 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1754 if (word == 0xffff) {
1755 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1756 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1757 ANTENNA_B);
1758 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1759 ANTENNA_B);
1760 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1761 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1762 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1763 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1764 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1765 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1766 }
1767
1768 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1769 if (word == 0xffff) {
1770 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1771 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1772 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1773 }
1774
1775 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1776 if (word == 0xffff) {
1777 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1778 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1779 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1780 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1781 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1782 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1783 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1784 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1785 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1786 LED_MODE_DEFAULT);
1787 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1788 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1789 }
1790
1791 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1792 if (word == 0xffff) {
1793 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1794 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1795 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1796 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1797 }
1798
1799 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1800 if (word == 0xffff) {
1801 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1802 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1803 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1804 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1805 } else {
1806 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1807 if (value < -10 || value > 10)
1808 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1809 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1810 if (value < -10 || value > 10)
1811 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1812 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1813 }
1814
1815 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1816 if (word == 0xffff) {
1817 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1818 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1819 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1820 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1821 } else {
1822 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1823 if (value < -10 || value > 10)
1824 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1825 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1826 if (value < -10 || value > 10)
1827 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1828 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1829 }
1830
1831 return 0;
1832 }
1833
1834 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1835 {
1836 u32 reg;
1837 u16 value;
1838 u16 eeprom;
1839
1840 /*
1841 * Read EEPROM word for configuration.
1842 */
1843 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1844
1845 /*
1846 * Identify RF chipset.
1847 */
1848 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1849 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1850 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1851
1852 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1853 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1854 return -ENODEV;
1855 }
1856
1857 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1858 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1859 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1860 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1861 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1862 return -ENODEV;
1863 }
1864
1865 /*
1866 * Identify default antenna configuration.
1867 */
1868 rt2x00dev->default_ant.tx =
1869 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1870 rt2x00dev->default_ant.rx =
1871 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1872
1873 /*
1874 * Read the Frame type.
1875 */
1876 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1877 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1878
1879 /*
1880 * Detect if this device has an hardware controlled radio.
1881 */
1882 #ifdef CONFIG_RT2X00_LIB_RFKILL
1883 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1884 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1885 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1886
1887 /*
1888 * Read frequency offset.
1889 */
1890 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1891 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1892
1893 /*
1894 * Read external LNA informations.
1895 */
1896 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1897
1898 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1899 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1900 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1901 }
1902
1903 /*
1904 * Store led settings, for correct led behaviour.
1905 */
1906 #ifdef CONFIG_RT2X00_LIB_LEDS
1907 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1908
1909 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1910 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1911 if (value == LED_MODE_SIGNAL_STRENGTH)
1912 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1913 LED_TYPE_QUALITY);
1914
1915 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1916 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1917 rt2x00_get_field16(eeprom,
1918 EEPROM_LED_POLARITY_GPIO_0));
1919 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1920 rt2x00_get_field16(eeprom,
1921 EEPROM_LED_POLARITY_GPIO_1));
1922 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1923 rt2x00_get_field16(eeprom,
1924 EEPROM_LED_POLARITY_GPIO_2));
1925 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1926 rt2x00_get_field16(eeprom,
1927 EEPROM_LED_POLARITY_GPIO_3));
1928 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1929 rt2x00_get_field16(eeprom,
1930 EEPROM_LED_POLARITY_GPIO_4));
1931 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1932 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1933 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1934 rt2x00_get_field16(eeprom,
1935 EEPROM_LED_POLARITY_RDY_G));
1936 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1937 rt2x00_get_field16(eeprom,
1938 EEPROM_LED_POLARITY_RDY_A));
1939 #endif /* CONFIG_RT2X00_LIB_LEDS */
1940
1941 return 0;
1942 }
1943
1944 /*
1945 * RF value list for RF2528
1946 * Supports: 2.4 GHz
1947 */
1948 static const struct rf_channel rf_vals_bg_2528[] = {
1949 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1950 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1951 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1952 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1953 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1954 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1955 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1956 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1957 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1958 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1959 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1960 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1961 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1962 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1963 };
1964
1965 /*
1966 * RF value list for RF5226
1967 * Supports: 2.4 GHz & 5.2 GHz
1968 */
1969 static const struct rf_channel rf_vals_5226[] = {
1970 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1971 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1972 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1973 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1974 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1975 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1976 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1977 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1978 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1979 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1980 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1981 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1982 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1983 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1984
1985 /* 802.11 UNI / HyperLan 2 */
1986 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1987 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1988 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1989 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1990 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1991 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1992 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1993 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1994
1995 /* 802.11 HyperLan 2 */
1996 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1997 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1998 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1999 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2000 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2001 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2002 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2003 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2004 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2005 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2006
2007 /* 802.11 UNII */
2008 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2009 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2010 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2011 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2012 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2013 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2014
2015 /* MMAC(Japan)J52 ch 34,38,42,46 */
2016 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2017 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2018 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2019 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2020 };
2021
2022 /*
2023 * RF value list for RF5225 & RF2527
2024 * Supports: 2.4 GHz & 5.2 GHz
2025 */
2026 static const struct rf_channel rf_vals_5225_2527[] = {
2027 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2028 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2029 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2030 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2031 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2032 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2033 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2034 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2035 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2036 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2037 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2038 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2039 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2040 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2041
2042 /* 802.11 UNI / HyperLan 2 */
2043 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2044 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2045 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2046 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2047 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2048 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2049 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2050 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2051
2052 /* 802.11 HyperLan 2 */
2053 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2054 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2055 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2056 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2057 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2058 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2059 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2060 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2061 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2062 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2063
2064 /* 802.11 UNII */
2065 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2066 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2067 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2068 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2069 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2070 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2071
2072 /* MMAC(Japan)J52 ch 34,38,42,46 */
2073 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2074 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2075 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2076 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2077 };
2078
2079
2080 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2081 {
2082 struct hw_mode_spec *spec = &rt2x00dev->spec;
2083 struct channel_info *info;
2084 char *tx_power;
2085 unsigned int i;
2086
2087 /*
2088 * Initialize all hw fields.
2089 */
2090 rt2x00dev->hw->flags =
2091 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2092 IEEE80211_HW_SIGNAL_DBM |
2093 IEEE80211_HW_SUPPORTS_PS |
2094 IEEE80211_HW_PS_NULLFUNC_STACK;
2095 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2096
2097 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2098 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2099 rt2x00_eeprom_addr(rt2x00dev,
2100 EEPROM_MAC_ADDR_0));
2101
2102 /*
2103 * Initialize hw_mode information.
2104 */
2105 spec->supported_bands = SUPPORT_BAND_2GHZ;
2106 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2107
2108 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2109 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2110 spec->channels = rf_vals_bg_2528;
2111 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2112 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2113 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2114 spec->channels = rf_vals_5226;
2115 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2116 spec->num_channels = 14;
2117 spec->channels = rf_vals_5225_2527;
2118 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2119 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2120 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2121 spec->channels = rf_vals_5225_2527;
2122 }
2123
2124 /*
2125 * Create channel information array
2126 */
2127 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2128 if (!info)
2129 return -ENOMEM;
2130
2131 spec->channels_info = info;
2132
2133 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2134 for (i = 0; i < 14; i++)
2135 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2136
2137 if (spec->num_channels > 14) {
2138 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2139 for (i = 14; i < spec->num_channels; i++)
2140 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2141 }
2142
2143 return 0;
2144 }
2145
2146 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2147 {
2148 int retval;
2149
2150 /*
2151 * Allocate eeprom data.
2152 */
2153 retval = rt73usb_validate_eeprom(rt2x00dev);
2154 if (retval)
2155 return retval;
2156
2157 retval = rt73usb_init_eeprom(rt2x00dev);
2158 if (retval)
2159 return retval;
2160
2161 /*
2162 * Initialize hw specifications.
2163 */
2164 retval = rt73usb_probe_hw_mode(rt2x00dev);
2165 if (retval)
2166 return retval;
2167
2168 /*
2169 * This device requires firmware.
2170 */
2171 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2172 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2173 if (!modparam_nohwcrypt)
2174 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2175
2176 /*
2177 * Set the rssi offset.
2178 */
2179 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2180
2181 return 0;
2182 }
2183
2184 /*
2185 * IEEE80211 stack callback functions.
2186 */
2187 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2188 const struct ieee80211_tx_queue_params *params)
2189 {
2190 struct rt2x00_dev *rt2x00dev = hw->priv;
2191 struct data_queue *queue;
2192 struct rt2x00_field32 field;
2193 int retval;
2194 u32 reg;
2195 u32 offset;
2196
2197 /*
2198 * First pass the configuration through rt2x00lib, that will
2199 * update the queue settings and validate the input. After that
2200 * we are free to update the registers based on the value
2201 * in the queue parameter.
2202 */
2203 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2204 if (retval)
2205 return retval;
2206
2207 /*
2208 * We only need to perform additional register initialization
2209 * for WMM queues/
2210 */
2211 if (queue_idx >= 4)
2212 return 0;
2213
2214 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2215
2216 /* Update WMM TXOP register */
2217 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2218 field.bit_offset = (queue_idx & 1) * 16;
2219 field.bit_mask = 0xffff << field.bit_offset;
2220
2221 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2222 rt2x00_set_field32(&reg, field, queue->txop);
2223 rt2x00usb_register_write(rt2x00dev, offset, reg);
2224
2225 /* Update WMM registers */
2226 field.bit_offset = queue_idx * 4;
2227 field.bit_mask = 0xf << field.bit_offset;
2228
2229 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2230 rt2x00_set_field32(&reg, field, queue->aifs);
2231 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2232
2233 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2234 rt2x00_set_field32(&reg, field, queue->cw_min);
2235 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2236
2237 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2238 rt2x00_set_field32(&reg, field, queue->cw_max);
2239 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2240
2241 return 0;
2242 }
2243
2244 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2245 {
2246 struct rt2x00_dev *rt2x00dev = hw->priv;
2247 u64 tsf;
2248 u32 reg;
2249
2250 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2251 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2252 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2253 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2254
2255 return tsf;
2256 }
2257
2258 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2259 .tx = rt2x00mac_tx,
2260 .start = rt2x00mac_start,
2261 .stop = rt2x00mac_stop,
2262 .add_interface = rt2x00mac_add_interface,
2263 .remove_interface = rt2x00mac_remove_interface,
2264 .config = rt2x00mac_config,
2265 .config_interface = rt2x00mac_config_interface,
2266 .configure_filter = rt2x00mac_configure_filter,
2267 .set_key = rt2x00mac_set_key,
2268 .get_stats = rt2x00mac_get_stats,
2269 .bss_info_changed = rt2x00mac_bss_info_changed,
2270 .conf_tx = rt73usb_conf_tx,
2271 .get_tx_stats = rt2x00mac_get_tx_stats,
2272 .get_tsf = rt73usb_get_tsf,
2273 };
2274
2275 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2276 .probe_hw = rt73usb_probe_hw,
2277 .get_firmware_name = rt73usb_get_firmware_name,
2278 .check_firmware = rt73usb_check_firmware,
2279 .load_firmware = rt73usb_load_firmware,
2280 .initialize = rt2x00usb_initialize,
2281 .uninitialize = rt2x00usb_uninitialize,
2282 .clear_entry = rt2x00usb_clear_entry,
2283 .set_device_state = rt73usb_set_device_state,
2284 .rfkill_poll = rt73usb_rfkill_poll,
2285 .link_stats = rt73usb_link_stats,
2286 .reset_tuner = rt73usb_reset_tuner,
2287 .link_tuner = rt73usb_link_tuner,
2288 .write_tx_desc = rt73usb_write_tx_desc,
2289 .write_tx_data = rt2x00usb_write_tx_data,
2290 .write_beacon = rt73usb_write_beacon,
2291 .get_tx_data_len = rt73usb_get_tx_data_len,
2292 .kick_tx_queue = rt73usb_kick_tx_queue,
2293 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2294 .fill_rxdone = rt73usb_fill_rxdone,
2295 .config_shared_key = rt73usb_config_shared_key,
2296 .config_pairwise_key = rt73usb_config_pairwise_key,
2297 .config_filter = rt73usb_config_filter,
2298 .config_intf = rt73usb_config_intf,
2299 .config_erp = rt73usb_config_erp,
2300 .config_ant = rt73usb_config_ant,
2301 .config = rt73usb_config,
2302 };
2303
2304 static const struct data_queue_desc rt73usb_queue_rx = {
2305 .entry_num = RX_ENTRIES,
2306 .data_size = DATA_FRAME_SIZE,
2307 .desc_size = RXD_DESC_SIZE,
2308 .priv_size = sizeof(struct queue_entry_priv_usb),
2309 };
2310
2311 static const struct data_queue_desc rt73usb_queue_tx = {
2312 .entry_num = TX_ENTRIES,
2313 .data_size = DATA_FRAME_SIZE,
2314 .desc_size = TXD_DESC_SIZE,
2315 .priv_size = sizeof(struct queue_entry_priv_usb),
2316 };
2317
2318 static const struct data_queue_desc rt73usb_queue_bcn = {
2319 .entry_num = 4 * BEACON_ENTRIES,
2320 .data_size = MGMT_FRAME_SIZE,
2321 .desc_size = TXINFO_SIZE,
2322 .priv_size = sizeof(struct queue_entry_priv_usb),
2323 };
2324
2325 static const struct rt2x00_ops rt73usb_ops = {
2326 .name = KBUILD_MODNAME,
2327 .max_sta_intf = 1,
2328 .max_ap_intf = 4,
2329 .eeprom_size = EEPROM_SIZE,
2330 .rf_size = RF_SIZE,
2331 .tx_queues = NUM_TX_QUEUES,
2332 .rx = &rt73usb_queue_rx,
2333 .tx = &rt73usb_queue_tx,
2334 .bcn = &rt73usb_queue_bcn,
2335 .lib = &rt73usb_rt2x00_ops,
2336 .hw = &rt73usb_mac80211_ops,
2337 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2338 .debugfs = &rt73usb_rt2x00debug,
2339 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2340 };
2341
2342 /*
2343 * rt73usb module information.
2344 */
2345 static struct usb_device_id rt73usb_device_table[] = {
2346 /* AboCom */
2347 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2348 /* Askey */
2349 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2350 /* ASUS */
2351 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2352 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2353 /* Belkin */
2354 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2355 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2356 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2357 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2358 /* Billionton */
2359 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2360 /* Buffalo */
2361 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2362 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2363 /* CNet */
2364 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2365 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2366 /* Conceptronic */
2367 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2368 /* Corega */
2369 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2370 /* D-Link */
2371 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2372 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2373 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2374 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2375 /* Gemtek */
2376 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2377 /* Gigabyte */
2378 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2379 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2380 /* Huawei-3Com */
2381 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2382 /* Hercules */
2383 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2384 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2385 /* Linksys */
2386 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2387 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2388 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2389 /* MSI */
2390 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2391 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2392 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2393 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2394 /* Ralink */
2395 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2396 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2397 /* Qcom */
2398 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2399 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2400 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2401 /* Senao */
2402 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2403 /* Sitecom */
2404 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2405 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2406 /* Surecom */
2407 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2408 /* Planex */
2409 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2410 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2411 { 0, }
2412 };
2413
2414 MODULE_AUTHOR(DRV_PROJECT);
2415 MODULE_VERSION(DRV_VERSION);
2416 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2417 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2418 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2419 MODULE_FIRMWARE(FIRMWARE_RT2571);
2420 MODULE_LICENSE("GPL");
2421
2422 static struct usb_driver rt73usb_driver = {
2423 .name = KBUILD_MODNAME,
2424 .id_table = rt73usb_device_table,
2425 .probe = rt2x00usb_probe,
2426 .disconnect = rt2x00usb_disconnect,
2427 .suspend = rt2x00usb_suspend,
2428 .resume = rt2x00usb_resume,
2429 };
2430
2431 static int __init rt73usb_init(void)
2432 {
2433 return usb_register(&rt73usb_driver);
2434 }
2435
2436 static void __exit rt73usb_exit(void)
2437 {
2438 usb_deregister(&rt73usb_driver);
2439 }
2440
2441 module_init(rt73usb_init);
2442 module_exit(rt73usb_exit);
kernel-based virtual machine