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tty: reorder ldisc locking
[linux-2.6/kvm.git] / drivers / ata / ata_piix.c
blob3971bc0a4838235ea26f4bff0b97ec7dd3335b69
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
118
119 /* constants for mapping table */
120 P0 = 0, /* port 0 */
121 P1 = 1, /* port 1 */
122 P2 = 2, /* port 2 */
123 P3 = 3, /* port 3 */
124 IDE = -1, /* IDE */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
127
128 PIIX_AHCI_DEVICE = 6,
129
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
132 };
133
134 enum piix_controller_ids {
135 /* controller IDs */
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
141 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
142 ich5_sata,
143 ich6_sata,
144 ich6m_sata,
145 ich8_sata,
146 ich8_2port_sata,
147 ich8m_apple_sata, /* locks up on second port enable */
148 tolapai_sata,
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
150 };
151
152 struct piix_map_db {
153 const u32 mask;
154 const u16 port_enable;
155 const int map[][4];
156 };
157
158 struct piix_host_priv {
159 const int *map;
160 u32 saved_iocfg;
161 spinlock_t sidpr_lock; /* FIXME: remove once locking in EH is fixed */
162 void __iomem *sidpr;
163 };
164
165 static int piix_init_one(struct pci_dev *pdev,
166 const struct pci_device_id *ent);
167 static void piix_remove_one(struct pci_dev *pdev);
168 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
169 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
170 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
171 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
172 static int ich_pata_cable_detect(struct ata_port *ap);
173 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
174 static int piix_sidpr_scr_read(struct ata_link *link,
175 unsigned int reg, u32 *val);
176 static int piix_sidpr_scr_write(struct ata_link *link,
177 unsigned int reg, u32 val);
178 static bool piix_irq_check(struct ata_port *ap);
179 #ifdef CONFIG_PM
180 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
181 static int piix_pci_device_resume(struct pci_dev *pdev);
182 #endif
183
184 static unsigned int in_module_init = 1;
185
186 static const struct pci_device_id piix_pci_tbl[] = {
187 /* Intel PIIX3 for the 430HX etc */
188 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
189 /* VMware ICH4 */
190 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
191 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
192 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
193 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
194 /* Intel PIIX4 */
195 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
196 /* Intel PIIX4 */
197 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
198 /* Intel PIIX */
199 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
200 /* Intel ICH (i810, i815, i840) UDMA 66*/
201 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
202 /* Intel ICH0 : UDMA 33*/
203 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
204 /* Intel ICH2M */
205 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
207 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* Intel ICH3M */
209 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH3 (E7500/1) UDMA 100 */
211 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
213 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 /* Intel ICH5 */
216 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* C-ICH (i810E2) */
218 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
220 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* ICH6 (and 6) (i915) UDMA 100 */
222 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
223 /* ICH7/7-R (i945, i975) UDMA 100*/
224 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
225 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
226 /* ICH8 Mobile PATA Controller */
227 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
228
229 /* SATA ports */
230
231 /* 82801EB (ICH5) */
232 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
233 /* 82801EB (ICH5) */
234 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
235 /* 6300ESB (ICH5 variant with broken PCS present bits) */
236 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
237 /* 6300ESB pretending RAID */
238 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
239 /* 82801FB/FW (ICH6/ICH6W) */
240 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
241 /* 82801FR/FRW (ICH6R/ICH6RW) */
242 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
243 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
244 * Attach iff the controller is in IDE mode. */
245 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
246 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
247 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
248 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
249 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
250 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
251 /* Enterprise Southbridge 2 (631xESB/632xESB) */
252 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
253 /* SATA Controller 1 IDE (ICH8) */
254 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
255 /* SATA Controller 2 IDE (ICH8) */
256 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
257 /* Mobile SATA Controller IDE (ICH8M), Apple */
258 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
259 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
260 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
261 /* Mobile SATA Controller IDE (ICH8M) */
262 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
263 /* SATA Controller IDE (ICH9) */
264 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
265 /* SATA Controller IDE (ICH9) */
266 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
267 /* SATA Controller IDE (ICH9) */
268 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
269 /* SATA Controller IDE (ICH9M) */
270 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
271 /* SATA Controller IDE (ICH9M) */
272 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
273 /* SATA Controller IDE (ICH9M) */
274 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
275 /* SATA Controller IDE (Tolapai) */
276 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
277 /* SATA Controller IDE (ICH10) */
278 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
279 /* SATA Controller IDE (ICH10) */
280 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
281 /* SATA Controller IDE (ICH10) */
282 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
283 /* SATA Controller IDE (ICH10) */
284 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
285 /* SATA Controller IDE (PCH) */
286 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
287 /* SATA Controller IDE (PCH) */
288 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
289 /* SATA Controller IDE (PCH) */
290 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
291 /* SATA Controller IDE (PCH) */
292 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
293 /* SATA Controller IDE (PCH) */
294 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
295 /* SATA Controller IDE (PCH) */
296 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
297 /* SATA Controller IDE (CPT) */
298 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
299 /* SATA Controller IDE (CPT) */
300 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
301 /* SATA Controller IDE (CPT) */
302 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303 /* SATA Controller IDE (CPT) */
304 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
305 { } /* terminate list */
306 };
307
308 static struct pci_driver piix_pci_driver = {
309 .name = DRV_NAME,
310 .id_table = piix_pci_tbl,
311 .probe = piix_init_one,
312 .remove = piix_remove_one,
313 #ifdef CONFIG_PM
314 .suspend = piix_pci_device_suspend,
315 .resume = piix_pci_device_resume,
316 #endif
317 };
318
319 static struct scsi_host_template piix_sht = {
320 ATA_BMDMA_SHT(DRV_NAME),
321 };
322
323 static struct ata_port_operations piix_sata_ops = {
324 .inherits = &ata_bmdma32_port_ops,
325 .sff_irq_check = piix_irq_check,
326 };
327
328 static struct ata_port_operations piix_pata_ops = {
329 .inherits = &piix_sata_ops,
330 .cable_detect = ata_cable_40wire,
331 .set_piomode = piix_set_piomode,
332 .set_dmamode = piix_set_dmamode,
333 .prereset = piix_pata_prereset,
334 };
335
336 static struct ata_port_operations piix_vmw_ops = {
337 .inherits = &piix_pata_ops,
338 .bmdma_status = piix_vmw_bmdma_status,
339 };
340
341 static struct ata_port_operations ich_pata_ops = {
342 .inherits = &piix_pata_ops,
343 .cable_detect = ich_pata_cable_detect,
344 .set_dmamode = ich_set_dmamode,
345 };
346
347 static struct ata_port_operations piix_sidpr_sata_ops = {
348 .inherits = &piix_sata_ops,
349 .hardreset = sata_std_hardreset,
350 .scr_read = piix_sidpr_scr_read,
351 .scr_write = piix_sidpr_scr_write,
352 };
353
354 static const struct piix_map_db ich5_map_db = {
355 .mask = 0x7,
356 .port_enable = 0x3,
357 .map = {
358 /* PM PS SM SS MAP */
359 { P0, NA, P1, NA }, /* 000b */
360 { P1, NA, P0, NA }, /* 001b */
361 { RV, RV, RV, RV },
362 { RV, RV, RV, RV },
363 { P0, P1, IDE, IDE }, /* 100b */
364 { P1, P0, IDE, IDE }, /* 101b */
365 { IDE, IDE, P0, P1 }, /* 110b */
366 { IDE, IDE, P1, P0 }, /* 111b */
367 },
368 };
369
370 static const struct piix_map_db ich6_map_db = {
371 .mask = 0x3,
372 .port_enable = 0xf,
373 .map = {
374 /* PM PS SM SS MAP */
375 { P0, P2, P1, P3 }, /* 00b */
376 { IDE, IDE, P1, P3 }, /* 01b */
377 { P0, P2, IDE, IDE }, /* 10b */
378 { RV, RV, RV, RV },
379 },
380 };
381
382 static const struct piix_map_db ich6m_map_db = {
383 .mask = 0x3,
384 .port_enable = 0x5,
385
386 /* Map 01b isn't specified in the doc but some notebooks use
387 * it anyway. MAP 01b have been spotted on both ICH6M and
388 * ICH7M.
389 */
390 .map = {
391 /* PM PS SM SS MAP */
392 { P0, P2, NA, NA }, /* 00b */
393 { IDE, IDE, P1, P3 }, /* 01b */
394 { P0, P2, IDE, IDE }, /* 10b */
395 { RV, RV, RV, RV },
396 },
397 };
398
399 static const struct piix_map_db ich8_map_db = {
400 .mask = 0x3,
401 .port_enable = 0xf,
402 .map = {
403 /* PM PS SM SS MAP */
404 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
405 { RV, RV, RV, RV },
406 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
407 { RV, RV, RV, RV },
408 },
409 };
410
411 static const struct piix_map_db ich8_2port_map_db = {
412 .mask = 0x3,
413 .port_enable = 0x3,
414 .map = {
415 /* PM PS SM SS MAP */
416 { P0, NA, P1, NA }, /* 00b */
417 { RV, RV, RV, RV }, /* 01b */
418 { RV, RV, RV, RV }, /* 10b */
419 { RV, RV, RV, RV },
420 },
421 };
422
423 static const struct piix_map_db ich8m_apple_map_db = {
424 .mask = 0x3,
425 .port_enable = 0x1,
426 .map = {
427 /* PM PS SM SS MAP */
428 { P0, NA, NA, NA }, /* 00b */
429 { RV, RV, RV, RV },
430 { P0, P2, IDE, IDE }, /* 10b */
431 { RV, RV, RV, RV },
432 },
433 };
434
435 static const struct piix_map_db tolapai_map_db = {
436 .mask = 0x3,
437 .port_enable = 0x3,
438 .map = {
439 /* PM PS SM SS MAP */
440 { P0, NA, P1, NA }, /* 00b */
441 { RV, RV, RV, RV }, /* 01b */
442 { RV, RV, RV, RV }, /* 10b */
443 { RV, RV, RV, RV },
444 },
445 };
446
447 static const struct piix_map_db *piix_map_db_table[] = {
448 [ich5_sata] = &ich5_map_db,
449 [ich6_sata] = &ich6_map_db,
450 [ich6m_sata] = &ich6m_map_db,
451 [ich8_sata] = &ich8_map_db,
452 [ich8_2port_sata] = &ich8_2port_map_db,
453 [ich8m_apple_sata] = &ich8m_apple_map_db,
454 [tolapai_sata] = &tolapai_map_db,
455 };
456
457 static struct ata_port_info piix_port_info[] = {
458 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
459 {
460 .flags = PIIX_PATA_FLAGS,
461 .pio_mask = ATA_PIO4,
462 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
463 .port_ops = &piix_pata_ops,
464 },
465
466 [piix_pata_33] = /* PIIX4 at 33MHz */
467 {
468 .flags = PIIX_PATA_FLAGS,
469 .pio_mask = ATA_PIO4,
470 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
471 .udma_mask = ATA_UDMA2,
472 .port_ops = &piix_pata_ops,
473 },
474
475 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
476 {
477 .flags = PIIX_PATA_FLAGS,
478 .pio_mask = ATA_PIO4,
479 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
480 .udma_mask = ATA_UDMA2,
481 .port_ops = &ich_pata_ops,
482 },
483
484 [ich_pata_66] = /* ICH controllers up to 66MHz */
485 {
486 .flags = PIIX_PATA_FLAGS,
487 .pio_mask = ATA_PIO4,
488 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
489 .udma_mask = ATA_UDMA4,
490 .port_ops = &ich_pata_ops,
491 },
492
493 [ich_pata_100] =
494 {
495 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
496 .pio_mask = ATA_PIO4,
497 .mwdma_mask = ATA_MWDMA12_ONLY,
498 .udma_mask = ATA_UDMA5,
499 .port_ops = &ich_pata_ops,
500 },
501
502 [ich_pata_100_nomwdma1] =
503 {
504 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
505 .pio_mask = ATA_PIO4,
506 .mwdma_mask = ATA_MWDMA2_ONLY,
507 .udma_mask = ATA_UDMA5,
508 .port_ops = &ich_pata_ops,
509 },
510
511 [ich5_sata] =
512 {
513 .flags = PIIX_SATA_FLAGS,
514 .pio_mask = ATA_PIO4,
515 .mwdma_mask = ATA_MWDMA2,
516 .udma_mask = ATA_UDMA6,
517 .port_ops = &piix_sata_ops,
518 },
519
520 [ich6_sata] =
521 {
522 .flags = PIIX_SATA_FLAGS,
523 .pio_mask = ATA_PIO4,
524 .mwdma_mask = ATA_MWDMA2,
525 .udma_mask = ATA_UDMA6,
526 .port_ops = &piix_sata_ops,
527 },
528
529 [ich6m_sata] =
530 {
531 .flags = PIIX_SATA_FLAGS,
532 .pio_mask = ATA_PIO4,
533 .mwdma_mask = ATA_MWDMA2,
534 .udma_mask = ATA_UDMA6,
535 .port_ops = &piix_sata_ops,
536 },
537
538 [ich8_sata] =
539 {
540 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
541 .pio_mask = ATA_PIO4,
542 .mwdma_mask = ATA_MWDMA2,
543 .udma_mask = ATA_UDMA6,
544 .port_ops = &piix_sata_ops,
545 },
546
547 [ich8_2port_sata] =
548 {
549 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
550 .pio_mask = ATA_PIO4,
551 .mwdma_mask = ATA_MWDMA2,
552 .udma_mask = ATA_UDMA6,
553 .port_ops = &piix_sata_ops,
554 },
555
556 [tolapai_sata] =
557 {
558 .flags = PIIX_SATA_FLAGS,
559 .pio_mask = ATA_PIO4,
560 .mwdma_mask = ATA_MWDMA2,
561 .udma_mask = ATA_UDMA6,
562 .port_ops = &piix_sata_ops,
563 },
564
565 [ich8m_apple_sata] =
566 {
567 .flags = PIIX_SATA_FLAGS,
568 .pio_mask = ATA_PIO4,
569 .mwdma_mask = ATA_MWDMA2,
570 .udma_mask = ATA_UDMA6,
571 .port_ops = &piix_sata_ops,
572 },
573
574 [piix_pata_vmw] =
575 {
576 .flags = PIIX_PATA_FLAGS,
577 .pio_mask = ATA_PIO4,
578 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
579 .udma_mask = ATA_UDMA2,
580 .port_ops = &piix_vmw_ops,
581 },
582
583 };
584
585 static struct pci_bits piix_enable_bits[] = {
586 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
587 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
588 };
589
590 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
591 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
592 MODULE_LICENSE("GPL");
593 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
594 MODULE_VERSION(DRV_VERSION);
595
596 struct ich_laptop {
597 u16 device;
598 u16 subvendor;
599 u16 subdevice;
600 };
601
602 /*
603 * List of laptops that use short cables rather than 80 wire
604 */
605
606 static const struct ich_laptop ich_laptop[] = {
607 /* devid, subvendor, subdev */
608 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
609 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
610 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
611 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
612 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
613 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
614 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
615 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
616 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
617 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
618 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
619 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
620 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
621 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
622 /* end marker */
623 { 0, }
624 };
625
626 /**
627 * ich_pata_cable_detect - Probe host controller cable detect info
628 * @ap: Port for which cable detect info is desired
629 *
630 * Read 80c cable indicator from ATA PCI device's PCI config
631 * register. This register is normally set by firmware (BIOS).
632 *
633 * LOCKING:
634 * None (inherited from caller).
635 */
636
637 static int ich_pata_cable_detect(struct ata_port *ap)
638 {
639 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
640 struct piix_host_priv *hpriv = ap->host->private_data;
641 const struct ich_laptop *lap = &ich_laptop[0];
642 u8 mask;
643
644 /* Check for specials - Acer Aspire 5602WLMi */
645 while (lap->device) {
646 if (lap->device == pdev->device &&
647 lap->subvendor == pdev->subsystem_vendor &&
648 lap->subdevice == pdev->subsystem_device)
649 return ATA_CBL_PATA40_SHORT;
650
651 lap++;
652 }
653
654 /* check BIOS cable detect results */
655 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
656 if ((hpriv->saved_iocfg & mask) == 0)
657 return ATA_CBL_PATA40;
658 return ATA_CBL_PATA80;
659 }
660
661 /**
662 * piix_pata_prereset - prereset for PATA host controller
663 * @link: Target link
664 * @deadline: deadline jiffies for the operation
665 *
666 * LOCKING:
667 * None (inherited from caller).
668 */
669 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
670 {
671 struct ata_port *ap = link->ap;
672 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
673
674 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
675 return -ENOENT;
676 return ata_sff_prereset(link, deadline);
677 }
678
679 static DEFINE_SPINLOCK(piix_lock);
680
681 /**
682 * piix_set_piomode - Initialize host controller PATA PIO timings
683 * @ap: Port whose timings we are configuring
684 * @adev: um
685 *
686 * Set PIO mode for device, in host controller PCI config space.
687 *
688 * LOCKING:
689 * None (inherited from caller).
690 */
691
692 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
693 {
694 struct pci_dev *dev = to_pci_dev(ap->host->dev);
695 unsigned long flags;
696 unsigned int pio = adev->pio_mode - XFER_PIO_0;
697 unsigned int is_slave = (adev->devno != 0);
698 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
699 unsigned int slave_port = 0x44;
700 u16 master_data;
701 u8 slave_data;
702 u8 udma_enable;
703 int control = 0;
704
705 /*
706 * See Intel Document 298600-004 for the timing programing rules
707 * for ICH controllers.
708 */
709
710 static const /* ISP RTC */
711 u8 timings[][2] = { { 0, 0 },
712 { 0, 0 },
713 { 1, 0 },
714 { 2, 1 },
715 { 2, 3 }, };
716
717 if (pio >= 2)
718 control |= 1; /* TIME1 enable */
719 if (ata_pio_need_iordy(adev))
720 control |= 2; /* IE enable */
721
722 /* Intel specifies that the PPE functionality is for disk only */
723 if (adev->class == ATA_DEV_ATA)
724 control |= 4; /* PPE enable */
725
726 spin_lock_irqsave(&piix_lock, flags);
727
728 /* PIO configuration clears DTE unconditionally. It will be
729 * programmed in set_dmamode which is guaranteed to be called
730 * after set_piomode if any DMA mode is available.
731 */
732 pci_read_config_word(dev, master_port, &master_data);
733 if (is_slave) {
734 /* clear TIME1|IE1|PPE1|DTE1 */
735 master_data &= 0xff0f;
736 /* Enable SITRE (separate slave timing register) */
737 master_data |= 0x4000;
738 /* enable PPE1, IE1 and TIME1 as needed */
739 master_data |= (control << 4);
740 pci_read_config_byte(dev, slave_port, &slave_data);
741 slave_data &= (ap->port_no ? 0x0f : 0xf0);
742 /* Load the timing nibble for this slave */
743 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
744 << (ap->port_no ? 4 : 0);
745 } else {
746 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
747 master_data &= 0xccf0;
748 /* Enable PPE, IE and TIME as appropriate */
749 master_data |= control;
750 /* load ISP and RCT */
751 master_data |=
752 (timings[pio][0] << 12) |
753 (timings[pio][1] << 8);
754 }
755 pci_write_config_word(dev, master_port, master_data);
756 if (is_slave)
757 pci_write_config_byte(dev, slave_port, slave_data);
758
759 /* Ensure the UDMA bit is off - it will be turned back on if
760 UDMA is selected */
761
762 if (ap->udma_mask) {
763 pci_read_config_byte(dev, 0x48, &udma_enable);
764 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
765 pci_write_config_byte(dev, 0x48, udma_enable);
766 }
767
768 spin_unlock_irqrestore(&piix_lock, flags);
769 }
770
771 /**
772 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
773 * @ap: Port whose timings we are configuring
774 * @adev: Drive in question
775 * @isich: set if the chip is an ICH device
776 *
777 * Set UDMA mode for device, in host controller PCI config space.
778 *
779 * LOCKING:
780 * None (inherited from caller).
781 */
782
783 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
784 {
785 struct pci_dev *dev = to_pci_dev(ap->host->dev);
786 unsigned long flags;
787 u8 master_port = ap->port_no ? 0x42 : 0x40;
788 u16 master_data;
789 u8 speed = adev->dma_mode;
790 int devid = adev->devno + 2 * ap->port_no;
791 u8 udma_enable = 0;
792
793 static const /* ISP RTC */
794 u8 timings[][2] = { { 0, 0 },
795 { 0, 0 },
796 { 1, 0 },
797 { 2, 1 },
798 { 2, 3 }, };
799
800 spin_lock_irqsave(&piix_lock, flags);
801
802 pci_read_config_word(dev, master_port, &master_data);
803 if (ap->udma_mask)
804 pci_read_config_byte(dev, 0x48, &udma_enable);
805
806 if (speed >= XFER_UDMA_0) {
807 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
808 u16 udma_timing;
809 u16 ideconf;
810 int u_clock, u_speed;
811
812 /*
813 * UDMA is handled by a combination of clock switching and
814 * selection of dividers
815 *
816 * Handy rule: Odd modes are UDMATIMx 01, even are 02
817 * except UDMA0 which is 00
818 */
819 u_speed = min(2 - (udma & 1), udma);
820 if (udma == 5)
821 u_clock = 0x1000; /* 100Mhz */
822 else if (udma > 2)
823 u_clock = 1; /* 66Mhz */
824 else
825 u_clock = 0; /* 33Mhz */
826
827 udma_enable |= (1 << devid);
828
829 /* Load the CT/RP selection */
830 pci_read_config_word(dev, 0x4A, &udma_timing);
831 udma_timing &= ~(3 << (4 * devid));
832 udma_timing |= u_speed << (4 * devid);
833 pci_write_config_word(dev, 0x4A, udma_timing);
834
835 if (isich) {
836 /* Select a 33/66/100Mhz clock */
837 pci_read_config_word(dev, 0x54, &ideconf);
838 ideconf &= ~(0x1001 << devid);
839 ideconf |= u_clock << devid;
840 /* For ICH or later we should set bit 10 for better
841 performance (WR_PingPong_En) */
842 pci_write_config_word(dev, 0x54, ideconf);
843 }
844 } else {
845 /*
846 * MWDMA is driven by the PIO timings. We must also enable
847 * IORDY unconditionally along with TIME1. PPE has already
848 * been set when the PIO timing was set.
849 */
850 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
851 unsigned int control;
852 u8 slave_data;
853 const unsigned int needed_pio[3] = {
854 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
855 };
856 int pio = needed_pio[mwdma] - XFER_PIO_0;
857
858 control = 3; /* IORDY|TIME1 */
859
860 /* If the drive MWDMA is faster than it can do PIO then
861 we must force PIO into PIO0 */
862
863 if (adev->pio_mode < needed_pio[mwdma])
864 /* Enable DMA timing only */
865 control |= 8; /* PIO cycles in PIO0 */
866
867 if (adev->devno) { /* Slave */
868 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
869 master_data |= control << 4;
870 pci_read_config_byte(dev, 0x44, &slave_data);
871 slave_data &= (ap->port_no ? 0x0f : 0xf0);
872 /* Load the matching timing */
873 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
874 pci_write_config_byte(dev, 0x44, slave_data);
875 } else { /* Master */
876 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
877 and master timing bits */
878 master_data |= control;
879 master_data |=
880 (timings[pio][0] << 12) |
881 (timings[pio][1] << 8);
882 }
883
884 if (ap->udma_mask)
885 udma_enable &= ~(1 << devid);
886
887 pci_write_config_word(dev, master_port, master_data);
888 }
889 /* Don't scribble on 0x48 if the controller does not support UDMA */
890 if (ap->udma_mask)
891 pci_write_config_byte(dev, 0x48, udma_enable);
892
893 spin_unlock_irqrestore(&piix_lock, flags);
894 }
895
896 /**
897 * piix_set_dmamode - Initialize host controller PATA DMA timings
898 * @ap: Port whose timings we are configuring
899 * @adev: um
900 *
901 * Set MW/UDMA mode for device, in host controller PCI config space.
902 *
903 * LOCKING:
904 * None (inherited from caller).
905 */
906
907 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
908 {
909 do_pata_set_dmamode(ap, adev, 0);
910 }
911
912 /**
913 * ich_set_dmamode - Initialize host controller PATA DMA timings
914 * @ap: Port whose timings we are configuring
915 * @adev: um
916 *
917 * Set MW/UDMA mode for device, in host controller PCI config space.
918 *
919 * LOCKING:
920 * None (inherited from caller).
921 */
922
923 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
924 {
925 do_pata_set_dmamode(ap, adev, 1);
926 }
927
928 /*
929 * Serial ATA Index/Data Pair Superset Registers access
930 *
931 * Beginning from ICH8, there's a sane way to access SCRs using index
932 * and data register pair located at BAR5 which means that we have
933 * separate SCRs for master and slave. This is handled using libata
934 * slave_link facility.
935 */
936 static const int piix_sidx_map[] = {
937 [SCR_STATUS] = 0,
938 [SCR_ERROR] = 2,
939 [SCR_CONTROL] = 1,
940 };
941
942 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
943 {
944 struct ata_port *ap = link->ap;
945 struct piix_host_priv *hpriv = ap->host->private_data;
946
947 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
948 hpriv->sidpr + PIIX_SIDPR_IDX);
949 }
950
951 static int piix_sidpr_scr_read(struct ata_link *link,
952 unsigned int reg, u32 *val)
953 {
954 struct piix_host_priv *hpriv = link->ap->host->private_data;
955 unsigned long flags;
956
957 if (reg >= ARRAY_SIZE(piix_sidx_map))
958 return -EINVAL;
959
960 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
961 piix_sidpr_sel(link, reg);
962 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
963 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
964 return 0;
965 }
966
967 static int piix_sidpr_scr_write(struct ata_link *link,
968 unsigned int reg, u32 val)
969 {
970 struct piix_host_priv *hpriv = link->ap->host->private_data;
971 unsigned long flags;
972
973 if (reg >= ARRAY_SIZE(piix_sidx_map))
974 return -EINVAL;
975
976 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
977 piix_sidpr_sel(link, reg);
978 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
979 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
980 return 0;
981 }
982
983 static bool piix_irq_check(struct ata_port *ap)
984 {
985 if (unlikely(!ap->ioaddr.bmdma_addr))
986 return false;
987
988 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
989 }
990
991 #ifdef CONFIG_PM
992 static int piix_broken_suspend(void)
993 {
994 static const struct dmi_system_id sysids[] = {
995 {
996 .ident = "TECRA M3",
997 .matches = {
998 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
999 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1000 },
1001 },
1002 {
1003 .ident = "TECRA M3",
1004 .matches = {
1005 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1006 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1007 },
1008 },
1009 {
1010 .ident = "TECRA M4",
1011 .matches = {
1012 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1013 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1014 },
1015 },
1016 {
1017 .ident = "TECRA M4",
1018 .matches = {
1019 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1020 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1021 },
1022 },
1023 {
1024 .ident = "TECRA M5",
1025 .matches = {
1026 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1027 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1028 },
1029 },
1030 {
1031 .ident = "TECRA M6",
1032 .matches = {
1033 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1034 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1035 },
1036 },
1037 {
1038 .ident = "TECRA M7",
1039 .matches = {
1040 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1041 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1042 },
1043 },
1044 {
1045 .ident = "TECRA A8",
1046 .matches = {
1047 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1048 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1049 },
1050 },
1051 {
1052 .ident = "Satellite R20",
1053 .matches = {
1054 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1055 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1056 },
1057 },
1058 {
1059 .ident = "Satellite R25",
1060 .matches = {
1061 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1062 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1063 },
1064 },
1065 {
1066 .ident = "Satellite U200",
1067 .matches = {
1068 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1069 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1070 },
1071 },
1072 {
1073 .ident = "Satellite U200",
1074 .matches = {
1075 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1076 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1077 },
1078 },
1079 {
1080 .ident = "Satellite Pro U200",
1081 .matches = {
1082 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1083 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1084 },
1085 },
1086 {
1087 .ident = "Satellite U205",
1088 .matches = {
1089 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1090 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1091 },
1092 },
1093 {
1094 .ident = "SATELLITE U205",
1095 .matches = {
1096 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1097 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1098 },
1099 },
1100 {
1101 .ident = "Portege M500",
1102 .matches = {
1103 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1104 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1105 },
1106 },
1107 {
1108 .ident = "VGN-BX297XP",
1109 .matches = {
1110 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1111 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1112 },
1113 },
1114
1115 { } /* terminate list */
1116 };
1117 static const char *oemstrs[] = {
1118 "Tecra M3,",
1119 };
1120 int i;
1121
1122 if (dmi_check_system(sysids))
1123 return 1;
1124
1125 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1126 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1127 return 1;
1128
1129 /* TECRA M4 sometimes forgets its identify and reports bogus
1130 * DMI information. As the bogus information is a bit
1131 * generic, match as many entries as possible. This manual
1132 * matching is necessary because dmi_system_id.matches is
1133 * limited to four entries.
1134 */
1135 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1136 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1137 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1138 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1139 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1140 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1141 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1142 return 1;
1143
1144 return 0;
1145 }
1146
1147 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1148 {
1149 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1150 unsigned long flags;
1151 int rc = 0;
1152
1153 rc = ata_host_suspend(host, mesg);
1154 if (rc)
1155 return rc;
1156
1157 /* Some braindamaged ACPI suspend implementations expect the
1158 * controller to be awake on entry; otherwise, it burns cpu
1159 * cycles and power trying to do something to the sleeping
1160 * beauty.
1161 */
1162 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1163 pci_save_state(pdev);
1164
1165 /* mark its power state as "unknown", since we don't
1166 * know if e.g. the BIOS will change its device state
1167 * when we suspend.
1168 */
1169 if (pdev->current_state == PCI_D0)
1170 pdev->current_state = PCI_UNKNOWN;
1171
1172 /* tell resume that it's waking up from broken suspend */
1173 spin_lock_irqsave(&host->lock, flags);
1174 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1175 spin_unlock_irqrestore(&host->lock, flags);
1176 } else
1177 ata_pci_device_do_suspend(pdev, mesg);
1178
1179 return 0;
1180 }
1181
1182 static int piix_pci_device_resume(struct pci_dev *pdev)
1183 {
1184 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1185 unsigned long flags;
1186 int rc;
1187
1188 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1189 spin_lock_irqsave(&host->lock, flags);
1190 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1191 spin_unlock_irqrestore(&host->lock, flags);
1192
1193 pci_set_power_state(pdev, PCI_D0);
1194 pci_restore_state(pdev);
1195
1196 /* PCI device wasn't disabled during suspend. Use
1197 * pci_reenable_device() to avoid affecting the enable
1198 * count.
1199 */
1200 rc = pci_reenable_device(pdev);
1201 if (rc)
1202 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1203 "device after resume (%d)\n", rc);
1204 } else
1205 rc = ata_pci_device_do_resume(pdev);
1206
1207 if (rc == 0)
1208 ata_host_resume(host);
1209
1210 return rc;
1211 }
1212 #endif
1213
1214 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1215 {
1216 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1217 }
1218
1219 #define AHCI_PCI_BAR 5
1220 #define AHCI_GLOBAL_CTL 0x04
1221 #define AHCI_ENABLE (1 << 31)
1222 static int piix_disable_ahci(struct pci_dev *pdev)
1223 {
1224 void __iomem *mmio;
1225 u32 tmp;
1226 int rc = 0;
1227
1228 /* BUG: pci_enable_device has not yet been called. This
1229 * works because this device is usually set up by BIOS.
1230 */
1231
1232 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1233 !pci_resource_len(pdev, AHCI_PCI_BAR))
1234 return 0;
1235
1236 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1237 if (!mmio)
1238 return -ENOMEM;
1239
1240 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1241 if (tmp & AHCI_ENABLE) {
1242 tmp &= ~AHCI_ENABLE;
1243 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1244
1245 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1246 if (tmp & AHCI_ENABLE)
1247 rc = -EIO;
1248 }
1249
1250 pci_iounmap(pdev, mmio);
1251 return rc;
1252 }
1253
1254 /**
1255 * piix_check_450nx_errata - Check for problem 450NX setup
1256 * @ata_dev: the PCI device to check
1257 *
1258 * Check for the present of 450NX errata #19 and errata #25. If
1259 * they are found return an error code so we can turn off DMA
1260 */
1261
1262 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1263 {
1264 struct pci_dev *pdev = NULL;
1265 u16 cfg;
1266 int no_piix_dma = 0;
1267
1268 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1269 /* Look for 450NX PXB. Check for problem configurations
1270 A PCI quirk checks bit 6 already */
1271 pci_read_config_word(pdev, 0x41, &cfg);
1272 /* Only on the original revision: IDE DMA can hang */
1273 if (pdev->revision == 0x00)
1274 no_piix_dma = 1;
1275 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1276 else if (cfg & (1<<14) && pdev->revision < 5)
1277 no_piix_dma = 2;
1278 }
1279 if (no_piix_dma)
1280 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1281 if (no_piix_dma == 2)
1282 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1283 return no_piix_dma;
1284 }
1285
1286 static void __devinit piix_init_pcs(struct ata_host *host,
1287 const struct piix_map_db *map_db)
1288 {
1289 struct pci_dev *pdev = to_pci_dev(host->dev);
1290 u16 pcs, new_pcs;
1291
1292 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1293
1294 new_pcs = pcs | map_db->port_enable;
1295
1296 if (new_pcs != pcs) {
1297 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1298 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1299 msleep(150);
1300 }
1301 }
1302
1303 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1304 struct ata_port_info *pinfo,
1305 const struct piix_map_db *map_db)
1306 {
1307 const int *map;
1308 int i, invalid_map = 0;
1309 u8 map_value;
1310
1311 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1312
1313 map = map_db->map[map_value & map_db->mask];
1314
1315 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1316 for (i = 0; i < 4; i++) {
1317 switch (map[i]) {
1318 case RV:
1319 invalid_map = 1;
1320 printk(" XX");
1321 break;
1322
1323 case NA:
1324 printk(" --");
1325 break;
1326
1327 case IDE:
1328 WARN_ON((i & 1) || map[i + 1] != IDE);
1329 pinfo[i / 2] = piix_port_info[ich_pata_100];
1330 i++;
1331 printk(" IDE IDE");
1332 break;
1333
1334 default:
1335 printk(" P%d", map[i]);
1336 if (i & 1)
1337 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1338 break;
1339 }
1340 }
1341 printk(" ]\n");
1342
1343 if (invalid_map)
1344 dev_printk(KERN_ERR, &pdev->dev,
1345 "invalid MAP value %u\n", map_value);
1346
1347 return map;
1348 }
1349
1350 static bool piix_no_sidpr(struct ata_host *host)
1351 {
1352 struct pci_dev *pdev = to_pci_dev(host->dev);
1353
1354 /*
1355 * Samsung DB-P70 only has three ATA ports exposed and
1356 * curiously the unconnected first port reports link online
1357 * while not responding to SRST protocol causing excessive
1358 * detection delay.
1359 *
1360 * Unfortunately, the system doesn't carry enough DMI
1361 * information to identify the machine but does have subsystem
1362 * vendor and device set. As it's unclear whether the
1363 * subsystem vendor/device is used only for this specific
1364 * board, the port can't be disabled solely with the
1365 * information; however, turning off SIDPR access works around
1366 * the problem. Turn it off.
1367 *
1368 * This problem is reported in bnc#441240.
1369 *
1370 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1371 */
1372 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1373 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1374 pdev->subsystem_device == 0xb049) {
1375 dev_printk(KERN_WARNING, host->dev,
1376 "Samsung DB-P70 detected, disabling SIDPR\n");
1377 return true;
1378 }
1379
1380 return false;
1381 }
1382
1383 static int __devinit piix_init_sidpr(struct ata_host *host)
1384 {
1385 struct pci_dev *pdev = to_pci_dev(host->dev);
1386 struct piix_host_priv *hpriv = host->private_data;
1387 struct ata_link *link0 = &host->ports[0]->link;
1388 u32 scontrol;
1389 int i, rc;
1390
1391 /* check for availability */
1392 for (i = 0; i < 4; i++)
1393 if (hpriv->map[i] == IDE)
1394 return 0;
1395
1396 /* is it blacklisted? */
1397 if (piix_no_sidpr(host))
1398 return 0;
1399
1400 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1401 return 0;
1402
1403 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1404 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1405 return 0;
1406
1407 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1408 return 0;
1409
1410 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1411
1412 /* SCR access via SIDPR doesn't work on some configurations.
1413 * Give it a test drive by inhibiting power save modes which
1414 * we'll do anyway.
1415 */
1416 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1417
1418 /* if IPM is already 3, SCR access is probably working. Don't
1419 * un-inhibit power save modes as BIOS might have inhibited
1420 * them for a reason.
1421 */
1422 if ((scontrol & 0xf00) != 0x300) {
1423 scontrol |= 0x300;
1424 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1425 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1426
1427 if ((scontrol & 0xf00) != 0x300) {
1428 dev_printk(KERN_INFO, host->dev, "SCR access via "
1429 "SIDPR is available but doesn't work\n");
1430 return 0;
1431 }
1432 }
1433
1434 /* okay, SCRs available, set ops and ask libata for slave_link */
1435 for (i = 0; i < 2; i++) {
1436 struct ata_port *ap = host->ports[i];
1437
1438 ap->ops = &piix_sidpr_sata_ops;
1439
1440 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1441 rc = ata_slave_link_init(ap);
1442 if (rc)
1443 return rc;
1444 }
1445 }
1446
1447 return 0;
1448 }
1449
1450 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1451 {
1452 static const struct dmi_system_id sysids[] = {
1453 {
1454 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1455 * isn't used to boot the system which
1456 * disables the channel.
1457 */
1458 .ident = "M570U",
1459 .matches = {
1460 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1461 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1462 },
1463 },
1464
1465 { } /* terminate list */
1466 };
1467 struct pci_dev *pdev = to_pci_dev(host->dev);
1468 struct piix_host_priv *hpriv = host->private_data;
1469
1470 if (!dmi_check_system(sysids))
1471 return;
1472
1473 /* The datasheet says that bit 18 is NOOP but certain systems
1474 * seem to use it to disable a channel. Clear the bit on the
1475 * affected systems.
1476 */
1477 if (hpriv->saved_iocfg & (1 << 18)) {
1478 dev_printk(KERN_INFO, &pdev->dev,
1479 "applying IOCFG bit18 quirk\n");
1480 pci_write_config_dword(pdev, PIIX_IOCFG,
1481 hpriv->saved_iocfg & ~(1 << 18));
1482 }
1483 }
1484
1485 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1486 {
1487 static const struct dmi_system_id broken_systems[] = {
1488 {
1489 .ident = "HP Compaq 2510p",
1490 .matches = {
1491 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1492 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1493 },
1494 /* PCI slot number of the controller */
1495 .driver_data = (void *)0x1FUL,
1496 },
1497 {
1498 .ident = "HP Compaq nc6000",
1499 .matches = {
1500 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1501 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1502 },
1503 /* PCI slot number of the controller */
1504 .driver_data = (void *)0x1FUL,
1505 },
1506
1507 { } /* terminate list */
1508 };
1509 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1510
1511 if (dmi) {
1512 unsigned long slot = (unsigned long)dmi->driver_data;
1513 /* apply the quirk only to on-board controllers */
1514 return slot == PCI_SLOT(pdev->devfn);
1515 }
1516
1517 return false;
1518 }
1519
1520 /**
1521 * piix_init_one - Register PIIX ATA PCI device with kernel services
1522 * @pdev: PCI device to register
1523 * @ent: Entry in piix_pci_tbl matching with @pdev
1524 *
1525 * Called from kernel PCI layer. We probe for combined mode (sigh),
1526 * and then hand over control to libata, for it to do the rest.
1527 *
1528 * LOCKING:
1529 * Inherited from PCI layer (may sleep).
1530 *
1531 * RETURNS:
1532 * Zero on success, or -ERRNO value.
1533 */
1534
1535 static int __devinit piix_init_one(struct pci_dev *pdev,
1536 const struct pci_device_id *ent)
1537 {
1538 static int printed_version;
1539 struct device *dev = &pdev->dev;
1540 struct ata_port_info port_info[2];
1541 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1542 unsigned long port_flags;
1543 struct ata_host *host;
1544 struct piix_host_priv *hpriv;
1545 int rc;
1546
1547 if (!printed_version++)
1548 dev_printk(KERN_DEBUG, &pdev->dev,
1549 "version " DRV_VERSION "\n");
1550
1551 /* no hotplugging support for later devices (FIXME) */
1552 if (!in_module_init && ent->driver_data >= ich5_sata)
1553 return -ENODEV;
1554
1555 if (piix_broken_system_poweroff(pdev)) {
1556 piix_port_info[ent->driver_data].flags |=
1557 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1558 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1559 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1560 "on poweroff and hibernation\n");
1561 }
1562
1563 port_info[0] = piix_port_info[ent->driver_data];
1564 port_info[1] = piix_port_info[ent->driver_data];
1565
1566 port_flags = port_info[0].flags;
1567
1568 /* enable device and prepare host */
1569 rc = pcim_enable_device(pdev);
1570 if (rc)
1571 return rc;
1572
1573 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1574 if (!hpriv)
1575 return -ENOMEM;
1576 spin_lock_init(&hpriv->sidpr_lock);
1577
1578 /* Save IOCFG, this will be used for cable detection, quirk
1579 * detection and restoration on detach. This is necessary
1580 * because some ACPI implementations mess up cable related
1581 * bits on _STM. Reported on kernel bz#11879.
1582 */
1583 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1584
1585 /* ICH6R may be driven by either ata_piix or ahci driver
1586 * regardless of BIOS configuration. Make sure AHCI mode is
1587 * off.
1588 */
1589 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1590 rc = piix_disable_ahci(pdev);
1591 if (rc)
1592 return rc;
1593 }
1594
1595 /* SATA map init can change port_info, do it before prepping host */
1596 if (port_flags & ATA_FLAG_SATA)
1597 hpriv->map = piix_init_sata_map(pdev, port_info,
1598 piix_map_db_table[ent->driver_data]);
1599
1600 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1601 if (rc)
1602 return rc;
1603 host->private_data = hpriv;
1604
1605 /* initialize controller */
1606 if (port_flags & ATA_FLAG_SATA) {
1607 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1608 rc = piix_init_sidpr(host);
1609 if (rc)
1610 return rc;
1611 }
1612
1613 /* apply IOCFG bit18 quirk */
1614 piix_iocfg_bit18_quirk(host);
1615
1616 /* On ICH5, some BIOSen disable the interrupt using the
1617 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1618 * On ICH6, this bit has the same effect, but only when
1619 * MSI is disabled (and it is disabled, as we don't use
1620 * message-signalled interrupts currently).
1621 */
1622 if (port_flags & PIIX_FLAG_CHECKINTR)
1623 pci_intx(pdev, 1);
1624
1625 if (piix_check_450nx_errata(pdev)) {
1626 /* This writes into the master table but it does not
1627 really matter for this errata as we will apply it to
1628 all the PIIX devices on the board */
1629 host->ports[0]->mwdma_mask = 0;
1630 host->ports[0]->udma_mask = 0;
1631 host->ports[1]->mwdma_mask = 0;
1632 host->ports[1]->udma_mask = 0;
1633 }
1634 host->flags |= ATA_HOST_PARALLEL_SCAN;
1635
1636 pci_set_master(pdev);
1637 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &piix_sht);
1638 }
1639
1640 static void piix_remove_one(struct pci_dev *pdev)
1641 {
1642 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1643 struct piix_host_priv *hpriv = host->private_data;
1644
1645 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1646
1647 ata_pci_remove_one(pdev);
1648 }
1649
1650 static int __init piix_init(void)
1651 {
1652 int rc;
1653
1654 DPRINTK("pci_register_driver\n");
1655 rc = pci_register_driver(&piix_pci_driver);
1656 if (rc)
1657 return rc;
1658
1659 in_module_init = 0;
1660
1661 DPRINTK("done\n");
1662 return 0;
1663 }
1664
1665 static void __exit piix_exit(void)
1666 {
1667 pci_unregister_driver(&piix_pci_driver);
1668 }
1669
1670 module_init(piix_init);
1671 module_exit(piix_exit);
kernel-based virtual machine