2 * linux/drivers/ide/pci/cs5530.c Version 0.71 Mar 10 2007
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * May be copied or modified under the terms of the GNU General Public License
10 * Development of this chipset driver was funded
11 * by the nice folks at National Semiconductor.
14 * CS5530 documentation available from National Semiconductor.
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/blkdev.h>
25 #include <linux/hdreg.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/ide.h>
34 * cs5530_xfer_set_mode - set a new transfer mode at the drive
35 * @drive: drive to tune
38 * Logging wrapper to the IDE driver speed configuration. This can
39 * probably go away now.
42 static int cs5530_set_xfer_mode (ide_drive_t
*drive
, u8 mode
)
44 printk(KERN_DEBUG
"%s: cs5530_set_xfer_mode(%s)\n",
45 drive
->name
, ide_xfer_verbose(mode
));
46 return (ide_config_drive_speed(drive
, mode
));
50 * Here are the standard PIO mode 0-4 timings for each "format".
51 * Format-0 uses fast data reg timings, with slower command reg timings.
52 * Format-1 uses fast timings for all registers, but won't work with all drives.
54 static unsigned int cs5530_pio_timings
[2][5] = {
55 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
56 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
60 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
62 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
63 #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
66 * cs5530_tuneproc - select/set PIO modes
68 * cs5530_tuneproc() handles selection/setting of PIO modes
69 * for both the chipset and drive.
71 * The ide_init_cs5530() routine guarantees that all drives
72 * will have valid default PIO timings set up before we get here.
75 static void cs5530_tuneproc (ide_drive_t
*drive
, u8 pio
) /* pio=255 means "autotune" */
77 ide_hwif_t
*hwif
= HWIF(drive
);
79 unsigned long basereg
= CS5530_BASEREG(hwif
);
80 static u8 modes
[5] = { XFER_PIO_0
, XFER_PIO_1
, XFER_PIO_2
, XFER_PIO_3
, XFER_PIO_4
};
82 pio
= ide_get_best_pio_mode(drive
, pio
, 4, NULL
);
83 if (!cs5530_set_xfer_mode(drive
, modes
[pio
])) {
84 format
= (inl(basereg
+ 4) >> 31) & 1;
85 outl(cs5530_pio_timings
[format
][pio
],
86 basereg
+(drive
->select
.b
.unit
<<3));
91 * cs5530_udma_filter - UDMA filter
94 * cs5530_udma_filter() does UDMA mask filtering for the given drive
95 * taking into the consideration capabilities of the mate device.
97 * The CS5530 specifies that two drives sharing a cable cannot mix
98 * UDMA/MDMA. It has to be one or the other, for the pair, though
99 * different timings can still be chosen for each drive. We could
100 * set the appropriate timing bits on the fly, but that might be
101 * a bit confusing. So, for now we statically handle this requirement
102 * by looking at our mate drive to see what it is capable of, before
103 * choosing a mode for our own drive.
105 * Note: This relies on the fact we never fail from UDMA to MWDMA2
106 * but instead drop to PIO.
109 static u8
cs5530_udma_filter(ide_drive_t
*drive
)
111 ide_hwif_t
*hwif
= drive
->hwif
;
112 ide_drive_t
*mate
= &hwif
->drives
[(drive
->dn
& 1) ^ 1];
113 struct hd_driveid
*mateid
= mate
->id
;
114 u8 mask
= hwif
->ultra_mask
;
116 if (mate
->present
== 0)
119 if ((mateid
->capability
& 1) && __ide_dma_bad_drive(mate
) == 0) {
120 if ((mateid
->field_valid
& 4) && (mateid
->dma_ultra
& 7))
122 if ((mateid
->field_valid
& 2) && (mateid
->dma_mword
& 7))
130 * cs5530_config_dma - set DMA/UDMA mode
131 * @drive: drive to tune
133 * cs5530_config_dma() handles setting of DMA/UDMA mode
134 * for both the chipset and drive.
137 static int cs5530_config_dma(ide_drive_t
*drive
)
139 ide_hwif_t
*hwif
= drive
->hwif
;
140 unsigned int reg
, timings
= 0;
141 unsigned long basereg
;
142 u8 unit
= drive
->dn
& 1, mode
= 0;
145 * Default to DMA-off in case we run into trouble here.
147 hwif
->dma_off_quietly(drive
);
149 if (ide_use_dma(drive
))
150 mode
= ide_max_dma_mode(drive
);
153 * Tell the drive to switch to the new mode; abort on failure.
155 if (!mode
|| cs5530_set_xfer_mode(drive
, mode
))
156 return 1; /* failure */
159 * Now tune the chipset to match the drive:
162 case XFER_UDMA_0
: timings
= 0x00921250; break;
163 case XFER_UDMA_1
: timings
= 0x00911140; break;
164 case XFER_UDMA_2
: timings
= 0x00911030; break;
165 case XFER_MW_DMA_0
: timings
= 0x00077771; break;
166 case XFER_MW_DMA_1
: timings
= 0x00012121; break;
167 case XFER_MW_DMA_2
: timings
= 0x00002020; break;
172 basereg
= CS5530_BASEREG(hwif
);
173 reg
= inl(basereg
+ 4); /* get drive0 config register */
174 timings
|= reg
& 0x80000000; /* preserve PIO format bit */
175 if (unit
== 0) { /* are we configuring drive0? */
176 outl(timings
, basereg
+ 4); /* write drive0 config register */
178 if (timings
& 0x00100000)
179 reg
|= 0x00100000; /* enable UDMA timings for both drives */
181 reg
&= ~0x00100000; /* disable UDMA timings for both drives */
182 outl(reg
, basereg
+ 4); /* write drive0 config register */
183 outl(timings
, basereg
+ 12); /* write drive1 config register */
186 return 0; /* success */
190 * init_chipset_5530 - set up 5530 bridge
194 * Initialize the cs5530 bridge for reliable IDE DMA operation.
197 static unsigned int __devinit
init_chipset_cs5530 (struct pci_dev
*dev
, const char *name
)
199 struct pci_dev
*master_0
= NULL
, *cs5530_0
= NULL
;
203 while ((dev
= pci_get_device(PCI_VENDOR_ID_CYRIX
, PCI_ANY_ID
, dev
)) != NULL
) {
204 switch (dev
->device
) {
205 case PCI_DEVICE_ID_CYRIX_PCI_MASTER
:
206 master_0
= pci_dev_get(dev
);
208 case PCI_DEVICE_ID_CYRIX_5530_LEGACY
:
209 cs5530_0
= pci_dev_get(dev
);
214 printk(KERN_ERR
"%s: unable to locate PCI MASTER function\n", name
);
218 printk(KERN_ERR
"%s: unable to locate CS5530 LEGACY function\n", name
);
222 spin_lock_irqsave(&ide_lock
, flags
);
223 /* all CPUs (there should only be one CPU with this chipset) */
226 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
227 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
230 pci_set_master(cs5530_0
);
231 pci_set_mwi(cs5530_0
);
234 * Set PCI CacheLineSize to 16-bytes:
235 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
238 pci_write_config_byte(cs5530_0
, PCI_CACHE_LINE_SIZE
, 0x04);
241 * Disable trapping of UDMA register accesses (Win98 hack):
242 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
245 pci_write_config_word(cs5530_0
, 0xd0, 0x5006);
248 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
249 * The other settings are what is necessary to get the register
250 * into a sane state for IDE DMA operation.
253 pci_write_config_byte(master_0
, 0x40, 0x1e);
256 * Set max PCI burst size (16-bytes seems to work best):
257 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
258 * all others: clear bit-1 at 0x41, and do:
259 * 128bytes: OR 0x00 at 0x41
260 * 256bytes: OR 0x04 at 0x41
261 * 512bytes: OR 0x08 at 0x41
262 * 1024bytes: OR 0x0c at 0x41
265 pci_write_config_byte(master_0
, 0x41, 0x14);
268 * These settings are necessary to get the chip
269 * into a sane state for IDE DMA operation.
272 pci_write_config_byte(master_0
, 0x42, 0x00);
273 pci_write_config_byte(master_0
, 0x43, 0xc1);
275 spin_unlock_irqrestore(&ide_lock
, flags
);
278 pci_dev_put(master_0
);
279 pci_dev_put(cs5530_0
);
284 * init_hwif_cs5530 - initialise an IDE channel
285 * @hwif: IDE to initialize
287 * This gets invoked by the IDE driver once for each channel. It
288 * performs channel-specific pre-initialization before drive probing.
291 static void __devinit
init_hwif_cs5530 (ide_hwif_t
*hwif
)
293 unsigned long basereg
;
298 hwif
->serialized
= hwif
->mate
->serialized
= 1;
300 hwif
->tuneproc
= &cs5530_tuneproc
;
301 basereg
= CS5530_BASEREG(hwif
);
302 d0_timings
= inl(basereg
+ 0);
303 if (CS5530_BAD_PIO(d0_timings
)) {
304 /* PIO timings not initialized? */
305 outl(cs5530_pio_timings
[(d0_timings
>> 31) & 1][0], basereg
+ 0);
306 if (!hwif
->drives
[0].autotune
)
307 hwif
->drives
[0].autotune
= 1;
308 /* needs autotuning later */
310 if (CS5530_BAD_PIO(inl(basereg
+ 8))) {
311 /* PIO timings not initialized? */
312 outl(cs5530_pio_timings
[(d0_timings
>> 31) & 1][0], basereg
+ 8);
313 if (!hwif
->drives
[1].autotune
)
314 hwif
->drives
[1].autotune
= 1;
315 /* needs autotuning later */
319 hwif
->ultra_mask
= 0x07;
320 hwif
->mwdma_mask
= 0x07;
322 hwif
->udma_filter
= cs5530_udma_filter
;
323 hwif
->ide_dma_check
= &cs5530_config_dma
;
326 hwif
->drives
[0].autodma
= hwif
->autodma
;
327 hwif
->drives
[1].autodma
= hwif
->autodma
;
330 static ide_pci_device_t cs5530_chipset __devinitdata
= {
332 .init_chipset
= init_chipset_cs5530
,
333 .init_hwif
= init_hwif_cs5530
,
336 .bootable
= ON_BOARD
,
339 static int __devinit
cs5530_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
341 return ide_setup_pci_device(dev
, &cs5530_chipset
);
344 static struct pci_device_id cs5530_pci_tbl
[] = {
345 { PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_5530_IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
348 MODULE_DEVICE_TABLE(pci
, cs5530_pci_tbl
);
350 static struct pci_driver driver
= {
351 .name
= "CS5530 IDE",
352 .id_table
= cs5530_pci_tbl
,
353 .probe
= cs5530_init_one
,
356 static int __init
cs5530_ide_init(void)
358 return ide_pci_register_driver(&driver
);
361 module_init(cs5530_ide_init
);
363 MODULE_AUTHOR("Mark Lord");
364 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
365 MODULE_LICENSE("GPL");