arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kdev_t.h>
  40 #include <linux/types.h>
  41 #include <linux/sched.h>
  42 #include <linux/pci.h>
  43 #include <linux/ide.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47 #include <linux/pm.h>
  48 #ifdef CONFIG_SERIAL_TXX9
  49 #include <linux/tty.h>
  50 #include <linux/serial.h>
  51 #include <linux/serial_core.h>
  52 #endif
  53
  54 #include <asm/addrspace.h>
  55 #include <asm/time.h>
  56 #include <asm/bcache.h>
  57 #include <asm/irq.h>
  58 #include <asm/reboot.h>
  59 #include <asm/gdb-stub.h>
  60 #include <asm/jmr3927/jmr3927.h>
  61 #include <asm/mipsregs.h>
  62 #include <asm/traps.h>
  63
  64 extern void puts(unsigned char *cp);
  65
  66 /* Tick Timer divider */
  67 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  68 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  69
  70 unsigned char led_state = 0xf;
  71
  72 struct {
  73     struct resource ram0;
  74     struct resource ram1;
  75     struct resource pcimem;
  76     struct resource iob;
  77     struct resource ioc;
  78     struct resource pciio;
  79     struct resource jmy1394;
  80     struct resource rom1;
  81     struct resource rom0;
  82     struct resource sio0;
  83     struct resource sio1;
  84 } jmr3927_resources = {
  85         {
  86                 .start  = 0,
  87                 .end    = 0x01FFFFFF,
  88                 .name   = "RAM0",
  89                 .flags = IORESOURCE_MEM
  90         }, {
  91                 .start  = 0x02000000,
  92                 .end    = 0x03FFFFFF,
  93                 .name   = "RAM1",
  94                 .flags = IORESOURCE_MEM
  95         }, {
  96                 .start  = 0x08000000,
  97                 .end    = 0x07FFFFFF,
  98                 .name   = "PCIMEM",
  99                 .flags = IORESOURCE_MEM
 100         }, {
 101                 .start  = 0x10000000,
 102                 .end    = 0x13FFFFFF,
 103                 .name   = "IOB"
 104         }, {
 105                 .start  = 0x14000000,
 106                 .end    = 0x14FFFFFF,
 107                 .name   = "IOC"
 108         }, {
 109                 .start  = 0x15000000,
 110                 .end    = 0x15FFFFFF,
 111                 .name   = "PCIIO"
 112         }, {
 113                 .start  = 0x1D000000,
 114                 .end    = 0x1D3FFFFF,
 115                 .name   = "JMY1394"
 116         }, {
 117                 .start  = 0x1E000000,
 118                 .end    = 0x1E3FFFFF,
 119                 .name   = "ROM1"
 120         }, {
 121                 .start  = 0x1FC00000,
 122                 .end    = 0x1FFFFFFF,
 123                 .name   = "ROM0"
 124         }, {
 125                 .start  = 0xFFFEF300,
 126                 .end    = 0xFFFEF3FF,
 127                 .name   = "SIO0"
 128         }, {
 129                 .start  = 0xFFFEF400,
 130                 .end    = 0xFFFEF4FF,
 131                 .name   = "SIO1"
 132         },
 133 };
 134
 135 /* don't enable - see errata */
 136 int jmr3927_ccfg_toeon = 0;
 137
 138 static inline void do_reset(void)
 139 {
 140 #ifdef CONFIG_TC35815
 141         extern void tc35815_killall(void);
 142         tc35815_killall();
 143 #endif
 144 #if 1   /* Resetting PCI bus */
 145         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 146         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
 147         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
 148         mdelay(1);
 149         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 150 #endif
 151         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
 152 }
 153
 154 static void jmr3927_machine_restart(char *command)
 155 {
 156         local_irq_disable();
 157         puts("Rebooting...");
 158         do_reset();
 159 }
 160
 161 static void jmr3927_machine_halt(void)
 162 {
 163         puts("JMR-TX3927 halted.\n");
 164         while (1);
 165 }
 166
 167 static void jmr3927_machine_power_off(void)
 168 {
 169         puts("JMR-TX3927 halted. Please turn off the power.\n");
 170         while (1);
 171 }
 172
 173 #define USE_RTC_DS1742
 174 #ifdef USE_RTC_DS1742
 175 extern void rtc_ds1742_init(unsigned long base);
 176 #endif
 177 static void __init jmr3927_time_init(void)
 178 {
 179 #ifdef USE_RTC_DS1742
 180         if (jmr3927_have_nvram()) {
 181                 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
 182         }
 183 #endif
 184 }
 185
 186 unsigned long jmr3927_do_gettimeoffset(void);
 187 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 188
 189 static void __init jmr3927_timer_setup(struct irqaction *irq)
 190 {
 191         do_gettimeoffset = jmr3927_do_gettimeoffset;
 192
 193         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 194         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 195         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 196         jmr3927_tmrptr->tcr =
 197                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 198
 199         setup_irq(JMR3927_IRQ_TICK, irq);
 200 }
 201
 202 #define USECS_PER_JIFFY (1000000/HZ)
 203
 204 unsigned long jmr3927_do_gettimeoffset(void)
 205 {
 206        unsigned long count;
 207        unsigned long res = 0;
 208
 209        /* MUST read TRR before TISR. */
 210        count = jmr3927_tmrptr->trr;
 211
 212        if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
 213                /* timer interrupt is pending.  use Max value. */
 214                res = USECS_PER_JIFFY - 1;
 215        } else {
 216                /* convert to usec */
 217                /* res = count / (JMR3927_TIMER_CLK / 1000000); */
 218                res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
 219
 220                /*
 221                 * Due to possible jiffies inconsistencies, we need to check
 222                 * the result so that we'll get a timer that is monotonic.
 223                 */
 224                if (res >= USECS_PER_JIFFY)
 225                        res = USECS_PER_JIFFY-1;
 226        }
 227
 228        return res;
 229 }
 230
 231
 232 //#undef DO_WRITE_THROUGH
 233 #define DO_WRITE_THROUGH
 234 #define DO_ENABLE_CACHE
 235
 236 extern char * __init prom_getcmdline(void);
 237 static void jmr3927_board_init(void);
 238 extern struct resource pci_io_resource;
 239 extern struct resource pci_mem_resource;
 240
 241 void __init plat_setup(void)
 242 {
 243         char *argptr;
 244
 245         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 246
 247         board_time_init = jmr3927_time_init;
 248         board_timer_setup = jmr3927_timer_setup;
 249
 250         _machine_restart = jmr3927_machine_restart;
 251         _machine_halt = jmr3927_machine_halt;
 252         pm_power_off = jmr3927_machine_power_off;
 253
 254         /*
 255          * IO/MEM resources.
 256          */
 257         ioport_resource.start = pci_io_resource.start;
 258         ioport_resource.end = pci_io_resource.end;
 259         iomem_resource.start = 0;
 260         iomem_resource.end = 0xffffffff;
 261
 262         /* Reboot on panic */
 263         panic_timeout = 180;
 264
 265         {
 266                 unsigned int conf;
 267                 conf = read_c0_conf();
 268         }
 269
 270 #if 1
 271         /* cache setup */
 272         {
 273                 unsigned int conf;
 274 #ifdef DO_ENABLE_CACHE
 275                 int mips_ic_disable = 0, mips_dc_disable = 0;
 276 #else
 277                 int mips_ic_disable = 1, mips_dc_disable = 1;
 278 #endif
 279 #ifdef DO_WRITE_THROUGH
 280                 int mips_config_cwfon = 0;
 281                 int mips_config_wbon = 0;
 282 #else
 283                 int mips_config_cwfon = 1;
 284                 int mips_config_wbon = 1;
 285 #endif
 286
 287                 conf = read_c0_conf();
 288                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 289                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 290                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 291                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 292                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 293
 294                 write_c0_conf(conf);
 295                 write_c0_cache(0);
 296         }
 297 #endif
 298
 299         /* initialize board */
 300         jmr3927_board_init();
 301
 302         argptr = prom_getcmdline();
 303
 304         if ((argptr = strstr(argptr, "toeon")) != NULL) {
 305                         jmr3927_ccfg_toeon = 1;
 306         }
 307         argptr = prom_getcmdline();
 308         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 309                 argptr = prom_getcmdline();
 310                 strcat(argptr, " ip=bootp");
 311         }
 312
 313 #ifdef CONFIG_SERIAL_TXX9
 314         {
 315                 extern int early_serial_txx9_setup(struct uart_port *port);
 316                 int i;
 317                 struct uart_port req;
 318                 for(i = 0; i < 2; i++) {
 319                         memset(&req, 0, sizeof(req));
 320                         req.line = i;
 321                         req.iotype = UPIO_MEM;
 322                         req.membase = (char *)TX3927_SIO_REG(i);
 323                         req.mapbase = TX3927_SIO_REG(i);
 324                         req.irq = i == 0 ?
 325                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 326                         if (i == 0)
 327                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 328                         req.uartclk = JMR3927_IMCLK;
 329                         early_serial_txx9_setup(&req);
 330                 }
 331         }
 332 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 333         argptr = prom_getcmdline();
 334         if ((argptr = strstr(argptr, "console=")) == NULL) {
 335                 argptr = prom_getcmdline();
 336                 strcat(argptr, " console=ttyS1,115200");
 337         }
 338 #endif
 339 #endif
 340 }
 341
 342 static void tx3927_setup(void);
 343
 344 #ifdef CONFIG_PCI
 345 unsigned long mips_pci_io_base;
 346 unsigned long mips_pci_io_size;
 347 unsigned long mips_pci_mem_base;
 348 unsigned long mips_pci_mem_size;
 349 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 350 unsigned long mips_pci_io_pciaddr = 0;
 351 #endif
 352
 353 static void __init jmr3927_board_init(void)
 354 {
 355         char *argptr;
 356
 357 #ifdef CONFIG_PCI
 358         mips_pci_io_base = JMR3927_PCIIO;
 359         mips_pci_io_size = JMR3927_PCIIO_SIZE;
 360         mips_pci_mem_base = JMR3927_PCIMEM;
 361         mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 362 #endif
 363
 364         tx3927_setup();
 365
 366         if (jmr3927_have_isac()) {
 367
 368 #ifdef CONFIG_FB_E1355
 369                 argptr = prom_getcmdline();
 370                 if ((argptr = strstr(argptr, "video=")) == NULL) {
 371                         argptr = prom_getcmdline();
 372                         strcat(argptr, " video=e1355fb:crt16h");
 373                 }
 374 #endif
 375
 376 #ifdef CONFIG_BLK_DEV_IDE
 377                 /* overrides PCI-IDE */
 378 #endif
 379         }
 380
 381         /* SIO0 DTR on */
 382         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 383
 384         jmr3927_led_set(0);
 385
 386
 387         if (jmr3927_have_isac())
 388                 jmr3927_io_led_set(0);
 389         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 390                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 391                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 392                jmr3927_dipsw1(), jmr3927_dipsw2(),
 393                jmr3927_dipsw3(), jmr3927_dipsw4());
 394         if (jmr3927_have_isac())
 395                 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
 396                        jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 397                        jmr3927_io_dipsw());
 398 }
 399
 400 void __init tx3927_setup(void)
 401 {
 402         int i;
 403
 404         /* SDRAMC are configured by PROM */
 405
 406         /* ROMC */
 407         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 408         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 409         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 410         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 411
 412         /* CCFG */
 413         /* enable Timeout BusError */
 414         if (jmr3927_ccfg_toeon)
 415                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 416
 417         /* clear BusErrorOnWrite flag */
 418         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 419         /* Disable PCI snoop */
 420         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 421
 422 #ifdef DO_WRITE_THROUGH
 423         /* Enable PCI SNOOP - with write through only */
 424         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 425 #endif
 426
 427         /* Pin selection */
 428         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 429         tx3927_ccfgptr->pcfg |=
 430                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 431                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 432
 433         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 434                tx3927_ccfgptr->crir,
 435                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 436
 437         /* IRC */
 438         /* disable interrupt control */
 439         tx3927_ircptr->cer = 0;
 440         /* mask all IRC interrupts */
 441         tx3927_ircptr->imr = 0;
 442         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 443                 tx3927_ircptr->ilr[i] = 0;
 444         }
 445         /* setup IRC interrupt mode (Low Active) */
 446         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 447                 tx3927_ircptr->cr[i] = 0;
 448         }
 449
 450         /* TMR */
 451         /* disable all timers */
 452         for (i = 0; i < TX3927_NR_TMR; i++) {
 453                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 454                 tx3927_tmrptr(i)->tisr = 0;
 455                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 456                 tx3927_tmrptr(i)->itmr = 0;
 457                 tx3927_tmrptr(i)->ccdr = 0;
 458                 tx3927_tmrptr(i)->pgmr = 0;
 459         }
 460
 461         /* DMA */
 462         tx3927_dmaptr->mcr = 0;
 463         for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
 464                 /* reset channel */
 465                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 466                 tx3927_dmaptr->ch[i].ccr = 0;
 467         }
 468         /* enable DMA */
 469 #ifdef __BIG_ENDIAN
 470         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 471 #else
 472         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 473 #endif
 474
 475 #ifdef CONFIG_PCI
 476         /* PCIC */
 477         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 478                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 479                tx3927_pcicptr->rid);
 480         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 481                 printk("External\n");
 482                 /* XXX */
 483         } else {
 484                 printk("Internal\n");
 485
 486                 /* Reset PCI Bus */
 487                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 488                 udelay(100);
 489                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 490                                     JMR3927_IOC_RESET_ADDR);
 491                 udelay(100);
 492                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 493
 494
 495                 /* Disable External PCI Config. Access */
 496                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 497 #ifdef __BIG_ENDIAN
 498                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 499                         TX3927_PCIC_LBC_TIBSE |
 500                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 501 #endif
 502                 /* LB->PCI mappings */
 503                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 504                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 505                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 506                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 507                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 508                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 509                 /* PCI->LB mappings */
 510                 tx3927_pcicptr->iobas = 0xffffffff;
 511                 tx3927_pcicptr->ioba = 0;
 512                 tx3927_pcicptr->tlbioma = 0;
 513                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 514                 tx3927_pcicptr->mba = 0;
 515                 tx3927_pcicptr->tlbmma = 0;
 516 #ifndef JMR3927_INIT_INDIRECT_PCI
 517                 /* Enable Direct mapping Address Space Decoder */
 518                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 519 #endif
 520
 521                 /* Clear All Local Bus Status */
 522                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 523                 /* Enable All Local Bus Interrupts */
 524                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 525                 /* Clear All PCI Status Error */
 526                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 527                 /* Enable All PCI Status Error Interrupts */
 528                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 529
 530                 /* PCIC Int => IRC IRQ10 */
 531                 tx3927_pcicptr->il = TX3927_IR_PCI;
 532 #if 1
 533                 /* Target Control (per errata) */
 534                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 535 #endif
 536
 537                 /* Enable Bus Arbiter */
 538 #if 0
 539                 tx3927_pcicptr->req_trace = 0x73737373;
 540 #endif
 541                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 542
 543                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 544                         PCI_COMMAND_MEMORY |
 545 #if 1
 546                         PCI_COMMAND_IO |
 547 #endif
 548                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 549         }
 550 #endif /* CONFIG_PCI */
 551
 552         /* PIO */
 553         /* PIO[15:12] connected to LEDs */
 554         tx3927_pioptr->dir = 0x0000f000;
 555         tx3927_pioptr->maskcpu = 0;
 556         tx3927_pioptr->maskext = 0;
 557         {
 558                 unsigned int conf;
 559
 560         conf = read_c0_conf();
 561                if (!(conf & TX39_CONF_ICE))
 562                        printk("TX3927 I-Cache disabled.\n");
 563                if (!(conf & TX39_CONF_DCE))
 564                        printk("TX3927 D-Cache disabled.\n");
 565                else if (!(conf & TX39_CONF_WBON))
 566                        printk("TX3927 D-Cache WriteThrough.\n");
 567                else if (!(conf & TX39_CONF_CWFON))
 568                        printk("TX3927 D-Cache WriteBack.\n");
 569                else
 570                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 571         }
 572 }