2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
11 * Variable system clock when/if it makes sense
12 * Power management on ports
15 * Documentation publically available.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
27 #define DRV_NAME "pata_amd"
28 #define DRV_VERSION "0.2.4"
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
44 static void timing_setup(struct ata_port
*ap
, struct ata_device
*adev
, int offset
, int speed
, int clock
)
46 static const unsigned char amd_cyc2udma
[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
50 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
51 struct ata_device
*peer
= ata_dev_pair(adev
);
52 int dn
= ap
->port_no
* 2 + adev
->devno
;
53 struct ata_timing at
, apeer
;
55 const int amd_clock
= 33333; /* KHz. */
58 T
= 1000000000 / amd_clock
;
59 UT
= T
/ min_t(int, max_t(int, clock
, 1), 2);
61 if (ata_timing_compute(adev
, speed
, &at
, T
, UT
) < 0) {
62 dev_printk(KERN_ERR
, &pdev
->dev
, "unknown mode %d.\n", speed
);
67 /* This may be over conservative */
69 ata_timing_compute(peer
, peer
->dma_mode
, &apeer
, T
, UT
);
70 ata_timing_merge(&apeer
, &at
, &at
, ATA_TIMING_8BIT
);
72 ata_timing_compute(peer
, peer
->pio_mode
, &apeer
, T
, UT
);
73 ata_timing_merge(&apeer
, &at
, &at
, ATA_TIMING_8BIT
);
76 if (speed
== XFER_UDMA_5
&& amd_clock
<= 33333) at
.udma
= 1;
77 if (speed
== XFER_UDMA_6
&& amd_clock
<= 33333) at
.udma
= 15;
80 * Now do the setup work
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev
, offset
+ 0x0C, &t
);
85 t
= (t
& ~(3 << ((3 - dn
) << 1))) | ((FIT(at
.setup
, 1, 4) - 1) << ((3 - dn
) << 1));
86 pci_write_config_byte(pdev
, offset
+ 0x0C , t
);
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev
, offset
+ 0x0E + (1 - (dn
>> 1)),
90 ((FIT(at
.act8b
, 1, 16) - 1) << 4) | (FIT(at
.rec8b
, 1, 16) - 1));
93 pci_write_config_byte(pdev
, offset
+ 0x08 + (3 - dn
),
94 ((FIT(at
.active
, 1, 16) - 1) << 4) | (FIT(at
.recover
, 1, 16) - 1));
98 t
= at
.udma
? (0xc0 | (FIT(at
.udma
, 2, 5) - 2)) : 0x03;
102 t
= at
.udma
? (0xc0 | amd_cyc2udma
[FIT(at
.udma
, 2, 10)]) : 0x03;
106 t
= at
.udma
? (0xc0 | amd_cyc2udma
[FIT(at
.udma
, 1, 10)]) : 0x03;
110 t
= at
.udma
? (0xc0 | amd_cyc2udma
[FIT(at
.udma
, 1, 15)]) : 0x03;
118 pci_write_config_byte(pdev
, offset
+ 0x10 + (3 - dn
), t
);
122 * amd_probe_init - cable detection
125 * Perform cable detection. The BIOS stores this in PCI config
129 static int amd_pre_reset(struct ata_port
*ap
)
131 static const u32 bitmask
[2] = {0x03, 0xC0};
132 static const struct pci_bits amd_enable_bits
[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
137 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
140 if (!pci_test_config_bits(pdev
, &amd_enable_bits
[ap
->port_no
]))
143 pci_read_config_byte(pdev
, 0x42, &ata66
);
144 if (ata66
& bitmask
[ap
->port_no
])
145 ap
->cbl
= ATA_CBL_PATA80
;
147 ap
->cbl
= ATA_CBL_PATA40
;
148 return ata_std_prereset(ap
);
152 static void amd_error_handler(struct ata_port
*ap
)
154 return ata_bmdma_drive_eh(ap
, amd_pre_reset
,
155 ata_std_softreset
, NULL
,
159 static int amd_early_pre_reset(struct ata_port
*ap
)
161 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
162 static struct pci_bits amd_enable_bits
[] = {
163 { 0x40, 1, 0x02, 0x02 },
164 { 0x40, 1, 0x01, 0x01 }
167 if (!pci_test_config_bits(pdev
, &amd_enable_bits
[ap
->port_no
]))
170 /* No host side cable detection */
171 ap
->cbl
= ATA_CBL_PATA80
;
172 return ata_std_prereset(ap
);
176 static void amd_early_error_handler(struct ata_port
*ap
)
178 ata_bmdma_drive_eh(ap
, amd_early_pre_reset
,
179 ata_std_softreset
, NULL
,
184 * amd33_set_piomode - set initial PIO mode data
188 * Program the AMD registers for PIO mode.
191 static void amd33_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
193 timing_setup(ap
, adev
, 0x40, adev
->pio_mode
, 1);
196 static void amd66_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
198 timing_setup(ap
, adev
, 0x40, adev
->pio_mode
, 2);
201 static void amd100_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
203 timing_setup(ap
, adev
, 0x40, adev
->pio_mode
, 3);
206 static void amd133_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
208 timing_setup(ap
, adev
, 0x40, adev
->pio_mode
, 4);
212 * amd33_set_dmamode - set initial DMA mode data
216 * Program the MWDMA/UDMA modes for the AMD and Nvidia
220 static void amd33_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
222 timing_setup(ap
, adev
, 0x40, adev
->dma_mode
, 1);
225 static void amd66_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
227 timing_setup(ap
, adev
, 0x40, adev
->dma_mode
, 2);
230 static void amd100_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
232 timing_setup(ap
, adev
, 0x40, adev
->dma_mode
, 3);
235 static void amd133_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
237 timing_setup(ap
, adev
, 0x40, adev
->dma_mode
, 4);
242 * nv_probe_init - cable detection
245 * Perform cable detection. The BIOS stores this in PCI config
249 static int nv_pre_reset(struct ata_port
*ap
) {
250 static const u8 bitmask
[2] = {0x03, 0xC0};
251 static const struct pci_bits nv_enable_bits
[] = {
252 { 0x50, 1, 0x02, 0x02 },
253 { 0x50, 1, 0x01, 0x01 }
256 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
260 if (!pci_test_config_bits(pdev
, &nv_enable_bits
[ap
->port_no
]))
263 pci_read_config_byte(pdev
, 0x52, &ata66
);
264 if (ata66
& bitmask
[ap
->port_no
])
265 ap
->cbl
= ATA_CBL_PATA80
;
267 ap
->cbl
= ATA_CBL_PATA40
;
269 /* We now have to double check because the Nvidia boxes BIOS
270 doesn't always set the cable bits but does set mode bits */
272 pci_read_config_word(pdev
, 0x62 - 2 * ap
->port_no
, &udma
);
273 if ((udma
& 0xC4) == 0xC4 || (udma
& 0xC400) == 0xC400)
274 ap
->cbl
= ATA_CBL_PATA80
;
275 return ata_std_prereset(ap
);
278 static void nv_error_handler(struct ata_port
*ap
)
280 ata_bmdma_drive_eh(ap
, nv_pre_reset
,
281 ata_std_softreset
, NULL
,
285 * nv100_set_piomode - set initial PIO mode data
289 * Program the AMD registers for PIO mode.
292 static void nv100_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
294 timing_setup(ap
, adev
, 0x50, adev
->pio_mode
, 3);
297 static void nv133_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
299 timing_setup(ap
, adev
, 0x50, adev
->pio_mode
, 4);
303 * nv100_set_dmamode - set initial DMA mode data
307 * Program the MWDMA/UDMA modes for the AMD and Nvidia
311 static void nv100_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
313 timing_setup(ap
, adev
, 0x50, adev
->dma_mode
, 3);
316 static void nv133_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
318 timing_setup(ap
, adev
, 0x50, adev
->dma_mode
, 4);
321 static struct scsi_host_template amd_sht
= {
322 .module
= THIS_MODULE
,
324 .ioctl
= ata_scsi_ioctl
,
325 .queuecommand
= ata_scsi_queuecmd
,
326 .can_queue
= ATA_DEF_QUEUE
,
327 .this_id
= ATA_SHT_THIS_ID
,
328 .sg_tablesize
= LIBATA_MAX_PRD
,
329 .max_sectors
= ATA_MAX_SECTORS
,
330 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
331 .emulated
= ATA_SHT_EMULATED
,
332 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
333 .proc_name
= DRV_NAME
,
334 .dma_boundary
= ATA_DMA_BOUNDARY
,
335 .slave_configure
= ata_scsi_slave_config
,
336 .bios_param
= ata_std_bios_param
,
339 static struct ata_port_operations amd33_port_ops
= {
340 .port_disable
= ata_port_disable
,
341 .set_piomode
= amd33_set_piomode
,
342 .set_dmamode
= amd33_set_dmamode
,
343 .mode_filter
= ata_pci_default_filter
,
344 .tf_load
= ata_tf_load
,
345 .tf_read
= ata_tf_read
,
346 .check_status
= ata_check_status
,
347 .exec_command
= ata_exec_command
,
348 .dev_select
= ata_std_dev_select
,
350 .freeze
= ata_bmdma_freeze
,
351 .thaw
= ata_bmdma_thaw
,
352 .error_handler
= amd_early_error_handler
,
353 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
355 .bmdma_setup
= ata_bmdma_setup
,
356 .bmdma_start
= ata_bmdma_start
,
357 .bmdma_stop
= ata_bmdma_stop
,
358 .bmdma_status
= ata_bmdma_status
,
360 .qc_prep
= ata_qc_prep
,
361 .qc_issue
= ata_qc_issue_prot
,
363 .data_xfer
= ata_pio_data_xfer
,
365 .irq_handler
= ata_interrupt
,
366 .irq_clear
= ata_bmdma_irq_clear
,
368 .port_start
= ata_port_start
,
369 .port_stop
= ata_port_stop
,
370 .host_stop
= ata_host_stop
373 static struct ata_port_operations amd66_port_ops
= {
374 .port_disable
= ata_port_disable
,
375 .set_piomode
= amd66_set_piomode
,
376 .set_dmamode
= amd66_set_dmamode
,
377 .mode_filter
= ata_pci_default_filter
,
378 .tf_load
= ata_tf_load
,
379 .tf_read
= ata_tf_read
,
380 .check_status
= ata_check_status
,
381 .exec_command
= ata_exec_command
,
382 .dev_select
= ata_std_dev_select
,
384 .freeze
= ata_bmdma_freeze
,
385 .thaw
= ata_bmdma_thaw
,
386 .error_handler
= amd_early_error_handler
,
387 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
389 .bmdma_setup
= ata_bmdma_setup
,
390 .bmdma_start
= ata_bmdma_start
,
391 .bmdma_stop
= ata_bmdma_stop
,
392 .bmdma_status
= ata_bmdma_status
,
394 .qc_prep
= ata_qc_prep
,
395 .qc_issue
= ata_qc_issue_prot
,
397 .data_xfer
= ata_pio_data_xfer
,
399 .irq_handler
= ata_interrupt
,
400 .irq_clear
= ata_bmdma_irq_clear
,
402 .port_start
= ata_port_start
,
403 .port_stop
= ata_port_stop
,
404 .host_stop
= ata_host_stop
407 static struct ata_port_operations amd100_port_ops
= {
408 .port_disable
= ata_port_disable
,
409 .set_piomode
= amd100_set_piomode
,
410 .set_dmamode
= amd100_set_dmamode
,
411 .mode_filter
= ata_pci_default_filter
,
412 .tf_load
= ata_tf_load
,
413 .tf_read
= ata_tf_read
,
414 .check_status
= ata_check_status
,
415 .exec_command
= ata_exec_command
,
416 .dev_select
= ata_std_dev_select
,
418 .freeze
= ata_bmdma_freeze
,
419 .thaw
= ata_bmdma_thaw
,
420 .error_handler
= amd_error_handler
,
421 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
423 .bmdma_setup
= ata_bmdma_setup
,
424 .bmdma_start
= ata_bmdma_start
,
425 .bmdma_stop
= ata_bmdma_stop
,
426 .bmdma_status
= ata_bmdma_status
,
428 .qc_prep
= ata_qc_prep
,
429 .qc_issue
= ata_qc_issue_prot
,
431 .data_xfer
= ata_pio_data_xfer
,
433 .irq_handler
= ata_interrupt
,
434 .irq_clear
= ata_bmdma_irq_clear
,
436 .port_start
= ata_port_start
,
437 .port_stop
= ata_port_stop
,
438 .host_stop
= ata_host_stop
441 static struct ata_port_operations amd133_port_ops
= {
442 .port_disable
= ata_port_disable
,
443 .set_piomode
= amd133_set_piomode
,
444 .set_dmamode
= amd133_set_dmamode
,
445 .mode_filter
= ata_pci_default_filter
,
446 .tf_load
= ata_tf_load
,
447 .tf_read
= ata_tf_read
,
448 .check_status
= ata_check_status
,
449 .exec_command
= ata_exec_command
,
450 .dev_select
= ata_std_dev_select
,
452 .freeze
= ata_bmdma_freeze
,
453 .thaw
= ata_bmdma_thaw
,
454 .error_handler
= amd_error_handler
,
455 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
457 .bmdma_setup
= ata_bmdma_setup
,
458 .bmdma_start
= ata_bmdma_start
,
459 .bmdma_stop
= ata_bmdma_stop
,
460 .bmdma_status
= ata_bmdma_status
,
462 .qc_prep
= ata_qc_prep
,
463 .qc_issue
= ata_qc_issue_prot
,
465 .data_xfer
= ata_pio_data_xfer
,
467 .irq_handler
= ata_interrupt
,
468 .irq_clear
= ata_bmdma_irq_clear
,
470 .port_start
= ata_port_start
,
471 .port_stop
= ata_port_stop
,
472 .host_stop
= ata_host_stop
475 static struct ata_port_operations nv100_port_ops
= {
476 .port_disable
= ata_port_disable
,
477 .set_piomode
= nv100_set_piomode
,
478 .set_dmamode
= nv100_set_dmamode
,
479 .mode_filter
= ata_pci_default_filter
,
480 .tf_load
= ata_tf_load
,
481 .tf_read
= ata_tf_read
,
482 .check_status
= ata_check_status
,
483 .exec_command
= ata_exec_command
,
484 .dev_select
= ata_std_dev_select
,
486 .freeze
= ata_bmdma_freeze
,
487 .thaw
= ata_bmdma_thaw
,
488 .error_handler
= nv_error_handler
,
489 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
491 .bmdma_setup
= ata_bmdma_setup
,
492 .bmdma_start
= ata_bmdma_start
,
493 .bmdma_stop
= ata_bmdma_stop
,
494 .bmdma_status
= ata_bmdma_status
,
496 .qc_prep
= ata_qc_prep
,
497 .qc_issue
= ata_qc_issue_prot
,
499 .data_xfer
= ata_pio_data_xfer
,
501 .irq_handler
= ata_interrupt
,
502 .irq_clear
= ata_bmdma_irq_clear
,
504 .port_start
= ata_port_start
,
505 .port_stop
= ata_port_stop
,
506 .host_stop
= ata_host_stop
509 static struct ata_port_operations nv133_port_ops
= {
510 .port_disable
= ata_port_disable
,
511 .set_piomode
= nv133_set_piomode
,
512 .set_dmamode
= nv133_set_dmamode
,
513 .mode_filter
= ata_pci_default_filter
,
514 .tf_load
= ata_tf_load
,
515 .tf_read
= ata_tf_read
,
516 .check_status
= ata_check_status
,
517 .exec_command
= ata_exec_command
,
518 .dev_select
= ata_std_dev_select
,
520 .freeze
= ata_bmdma_freeze
,
521 .thaw
= ata_bmdma_thaw
,
522 .error_handler
= nv_error_handler
,
523 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
525 .bmdma_setup
= ata_bmdma_setup
,
526 .bmdma_start
= ata_bmdma_start
,
527 .bmdma_stop
= ata_bmdma_stop
,
528 .bmdma_status
= ata_bmdma_status
,
530 .qc_prep
= ata_qc_prep
,
531 .qc_issue
= ata_qc_issue_prot
,
533 .data_xfer
= ata_pio_data_xfer
,
535 .irq_handler
= ata_interrupt
,
536 .irq_clear
= ata_bmdma_irq_clear
,
538 .port_start
= ata_port_start
,
539 .port_stop
= ata_port_stop
,
540 .host_stop
= ata_host_stop
543 static int amd_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
545 static struct ata_port_info info
[10] = {
548 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
550 .mwdma_mask
= 0x07, /* No SWDMA */
551 .udma_mask
= 0x07, /* UDMA 33 */
552 .port_ops
= &amd33_port_ops
554 { /* 1: Early AMD7409 - no swdma */
556 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
559 .udma_mask
= 0x1f, /* UDMA 66 */
560 .port_ops
= &amd66_port_ops
562 { /* 2: AMD 7409, no swdma errata */
564 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
567 .udma_mask
= 0x1f, /* UDMA 66 */
568 .port_ops
= &amd66_port_ops
572 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
575 .udma_mask
= 0x3f, /* UDMA 100 */
576 .port_ops
= &amd100_port_ops
580 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
583 .udma_mask
= 0x3f, /* UDMA 100 */
584 .port_ops
= &amd100_port_ops
588 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
591 .udma_mask
= 0x7f, /* UDMA 133, no swdma */
592 .port_ops
= &amd133_port_ops
594 { /* 6: AMD 8111 UDMA 100 (Serenade) */
596 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
599 .udma_mask
= 0x3f, /* UDMA 100, no swdma */
600 .port_ops
= &amd133_port_ops
602 { /* 7: Nvidia Nforce */
604 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
607 .udma_mask
= 0x3f, /* UDMA 100 */
608 .port_ops
= &nv100_port_ops
610 { /* 8: Nvidia Nforce2 and later */
612 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
615 .udma_mask
= 0x7f, /* UDMA 133, no swdma */
616 .port_ops
= &nv133_port_ops
618 { /* 9: AMD CS5536 (Geode companion) */
620 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
623 .udma_mask
= 0x3f, /* UDMA 100 */
624 .port_ops
= &amd100_port_ops
627 static struct ata_port_info
*port_info
[2];
628 static int printed_version
;
629 int type
= id
->driver_data
;
633 if (!printed_version
++)
634 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
636 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
637 pci_read_config_byte(pdev
, 0x41, &fifo
);
639 /* Check for AMD7409 without swdma errata and if found adjust type */
640 if (type
== 1 && rev
> 0x7)
643 /* Check for AMD7411 */
646 pci_write_config_byte(pdev
, 0x41, fifo
& 0x0F);
648 pci_write_config_byte(pdev
, 0x41, fifo
| 0xF0);
651 if (type
== 5 && pdev
->subsystem_vendor
== PCI_VENDOR_ID_AMD
&&
652 pdev
->subsystem_device
== PCI_DEVICE_ID_AMD_SERENADE
)
653 type
= 6; /* UDMA 100 only */
656 ata_pci_clear_simplex(pdev
);
660 port_info
[0] = port_info
[1] = &info
[type
];
661 return ata_pci_init_one(pdev
, port_info
, 2);
664 static const struct pci_device_id amd
[] = {
665 { PCI_VDEVICE(AMD
, PCI_DEVICE_ID_AMD_COBRA_7401
), 0 },
666 { PCI_VDEVICE(AMD
, PCI_DEVICE_ID_AMD_VIPER_7409
), 1 },
667 { PCI_VDEVICE(AMD
, PCI_DEVICE_ID_AMD_VIPER_7411
), 3 },
668 { PCI_VDEVICE(AMD
, PCI_DEVICE_ID_AMD_OPUS_7441
), 4 },
669 { PCI_VDEVICE(AMD
, PCI_DEVICE_ID_AMD_8111_IDE
), 5 },
670 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE
), 7 },
671 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE
), 8 },
672 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE
), 8 },
673 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE
), 8 },
674 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE
), 8 },
675 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE
), 8 },
676 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE
), 8 },
677 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE
), 8 },
678 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE
), 8 },
679 { PCI_VDEVICE(NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE
), 8 },
680 { PCI_VDEVICE(AMD
, PCI_DEVICE_ID_AMD_CS5536_IDE
), 9 },
685 static struct pci_driver amd_pci_driver
= {
688 .probe
= amd_init_one
,
689 .remove
= ata_pci_remove_one
692 static int __init
amd_init(void)
694 return pci_register_driver(&amd_pci_driver
);
697 static void __exit
amd_exit(void)
699 pci_unregister_driver(&amd_pci_driver
);
702 MODULE_AUTHOR("Alan Cox");
703 MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
704 MODULE_LICENSE("GPL");
705 MODULE_DEVICE_TABLE(pci
, amd
);
706 MODULE_VERSION(DRV_VERSION
);
708 module_init(amd_init
);
709 module_exit(amd_exit
);