[ARM] pxa: mmc: add 3rd host controller support for pxa310
[linux-2.6/kvm.git] / arch / arm / mach-pxa / devices.c
blob061ec92eb1e289550355e09599783f091a072367
1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/platform_device.h>
5 #include <linux/dma-mapping.h>
7 #include <asm/arch/gpio.h>
8 #include <asm/arch/udc.h>
9 #include <asm/arch/pxafb.h>
10 #include <asm/arch/mmc.h>
11 #include <asm/arch/irda.h>
12 #include <asm/arch/i2c.h>
14 #include "devices.h"
16 void __init pxa_register_device(struct platform_device *dev, void *data)
18 int ret;
20 dev->dev.platform_data = data;
22 ret = platform_device_register(dev);
23 if (ret)
24 dev_err(&dev->dev, "unable to register device: %d\n", ret);
27 static struct resource pxamci_resources[] = {
28 [0] = {
29 .start = 0x41100000,
30 .end = 0x41100fff,
31 .flags = IORESOURCE_MEM,
33 [1] = {
34 .start = IRQ_MMC,
35 .end = IRQ_MMC,
36 .flags = IORESOURCE_IRQ,
38 [2] = {
39 .start = 21,
40 .end = 21,
41 .flags = IORESOURCE_DMA,
43 [3] = {
44 .start = 22,
45 .end = 22,
46 .flags = IORESOURCE_DMA,
50 static u64 pxamci_dmamask = 0xffffffffUL;
52 struct platform_device pxa_device_mci = {
53 .name = "pxa2xx-mci",
54 .id = 0,
55 .dev = {
56 .dma_mask = &pxamci_dmamask,
57 .coherent_dma_mask = 0xffffffff,
59 .num_resources = ARRAY_SIZE(pxamci_resources),
60 .resource = pxamci_resources,
63 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
65 pxa_register_device(&pxa_device_mci, info);
69 static struct pxa2xx_udc_mach_info pxa_udc_info;
71 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
73 memcpy(&pxa_udc_info, info, sizeof *info);
76 static struct resource pxa2xx_udc_resources[] = {
77 [0] = {
78 .start = 0x40600000,
79 .end = 0x4060ffff,
80 .flags = IORESOURCE_MEM,
82 [1] = {
83 .start = IRQ_USB,
84 .end = IRQ_USB,
85 .flags = IORESOURCE_IRQ,
89 static u64 udc_dma_mask = ~(u32)0;
91 struct platform_device pxa_device_udc = {
92 .name = "pxa2xx-udc",
93 .id = -1,
94 .resource = pxa2xx_udc_resources,
95 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
96 .dev = {
97 .platform_data = &pxa_udc_info,
98 .dma_mask = &udc_dma_mask,
102 static struct resource pxafb_resources[] = {
103 [0] = {
104 .start = 0x44000000,
105 .end = 0x4400ffff,
106 .flags = IORESOURCE_MEM,
108 [1] = {
109 .start = IRQ_LCD,
110 .end = IRQ_LCD,
111 .flags = IORESOURCE_IRQ,
115 static u64 fb_dma_mask = ~(u64)0;
117 struct platform_device pxa_device_fb = {
118 .name = "pxa2xx-fb",
119 .id = -1,
120 .dev = {
121 .dma_mask = &fb_dma_mask,
122 .coherent_dma_mask = 0xffffffff,
124 .num_resources = ARRAY_SIZE(pxafb_resources),
125 .resource = pxafb_resources,
128 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
130 pxa_register_device(&pxa_device_fb, info);
133 void __init set_pxa_fb_parent(struct device *parent_dev)
135 pxa_device_fb.dev.parent = parent_dev;
138 static struct resource pxa_resource_ffuart[] = {
140 .start = __PREG(FFUART),
141 .end = __PREG(FFUART) + 35,
142 .flags = IORESOURCE_MEM,
143 }, {
144 .start = IRQ_FFUART,
145 .end = IRQ_FFUART,
146 .flags = IORESOURCE_IRQ,
150 struct platform_device pxa_device_ffuart= {
151 .name = "pxa2xx-uart",
152 .id = 0,
153 .resource = pxa_resource_ffuart,
154 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
157 static struct resource pxa_resource_btuart[] = {
159 .start = __PREG(BTUART),
160 .end = __PREG(BTUART) + 35,
161 .flags = IORESOURCE_MEM,
162 }, {
163 .start = IRQ_BTUART,
164 .end = IRQ_BTUART,
165 .flags = IORESOURCE_IRQ,
169 struct platform_device pxa_device_btuart = {
170 .name = "pxa2xx-uart",
171 .id = 1,
172 .resource = pxa_resource_btuart,
173 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
176 static struct resource pxa_resource_stuart[] = {
178 .start = __PREG(STUART),
179 .end = __PREG(STUART) + 35,
180 .flags = IORESOURCE_MEM,
181 }, {
182 .start = IRQ_STUART,
183 .end = IRQ_STUART,
184 .flags = IORESOURCE_IRQ,
188 struct platform_device pxa_device_stuart = {
189 .name = "pxa2xx-uart",
190 .id = 2,
191 .resource = pxa_resource_stuart,
192 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
195 static struct resource pxa_resource_hwuart[] = {
197 .start = __PREG(HWUART),
198 .end = __PREG(HWUART) + 47,
199 .flags = IORESOURCE_MEM,
200 }, {
201 .start = IRQ_HWUART,
202 .end = IRQ_HWUART,
203 .flags = IORESOURCE_IRQ,
207 struct platform_device pxa_device_hwuart = {
208 .name = "pxa2xx-uart",
209 .id = 3,
210 .resource = pxa_resource_hwuart,
211 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
214 static struct resource pxai2c_resources[] = {
216 .start = 0x40301680,
217 .end = 0x403016a3,
218 .flags = IORESOURCE_MEM,
219 }, {
220 .start = IRQ_I2C,
221 .end = IRQ_I2C,
222 .flags = IORESOURCE_IRQ,
226 struct platform_device pxa_device_i2c = {
227 .name = "pxa2xx-i2c",
228 .id = 0,
229 .resource = pxai2c_resources,
230 .num_resources = ARRAY_SIZE(pxai2c_resources),
233 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
235 pxa_register_device(&pxa_device_i2c, info);
238 static struct resource pxai2s_resources[] = {
240 .start = 0x40400000,
241 .end = 0x40400083,
242 .flags = IORESOURCE_MEM,
243 }, {
244 .start = IRQ_I2S,
245 .end = IRQ_I2S,
246 .flags = IORESOURCE_IRQ,
250 struct platform_device pxa_device_i2s = {
251 .name = "pxa2xx-i2s",
252 .id = -1,
253 .resource = pxai2s_resources,
254 .num_resources = ARRAY_SIZE(pxai2s_resources),
257 static u64 pxaficp_dmamask = ~(u32)0;
259 struct platform_device pxa_device_ficp = {
260 .name = "pxa2xx-ir",
261 .id = -1,
262 .dev = {
263 .dma_mask = &pxaficp_dmamask,
264 .coherent_dma_mask = 0xffffffff,
268 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
270 pxa_register_device(&pxa_device_ficp, info);
273 struct platform_device pxa_device_rtc = {
274 .name = "sa1100-rtc",
275 .id = -1,
278 #ifdef CONFIG_PXA25x
280 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
282 static struct resource pxa25x_resource_ssp[] = {
283 [0] = {
284 .start = 0x41000000,
285 .end = 0x4100001f,
286 .flags = IORESOURCE_MEM,
288 [1] = {
289 .start = IRQ_SSP,
290 .end = IRQ_SSP,
291 .flags = IORESOURCE_IRQ,
293 [2] = {
294 /* DRCMR for RX */
295 .start = 13,
296 .end = 13,
297 .flags = IORESOURCE_DMA,
299 [3] = {
300 /* DRCMR for TX */
301 .start = 14,
302 .end = 14,
303 .flags = IORESOURCE_DMA,
307 struct platform_device pxa25x_device_ssp = {
308 .name = "pxa25x-ssp",
309 .id = 0,
310 .dev = {
311 .dma_mask = &pxa25x_ssp_dma_mask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
314 .resource = pxa25x_resource_ssp,
315 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
318 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
320 static struct resource pxa25x_resource_nssp[] = {
321 [0] = {
322 .start = 0x41400000,
323 .end = 0x4140002f,
324 .flags = IORESOURCE_MEM,
326 [1] = {
327 .start = IRQ_NSSP,
328 .end = IRQ_NSSP,
329 .flags = IORESOURCE_IRQ,
331 [2] = {
332 /* DRCMR for RX */
333 .start = 15,
334 .end = 15,
335 .flags = IORESOURCE_DMA,
337 [3] = {
338 /* DRCMR for TX */
339 .start = 16,
340 .end = 16,
341 .flags = IORESOURCE_DMA,
345 struct platform_device pxa25x_device_nssp = {
346 .name = "pxa25x-nssp",
347 .id = 1,
348 .dev = {
349 .dma_mask = &pxa25x_nssp_dma_mask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
352 .resource = pxa25x_resource_nssp,
353 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
356 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
358 static struct resource pxa25x_resource_assp[] = {
359 [0] = {
360 .start = 0x41500000,
361 .end = 0x4150002f,
362 .flags = IORESOURCE_MEM,
364 [1] = {
365 .start = IRQ_ASSP,
366 .end = IRQ_ASSP,
367 .flags = IORESOURCE_IRQ,
369 [2] = {
370 /* DRCMR for RX */
371 .start = 23,
372 .end = 23,
373 .flags = IORESOURCE_DMA,
375 [3] = {
376 /* DRCMR for TX */
377 .start = 24,
378 .end = 24,
379 .flags = IORESOURCE_DMA,
383 struct platform_device pxa25x_device_assp = {
384 /* ASSP is basically equivalent to NSSP */
385 .name = "pxa25x-nssp",
386 .id = 2,
387 .dev = {
388 .dma_mask = &pxa25x_assp_dma_mask,
389 .coherent_dma_mask = DMA_BIT_MASK(32),
391 .resource = pxa25x_resource_assp,
392 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
394 #endif /* CONFIG_PXA25x */
396 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
398 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
400 static struct resource pxa27x_resource_ssp1[] = {
401 [0] = {
402 .start = 0x41000000,
403 .end = 0x4100003f,
404 .flags = IORESOURCE_MEM,
406 [1] = {
407 .start = IRQ_SSP,
408 .end = IRQ_SSP,
409 .flags = IORESOURCE_IRQ,
411 [2] = {
412 /* DRCMR for RX */
413 .start = 13,
414 .end = 13,
415 .flags = IORESOURCE_DMA,
417 [3] = {
418 /* DRCMR for TX */
419 .start = 14,
420 .end = 14,
421 .flags = IORESOURCE_DMA,
425 struct platform_device pxa27x_device_ssp1 = {
426 .name = "pxa27x-ssp",
427 .id = 0,
428 .dev = {
429 .dma_mask = &pxa27x_ssp1_dma_mask,
430 .coherent_dma_mask = DMA_BIT_MASK(32),
432 .resource = pxa27x_resource_ssp1,
433 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
436 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
438 static struct resource pxa27x_resource_ssp2[] = {
439 [0] = {
440 .start = 0x41700000,
441 .end = 0x4170003f,
442 .flags = IORESOURCE_MEM,
444 [1] = {
445 .start = IRQ_SSP2,
446 .end = IRQ_SSP2,
447 .flags = IORESOURCE_IRQ,
449 [2] = {
450 /* DRCMR for RX */
451 .start = 15,
452 .end = 15,
453 .flags = IORESOURCE_DMA,
455 [3] = {
456 /* DRCMR for TX */
457 .start = 16,
458 .end = 16,
459 .flags = IORESOURCE_DMA,
463 struct platform_device pxa27x_device_ssp2 = {
464 .name = "pxa27x-ssp",
465 .id = 1,
466 .dev = {
467 .dma_mask = &pxa27x_ssp2_dma_mask,
468 .coherent_dma_mask = DMA_BIT_MASK(32),
470 .resource = pxa27x_resource_ssp2,
471 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
474 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
476 static struct resource pxa27x_resource_ssp3[] = {
477 [0] = {
478 .start = 0x41900000,
479 .end = 0x4190003f,
480 .flags = IORESOURCE_MEM,
482 [1] = {
483 .start = IRQ_SSP3,
484 .end = IRQ_SSP3,
485 .flags = IORESOURCE_IRQ,
487 [2] = {
488 /* DRCMR for RX */
489 .start = 66,
490 .end = 66,
491 .flags = IORESOURCE_DMA,
493 [3] = {
494 /* DRCMR for TX */
495 .start = 67,
496 .end = 67,
497 .flags = IORESOURCE_DMA,
501 struct platform_device pxa27x_device_ssp3 = {
502 .name = "pxa27x-ssp",
503 .id = 2,
504 .dev = {
505 .dma_mask = &pxa27x_ssp3_dma_mask,
506 .coherent_dma_mask = DMA_BIT_MASK(32),
508 .resource = pxa27x_resource_ssp3,
509 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
511 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
513 #ifdef CONFIG_PXA3xx
514 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
516 static struct resource pxa3xx_resource_ssp4[] = {
517 [0] = {
518 .start = 0x41a00000,
519 .end = 0x41a0003f,
520 .flags = IORESOURCE_MEM,
522 [1] = {
523 .start = IRQ_SSP4,
524 .end = IRQ_SSP4,
525 .flags = IORESOURCE_IRQ,
527 [2] = {
528 /* DRCMR for RX */
529 .start = 2,
530 .end = 2,
531 .flags = IORESOURCE_DMA,
533 [3] = {
534 /* DRCMR for TX */
535 .start = 3,
536 .end = 3,
537 .flags = IORESOURCE_DMA,
541 struct platform_device pxa3xx_device_ssp4 = {
542 /* PXA3xx SSP is basically equivalent to PXA27x */
543 .name = "pxa27x-ssp",
544 .id = 3,
545 .dev = {
546 .dma_mask = &pxa3xx_ssp4_dma_mask,
547 .coherent_dma_mask = DMA_BIT_MASK(32),
549 .resource = pxa3xx_resource_ssp4,
550 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
553 static struct resource pxa3xx_resources_mci2[] = {
554 [0] = {
555 .start = 0x42000000,
556 .end = 0x42000fff,
557 .flags = IORESOURCE_MEM,
559 [1] = {
560 .start = IRQ_MMC2,
561 .end = IRQ_MMC2,
562 .flags = IORESOURCE_IRQ,
564 [2] = {
565 .start = 93,
566 .end = 93,
567 .flags = IORESOURCE_DMA,
569 [3] = {
570 .start = 94,
571 .end = 94,
572 .flags = IORESOURCE_DMA,
576 struct platform_device pxa3xx_device_mci2 = {
577 .name = "pxa2xx-mci",
578 .id = 1,
579 .dev = {
580 .dma_mask = &pxamci_dmamask,
581 .coherent_dma_mask = 0xffffffff,
583 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
584 .resource = pxa3xx_resources_mci2,
587 void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
589 pxa_register_device(&pxa3xx_device_mci2, info);
592 static struct resource pxa3xx_resources_mci3[] = {
593 [0] = {
594 .start = 0x42500000,
595 .end = 0x42500fff,
596 .flags = IORESOURCE_MEM,
598 [1] = {
599 .start = IRQ_MMC3,
600 .end = IRQ_MMC3,
601 .flags = IORESOURCE_IRQ,
603 [2] = {
604 .start = 100,
605 .end = 100,
606 .flags = IORESOURCE_DMA,
608 [3] = {
609 .start = 101,
610 .end = 101,
611 .flags = IORESOURCE_DMA,
615 struct platform_device pxa3xx_device_mci3 = {
616 .name = "pxa2xx-mci",
617 .id = 2,
618 .dev = {
619 .dma_mask = &pxamci_dmamask,
620 .coherent_dma_mask = 0xffffffff,
622 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
623 .resource = pxa3xx_resources_mci3,
626 void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
628 pxa_register_device(&pxa3xx_device_mci3, info);
631 #endif /* CONFIG_PXA3xx */