2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 unsigned int pci_pm_d3_delay
= PCI_PM_D3_WAIT
;
29 #ifdef CONFIG_PCI_DOMAINS
30 int pci_domains_supported
= 1;
33 #define DEFAULT_CARDBUS_IO_SIZE (256)
34 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
35 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
36 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
37 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
40 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
41 * @bus: pointer to PCI bus structure to search
43 * Given a PCI bus, returns the highest PCI bus number present in the set
44 * including the given PCI bus and its list of child PCI buses.
46 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
48 struct list_head
*tmp
;
51 max
= bus
->subordinate
;
52 list_for_each(tmp
, &bus
->children
) {
53 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
59 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
61 #ifdef CONFIG_HAS_IOMEM
62 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
65 * Make sure the BAR is actually a memory resource, not an IO resource
67 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
71 return ioremap_nocache(pci_resource_start(pdev
, bar
),
72 pci_resource_len(pdev
, bar
));
74 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
79 * pci_max_busnr - returns maximum PCI bus number
81 * Returns the highest PCI bus number present in the system global list of
84 unsigned char __devinit
87 struct pci_bus
*bus
= NULL
;
91 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
92 n
= pci_bus_max_busnr(bus
);
101 #define PCI_FIND_CAP_TTL 48
103 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
104 u8 pos
, int cap
, int *ttl
)
109 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
113 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
119 pos
+= PCI_CAP_LIST_NEXT
;
124 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
127 int ttl
= PCI_FIND_CAP_TTL
;
129 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
132 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
134 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
135 pos
+ PCI_CAP_LIST_NEXT
, cap
);
137 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
139 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
140 unsigned int devfn
, u8 hdr_type
)
144 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
145 if (!(status
& PCI_STATUS_CAP_LIST
))
149 case PCI_HEADER_TYPE_NORMAL
:
150 case PCI_HEADER_TYPE_BRIDGE
:
151 return PCI_CAPABILITY_LIST
;
152 case PCI_HEADER_TYPE_CARDBUS
:
153 return PCI_CB_CAPABILITY_LIST
;
162 * pci_find_capability - query for devices' capabilities
163 * @dev: PCI device to query
164 * @cap: capability code
166 * Tell if a device supports a given PCI capability.
167 * Returns the address of the requested capability structure within the
168 * device's PCI configuration space or 0 in case the device does not
169 * support it. Possible values for @cap:
171 * %PCI_CAP_ID_PM Power Management
172 * %PCI_CAP_ID_AGP Accelerated Graphics Port
173 * %PCI_CAP_ID_VPD Vital Product Data
174 * %PCI_CAP_ID_SLOTID Slot Identification
175 * %PCI_CAP_ID_MSI Message Signalled Interrupts
176 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
177 * %PCI_CAP_ID_PCIX PCI-X
178 * %PCI_CAP_ID_EXP PCI Express
180 int pci_find_capability(struct pci_dev
*dev
, int cap
)
184 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
186 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
192 * pci_bus_find_capability - query for devices' capabilities
193 * @bus: the PCI bus to query
194 * @devfn: PCI device to query
195 * @cap: capability code
197 * Like pci_find_capability() but works for pci devices that do not have a
198 * pci_dev structure set up yet.
200 * Returns the address of the requested capability structure within the
201 * device's PCI configuration space or 0 in case the device does not
204 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
209 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
211 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
213 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
219 * pci_find_ext_capability - Find an extended capability
220 * @dev: PCI device to query
221 * @cap: capability code
223 * Returns the address of the requested extended capability structure
224 * within the device's PCI configuration space or 0 if the device does
225 * not support it. Possible values for @cap:
227 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
228 * %PCI_EXT_CAP_ID_VC Virtual Channel
229 * %PCI_EXT_CAP_ID_DSN Device Serial Number
230 * %PCI_EXT_CAP_ID_PWR Power Budgeting
232 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
236 int pos
= PCI_CFG_SPACE_SIZE
;
238 /* minimum 8 bytes per capability */
239 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
241 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
244 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
248 * If we have no capabilities, this is indicated by cap ID,
249 * cap version and next pointer all being 0.
255 if (PCI_EXT_CAP_ID(header
) == cap
)
258 pos
= PCI_EXT_CAP_NEXT(header
);
259 if (pos
< PCI_CFG_SPACE_SIZE
)
262 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
268 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
270 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
272 int rc
, ttl
= PCI_FIND_CAP_TTL
;
275 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
276 mask
= HT_3BIT_CAP_MASK
;
278 mask
= HT_5BIT_CAP_MASK
;
280 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
281 PCI_CAP_ID_HT
, &ttl
);
283 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
284 if (rc
!= PCIBIOS_SUCCESSFUL
)
287 if ((cap
& mask
) == ht_cap
)
290 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
291 pos
+ PCI_CAP_LIST_NEXT
,
292 PCI_CAP_ID_HT
, &ttl
);
298 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
299 * @dev: PCI device to query
300 * @pos: Position from which to continue searching
301 * @ht_cap: Hypertransport capability code
303 * To be used in conjunction with pci_find_ht_capability() to search for
304 * all capabilities matching @ht_cap. @pos should always be a value returned
305 * from pci_find_ht_capability().
307 * NB. To be 100% safe against broken PCI devices, the caller should take
308 * steps to avoid an infinite loop.
310 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
312 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
314 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
317 * pci_find_ht_capability - query a device's Hypertransport capabilities
318 * @dev: PCI device to query
319 * @ht_cap: Hypertransport capability code
321 * Tell if a device supports a given Hypertransport capability.
322 * Returns an address within the device's PCI configuration space
323 * or 0 in case the device does not support the request capability.
324 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
325 * which has a Hypertransport capability matching @ht_cap.
327 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
331 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
333 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
337 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
340 * pci_find_parent_resource - return resource region of parent bus of given region
341 * @dev: PCI device structure contains resources to be searched
342 * @res: child resource record for which parent is sought
344 * For given resource region of given device, return the resource
345 * region of parent bus the given region is contained in or where
346 * it should be allocated from.
349 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
351 const struct pci_bus
*bus
= dev
->bus
;
353 struct resource
*best
= NULL
;
355 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
356 struct resource
*r
= bus
->resource
[i
];
359 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
360 continue; /* Not contained */
361 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
362 continue; /* Wrong type */
363 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
364 return r
; /* Exact match */
365 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
366 best
= r
; /* Approximating prefetchable by non-prefetchable */
372 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
373 * @dev: PCI device to have its BARs restored
375 * Restore the BAR values for a given device, so as to make it
376 * accessible by its driver.
379 pci_restore_bars(struct pci_dev
*dev
)
383 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
384 pci_update_resource(dev
, i
);
387 static struct pci_platform_pm_ops
*pci_platform_pm
;
389 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
391 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
392 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
394 pci_platform_pm
= ops
;
398 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
400 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
403 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
406 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
409 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
411 return pci_platform_pm
?
412 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
415 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
417 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
420 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
422 return pci_platform_pm
?
423 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
427 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
429 * @dev: PCI device to handle.
430 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
433 * -EINVAL if the requested state is invalid.
434 * -EIO if device does not support PCI PM or its PM capabilities register has a
435 * wrong version, or device doesn't support the requested state.
436 * 0 if device already is in the requested state.
437 * 0 if device's power state has been successfully changed.
439 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
442 bool need_restore
= false;
444 /* Check if we're already there */
445 if (dev
->current_state
== state
)
451 if (state
< PCI_D0
|| state
> PCI_D3hot
)
454 /* Validate current state:
455 * Can enter D0 from any state, but if we can only go deeper
456 * to sleep if we're already in a low power state
458 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
459 && dev
->current_state
> state
) {
460 dev_err(&dev
->dev
, "invalid power transition "
461 "(from state %d to %d)\n", dev
->current_state
, state
);
465 /* check if this device supports the desired state */
466 if ((state
== PCI_D1
&& !dev
->d1_support
)
467 || (state
== PCI_D2
&& !dev
->d2_support
))
470 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
472 /* If we're (effectively) in D3, force entire word to 0.
473 * This doesn't affect PME_Status, disables PME_En, and
474 * sets PowerState to 0.
476 switch (dev
->current_state
) {
480 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
483 case PCI_UNKNOWN
: /* Boot-up */
484 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
485 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
487 /* Fall-through: force to D0 */
493 /* enter specified state */
494 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
496 /* Mandatory power management transition delays */
497 /* see PCI PM 1.1 5.6.1 table 18 */
498 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
499 msleep(pci_pm_d3_delay
);
500 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
501 udelay(PCI_PM_D2_DELAY
);
503 dev
->current_state
= state
;
505 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
506 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
507 * from D3hot to D0 _may_ perform an internal reset, thereby
508 * going to "D0 Uninitialized" rather than "D0 Initialized".
509 * For example, at least some versions of the 3c905B and the
510 * 3c556B exhibit this behaviour.
512 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
513 * devices in a D3hot state at boot. Consequently, we need to
514 * restore at least the BARs so that the device will be
515 * accessible to its driver.
518 pci_restore_bars(dev
);
521 pcie_aspm_pm_state_change(dev
->bus
->self
);
527 * pci_update_current_state - Read PCI power state of given device from its
528 * PCI PM registers and cache it
529 * @dev: PCI device to handle.
530 * @state: State to cache in case the device doesn't have the PM capability
532 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
537 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
538 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
540 dev
->current_state
= state
;
545 * pci_platform_power_transition - Use platform to change device power state
546 * @dev: PCI device to handle.
547 * @state: State to put the device into.
549 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
553 if (platform_pci_power_manageable(dev
)) {
554 error
= platform_pci_set_power_state(dev
, state
);
556 pci_update_current_state(dev
, state
);
559 /* Fall back to PCI_D0 if native PM is not supported */
560 pci_update_current_state(dev
, PCI_D0
);
567 * __pci_start_power_transition - Start power transition of a PCI device
568 * @dev: PCI device to handle.
569 * @state: State to put the device into.
571 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
574 pci_platform_power_transition(dev
, PCI_D0
);
578 * __pci_complete_power_transition - Complete power transition of a PCI device
579 * @dev: PCI device to handle.
580 * @state: State to put the device into.
582 * This function should not be called directly by device drivers.
584 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
586 return state
> PCI_D0
?
587 pci_platform_power_transition(dev
, state
) : -EINVAL
;
589 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
592 * pci_set_power_state - Set the power state of a PCI device
593 * @dev: PCI device to handle.
594 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
596 * Transition a device to a new power state, using the platform firmware and/or
597 * the device's PCI PM registers.
600 * -EINVAL if the requested state is invalid.
601 * -EIO if device does not support PCI PM or its PM capabilities register has a
602 * wrong version, or device doesn't support the requested state.
603 * 0 if device already is in the requested state.
604 * 0 if device's power state has been successfully changed.
606 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
610 /* bound the state we're entering */
611 if (state
> PCI_D3hot
)
613 else if (state
< PCI_D0
)
615 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
617 * If the device or the parent bridge do not support PCI PM,
618 * ignore the request if we're doing anything other than putting
619 * it into D0 (which would only happen on boot).
623 /* Check if we're already there */
624 if (dev
->current_state
== state
)
627 __pci_start_power_transition(dev
, state
);
629 /* This device is quirked not to be put into D3, so
630 don't put it in D3 */
631 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
634 error
= pci_raw_set_power_state(dev
, state
);
636 if (!__pci_complete_power_transition(dev
, state
))
643 * pci_choose_state - Choose the power state of a PCI device
644 * @dev: PCI device to be suspended
645 * @state: target sleep state for the whole system. This is the value
646 * that is passed to suspend() function.
648 * Returns PCI power state suitable for given device and given system
652 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
656 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
659 ret
= platform_pci_choose_state(dev
);
660 if (ret
!= PCI_POWER_ERROR
)
663 switch (state
.event
) {
666 case PM_EVENT_FREEZE
:
667 case PM_EVENT_PRETHAW
:
668 /* REVISIT both freeze and pre-thaw "should" use D0 */
669 case PM_EVENT_SUSPEND
:
670 case PM_EVENT_HIBERNATE
:
673 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
680 EXPORT_SYMBOL(pci_choose_state
);
682 #define PCI_EXP_SAVE_REGS 7
684 #define pcie_cap_has_devctl(type, flags) 1
685 #define pcie_cap_has_lnkctl(type, flags) \
686 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
687 (type == PCI_EXP_TYPE_ROOT_PORT || \
688 type == PCI_EXP_TYPE_ENDPOINT || \
689 type == PCI_EXP_TYPE_LEG_END))
690 #define pcie_cap_has_sltctl(type, flags) \
691 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
692 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
693 (type == PCI_EXP_TYPE_DOWNSTREAM && \
694 (flags & PCI_EXP_FLAGS_SLOT))))
695 #define pcie_cap_has_rtctl(type, flags) \
696 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
697 (type == PCI_EXP_TYPE_ROOT_PORT || \
698 type == PCI_EXP_TYPE_RC_EC))
699 #define pcie_cap_has_devctl2(type, flags) \
700 ((flags & PCI_EXP_FLAGS_VERS) > 1)
701 #define pcie_cap_has_lnkctl2(type, flags) \
702 ((flags & PCI_EXP_FLAGS_VERS) > 1)
703 #define pcie_cap_has_sltctl2(type, flags) \
704 ((flags & PCI_EXP_FLAGS_VERS) > 1)
706 static int pci_save_pcie_state(struct pci_dev
*dev
)
709 struct pci_cap_saved_state
*save_state
;
713 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
717 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
719 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
722 cap
= (u16
*)&save_state
->data
[0];
724 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
726 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
727 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
728 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
729 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
730 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
731 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
732 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
733 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
734 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
735 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
736 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
737 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
738 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
739 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
744 static void pci_restore_pcie_state(struct pci_dev
*dev
)
747 struct pci_cap_saved_state
*save_state
;
751 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
752 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
753 if (!save_state
|| pos
<= 0)
755 cap
= (u16
*)&save_state
->data
[0];
757 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
759 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
760 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
761 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
762 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
763 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
764 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
765 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
766 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
767 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
768 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
769 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
770 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
771 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
772 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
776 static int pci_save_pcix_state(struct pci_dev
*dev
)
779 struct pci_cap_saved_state
*save_state
;
781 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
785 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
787 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
791 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
796 static void pci_restore_pcix_state(struct pci_dev
*dev
)
799 struct pci_cap_saved_state
*save_state
;
802 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
803 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
804 if (!save_state
|| pos
<= 0)
806 cap
= (u16
*)&save_state
->data
[0];
808 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
813 * pci_save_state - save the PCI configuration space of a device before suspending
814 * @dev: - PCI device that we're dealing with
817 pci_save_state(struct pci_dev
*dev
)
820 /* XXX: 100% dword access ok here? */
821 for (i
= 0; i
< 16; i
++)
822 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
823 dev
->state_saved
= true;
824 if ((i
= pci_save_pcie_state(dev
)) != 0)
826 if ((i
= pci_save_pcix_state(dev
)) != 0)
832 * pci_restore_state - Restore the saved state of a PCI device
833 * @dev: - PCI device that we're dealing with
836 pci_restore_state(struct pci_dev
*dev
)
841 /* PCI Express register must be restored first */
842 pci_restore_pcie_state(dev
);
845 * The Base Address register should be programmed before the command
848 for (i
= 15; i
>= 0; i
--) {
849 pci_read_config_dword(dev
, i
* 4, &val
);
850 if (val
!= dev
->saved_config_space
[i
]) {
851 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
852 "space at offset %#x (was %#x, writing %#x)\n",
853 i
, val
, (int)dev
->saved_config_space
[i
]);
854 pci_write_config_dword(dev
,i
* 4,
855 dev
->saved_config_space
[i
]);
858 pci_restore_pcix_state(dev
);
859 pci_restore_msi_state(dev
);
860 pci_restore_iov_state(dev
);
865 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
869 err
= pci_set_power_state(dev
, PCI_D0
);
870 if (err
< 0 && err
!= -EIO
)
872 err
= pcibios_enable_device(dev
, bars
);
875 pci_fixup_device(pci_fixup_enable
, dev
);
881 * pci_reenable_device - Resume abandoned device
882 * @dev: PCI device to be resumed
884 * Note this function is a backend of pci_default_resume and is not supposed
885 * to be called by normal code, write proper resume handler and use it instead.
887 int pci_reenable_device(struct pci_dev
*dev
)
889 if (pci_is_enabled(dev
))
890 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
894 static int __pci_enable_device_flags(struct pci_dev
*dev
,
895 resource_size_t flags
)
900 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
901 return 0; /* already enabled */
903 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
904 if (dev
->resource
[i
].flags
& flags
)
907 err
= do_pci_enable_device(dev
, bars
);
909 atomic_dec(&dev
->enable_cnt
);
914 * pci_enable_device_io - Initialize a device for use with IO space
915 * @dev: PCI device to be initialized
917 * Initialize device before it's used by a driver. Ask low-level code
918 * to enable I/O resources. Wake up the device if it was suspended.
919 * Beware, this function can fail.
921 int pci_enable_device_io(struct pci_dev
*dev
)
923 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
927 * pci_enable_device_mem - Initialize a device for use with Memory space
928 * @dev: PCI device to be initialized
930 * Initialize device before it's used by a driver. Ask low-level code
931 * to enable Memory resources. Wake up the device if it was suspended.
932 * Beware, this function can fail.
934 int pci_enable_device_mem(struct pci_dev
*dev
)
936 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
940 * pci_enable_device - Initialize device before it's used by a driver.
941 * @dev: PCI device to be initialized
943 * Initialize device before it's used by a driver. Ask low-level code
944 * to enable I/O and memory. Wake up the device if it was suspended.
945 * Beware, this function can fail.
947 * Note we don't actually enable the device many times if we call
948 * this function repeatedly (we just increment the count).
950 int pci_enable_device(struct pci_dev
*dev
)
952 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
956 * Managed PCI resources. This manages device on/off, intx/msi/msix
957 * on/off and BAR regions. pci_dev itself records msi/msix status, so
958 * there's no need to track it separately. pci_devres is initialized
959 * when a device is enabled using managed PCI device enable interface.
962 unsigned int enabled
:1;
963 unsigned int pinned
:1;
964 unsigned int orig_intx
:1;
965 unsigned int restore_intx
:1;
969 static void pcim_release(struct device
*gendev
, void *res
)
971 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
972 struct pci_devres
*this = res
;
975 if (dev
->msi_enabled
)
976 pci_disable_msi(dev
);
977 if (dev
->msix_enabled
)
978 pci_disable_msix(dev
);
980 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
981 if (this->region_mask
& (1 << i
))
982 pci_release_region(dev
, i
);
984 if (this->restore_intx
)
985 pci_intx(dev
, this->orig_intx
);
987 if (this->enabled
&& !this->pinned
)
988 pci_disable_device(dev
);
991 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
993 struct pci_devres
*dr
, *new_dr
;
995 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
999 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1002 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1005 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1007 if (pci_is_managed(pdev
))
1008 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1013 * pcim_enable_device - Managed pci_enable_device()
1014 * @pdev: PCI device to be initialized
1016 * Managed pci_enable_device().
1018 int pcim_enable_device(struct pci_dev
*pdev
)
1020 struct pci_devres
*dr
;
1023 dr
= get_pci_dr(pdev
);
1029 rc
= pci_enable_device(pdev
);
1031 pdev
->is_managed
= 1;
1038 * pcim_pin_device - Pin managed PCI device
1039 * @pdev: PCI device to pin
1041 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1042 * driver detach. @pdev must have been enabled with
1043 * pcim_enable_device().
1045 void pcim_pin_device(struct pci_dev
*pdev
)
1047 struct pci_devres
*dr
;
1049 dr
= find_pci_dr(pdev
);
1050 WARN_ON(!dr
|| !dr
->enabled
);
1056 * pcibios_disable_device - disable arch specific PCI resources for device dev
1057 * @dev: the PCI device to disable
1059 * Disables architecture specific PCI resources for the device. This
1060 * is the default implementation. Architecture implementations can
1063 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1065 static void do_pci_disable_device(struct pci_dev
*dev
)
1069 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1070 if (pci_command
& PCI_COMMAND_MASTER
) {
1071 pci_command
&= ~PCI_COMMAND_MASTER
;
1072 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1075 pcibios_disable_device(dev
);
1079 * pci_disable_enabled_device - Disable device without updating enable_cnt
1080 * @dev: PCI device to disable
1082 * NOTE: This function is a backend of PCI power management routines and is
1083 * not supposed to be called drivers.
1085 void pci_disable_enabled_device(struct pci_dev
*dev
)
1087 if (pci_is_enabled(dev
))
1088 do_pci_disable_device(dev
);
1092 * pci_disable_device - Disable PCI device after use
1093 * @dev: PCI device to be disabled
1095 * Signal to the system that the PCI device is not in use by the system
1096 * anymore. This only involves disabling PCI bus-mastering, if active.
1098 * Note we don't actually disable the device until all callers of
1099 * pci_device_enable() have called pci_device_disable().
1102 pci_disable_device(struct pci_dev
*dev
)
1104 struct pci_devres
*dr
;
1106 dr
= find_pci_dr(dev
);
1110 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1113 do_pci_disable_device(dev
);
1115 dev
->is_busmaster
= 0;
1119 * pcibios_set_pcie_reset_state - set reset state for device dev
1120 * @dev: the PCI-E device reset
1121 * @state: Reset state to enter into
1124 * Sets the PCI-E reset state for the device. This is the default
1125 * implementation. Architecture implementations can override this.
1127 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1128 enum pcie_reset_state state
)
1134 * pci_set_pcie_reset_state - set reset state for device dev
1135 * @dev: the PCI-E device reset
1136 * @state: Reset state to enter into
1139 * Sets the PCI reset state for the device.
1141 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1143 return pcibios_set_pcie_reset_state(dev
, state
);
1147 * pci_pme_capable - check the capability of PCI device to generate PME#
1148 * @dev: PCI device to handle.
1149 * @state: PCI state from which device will issue PME#.
1151 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1156 return !!(dev
->pme_support
& (1 << state
));
1160 * pci_pme_active - enable or disable PCI device's PME# function
1161 * @dev: PCI device to handle.
1162 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1164 * The caller must verify that the device is capable of generating PME# before
1165 * calling this function with @enable equal to 'true'.
1167 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1174 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1175 /* Clear PME_Status by writing 1 to it and enable PME# */
1176 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1178 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1180 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1182 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1183 enable
? "enabled" : "disabled");
1187 * pci_enable_wake - enable PCI device as wakeup event source
1188 * @dev: PCI device affected
1189 * @state: PCI state from which device will issue wakeup events
1190 * @enable: True to enable event generation; false to disable
1192 * This enables the device as a wakeup event source, or disables it.
1193 * When such events involves platform-specific hooks, those hooks are
1194 * called automatically by this routine.
1196 * Devices with legacy power management (no standard PCI PM capabilities)
1197 * always require such platform hooks.
1200 * 0 is returned on success
1201 * -EINVAL is returned if device is not supposed to wake up the system
1202 * Error code depending on the platform is returned if both the platform and
1203 * the native mechanism fail to enable the generation of wake-up events
1205 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1208 bool pme_done
= false;
1210 if (enable
&& !device_may_wakeup(&dev
->dev
))
1214 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1215 * Anderson we should be doing PME# wake enable followed by ACPI wake
1216 * enable. To disable wake-up we call the platform first, for symmetry.
1219 if (!enable
&& platform_pci_can_wakeup(dev
))
1220 error
= platform_pci_sleep_wake(dev
, false);
1222 if (!enable
|| pci_pme_capable(dev
, state
)) {
1223 pci_pme_active(dev
, enable
);
1227 if (enable
&& platform_pci_can_wakeup(dev
))
1228 error
= platform_pci_sleep_wake(dev
, true);
1230 return pme_done
? 0 : error
;
1234 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1235 * @dev: PCI device to prepare
1236 * @enable: True to enable wake-up event generation; false to disable
1238 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1239 * and this function allows them to set that up cleanly - pci_enable_wake()
1240 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1241 * ordering constraints.
1243 * This function only returns error code if the device is not capable of
1244 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1245 * enable wake-up power for it.
1247 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1249 return pci_pme_capable(dev
, PCI_D3cold
) ?
1250 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1251 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1255 * pci_target_state - find an appropriate low power state for a given PCI dev
1258 * Use underlying platform code to find a supported low power state for @dev.
1259 * If the platform can't manage @dev, return the deepest state from which it
1260 * can generate wake events, based on any available PME info.
1262 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1264 pci_power_t target_state
= PCI_D3hot
;
1266 if (platform_pci_power_manageable(dev
)) {
1268 * Call the platform to choose the target state of the device
1269 * and enable wake-up from this state if supported.
1271 pci_power_t state
= platform_pci_choose_state(dev
);
1274 case PCI_POWER_ERROR
:
1279 if (pci_no_d1d2(dev
))
1282 target_state
= state
;
1284 } else if (device_may_wakeup(&dev
->dev
)) {
1286 * Find the deepest state from which the device can generate
1287 * wake-up events, make it the target state and enable device
1291 return PCI_POWER_ERROR
;
1293 if (dev
->pme_support
) {
1295 && !(dev
->pme_support
& (1 << target_state
)))
1300 return target_state
;
1304 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1305 * @dev: Device to handle.
1307 * Choose the power state appropriate for the device depending on whether
1308 * it can wake up the system and/or is power manageable by the platform
1309 * (PCI_D3hot is the default) and put the device into that state.
1311 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1313 pci_power_t target_state
= pci_target_state(dev
);
1316 if (target_state
== PCI_POWER_ERROR
)
1319 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1321 error
= pci_set_power_state(dev
, target_state
);
1324 pci_enable_wake(dev
, target_state
, false);
1330 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1331 * @dev: Device to handle.
1333 * Disable device's sytem wake-up capability and put it into D0.
1335 int pci_back_from_sleep(struct pci_dev
*dev
)
1337 pci_enable_wake(dev
, PCI_D0
, false);
1338 return pci_set_power_state(dev
, PCI_D0
);
1342 * pci_pm_init - Initialize PM functions of given PCI device
1343 * @dev: PCI device to handle.
1345 void pci_pm_init(struct pci_dev
*dev
)
1352 /* find PCI PM capability in list */
1353 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1356 /* Check device's ability to generate PME# */
1357 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1359 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1360 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1361 pmc
& PCI_PM_CAP_VER_MASK
);
1367 dev
->d1_support
= false;
1368 dev
->d2_support
= false;
1369 if (!pci_no_d1d2(dev
)) {
1370 if (pmc
& PCI_PM_CAP_D1
)
1371 dev
->d1_support
= true;
1372 if (pmc
& PCI_PM_CAP_D2
)
1373 dev
->d2_support
= true;
1375 if (dev
->d1_support
|| dev
->d2_support
)
1376 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1377 dev
->d1_support
? " D1" : "",
1378 dev
->d2_support
? " D2" : "");
1381 pmc
&= PCI_PM_CAP_PME_MASK
;
1383 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1384 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1385 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1386 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1387 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1388 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1389 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1391 * Make device's PM flags reflect the wake-up capability, but
1392 * let the user space enable it to wake up the system as needed.
1394 device_set_wakeup_capable(&dev
->dev
, true);
1395 device_set_wakeup_enable(&dev
->dev
, false);
1396 /* Disable the PME# generation functionality */
1397 pci_pme_active(dev
, false);
1399 dev
->pme_support
= 0;
1404 * platform_pci_wakeup_init - init platform wakeup if present
1407 * Some devices don't have PCI PM caps but can still generate wakeup
1408 * events through platform methods (like ACPI events). If @dev supports
1409 * platform wakeup events, set the device flag to indicate as much. This
1410 * may be redundant if the device also supports PCI PM caps, but double
1411 * initialization should be safe in that case.
1413 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1415 if (!platform_pci_can_wakeup(dev
))
1418 device_set_wakeup_capable(&dev
->dev
, true);
1419 device_set_wakeup_enable(&dev
->dev
, false);
1420 platform_pci_sleep_wake(dev
, false);
1424 * pci_add_save_buffer - allocate buffer for saving given capability registers
1425 * @dev: the PCI device
1426 * @cap: the capability to allocate the buffer for
1427 * @size: requested size of the buffer
1429 static int pci_add_cap_save_buffer(
1430 struct pci_dev
*dev
, char cap
, unsigned int size
)
1433 struct pci_cap_saved_state
*save_state
;
1435 pos
= pci_find_capability(dev
, cap
);
1439 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1443 save_state
->cap_nr
= cap
;
1444 pci_add_saved_cap(dev
, save_state
);
1450 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1451 * @dev: the PCI device
1453 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1457 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1458 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1461 "unable to preallocate PCI Express save buffer\n");
1463 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1466 "unable to preallocate PCI-X save buffer\n");
1470 * pci_enable_ari - enable ARI forwarding if hardware support it
1471 * @dev: the PCI device
1473 void pci_enable_ari(struct pci_dev
*dev
)
1478 struct pci_dev
*bridge
;
1480 if (!dev
->is_pcie
|| dev
->devfn
)
1483 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1487 bridge
= dev
->bus
->self
;
1488 if (!bridge
|| !bridge
->is_pcie
)
1491 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1495 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1496 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1499 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1500 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1501 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1503 bridge
->ari_enabled
= 1;
1507 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1508 * @dev: the PCI device
1509 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1511 * Perform INTx swizzling for a device behind one level of bridge. This is
1512 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1513 * behind bridges on add-in cards.
1515 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1517 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1521 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1529 while (dev
->bus
->parent
) {
1530 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1531 dev
= dev
->bus
->self
;
1538 * pci_common_swizzle - swizzle INTx all the way to root bridge
1539 * @dev: the PCI device
1540 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1542 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1543 * bridges all the way up to a PCI root bus.
1545 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1549 while (dev
->bus
->parent
) {
1550 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1551 dev
= dev
->bus
->self
;
1554 return PCI_SLOT(dev
->devfn
);
1558 * pci_release_region - Release a PCI bar
1559 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1560 * @bar: BAR to release
1562 * Releases the PCI I/O and memory resources previously reserved by a
1563 * successful call to pci_request_region. Call this function only
1564 * after all use of the PCI regions has ceased.
1566 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1568 struct pci_devres
*dr
;
1570 if (pci_resource_len(pdev
, bar
) == 0)
1572 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1573 release_region(pci_resource_start(pdev
, bar
),
1574 pci_resource_len(pdev
, bar
));
1575 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1576 release_mem_region(pci_resource_start(pdev
, bar
),
1577 pci_resource_len(pdev
, bar
));
1579 dr
= find_pci_dr(pdev
);
1581 dr
->region_mask
&= ~(1 << bar
);
1585 * __pci_request_region - Reserved PCI I/O and memory resource
1586 * @pdev: PCI device whose resources are to be reserved
1587 * @bar: BAR to be reserved
1588 * @res_name: Name to be associated with resource.
1589 * @exclusive: whether the region access is exclusive or not
1591 * Mark the PCI region associated with PCI device @pdev BR @bar as
1592 * being reserved by owner @res_name. Do not access any
1593 * address inside the PCI regions unless this call returns
1596 * If @exclusive is set, then the region is marked so that userspace
1597 * is explicitly not allowed to map the resource via /dev/mem or
1598 * sysfs MMIO access.
1600 * Returns 0 on success, or %EBUSY on error. A warning
1601 * message is also printed on failure.
1603 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1606 struct pci_devres
*dr
;
1608 if (pci_resource_len(pdev
, bar
) == 0)
1611 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1612 if (!request_region(pci_resource_start(pdev
, bar
),
1613 pci_resource_len(pdev
, bar
), res_name
))
1616 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1617 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1618 pci_resource_len(pdev
, bar
), res_name
,
1623 dr
= find_pci_dr(pdev
);
1625 dr
->region_mask
|= 1 << bar
;
1630 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1632 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1633 &pdev
->resource
[bar
]);
1638 * pci_request_region - Reserve PCI I/O and memory resource
1639 * @pdev: PCI device whose resources are to be reserved
1640 * @bar: BAR to be reserved
1641 * @res_name: Name to be associated with resource
1643 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1644 * being reserved by owner @res_name. Do not access any
1645 * address inside the PCI regions unless this call returns
1648 * Returns 0 on success, or %EBUSY on error. A warning
1649 * message is also printed on failure.
1651 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1653 return __pci_request_region(pdev
, bar
, res_name
, 0);
1657 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1658 * @pdev: PCI device whose resources are to be reserved
1659 * @bar: BAR to be reserved
1660 * @res_name: Name to be associated with resource.
1662 * Mark the PCI region associated with PCI device @pdev BR @bar as
1663 * being reserved by owner @res_name. Do not access any
1664 * address inside the PCI regions unless this call returns
1667 * Returns 0 on success, or %EBUSY on error. A warning
1668 * message is also printed on failure.
1670 * The key difference that _exclusive makes it that userspace is
1671 * explicitly not allowed to map the resource via /dev/mem or
1674 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1676 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1679 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1680 * @pdev: PCI device whose resources were previously reserved
1681 * @bars: Bitmask of BARs to be released
1683 * Release selected PCI I/O and memory resources previously reserved.
1684 * Call this function only after all use of the PCI regions has ceased.
1686 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1690 for (i
= 0; i
< 6; i
++)
1691 if (bars
& (1 << i
))
1692 pci_release_region(pdev
, i
);
1695 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1696 const char *res_name
, int excl
)
1700 for (i
= 0; i
< 6; i
++)
1701 if (bars
& (1 << i
))
1702 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1708 if (bars
& (1 << i
))
1709 pci_release_region(pdev
, i
);
1716 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1717 * @pdev: PCI device whose resources are to be reserved
1718 * @bars: Bitmask of BARs to be requested
1719 * @res_name: Name to be associated with resource
1721 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1722 const char *res_name
)
1724 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1727 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1728 int bars
, const char *res_name
)
1730 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1731 IORESOURCE_EXCLUSIVE
);
1735 * pci_release_regions - Release reserved PCI I/O and memory resources
1736 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1738 * Releases all PCI I/O and memory resources previously reserved by a
1739 * successful call to pci_request_regions. Call this function only
1740 * after all use of the PCI regions has ceased.
1743 void pci_release_regions(struct pci_dev
*pdev
)
1745 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1749 * pci_request_regions - Reserved PCI I/O and memory resources
1750 * @pdev: PCI device whose resources are to be reserved
1751 * @res_name: Name to be associated with resource.
1753 * Mark all PCI regions associated with PCI device @pdev as
1754 * being reserved by owner @res_name. Do not access any
1755 * address inside the PCI regions unless this call returns
1758 * Returns 0 on success, or %EBUSY on error. A warning
1759 * message is also printed on failure.
1761 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1763 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1767 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1768 * @pdev: PCI device whose resources are to be reserved
1769 * @res_name: Name to be associated with resource.
1771 * Mark all PCI regions associated with PCI device @pdev as
1772 * being reserved by owner @res_name. Do not access any
1773 * address inside the PCI regions unless this call returns
1776 * pci_request_regions_exclusive() will mark the region so that
1777 * /dev/mem and the sysfs MMIO access will not be allowed.
1779 * Returns 0 on success, or %EBUSY on error. A warning
1780 * message is also printed on failure.
1782 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1784 return pci_request_selected_regions_exclusive(pdev
,
1785 ((1 << 6) - 1), res_name
);
1788 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
1792 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
1794 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
1796 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
1797 if (cmd
!= old_cmd
) {
1798 dev_dbg(&dev
->dev
, "%s bus mastering\n",
1799 enable
? "enabling" : "disabling");
1800 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1802 dev
->is_busmaster
= enable
;
1806 * pci_set_master - enables bus-mastering for device dev
1807 * @dev: the PCI device to enable
1809 * Enables bus-mastering on the device and calls pcibios_set_master()
1810 * to do the needed arch specific settings.
1812 void pci_set_master(struct pci_dev
*dev
)
1814 __pci_set_master(dev
, true);
1815 pcibios_set_master(dev
);
1819 * pci_clear_master - disables bus-mastering for device dev
1820 * @dev: the PCI device to disable
1822 void pci_clear_master(struct pci_dev
*dev
)
1824 __pci_set_master(dev
, false);
1827 #ifdef PCI_DISABLE_MWI
1828 int pci_set_mwi(struct pci_dev
*dev
)
1833 int pci_try_set_mwi(struct pci_dev
*dev
)
1838 void pci_clear_mwi(struct pci_dev
*dev
)
1844 #ifndef PCI_CACHE_LINE_BYTES
1845 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1848 /* This can be overridden by arch code. */
1849 /* Don't forget this is measured in 32-bit words, not bytes */
1850 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1853 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1854 * @dev: the PCI device for which MWI is to be enabled
1856 * Helper function for pci_set_mwi.
1857 * Originally copied from drivers/net/acenic.c.
1858 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1860 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1863 pci_set_cacheline_size(struct pci_dev
*dev
)
1867 if (!pci_cache_line_size
)
1868 return -EINVAL
; /* The system doesn't support MWI. */
1870 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1871 equal to or multiple of the right value. */
1872 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1873 if (cacheline_size
>= pci_cache_line_size
&&
1874 (cacheline_size
% pci_cache_line_size
) == 0)
1877 /* Write the correct value. */
1878 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1880 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1881 if (cacheline_size
== pci_cache_line_size
)
1884 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1885 "supported\n", pci_cache_line_size
<< 2);
1891 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1892 * @dev: the PCI device for which MWI is enabled
1894 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1896 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1899 pci_set_mwi(struct pci_dev
*dev
)
1904 rc
= pci_set_cacheline_size(dev
);
1908 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1909 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1910 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1911 cmd
|= PCI_COMMAND_INVALIDATE
;
1912 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1919 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1920 * @dev: the PCI device for which MWI is enabled
1922 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1923 * Callers are not required to check the return value.
1925 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1927 int pci_try_set_mwi(struct pci_dev
*dev
)
1929 int rc
= pci_set_mwi(dev
);
1934 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1935 * @dev: the PCI device to disable
1937 * Disables PCI Memory-Write-Invalidate transaction on the device
1940 pci_clear_mwi(struct pci_dev
*dev
)
1944 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1945 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1946 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1947 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1950 #endif /* ! PCI_DISABLE_MWI */
1953 * pci_intx - enables/disables PCI INTx for device dev
1954 * @pdev: the PCI device to operate on
1955 * @enable: boolean: whether to enable or disable PCI INTx
1957 * Enables/disables PCI INTx for device dev
1960 pci_intx(struct pci_dev
*pdev
, int enable
)
1962 u16 pci_command
, new;
1964 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1967 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1969 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1972 if (new != pci_command
) {
1973 struct pci_devres
*dr
;
1975 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1977 dr
= find_pci_dr(pdev
);
1978 if (dr
&& !dr
->restore_intx
) {
1979 dr
->restore_intx
= 1;
1980 dr
->orig_intx
= !enable
;
1986 * pci_msi_off - disables any msi or msix capabilities
1987 * @dev: the PCI device to operate on
1989 * If you want to use msi see pci_enable_msi and friends.
1990 * This is a lower level primitive that allows us to disable
1991 * msi operation at the device level.
1993 void pci_msi_off(struct pci_dev
*dev
)
1998 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2000 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2001 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2002 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2004 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2006 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2007 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2008 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2012 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2014 * These can be overridden by arch-specific implementations
2017 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
2019 if (!pci_dma_supported(dev
, mask
))
2022 dev
->dma_mask
= mask
;
2028 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
2030 if (!pci_dma_supported(dev
, mask
))
2033 dev
->dev
.coherent_dma_mask
= mask
;
2039 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2040 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2042 return dma_set_max_seg_size(&dev
->dev
, size
);
2044 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2047 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2048 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2050 return dma_set_seg_boundary(&dev
->dev
, mask
);
2052 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2055 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
2059 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2063 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
2064 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2070 pci_block_user_cfg_access(dev
);
2072 /* Wait for Transaction Pending bit clean */
2073 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2074 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2075 goto transaction_done
;
2078 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2079 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2080 goto transaction_done
;
2082 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
2083 "sleeping for 1 second\n");
2085 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2086 if (status
& PCI_EXP_DEVSTA_TRPND
)
2087 dev_info(&dev
->dev
, "Still busy after 1s; "
2088 "proceeding with reset anyway\n");
2091 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
2092 PCI_EXP_DEVCTL_BCR_FLR
);
2095 pci_unblock_user_cfg_access(dev
);
2099 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
2101 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2107 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
2108 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2114 pci_block_user_cfg_access(dev
);
2116 /* Wait for Transaction Pending bit clean */
2117 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2118 if (!(status
& PCI_AF_STATUS_TP
))
2119 goto transaction_done
;
2122 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2123 if (!(status
& PCI_AF_STATUS_TP
))
2124 goto transaction_done
;
2126 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
2127 " reset; sleeping for 1 second\n");
2129 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2130 if (status
& PCI_AF_STATUS_TP
)
2131 dev_info(&dev
->dev
, "Still busy after 1s; "
2132 "proceeding with reset anyway\n");
2135 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2138 pci_unblock_user_cfg_access(dev
);
2142 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
2146 res
= __pcie_flr(pdev
, probe
);
2150 res
= __pci_af_flr(pdev
, probe
);
2158 * pci_execute_reset_function() - Reset a PCI device function
2159 * @dev: Device function to reset
2161 * Some devices allow an individual function to be reset without affecting
2162 * other functions in the same device. The PCI device must be responsive
2163 * to PCI config space in order to use this function.
2165 * The device function is presumed to be unused when this function is called.
2166 * Resetting the device will make the contents of PCI configuration space
2167 * random, so any caller of this must be prepared to reinitialise the
2168 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2171 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2172 * device doesn't support resetting a single function.
2174 int pci_execute_reset_function(struct pci_dev
*dev
)
2176 return __pci_reset_function(dev
, 0);
2178 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
2181 * pci_reset_function() - quiesce and reset a PCI device function
2182 * @dev: Device function to reset
2184 * Some devices allow an individual function to be reset without affecting
2185 * other functions in the same device. The PCI device must be responsive
2186 * to PCI config space in order to use this function.
2188 * This function does not just reset the PCI portion of a device, but
2189 * clears all the state associated with the device. This function differs
2190 * from pci_execute_reset_function in that it saves and restores device state
2193 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2194 * device doesn't support resetting a single function.
2196 int pci_reset_function(struct pci_dev
*dev
)
2198 int r
= __pci_reset_function(dev
, 1);
2203 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2204 disable_irq(dev
->irq
);
2205 pci_save_state(dev
);
2207 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2209 r
= pci_execute_reset_function(dev
);
2211 pci_restore_state(dev
);
2212 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2213 enable_irq(dev
->irq
);
2217 EXPORT_SYMBOL_GPL(pci_reset_function
);
2220 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2221 * @dev: PCI device to query
2223 * Returns mmrbc: maximum designed memory read count in bytes
2224 * or appropriate error value.
2226 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2231 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2235 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2239 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2241 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2244 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2245 * @dev: PCI device to query
2247 * Returns mmrbc: maximum memory read count in bytes
2248 * or appropriate error value.
2250 int pcix_get_mmrbc(struct pci_dev
*dev
)
2255 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2259 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2261 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2265 EXPORT_SYMBOL(pcix_get_mmrbc
);
2268 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2269 * @dev: PCI device to query
2270 * @mmrbc: maximum memory read count in bytes
2271 * valid values are 512, 1024, 2048, 4096
2273 * If possible sets maximum memory read byte count, some bridges have erratas
2274 * that prevent this.
2276 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2278 int cap
, err
= -EINVAL
;
2279 u32 stat
, cmd
, v
, o
;
2281 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2284 v
= ffs(mmrbc
) - 10;
2286 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2290 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2294 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2297 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2301 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2303 if (v
> o
&& dev
->bus
&&
2304 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2307 cmd
&= ~PCI_X_CMD_MAX_READ
;
2309 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2314 EXPORT_SYMBOL(pcix_set_mmrbc
);
2317 * pcie_get_readrq - get PCI Express read request size
2318 * @dev: PCI device to query
2320 * Returns maximum memory read request in bytes
2321 * or appropriate error value.
2323 int pcie_get_readrq(struct pci_dev
*dev
)
2328 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2332 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2334 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2338 EXPORT_SYMBOL(pcie_get_readrq
);
2341 * pcie_set_readrq - set PCI Express maximum memory read request
2342 * @dev: PCI device to query
2343 * @rq: maximum memory read count in bytes
2344 * valid values are 128, 256, 512, 1024, 2048, 4096
2346 * If possible sets maximum read byte count
2348 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2350 int cap
, err
= -EINVAL
;
2353 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2356 v
= (ffs(rq
) - 8) << 12;
2358 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2362 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2366 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2367 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2369 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2375 EXPORT_SYMBOL(pcie_set_readrq
);
2378 * pci_select_bars - Make BAR mask from the type of resource
2379 * @dev: the PCI device for which BAR mask is made
2380 * @flags: resource type mask to be selected
2382 * This helper routine makes bar mask from the type of resource.
2384 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2387 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2388 if (pci_resource_flags(dev
, i
) & flags
)
2394 * pci_resource_bar - get position of the BAR associated with a resource
2395 * @dev: the PCI device
2396 * @resno: the resource number
2397 * @type: the BAR type to be filled in
2399 * Returns BAR position in config space, or 0 if the BAR is invalid.
2401 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2405 if (resno
< PCI_ROM_RESOURCE
) {
2406 *type
= pci_bar_unknown
;
2407 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2408 } else if (resno
== PCI_ROM_RESOURCE
) {
2409 *type
= pci_bar_mem32
;
2410 return dev
->rom_base_reg
;
2411 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
2412 /* device specific resource */
2413 reg
= pci_iov_resource_bar(dev
, resno
, type
);
2418 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2422 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2423 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2424 spinlock_t resource_alignment_lock
= SPIN_LOCK_UNLOCKED
;
2427 * pci_specified_resource_alignment - get resource alignment specified by user.
2428 * @dev: the PCI device to get
2430 * RETURNS: Resource alignment if it is specified.
2431 * Zero if it is not specified.
2433 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2435 int seg
, bus
, slot
, func
, align_order
, count
;
2436 resource_size_t align
= 0;
2439 spin_lock(&resource_alignment_lock
);
2440 p
= resource_alignment_param
;
2443 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2449 if (sscanf(p
, "%x:%x:%x.%x%n",
2450 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2452 if (sscanf(p
, "%x:%x.%x%n",
2453 &bus
, &slot
, &func
, &count
) != 3) {
2454 /* Invalid format */
2455 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2461 if (seg
== pci_domain_nr(dev
->bus
) &&
2462 bus
== dev
->bus
->number
&&
2463 slot
== PCI_SLOT(dev
->devfn
) &&
2464 func
== PCI_FUNC(dev
->devfn
)) {
2465 if (align_order
== -1) {
2468 align
= 1 << align_order
;
2473 if (*p
!= ';' && *p
!= ',') {
2474 /* End of param or invalid format */
2479 spin_unlock(&resource_alignment_lock
);
2484 * pci_is_reassigndev - check if specified PCI is target device to reassign
2485 * @dev: the PCI device to check
2487 * RETURNS: non-zero for PCI device is a target device to reassign,
2490 int pci_is_reassigndev(struct pci_dev
*dev
)
2492 return (pci_specified_resource_alignment(dev
) != 0);
2495 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
2497 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
2498 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
2499 spin_lock(&resource_alignment_lock
);
2500 strncpy(resource_alignment_param
, buf
, count
);
2501 resource_alignment_param
[count
] = '\0';
2502 spin_unlock(&resource_alignment_lock
);
2506 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
2509 spin_lock(&resource_alignment_lock
);
2510 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
2511 spin_unlock(&resource_alignment_lock
);
2515 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
2517 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
2520 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
2521 const char *buf
, size_t count
)
2523 return pci_set_resource_alignment_param(buf
, count
);
2526 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
2527 pci_resource_alignment_store
);
2529 static int __init
pci_resource_alignment_sysfs_init(void)
2531 return bus_create_file(&pci_bus_type
,
2532 &bus_attr_resource_alignment
);
2535 late_initcall(pci_resource_alignment_sysfs_init
);
2537 static void __devinit
pci_no_domains(void)
2539 #ifdef CONFIG_PCI_DOMAINS
2540 pci_domains_supported
= 0;
2545 * pci_ext_cfg_enabled - can we access extended PCI config space?
2546 * @dev: The PCI device of the root bridge.
2548 * Returns 1 if we can access PCI extended config space (offsets
2549 * greater than 0xff). This is the default implementation. Architecture
2550 * implementations can override this.
2552 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2557 static int __devinit
pci_init(void)
2559 struct pci_dev
*dev
= NULL
;
2561 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2562 pci_fixup_device(pci_fixup_final
, dev
);
2568 static int __init
pci_setup(char *str
)
2571 char *k
= strchr(str
, ',');
2574 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2575 if (!strcmp(str
, "nomsi")) {
2577 } else if (!strcmp(str
, "noaer")) {
2579 } else if (!strcmp(str
, "nodomains")) {
2581 } else if (!strncmp(str
, "cbiosize=", 9)) {
2582 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2583 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2584 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2585 } else if (!strncmp(str
, "resource_alignment=", 19)) {
2586 pci_set_resource_alignment_param(str
+ 19,
2589 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2597 early_param("pci", pci_setup
);
2599 device_initcall(pci_init
);
2601 EXPORT_SYMBOL(pci_reenable_device
);
2602 EXPORT_SYMBOL(pci_enable_device_io
);
2603 EXPORT_SYMBOL(pci_enable_device_mem
);
2604 EXPORT_SYMBOL(pci_enable_device
);
2605 EXPORT_SYMBOL(pcim_enable_device
);
2606 EXPORT_SYMBOL(pcim_pin_device
);
2607 EXPORT_SYMBOL(pci_disable_device
);
2608 EXPORT_SYMBOL(pci_find_capability
);
2609 EXPORT_SYMBOL(pci_bus_find_capability
);
2610 EXPORT_SYMBOL(pci_release_regions
);
2611 EXPORT_SYMBOL(pci_request_regions
);
2612 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2613 EXPORT_SYMBOL(pci_release_region
);
2614 EXPORT_SYMBOL(pci_request_region
);
2615 EXPORT_SYMBOL(pci_request_region_exclusive
);
2616 EXPORT_SYMBOL(pci_release_selected_regions
);
2617 EXPORT_SYMBOL(pci_request_selected_regions
);
2618 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2619 EXPORT_SYMBOL(pci_set_master
);
2620 EXPORT_SYMBOL(pci_clear_master
);
2621 EXPORT_SYMBOL(pci_set_mwi
);
2622 EXPORT_SYMBOL(pci_try_set_mwi
);
2623 EXPORT_SYMBOL(pci_clear_mwi
);
2624 EXPORT_SYMBOL_GPL(pci_intx
);
2625 EXPORT_SYMBOL(pci_set_dma_mask
);
2626 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2627 EXPORT_SYMBOL(pci_assign_resource
);
2628 EXPORT_SYMBOL(pci_find_parent_resource
);
2629 EXPORT_SYMBOL(pci_select_bars
);
2631 EXPORT_SYMBOL(pci_set_power_state
);
2632 EXPORT_SYMBOL(pci_save_state
);
2633 EXPORT_SYMBOL(pci_restore_state
);
2634 EXPORT_SYMBOL(pci_pme_capable
);
2635 EXPORT_SYMBOL(pci_pme_active
);
2636 EXPORT_SYMBOL(pci_enable_wake
);
2637 EXPORT_SYMBOL(pci_wake_from_d3
);
2638 EXPORT_SYMBOL(pci_target_state
);
2639 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2640 EXPORT_SYMBOL(pci_back_from_sleep
);
2641 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);