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[libata] restore sg on DMA mapping failure
[linux-2.6/kvm.git] / drivers / mmc / pxamci.c
blobf31e247b2cbeabf479c912ae896453db70278935
1 /*
2 * linux/drivers/mmc/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/protocol.h>
29
30 #include <asm/dma.h>
31 #include <asm/io.h>
32 #include <asm/scatterlist.h>
33 #include <asm/sizes.h>
34
35 #include <asm/arch/pxa-regs.h>
36 #include <asm/arch/mmc.h>
37
38 #include "pxamci.h"
39
40 #ifdef CONFIG_MMC_DEBUG
41 #define DBG(x...) printk(KERN_DEBUG x)
42 #else
43 #define DBG(x...) do { } while (0)
44 #endif
45
46 #define DRIVER_NAME "pxa2xx-mci"
47
48 #define NR_SG 1
49
50 struct pxamci_host {
51 struct mmc_host *mmc;
52 spinlock_t lock;
53 struct resource *res;
54 void __iomem *base;
55 int irq;
56 int dma;
57 unsigned int clkrt;
58 unsigned int cmdat;
59 unsigned int imask;
60 unsigned int power_mode;
61 struct pxamci_platform_data *pdata;
62
63 struct mmc_request *mrq;
64 struct mmc_command *cmd;
65 struct mmc_data *data;
66
67 dma_addr_t sg_dma;
68 struct pxa_dma_desc *sg_cpu;
69 unsigned int dma_len;
70
71 unsigned int dma_dir;
72 };
73
74 static inline unsigned int ns_to_clocks(unsigned int ns)
75 {
76 return (ns * (CLOCKRATE / 1000000) + 999) / 1000;
77 }
78
79 static void pxamci_stop_clock(struct pxamci_host *host)
80 {
81 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
82 unsigned long timeout = 10000;
83 unsigned int v;
84
85 writel(STOP_CLOCK, host->base + MMC_STRPCL);
86
87 do {
88 v = readl(host->base + MMC_STAT);
89 if (!(v & STAT_CLK_EN))
90 break;
91 udelay(1);
92 } while (timeout--);
93
94 if (v & STAT_CLK_EN)
95 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
96 }
97 }
98
99 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
100 {
101 unsigned long flags;
102
103 spin_lock_irqsave(&host->lock, flags);
104 host->imask &= ~mask;
105 writel(host->imask, host->base + MMC_I_MASK);
106 spin_unlock_irqrestore(&host->lock, flags);
107 }
108
109 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
110 {
111 unsigned long flags;
112
113 spin_lock_irqsave(&host->lock, flags);
114 host->imask |= mask;
115 writel(host->imask, host->base + MMC_I_MASK);
116 spin_unlock_irqrestore(&host->lock, flags);
117 }
118
119 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
120 {
121 unsigned int nob = data->blocks;
122 unsigned int timeout;
123 u32 dcmd;
124 int i;
125
126 host->data = data;
127
128 if (data->flags & MMC_DATA_STREAM)
129 nob = 0xffff;
130
131 writel(nob, host->base + MMC_NOB);
132 writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
133
134 timeout = ns_to_clocks(data->timeout_ns) + data->timeout_clks;
135 writel((timeout + 255) / 256, host->base + MMC_RDTO);
136
137 if (data->flags & MMC_DATA_READ) {
138 host->dma_dir = DMA_FROM_DEVICE;
139 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
140 DRCMRTXMMC = 0;
141 DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
142 } else {
143 host->dma_dir = DMA_TO_DEVICE;
144 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
145 DRCMRRXMMC = 0;
146 DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
147 }
148
149 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
150
151 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
152 host->dma_dir);
153
154 for (i = 0; i < host->dma_len; i++) {
155 if (data->flags & MMC_DATA_READ) {
156 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
157 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
158 } else {
159 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
160 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
161 }
162 host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
163 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
164 sizeof(struct pxa_dma_desc);
165 }
166 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
167 wmb();
168
169 DDADR(host->dma) = host->sg_dma;
170 DCSR(host->dma) = DCSR_RUN;
171 }
172
173 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
174 {
175 WARN_ON(host->cmd != NULL);
176 host->cmd = cmd;
177
178 if (cmd->flags & MMC_RSP_BUSY)
179 cmdat |= CMDAT_BUSY;
180
181 switch (cmd->flags & (MMC_RSP_MASK | MMC_RSP_CRC)) {
182 case MMC_RSP_SHORT | MMC_RSP_CRC:
183 cmdat |= CMDAT_RESP_SHORT;
184 break;
185 case MMC_RSP_SHORT:
186 cmdat |= CMDAT_RESP_R3;
187 break;
188 case MMC_RSP_LONG | MMC_RSP_CRC:
189 cmdat |= CMDAT_RESP_R2;
190 break;
191 default:
192 break;
193 }
194
195 writel(cmd->opcode, host->base + MMC_CMD);
196 writel(cmd->arg >> 16, host->base + MMC_ARGH);
197 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
198 writel(cmdat, host->base + MMC_CMDAT);
199 writel(host->clkrt, host->base + MMC_CLKRT);
200
201 writel(START_CLOCK, host->base + MMC_STRPCL);
202
203 pxamci_enable_irq(host, END_CMD_RES);
204 }
205
206 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
207 {
208 DBG("PXAMCI: request done\n");
209 host->mrq = NULL;
210 host->cmd = NULL;
211 host->data = NULL;
212 mmc_request_done(host->mmc, mrq);
213 }
214
215 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
216 {
217 struct mmc_command *cmd = host->cmd;
218 int i;
219 u32 v;
220
221 if (!cmd)
222 return 0;
223
224 host->cmd = NULL;
225
226 /*
227 * Did I mention this is Sick. We always need to
228 * discard the upper 8 bits of the first 16-bit word.
229 */
230 v = readl(host->base + MMC_RES) & 0xffff;
231 for (i = 0; i < 4; i++) {
232 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
233 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
234 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
235 v = w2;
236 }
237
238 if (stat & STAT_TIME_OUT_RESPONSE) {
239 cmd->error = MMC_ERR_TIMEOUT;
240 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
241 #ifdef CONFIG_PXA27x
242 /*
243 * workaround for erratum #42:
244 * Intel PXA27x Family Processor Specification Update Rev 001
245 */
246 if (cmd->opcode == MMC_ALL_SEND_CID ||
247 cmd->opcode == MMC_SEND_CSD ||
248 cmd->opcode == MMC_SEND_CID) {
249 /* a bogus CRC error can appear if the msb of
250 the 15 byte response is a one */
251 if ((cmd->resp[0] & 0x80000000) == 0)
252 cmd->error = MMC_ERR_BADCRC;
253 } else {
254 DBG("ignoring CRC from command %d - *risky*\n",cmd->opcode);
255 }
256 #else
257 cmd->error = MMC_ERR_BADCRC;
258 #endif
259 }
260
261 pxamci_disable_irq(host, END_CMD_RES);
262 if (host->data && cmd->error == MMC_ERR_NONE) {
263 pxamci_enable_irq(host, DATA_TRAN_DONE);
264 } else {
265 pxamci_finish_request(host, host->mrq);
266 }
267
268 return 1;
269 }
270
271 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
272 {
273 struct mmc_data *data = host->data;
274
275 if (!data)
276 return 0;
277
278 DCSR(host->dma) = 0;
279 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
280 host->dma_dir);
281
282 if (stat & STAT_READ_TIME_OUT)
283 data->error = MMC_ERR_TIMEOUT;
284 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
285 data->error = MMC_ERR_BADCRC;
286
287 /*
288 * There appears to be a hardware design bug here. There seems to
289 * be no way to find out how much data was transferred to the card.
290 * This means that if there was an error on any block, we mark all
291 * data blocks as being in error.
292 */
293 if (data->error == MMC_ERR_NONE)
294 data->bytes_xfered = data->blocks << data->blksz_bits;
295 else
296 data->bytes_xfered = 0;
297
298 pxamci_disable_irq(host, DATA_TRAN_DONE);
299
300 host->data = NULL;
301 if (host->mrq->stop && data->error == MMC_ERR_NONE) {
302 pxamci_stop_clock(host);
303 pxamci_start_cmd(host, host->mrq->stop, 0);
304 } else {
305 pxamci_finish_request(host, host->mrq);
306 }
307
308 return 1;
309 }
310
311 static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
312 {
313 struct pxamci_host *host = devid;
314 unsigned int ireg;
315 int handled = 0;
316
317 ireg = readl(host->base + MMC_I_REG);
318
319 DBG("PXAMCI: irq %08x\n", ireg);
320
321 if (ireg) {
322 unsigned stat = readl(host->base + MMC_STAT);
323
324 DBG("PXAMCI: stat %08x\n", stat);
325
326 if (ireg & END_CMD_RES)
327 handled |= pxamci_cmd_done(host, stat);
328 if (ireg & DATA_TRAN_DONE)
329 handled |= pxamci_data_done(host, stat);
330 }
331
332 return IRQ_RETVAL(handled);
333 }
334
335 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
336 {
337 struct pxamci_host *host = mmc_priv(mmc);
338 unsigned int cmdat;
339
340 WARN_ON(host->mrq != NULL);
341
342 host->mrq = mrq;
343
344 pxamci_stop_clock(host);
345
346 cmdat = host->cmdat;
347 host->cmdat &= ~CMDAT_INIT;
348
349 if (mrq->data) {
350 pxamci_setup_data(host, mrq->data);
351
352 cmdat &= ~CMDAT_BUSY;
353 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
354 if (mrq->data->flags & MMC_DATA_WRITE)
355 cmdat |= CMDAT_WRITE;
356
357 if (mrq->data->flags & MMC_DATA_STREAM)
358 cmdat |= CMDAT_STREAM;
359 }
360
361 pxamci_start_cmd(host, mrq->cmd, cmdat);
362 }
363
364 static int pxamci_get_ro(struct mmc_host *mmc)
365 {
366 struct pxamci_host *host = mmc_priv(mmc);
367
368 if (host->pdata && host->pdata->get_ro)
369 return host->pdata->get_ro(mmc->dev);
370 /* Host doesn't support read only detection so assume writeable */
371 return 0;
372 }
373
374 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
375 {
376 struct pxamci_host *host = mmc_priv(mmc);
377
378 DBG("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
379 ios->clock, ios->power_mode, ios->vdd / 100,
380 ios->vdd % 100);
381
382 if (ios->clock) {
383 unsigned int clk = CLOCKRATE / ios->clock;
384 if (CLOCKRATE / clk > ios->clock)
385 clk <<= 1;
386 host->clkrt = fls(clk) - 1;
387 pxa_set_cken(CKEN12_MMC, 1);
388
389 /*
390 * we write clkrt on the next command
391 */
392 } else {
393 pxamci_stop_clock(host);
394 pxa_set_cken(CKEN12_MMC, 0);
395 }
396
397 if (host->power_mode != ios->power_mode) {
398 host->power_mode = ios->power_mode;
399
400 if (host->pdata && host->pdata->setpower)
401 host->pdata->setpower(mmc->dev, ios->vdd);
402
403 if (ios->power_mode == MMC_POWER_ON)
404 host->cmdat |= CMDAT_INIT;
405 }
406
407 DBG("pxamci_set_ios: clkrt = %x cmdat = %x\n",
408 host->clkrt, host->cmdat);
409 }
410
411 static struct mmc_host_ops pxamci_ops = {
412 .request = pxamci_request,
413 .get_ro = pxamci_get_ro,
414 .set_ios = pxamci_set_ios,
415 };
416
417 static void pxamci_dma_irq(int dma, void *devid, struct pt_regs *regs)
418 {
419 printk(KERN_ERR "DMA%d: IRQ???\n", dma);
420 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
421 }
422
423 static irqreturn_t pxamci_detect_irq(int irq, void *devid, struct pt_regs *regs)
424 {
425 struct pxamci_host *host = mmc_priv(devid);
426
427 mmc_detect_change(devid, host->pdata->detect_delay);
428 return IRQ_HANDLED;
429 }
430
431 static int pxamci_probe(struct device *dev)
432 {
433 struct platform_device *pdev = to_platform_device(dev);
434 struct mmc_host *mmc;
435 struct pxamci_host *host = NULL;
436 struct resource *r;
437 int ret, irq;
438
439 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
440 irq = platform_get_irq(pdev, 0);
441 if (!r || irq == NO_IRQ)
442 return -ENXIO;
443
444 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
445 if (!r)
446 return -EBUSY;
447
448 mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
449 if (!mmc) {
450 ret = -ENOMEM;
451 goto out;
452 }
453
454 mmc->ops = &pxamci_ops;
455 mmc->f_min = CLOCKRATE_MIN;
456 mmc->f_max = CLOCKRATE_MAX;
457
458 /*
459 * We can do SG-DMA, but we don't because we never know how much
460 * data we successfully wrote to the card.
461 */
462 mmc->max_phys_segs = NR_SG;
463
464 /*
465 * Our hardware DMA can handle a maximum of one page per SG entry.
466 */
467 mmc->max_seg_size = PAGE_SIZE;
468
469 host = mmc_priv(mmc);
470 host->mmc = mmc;
471 host->dma = -1;
472 host->pdata = pdev->dev.platform_data;
473 mmc->ocr_avail = host->pdata ?
474 host->pdata->ocr_mask :
475 MMC_VDD_32_33|MMC_VDD_33_34;
476
477 host->sg_cpu = dma_alloc_coherent(dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
478 if (!host->sg_cpu) {
479 ret = -ENOMEM;
480 goto out;
481 }
482
483 spin_lock_init(&host->lock);
484 host->res = r;
485 host->irq = irq;
486 host->imask = MMC_I_MASK_ALL;
487
488 host->base = ioremap(r->start, SZ_4K);
489 if (!host->base) {
490 ret = -ENOMEM;
491 goto out;
492 }
493
494 /*
495 * Ensure that the host controller is shut down, and setup
496 * with our defaults.
497 */
498 pxamci_stop_clock(host);
499 writel(0, host->base + MMC_SPI);
500 writel(64, host->base + MMC_RESTO);
501 writel(host->imask, host->base + MMC_I_MASK);
502
503 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
504 pxamci_dma_irq, host);
505 if (host->dma < 0) {
506 ret = -EBUSY;
507 goto out;
508 }
509
510 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
511 if (ret)
512 goto out;
513
514 dev_set_drvdata(dev, mmc);
515
516 if (host->pdata && host->pdata->init)
517 host->pdata->init(dev, pxamci_detect_irq, mmc);
518
519 mmc_add_host(mmc);
520
521 return 0;
522
523 out:
524 if (host) {
525 if (host->dma >= 0)
526 pxa_free_dma(host->dma);
527 if (host->base)
528 iounmap(host->base);
529 if (host->sg_cpu)
530 dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
531 }
532 if (mmc)
533 mmc_free_host(mmc);
534 release_resource(r);
535 return ret;
536 }
537
538 static int pxamci_remove(struct device *dev)
539 {
540 struct mmc_host *mmc = dev_get_drvdata(dev);
541
542 dev_set_drvdata(dev, NULL);
543
544 if (mmc) {
545 struct pxamci_host *host = mmc_priv(mmc);
546
547 if (host->pdata && host->pdata->exit)
548 host->pdata->exit(dev, mmc);
549
550 mmc_remove_host(mmc);
551
552 pxamci_stop_clock(host);
553 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
554 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
555 host->base + MMC_I_MASK);
556
557 DRCMRRXMMC = 0;
558 DRCMRTXMMC = 0;
559
560 free_irq(host->irq, host);
561 pxa_free_dma(host->dma);
562 iounmap(host->base);
563 dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
564
565 release_resource(host->res);
566
567 mmc_free_host(mmc);
568 }
569 return 0;
570 }
571
572 #ifdef CONFIG_PM
573 static int pxamci_suspend(struct device *dev, pm_message_t state)
574 {
575 struct mmc_host *mmc = dev_get_drvdata(dev);
576 int ret = 0;
577
578 if (mmc)
579 ret = mmc_suspend_host(mmc, state);
580
581 return ret;
582 }
583
584 static int pxamci_resume(struct device *dev)
585 {
586 struct mmc_host *mmc = dev_get_drvdata(dev);
587 int ret = 0;
588
589 if (mmc)
590 ret = mmc_resume_host(mmc);
591
592 return ret;
593 }
594 #else
595 #define pxamci_suspend NULL
596 #define pxamci_resume NULL
597 #endif
598
599 static struct device_driver pxamci_driver = {
600 .name = DRIVER_NAME,
601 .bus = &platform_bus_type,
602 .probe = pxamci_probe,
603 .remove = pxamci_remove,
604 .suspend = pxamci_suspend,
605 .resume = pxamci_resume,
606 };
607
608 static int __init pxamci_init(void)
609 {
610 return driver_register(&pxamci_driver);
611 }
612
613 static void __exit pxamci_exit(void)
614 {
615 driver_unregister(&pxamci_driver);
616 }
617
618 module_init(pxamci_init);
619 module_exit(pxamci_exit);
620
621 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
622 MODULE_LICENSE("GPL");
kernel-based virtual machine