| blob | 61ac2a418bd0461a1aa61f1cc3c872414414f9ae |
1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
4 /*
5 * OMAP2/3 PRCM base and module definitions
6 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2007-2009 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 * OMAP4 defines in this file are automatically generated from the OMAP hardware
12 * databases.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
20 /* Module offsets from both CM_BASE & PRM_BASE */
22 /*
23 * Offsets that are the same on 24xx and 34xx
24 *
25 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
26 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
27 */
28 #define OCP_MOD 0x000
29 #define MPU_MOD 0x100
30 #define CORE_MOD 0x200
31 #define GFX_MOD 0x300
32 #define WKUP_MOD 0x400
33 #define PLL_MOD 0x500
36 /* Chip-specific module offsets */
37 #define OMAP24XX_GR_MOD OCP_MOD
38 #define OMAP24XX_DSP_MOD 0x800
40 #define OMAP2430_MDM_MOD 0xc00
42 /* IVA2 module is < base on 3430 */
43 #define OMAP3430_IVA2_MOD -0x800
44 #define OMAP3430ES2_SGX_MOD GFX_MOD
45 #define OMAP3430_CCR_MOD PLL_MOD
46 #define OMAP3430_DSS_MOD 0x600
47 #define OMAP3430_CAM_MOD 0x700
48 #define OMAP3430_PER_MOD 0x800
49 #define OMAP3430_EMU_MOD 0x900
50 #define OMAP3430_GR_MOD 0xa00
51 #define OMAP3430_NEON_MOD 0xb00
52 #define OMAP3430ES2_USBHOST_MOD 0xc00
54 #define BITS(n_bit) \
55 (((1 << n_bit) - 1) | (1 << n_bit))
57 #define BITFIELD(l_bit, u_bit) \
58 (BITS(u_bit) & ~((BITS(l_bit)) >> 1))
60 /* OMAP44XX specific module offsets */
62 /* CM1 instances */
64 #define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000
65 #define OMAP4430_CM1_CKGEN_MOD 0x0100
66 #define OMAP4430_CM1_MPU_MOD 0x0300
67 #define OMAP4430_CM1_TESLA_MOD 0x0400
68 #define OMAP4430_CM1_ABE_MOD 0x0500
69 #define OMAP4430_CM1_RESTORE_MOD 0x0e00
70 #define OMAP4430_CM1_INSTR_MOD 0x0f00
72 /* CM2 instances */
74 #define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000
75 #define OMAP4430_CM2_CKGEN_MOD 0x0100
76 #define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600
77 #define OMAP4430_CM2_CORE_MOD 0x0700
78 #define OMAP4430_CM2_IVAHD_MOD 0x0f00
79 #define OMAP4430_CM2_CAM_MOD 0x1000
80 #define OMAP4430_CM2_DSS_MOD 0x1100
81 #define OMAP4430_CM2_GFX_MOD 0x1200
82 #define OMAP4430_CM2_L3INIT_MOD 0x1300
83 #define OMAP4430_CM2_L4PER_MOD 0x1400
84 #define OMAP4430_CM2_CEFUSE_MOD 0x1600
85 #define OMAP4430_CM2_RESTORE_MOD 0x1e00
86 #define OMAP4430_CM2_INSTR_MOD 0x1f00
88 /* PRM instances */
90 #define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000
91 #define OMAP4430_PRM_CKGEN_MOD 0x0100
92 #define OMAP4430_PRM_MPU_MOD 0x0300
93 #define OMAP4430_PRM_TESLA_MOD 0x0400
94 #define OMAP4430_PRM_ABE_MOD 0x0500
95 #define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600
96 #define OMAP4430_PRM_CORE_MOD 0x0700
97 #define OMAP4430_PRM_IVAHD_MOD 0x0f00
98 #define OMAP4430_PRM_CAM_MOD 0x1000
99 #define OMAP4430_PRM_DSS_MOD 0x1100
100 #define OMAP4430_PRM_GFX_MOD 0x1200
101 #define OMAP4430_PRM_L3INIT_MOD 0x1300
102 #define OMAP4430_PRM_L4PER_MOD 0x1400
103 #define OMAP4430_PRM_CEFUSE_MOD 0x1600
104 #define OMAP4430_PRM_WKUP_MOD 0x1700
105 #define OMAP4430_PRM_WKUP_CM_MOD 0x1800
106 #define OMAP4430_PRM_EMU_MOD 0x1900
107 #define OMAP4430_PRM_EMU_CM_MOD 0x1a00
108 #define OMAP4430_PRM_DEVICE_MOD 0x1b00
109 #define OMAP4430_PRM_INSTR_MOD 0x1f00
111 /* SCRM instances */
113 #define OMAP4430_SCRM_SCRM_MOD 0x0000
115 /* CHIRONSS instances */
117 #define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000
118 #define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200
119 #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400
120 #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800
122 /* 24XX register bits shared between CM & PRM registers */
124 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
125 #define OMAP2420_EN_MMC_SHIFT 26
126 #define OMAP2420_EN_MMC (1 << 26)
127 #define OMAP24XX_EN_UART2_SHIFT 22
128 #define OMAP24XX_EN_UART2 (1 << 22)
129 #define OMAP24XX_EN_UART1_SHIFT 21
130 #define OMAP24XX_EN_UART1 (1 << 21)
131 #define OMAP24XX_EN_MCSPI2_SHIFT 18
132 #define OMAP24XX_EN_MCSPI2 (1 << 18)
133 #define OMAP24XX_EN_MCSPI1_SHIFT 17
134 #define OMAP24XX_EN_MCSPI1 (1 << 17)
135 #define OMAP24XX_EN_MCBSP2_SHIFT 16
136 #define OMAP24XX_EN_MCBSP2 (1 << 16)
137 #define OMAP24XX_EN_MCBSP1_SHIFT 15
138 #define OMAP24XX_EN_MCBSP1 (1 << 15)
139 #define OMAP24XX_EN_GPT12_SHIFT 14
140 #define OMAP24XX_EN_GPT12 (1 << 14)
141 #define OMAP24XX_EN_GPT11_SHIFT 13
142 #define OMAP24XX_EN_GPT11 (1 << 13)
143 #define OMAP24XX_EN_GPT10_SHIFT 12
144 #define OMAP24XX_EN_GPT10 (1 << 12)
145 #define OMAP24XX_EN_GPT9_SHIFT 11
146 #define OMAP24XX_EN_GPT9 (1 << 11)
147 #define OMAP24XX_EN_GPT8_SHIFT 10
148 #define OMAP24XX_EN_GPT8 (1 << 10)
149 #define OMAP24XX_EN_GPT7_SHIFT 9
150 #define OMAP24XX_EN_GPT7 (1 << 9)
151 #define OMAP24XX_EN_GPT6_SHIFT 8
152 #define OMAP24XX_EN_GPT6 (1 << 8)
153 #define OMAP24XX_EN_GPT5_SHIFT 7
154 #define OMAP24XX_EN_GPT5 (1 << 7)
155 #define OMAP24XX_EN_GPT4_SHIFT 6
156 #define OMAP24XX_EN_GPT4 (1 << 6)
157 #define OMAP24XX_EN_GPT3_SHIFT 5
158 #define OMAP24XX_EN_GPT3 (1 << 5)
159 #define OMAP24XX_EN_GPT2_SHIFT 4
160 #define OMAP24XX_EN_GPT2 (1 << 4)
161 #define OMAP2420_EN_VLYNQ_SHIFT 3
162 #define OMAP2420_EN_VLYNQ (1 << 3)
164 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
165 #define OMAP2430_EN_GPIO5_SHIFT 10
166 #define OMAP2430_EN_GPIO5 (1 << 10)
167 #define OMAP2430_EN_MCSPI3_SHIFT 9
168 #define OMAP2430_EN_MCSPI3 (1 << 9)
169 #define OMAP2430_EN_MMCHS2_SHIFT 8
170 #define OMAP2430_EN_MMCHS2 (1 << 8)
171 #define OMAP2430_EN_MMCHS1_SHIFT 7
172 #define OMAP2430_EN_MMCHS1 (1 << 7)
173 #define OMAP24XX_EN_UART3_SHIFT 2
174 #define OMAP24XX_EN_UART3 (1 << 2)
175 #define OMAP24XX_EN_USB_SHIFT 0
176 #define OMAP24XX_EN_USB (1 << 0)
178 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
179 #define OMAP2430_EN_MDM_INTC_SHIFT 11
180 #define OMAP2430_EN_MDM_INTC (1 << 11)
181 #define OMAP2430_EN_USBHS_SHIFT 6
182 #define OMAP2430_EN_USBHS (1 << 6)
184 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
185 #define OMAP2420_ST_MMC_SHIFT 26
186 #define OMAP2420_ST_MMC_MASK (1 << 26)
187 #define OMAP24XX_ST_UART2_SHIFT 22
188 #define OMAP24XX_ST_UART2_MASK (1 << 22)
189 #define OMAP24XX_ST_UART1_SHIFT 21
190 #define OMAP24XX_ST_UART1_MASK (1 << 21)
191 #define OMAP24XX_ST_MCSPI2_SHIFT 18
192 #define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
193 #define OMAP24XX_ST_MCSPI1_SHIFT 17
194 #define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
195 #define OMAP24XX_ST_GPT12_SHIFT 14
196 #define OMAP24XX_ST_GPT12_MASK (1 << 14)
197 #define OMAP24XX_ST_GPT11_SHIFT 13
198 #define OMAP24XX_ST_GPT11_MASK (1 << 13)
199 #define OMAP24XX_ST_GPT10_SHIFT 12
200 #define OMAP24XX_ST_GPT10_MASK (1 << 12)
201 #define OMAP24XX_ST_GPT9_SHIFT 11
202 #define OMAP24XX_ST_GPT9_MASK (1 << 11)
203 #define OMAP24XX_ST_GPT8_SHIFT 10
204 #define OMAP24XX_ST_GPT8_MASK (1 << 10)
205 #define OMAP24XX_ST_GPT7_SHIFT 9
206 #define OMAP24XX_ST_GPT7_MASK (1 << 9)
207 #define OMAP24XX_ST_GPT6_SHIFT 8
208 #define OMAP24XX_ST_GPT6_MASK (1 << 8)
209 #define OMAP24XX_ST_GPT5_SHIFT 7
210 #define OMAP24XX_ST_GPT5_MASK (1 << 7)
211 #define OMAP24XX_ST_GPT4_SHIFT 6
212 #define OMAP24XX_ST_GPT4_MASK (1 << 6)
213 #define OMAP24XX_ST_GPT3_SHIFT 5
214 #define OMAP24XX_ST_GPT3_MASK (1 << 5)
215 #define OMAP24XX_ST_GPT2_SHIFT 4
216 #define OMAP24XX_ST_GPT2_MASK (1 << 4)
217 #define OMAP2420_ST_VLYNQ_SHIFT 3
218 #define OMAP2420_ST_VLYNQ_MASK (1 << 3)
220 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
221 #define OMAP2430_ST_MDM_INTC_SHIFT 11
222 #define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
223 #define OMAP2430_ST_GPIO5_SHIFT 10
224 #define OMAP2430_ST_GPIO5_MASK (1 << 10)
225 #define OMAP2430_ST_MCSPI3_SHIFT 9
226 #define OMAP2430_ST_MCSPI3_MASK (1 << 9)
227 #define OMAP2430_ST_MMCHS2_SHIFT 8
228 #define OMAP2430_ST_MMCHS2_MASK (1 << 8)
229 #define OMAP2430_ST_MMCHS1_SHIFT 7
230 #define OMAP2430_ST_MMCHS1_MASK (1 << 7)
231 #define OMAP2430_ST_USBHS_SHIFT 6
232 #define OMAP2430_ST_USBHS_MASK (1 << 6)
233 #define OMAP24XX_ST_UART3_SHIFT 2
234 #define OMAP24XX_ST_UART3_MASK (1 << 2)
235 #define OMAP24XX_ST_USB_SHIFT 0
236 #define OMAP24XX_ST_USB_MASK (1 << 0)
238 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
239 #define OMAP24XX_EN_GPIOS_SHIFT 2
240 #define OMAP24XX_EN_GPIOS (1 << 2)
241 #define OMAP24XX_EN_GPT1_SHIFT 0
242 #define OMAP24XX_EN_GPT1 (1 << 0)
244 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
245 #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
246 #define OMAP24XX_ST_GPIOS_MASK 2
247 #define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
248 #define OMAP24XX_ST_GPT1_MASK 0
250 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
251 #define OMAP2430_ST_MDM_SHIFT (1 << 0)
254 /* 3430 register bits shared between CM & PRM registers */
256 /* CM_REVISION, PRM_REVISION shared bits */
257 #define OMAP3430_REV_SHIFT 0
258 #define OMAP3430_REV_MASK (0xff << 0)
260 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
261 #define OMAP3430_AUTOIDLE (1 << 0)
263 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
264 #define OMAP3430_EN_MMC2 (1 << 25)
265 #define OMAP3430_EN_MMC2_SHIFT 25
266 #define OMAP3430_EN_MMC1 (1 << 24)
267 #define OMAP3430_EN_MMC1_SHIFT 24
268 #define OMAP3430_EN_MCSPI4 (1 << 21)
269 #define OMAP3430_EN_MCSPI4_SHIFT 21
270 #define OMAP3430_EN_MCSPI3 (1 << 20)
271 #define OMAP3430_EN_MCSPI3_SHIFT 20
272 #define OMAP3430_EN_MCSPI2 (1 << 19)
273 #define OMAP3430_EN_MCSPI2_SHIFT 19
274 #define OMAP3430_EN_MCSPI1 (1 << 18)
275 #define OMAP3430_EN_MCSPI1_SHIFT 18
276 #define OMAP3430_EN_I2C3 (1 << 17)
277 #define OMAP3430_EN_I2C3_SHIFT 17
278 #define OMAP3430_EN_I2C2 (1 << 16)
279 #define OMAP3430_EN_I2C2_SHIFT 16
280 #define OMAP3430_EN_I2C1 (1 << 15)
281 #define OMAP3430_EN_I2C1_SHIFT 15
282 #define OMAP3430_EN_UART2 (1 << 14)
283 #define OMAP3430_EN_UART2_SHIFT 14
284 #define OMAP3430_EN_UART1 (1 << 13)
285 #define OMAP3430_EN_UART1_SHIFT 13
286 #define OMAP3430_EN_GPT11 (1 << 12)
287 #define OMAP3430_EN_GPT11_SHIFT 12
288 #define OMAP3430_EN_GPT10 (1 << 11)
289 #define OMAP3430_EN_GPT10_SHIFT 11
290 #define OMAP3430_EN_MCBSP5 (1 << 10)
291 #define OMAP3430_EN_MCBSP5_SHIFT 10
292 #define OMAP3430_EN_MCBSP1 (1 << 9)
293 #define OMAP3430_EN_MCBSP1_SHIFT 9
294 #define OMAP3430_EN_FSHOSTUSB (1 << 5)
295 #define OMAP3430_EN_FSHOSTUSB_SHIFT 5
296 #define OMAP3430_EN_D2D (1 << 3)
297 #define OMAP3430_EN_D2D_SHIFT 3
299 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
300 #define OMAP3430_EN_HSOTGUSB (1 << 4)
301 #define OMAP3430_EN_HSOTGUSB_SHIFT 4
303 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
304 #define OMAP3430_ST_MMC2_SHIFT 25
305 #define OMAP3430_ST_MMC2_MASK (1 << 25)
306 #define OMAP3430_ST_MMC1_SHIFT 24
307 #define OMAP3430_ST_MMC1_MASK (1 << 24)
308 #define OMAP3430_ST_MCSPI4_SHIFT 21
309 #define OMAP3430_ST_MCSPI4_MASK (1 << 21)
310 #define OMAP3430_ST_MCSPI3_SHIFT 20
311 #define OMAP3430_ST_MCSPI3_MASK (1 << 20)
312 #define OMAP3430_ST_MCSPI2_SHIFT 19
313 #define OMAP3430_ST_MCSPI2_MASK (1 << 19)
314 #define OMAP3430_ST_MCSPI1_SHIFT 18
315 #define OMAP3430_ST_MCSPI1_MASK (1 << 18)
316 #define OMAP3430_ST_I2C3_SHIFT 17
317 #define OMAP3430_ST_I2C3_MASK (1 << 17)
318 #define OMAP3430_ST_I2C2_SHIFT 16
319 #define OMAP3430_ST_I2C2_MASK (1 << 16)
320 #define OMAP3430_ST_I2C1_SHIFT 15
321 #define OMAP3430_ST_I2C1_MASK (1 << 15)
322 #define OMAP3430_ST_UART2_SHIFT 14
323 #define OMAP3430_ST_UART2_MASK (1 << 14)
324 #define OMAP3430_ST_UART1_SHIFT 13
325 #define OMAP3430_ST_UART1_MASK (1 << 13)
326 #define OMAP3430_ST_GPT11_SHIFT 12
327 #define OMAP3430_ST_GPT11_MASK (1 << 12)
328 #define OMAP3430_ST_GPT10_SHIFT 11
329 #define OMAP3430_ST_GPT10_MASK (1 << 11)
330 #define OMAP3430_ST_MCBSP5_SHIFT 10
331 #define OMAP3430_ST_MCBSP5_MASK (1 << 10)
332 #define OMAP3430_ST_MCBSP1_SHIFT 9
333 #define OMAP3430_ST_MCBSP1_MASK (1 << 9)
334 #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
335 #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
336 #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
337 #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
338 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
339 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
340 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
341 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
342 #define OMAP3430_ST_D2D_SHIFT 3
343 #define OMAP3430_ST_D2D_MASK (1 << 3)
345 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
346 #define OMAP3430_EN_GPIO1 (1 << 3)
347 #define OMAP3430_EN_GPIO1_SHIFT 3
348 #define OMAP3430_EN_GPT12 (1 << 1)
349 #define OMAP3430_EN_GPT12_SHIFT 1
350 #define OMAP3430_EN_GPT1 (1 << 0)
351 #define OMAP3430_EN_GPT1_SHIFT 0
353 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
354 #define OMAP3430_EN_SR2 (1 << 7)
355 #define OMAP3430_EN_SR2_SHIFT 7
356 #define OMAP3430_EN_SR1 (1 << 6)
357 #define OMAP3430_EN_SR1_SHIFT 6
359 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
360 #define OMAP3430_EN_GPT12 (1 << 1)
361 #define OMAP3430_EN_GPT12_SHIFT 1
363 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
364 #define OMAP3430_ST_SR2_SHIFT 7
365 #define OMAP3430_ST_SR2_MASK (1 << 7)
366 #define OMAP3430_ST_SR1_SHIFT 6
367 #define OMAP3430_ST_SR1_MASK (1 << 6)
368 #define OMAP3430_ST_GPIO1_SHIFT 3
369 #define OMAP3430_ST_GPIO1_MASK (1 << 3)
370 #define OMAP3430_ST_GPT12_SHIFT 1
371 #define OMAP3430_ST_GPT12_MASK (1 << 1)
372 #define OMAP3430_ST_GPT1_SHIFT 0
373 #define OMAP3430_ST_GPT1_MASK (1 << 0)
375 /*
376 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
377 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
378 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
379 */
380 #define OMAP3430_EN_MPU (1 << 1)
381 #define OMAP3430_EN_MPU_SHIFT 1
383 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
384 #define OMAP3430_EN_GPIO6 (1 << 17)
385 #define OMAP3430_EN_GPIO6_SHIFT 17
386 #define OMAP3430_EN_GPIO5 (1 << 16)
387 #define OMAP3430_EN_GPIO5_SHIFT 16
388 #define OMAP3430_EN_GPIO4 (1 << 15)
389 #define OMAP3430_EN_GPIO4_SHIFT 15
390 #define OMAP3430_EN_GPIO3 (1 << 14)
391 #define OMAP3430_EN_GPIO3_SHIFT 14
392 #define OMAP3430_EN_GPIO2 (1 << 13)
393 #define OMAP3430_EN_GPIO2_SHIFT 13
394 #define OMAP3430_EN_UART3 (1 << 11)
395 #define OMAP3430_EN_UART3_SHIFT 11
396 #define OMAP3430_EN_GPT9 (1 << 10)
397 #define OMAP3430_EN_GPT9_SHIFT 10
398 #define OMAP3430_EN_GPT8 (1 << 9)
399 #define OMAP3430_EN_GPT8_SHIFT 9
400 #define OMAP3430_EN_GPT7 (1 << 8)
401 #define OMAP3430_EN_GPT7_SHIFT 8
402 #define OMAP3430_EN_GPT6 (1 << 7)
403 #define OMAP3430_EN_GPT6_SHIFT 7
404 #define OMAP3430_EN_GPT5 (1 << 6)
405 #define OMAP3430_EN_GPT5_SHIFT 6
406 #define OMAP3430_EN_GPT4 (1 << 5)
407 #define OMAP3430_EN_GPT4_SHIFT 5
408 #define OMAP3430_EN_GPT3 (1 << 4)
409 #define OMAP3430_EN_GPT3_SHIFT 4
410 #define OMAP3430_EN_GPT2 (1 << 3)
411 #define OMAP3430_EN_GPT2_SHIFT 3
413 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
414 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
415 * be ST_* bits instead? */
416 #define OMAP3430_EN_MCBSP4 (1 << 2)
417 #define OMAP3430_EN_MCBSP4_SHIFT 2
418 #define OMAP3430_EN_MCBSP3 (1 << 1)
419 #define OMAP3430_EN_MCBSP3_SHIFT 1
420 #define OMAP3430_EN_MCBSP2 (1 << 0)
421 #define OMAP3430_EN_MCBSP2_SHIFT 0
423 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
424 #define OMAP3430_ST_GPIO6_SHIFT 17
425 #define OMAP3430_ST_GPIO6_MASK (1 << 17)
426 #define OMAP3430_ST_GPIO5_SHIFT 16
427 #define OMAP3430_ST_GPIO5_MASK (1 << 16)
428 #define OMAP3430_ST_GPIO4_SHIFT 15
429 #define OMAP3430_ST_GPIO4_MASK (1 << 15)
430 #define OMAP3430_ST_GPIO3_SHIFT 14
431 #define OMAP3430_ST_GPIO3_MASK (1 << 14)
432 #define OMAP3430_ST_GPIO2_SHIFT 13
433 #define OMAP3430_ST_GPIO2_MASK (1 << 13)
434 #define OMAP3430_ST_UART3_SHIFT 11
435 #define OMAP3430_ST_UART3_MASK (1 << 11)
436 #define OMAP3430_ST_GPT9_SHIFT 10
437 #define OMAP3430_ST_GPT9_MASK (1 << 10)
438 #define OMAP3430_ST_GPT8_SHIFT 9
439 #define OMAP3430_ST_GPT8_MASK (1 << 9)
440 #define OMAP3430_ST_GPT7_SHIFT 8
441 #define OMAP3430_ST_GPT7_MASK (1 << 8)
442 #define OMAP3430_ST_GPT6_SHIFT 7
443 #define OMAP3430_ST_GPT6_MASK (1 << 7)
444 #define OMAP3430_ST_GPT5_SHIFT 6
445 #define OMAP3430_ST_GPT5_MASK (1 << 6)
446 #define OMAP3430_ST_GPT4_SHIFT 5
447 #define OMAP3430_ST_GPT4_MASK (1 << 5)
448 #define OMAP3430_ST_GPT3_SHIFT 4
449 #define OMAP3430_ST_GPT3_MASK (1 << 4)
450 #define OMAP3430_ST_GPT2_SHIFT 3
451 #define OMAP3430_ST_GPT2_MASK (1 << 3)
453 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
454 #define OMAP3430_EN_CORE_SHIFT 0
455 #define OMAP3430_EN_CORE_MASK (1 << 0)
457 #endif