2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. This method will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/platform_device.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
97 #include "gianfar_mii.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name
[] = "Gianfar Ethernet";
104 const char gfar_driver_version
[] = "1.3";
106 static int gfar_enet_open(struct net_device
*dev
);
107 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
108 static void gfar_reset_task(struct work_struct
*work
);
109 static void gfar_timeout(struct net_device
*dev
);
110 static int gfar_close(struct net_device
*dev
);
111 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
112 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
113 struct sk_buff
*skb
);
114 static int gfar_set_mac_address(struct net_device
*dev
);
115 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
116 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
118 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
119 static void adjust_link(struct net_device
*dev
);
120 static void init_registers(struct net_device
*dev
);
121 static int init_phy(struct net_device
*dev
);
122 static int gfar_probe(struct platform_device
*pdev
);
123 static int gfar_remove(struct platform_device
*pdev
);
124 static void free_skb_resources(struct gfar_private
*priv
);
125 static void gfar_set_multi(struct net_device
*dev
);
126 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
127 static void gfar_configure_serdes(struct net_device
*dev
);
128 static int gfar_poll(struct napi_struct
*napi
, int budget
);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device
*dev
);
132 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
133 static int gfar_clean_tx_ring(struct net_device
*dev
);
134 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
135 static void gfar_vlan_rx_register(struct net_device
*netdev
,
136 struct vlan_group
*grp
);
137 void gfar_halt(struct net_device
*dev
);
138 static void gfar_halt_nodisable(struct net_device
*dev
);
139 void gfar_start(struct net_device
*dev
);
140 static void gfar_clear_exact_match(struct net_device
*dev
);
141 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
143 extern const struct ethtool_ops gfar_ethtool_ops
;
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
149 /* Returns 1 if incoming frames use an FCB */
150 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
152 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
155 /* Set up the ethernet device structure, private data,
156 * and anything else we need before we start */
157 static int gfar_probe(struct platform_device
*pdev
)
160 struct net_device
*dev
= NULL
;
161 struct gfar_private
*priv
= NULL
;
162 struct gianfar_platform_data
*einfo
;
165 DECLARE_MAC_BUF(mac
);
167 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
170 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
176 /* Create an ethernet device instance */
177 dev
= alloc_etherdev(sizeof (*priv
));
182 priv
= netdev_priv(dev
);
185 /* Set the info in the priv to the current info */
188 /* fill out IRQ fields */
189 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
190 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
191 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
192 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
193 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
196 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
197 if (priv
->interruptTransmit
< 0)
201 /* get a pointer to the register memory */
202 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
203 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
205 if (NULL
== priv
->regs
) {
210 spin_lock_init(&priv
->txlock
);
211 spin_lock_init(&priv
->rxlock
);
212 spin_lock_init(&priv
->bflock
);
213 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
215 platform_set_drvdata(pdev
, dev
);
217 /* Stop the DMA engine now, in case it was running before */
218 /* (The firmware could have used it, and left it running). */
219 /* To do this, we write Graceful Receive Stop and Graceful */
220 /* Transmit Stop, and then wait until the corresponding bits */
221 /* in IEVENT indicate the stops have completed. */
222 tempval
= gfar_read(&priv
->regs
->dmactrl
);
223 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
224 gfar_write(&priv
->regs
->dmactrl
, tempval
);
226 tempval
= gfar_read(&priv
->regs
->dmactrl
);
227 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
228 gfar_write(&priv
->regs
->dmactrl
, tempval
);
230 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
233 /* Reset MAC layer */
234 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
236 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
237 gfar_write(&priv
->regs
->maccfg1
, tempval
);
239 /* Initialize MACCFG2. */
240 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
242 /* Initialize ECNTRL */
243 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
245 /* Copy the station address into the dev structure, */
246 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
248 /* Set the dev->base_addr to the gfar reg region */
249 dev
->base_addr
= (unsigned long) (priv
->regs
);
251 SET_NETDEV_DEV(dev
, &pdev
->dev
);
253 /* Fill in the dev structure */
254 dev
->open
= gfar_enet_open
;
255 dev
->hard_start_xmit
= gfar_start_xmit
;
256 dev
->tx_timeout
= gfar_timeout
;
257 dev
->watchdog_timeo
= TX_TIMEOUT
;
258 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
259 #ifdef CONFIG_NET_POLL_CONTROLLER
260 dev
->poll_controller
= gfar_netpoll
;
262 dev
->stop
= gfar_close
;
263 dev
->change_mtu
= gfar_change_mtu
;
265 dev
->set_multicast_list
= gfar_set_multi
;
267 dev
->ethtool_ops
= &gfar_ethtool_ops
;
269 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
270 priv
->rx_csum_enable
= 1;
271 dev
->features
|= NETIF_F_IP_CSUM
;
273 priv
->rx_csum_enable
= 0;
277 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
278 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
280 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
282 priv
->vlan_enable
= 1;
285 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
286 priv
->extended_hash
= 1;
287 priv
->hash_width
= 9;
289 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
290 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
291 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
292 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
293 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
294 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
295 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
296 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
297 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
298 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
299 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
300 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
301 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
302 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
303 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
304 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
307 priv
->extended_hash
= 0;
308 priv
->hash_width
= 8;
310 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
311 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
312 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
313 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
314 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
315 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
316 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
317 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
320 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
321 priv
->padding
= DEFAULT_PADDING
;
325 if (dev
->features
& NETIF_F_IP_CSUM
)
326 dev
->hard_header_len
+= GMAC_FCB_LEN
;
328 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
329 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
330 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
332 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
333 priv
->txcount
= DEFAULT_TXCOUNT
;
334 priv
->txtime
= DEFAULT_TXTIME
;
335 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
336 priv
->rxcount
= DEFAULT_RXCOUNT
;
337 priv
->rxtime
= DEFAULT_RXTIME
;
339 /* Enable most messages by default */
340 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
342 /* Carrier starts down, phylib will bring it up */
343 netif_carrier_off(dev
);
345 err
= register_netdev(dev
);
348 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
353 /* Create all the sysfs files */
354 gfar_init_sysfs(dev
);
356 /* Print out the device info */
357 printk(KERN_INFO DEVICE_NAME
"%s\n",
358 dev
->name
, print_mac(mac
, dev
->dev_addr
));
360 /* Even more device info helps when determining which kernel */
361 /* provided which set of benchmarks. */
362 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
363 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
364 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
375 static int gfar_remove(struct platform_device
*pdev
)
377 struct net_device
*dev
= platform_get_drvdata(pdev
);
378 struct gfar_private
*priv
= netdev_priv(dev
);
380 platform_set_drvdata(pdev
, NULL
);
389 static int gfar_suspend(struct platform_device
*pdev
, pm_message_t state
)
391 struct net_device
*dev
= platform_get_drvdata(pdev
);
392 struct gfar_private
*priv
= netdev_priv(dev
);
396 int magic_packet
= priv
->wol_en
&&
397 (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
399 netif_device_detach(dev
);
401 if (netif_running(dev
)) {
402 spin_lock_irqsave(&priv
->txlock
, flags
);
403 spin_lock(&priv
->rxlock
);
405 gfar_halt_nodisable(dev
);
407 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
408 tempval
= gfar_read(&priv
->regs
->maccfg1
);
410 tempval
&= ~MACCFG1_TX_EN
;
413 tempval
&= ~MACCFG1_RX_EN
;
415 gfar_write(&priv
->regs
->maccfg1
, tempval
);
417 spin_unlock(&priv
->rxlock
);
418 spin_unlock_irqrestore(&priv
->txlock
, flags
);
420 napi_disable(&priv
->napi
);
423 /* Enable interrupt on Magic Packet */
424 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
426 /* Enable Magic Packet mode */
427 tempval
= gfar_read(&priv
->regs
->maccfg2
);
428 tempval
|= MACCFG2_MPEN
;
429 gfar_write(&priv
->regs
->maccfg2
, tempval
);
431 phy_stop(priv
->phydev
);
438 static int gfar_resume(struct platform_device
*pdev
)
440 struct net_device
*dev
= platform_get_drvdata(pdev
);
441 struct gfar_private
*priv
= netdev_priv(dev
);
444 int magic_packet
= priv
->wol_en
&&
445 (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
447 if (!netif_running(dev
)) {
448 netif_device_attach(dev
);
452 if (!magic_packet
&& priv
->phydev
)
453 phy_start(priv
->phydev
);
455 /* Disable Magic Packet mode, in case something
459 spin_lock_irqsave(&priv
->txlock
, flags
);
460 spin_lock(&priv
->rxlock
);
462 tempval
= gfar_read(&priv
->regs
->maccfg2
);
463 tempval
&= ~MACCFG2_MPEN
;
464 gfar_write(&priv
->regs
->maccfg2
, tempval
);
468 spin_unlock(&priv
->rxlock
);
469 spin_unlock_irqrestore(&priv
->txlock
, flags
);
471 netif_device_attach(dev
);
473 napi_enable(&priv
->napi
);
478 #define gfar_suspend NULL
479 #define gfar_resume NULL
482 /* Reads the controller's registers to determine what interface
483 * connects it to the PHY.
485 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
487 struct gfar_private
*priv
= netdev_priv(dev
);
488 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
490 if (ecntrl
& ECNTRL_SGMII_MODE
)
491 return PHY_INTERFACE_MODE_SGMII
;
493 if (ecntrl
& ECNTRL_TBI_MODE
) {
494 if (ecntrl
& ECNTRL_REDUCED_MODE
)
495 return PHY_INTERFACE_MODE_RTBI
;
497 return PHY_INTERFACE_MODE_TBI
;
500 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
501 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
502 return PHY_INTERFACE_MODE_RMII
;
504 phy_interface_t interface
= priv
->einfo
->interface
;
507 * This isn't autodetected right now, so it must
508 * be set by the device tree or platform code.
510 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
511 return PHY_INTERFACE_MODE_RGMII_ID
;
513 return PHY_INTERFACE_MODE_RGMII
;
517 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
518 return PHY_INTERFACE_MODE_GMII
;
520 return PHY_INTERFACE_MODE_MII
;
524 /* Initializes driver's PHY state, and attaches to the PHY.
525 * Returns 0 on success.
527 static int init_phy(struct net_device
*dev
)
529 struct gfar_private
*priv
= netdev_priv(dev
);
530 uint gigabit_support
=
531 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
532 SUPPORTED_1000baseT_Full
: 0;
533 struct phy_device
*phydev
;
534 char phy_id
[BUS_ID_SIZE
];
535 phy_interface_t interface
;
539 priv
->oldduplex
= -1;
541 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
543 interface
= gfar_get_interface(dev
);
545 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
547 if (interface
== PHY_INTERFACE_MODE_SGMII
)
548 gfar_configure_serdes(dev
);
550 if (IS_ERR(phydev
)) {
551 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
552 return PTR_ERR(phydev
);
555 /* Remove any features not supported by the controller */
556 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
557 phydev
->advertising
= phydev
->supported
;
559 priv
->phydev
= phydev
;
565 * Initialize TBI PHY interface for communicating with the
566 * SERDES lynx PHY on the chip. We communicate with this PHY
567 * through the MDIO bus on each controller, treating it as a
568 * "normal" PHY at the address found in the TBIPA register. We assume
569 * that the TBIPA register is valid. Either the MDIO bus code will set
570 * it to a value that doesn't conflict with other PHYs on the bus, or the
571 * value doesn't matter, as there are no other PHYs on the bus.
573 static void gfar_configure_serdes(struct net_device
*dev
)
575 struct gfar_private
*priv
= netdev_priv(dev
);
576 struct gfar_mii __iomem
*regs
=
577 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
578 int tbipa
= gfar_read(&priv
->regs
->tbipa
);
580 /* Single clk mode, mii mode off(for serdes communication) */
581 gfar_local_mdio_write(regs
, tbipa
, MII_TBICON
, TBICON_CLK_SELECT
);
583 gfar_local_mdio_write(regs
, tbipa
, MII_ADVERTISE
,
584 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
585 ADVERTISE_1000XPSE_ASYM
);
587 gfar_local_mdio_write(regs
, tbipa
, MII_BMCR
, BMCR_ANENABLE
|
588 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
591 static void init_registers(struct net_device
*dev
)
593 struct gfar_private
*priv
= netdev_priv(dev
);
596 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
598 /* Initialize IMASK */
599 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
601 /* Init hash registers to zero */
602 gfar_write(&priv
->regs
->igaddr0
, 0);
603 gfar_write(&priv
->regs
->igaddr1
, 0);
604 gfar_write(&priv
->regs
->igaddr2
, 0);
605 gfar_write(&priv
->regs
->igaddr3
, 0);
606 gfar_write(&priv
->regs
->igaddr4
, 0);
607 gfar_write(&priv
->regs
->igaddr5
, 0);
608 gfar_write(&priv
->regs
->igaddr6
, 0);
609 gfar_write(&priv
->regs
->igaddr7
, 0);
611 gfar_write(&priv
->regs
->gaddr0
, 0);
612 gfar_write(&priv
->regs
->gaddr1
, 0);
613 gfar_write(&priv
->regs
->gaddr2
, 0);
614 gfar_write(&priv
->regs
->gaddr3
, 0);
615 gfar_write(&priv
->regs
->gaddr4
, 0);
616 gfar_write(&priv
->regs
->gaddr5
, 0);
617 gfar_write(&priv
->regs
->gaddr6
, 0);
618 gfar_write(&priv
->regs
->gaddr7
, 0);
620 /* Zero out the rmon mib registers if it has them */
621 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
622 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
624 /* Mask off the CAM interrupts */
625 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
626 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
629 /* Initialize the max receive buffer length */
630 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
632 /* Initialize the Minimum Frame Length Register */
633 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
637 /* Halt the receive and transmit queues */
638 static void gfar_halt_nodisable(struct net_device
*dev
)
640 struct gfar_private
*priv
= netdev_priv(dev
);
641 struct gfar __iomem
*regs
= priv
->regs
;
644 /* Mask all interrupts */
645 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
647 /* Clear all interrupts */
648 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
650 /* Stop the DMA, and wait for it to stop */
651 tempval
= gfar_read(&priv
->regs
->dmactrl
);
652 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
653 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
654 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
655 gfar_write(&priv
->regs
->dmactrl
, tempval
);
657 while (!(gfar_read(&priv
->regs
->ievent
) &
658 (IEVENT_GRSC
| IEVENT_GTSC
)))
663 /* Halt the receive and transmit queues */
664 void gfar_halt(struct net_device
*dev
)
666 struct gfar_private
*priv
= netdev_priv(dev
);
667 struct gfar __iomem
*regs
= priv
->regs
;
670 gfar_halt_nodisable(dev
);
672 /* Disable Rx and Tx */
673 tempval
= gfar_read(®s
->maccfg1
);
674 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
675 gfar_write(®s
->maccfg1
, tempval
);
678 void stop_gfar(struct net_device
*dev
)
680 struct gfar_private
*priv
= netdev_priv(dev
);
681 struct gfar __iomem
*regs
= priv
->regs
;
684 phy_stop(priv
->phydev
);
687 spin_lock_irqsave(&priv
->txlock
, flags
);
688 spin_lock(&priv
->rxlock
);
692 spin_unlock(&priv
->rxlock
);
693 spin_unlock_irqrestore(&priv
->txlock
, flags
);
696 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
697 free_irq(priv
->interruptError
, dev
);
698 free_irq(priv
->interruptTransmit
, dev
);
699 free_irq(priv
->interruptReceive
, dev
);
701 free_irq(priv
->interruptTransmit
, dev
);
704 free_skb_resources(priv
);
706 dma_free_coherent(&dev
->dev
,
707 sizeof(struct txbd8
)*priv
->tx_ring_size
708 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
710 gfar_read(®s
->tbase0
));
713 /* If there are any tx skbs or rx skbs still around, free them.
714 * Then free tx_skbuff and rx_skbuff */
715 static void free_skb_resources(struct gfar_private
*priv
)
721 /* Go through all the buffer descriptors and free their data buffers */
722 txbdp
= priv
->tx_bd_base
;
724 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
726 if (priv
->tx_skbuff
[i
]) {
727 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
730 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
731 priv
->tx_skbuff
[i
] = NULL
;
737 kfree(priv
->tx_skbuff
);
739 rxbdp
= priv
->rx_bd_base
;
741 /* rx_skbuff is not guaranteed to be allocated, so only
742 * free it and its contents if it is allocated */
743 if(priv
->rx_skbuff
!= NULL
) {
744 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
745 if (priv
->rx_skbuff
[i
]) {
746 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
747 priv
->rx_buffer_size
,
750 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
751 priv
->rx_skbuff
[i
] = NULL
;
761 kfree(priv
->rx_skbuff
);
765 void gfar_start(struct net_device
*dev
)
767 struct gfar_private
*priv
= netdev_priv(dev
);
768 struct gfar __iomem
*regs
= priv
->regs
;
771 /* Enable Rx and Tx in MACCFG1 */
772 tempval
= gfar_read(®s
->maccfg1
);
773 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
774 gfar_write(®s
->maccfg1
, tempval
);
776 /* Initialize DMACTRL to have WWR and WOP */
777 tempval
= gfar_read(&priv
->regs
->dmactrl
);
778 tempval
|= DMACTRL_INIT_SETTINGS
;
779 gfar_write(&priv
->regs
->dmactrl
, tempval
);
781 /* Make sure we aren't stopped */
782 tempval
= gfar_read(&priv
->regs
->dmactrl
);
783 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
784 gfar_write(&priv
->regs
->dmactrl
, tempval
);
786 /* Clear THLT/RHLT, so that the DMA starts polling now */
787 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
788 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
790 /* Unmask the interrupts we look for */
791 gfar_write(®s
->imask
, IMASK_DEFAULT
);
794 /* Bring the controller up and running */
795 int startup_gfar(struct net_device
*dev
)
802 struct gfar_private
*priv
= netdev_priv(dev
);
803 struct gfar __iomem
*regs
= priv
->regs
;
808 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
810 /* Allocate memory for the buffer descriptors */
811 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
812 sizeof (struct txbd8
) * priv
->tx_ring_size
+
813 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
817 if (netif_msg_ifup(priv
))
818 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
823 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
825 /* enet DMA only understands physical addresses */
826 gfar_write(®s
->tbase0
, addr
);
828 /* Start the rx descriptor ring where the tx ring leaves off */
829 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
830 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
831 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
832 gfar_write(®s
->rbase0
, addr
);
834 /* Setup the skbuff rings */
836 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
837 priv
->tx_ring_size
, GFP_KERNEL
);
839 if (NULL
== priv
->tx_skbuff
) {
840 if (netif_msg_ifup(priv
))
841 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
847 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
848 priv
->tx_skbuff
[i
] = NULL
;
851 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
852 priv
->rx_ring_size
, GFP_KERNEL
);
854 if (NULL
== priv
->rx_skbuff
) {
855 if (netif_msg_ifup(priv
))
856 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
862 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
863 priv
->rx_skbuff
[i
] = NULL
;
865 /* Initialize some variables in our dev structure */
866 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
867 priv
->cur_rx
= priv
->rx_bd_base
;
868 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
871 /* Initialize Transmit Descriptor Ring */
872 txbdp
= priv
->tx_bd_base
;
873 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
880 /* Set the last descriptor in the ring to indicate wrap */
882 txbdp
->status
|= TXBD_WRAP
;
884 rxbdp
= priv
->rx_bd_base
;
885 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
888 skb
= gfar_new_skb(dev
);
891 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
894 goto err_rxalloc_fail
;
897 priv
->rx_skbuff
[i
] = skb
;
899 gfar_new_rxbdp(dev
, rxbdp
, skb
);
904 /* Set the last descriptor in the ring to wrap */
906 rxbdp
->status
|= RXBD_WRAP
;
908 /* If the device has multiple interrupts, register for
909 * them. Otherwise, only register for the one */
910 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
911 /* Install our interrupt handlers for Error,
912 * Transmit, and Receive */
913 if (request_irq(priv
->interruptError
, gfar_error
,
914 0, "enet_error", dev
) < 0) {
915 if (netif_msg_intr(priv
))
916 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
917 dev
->name
, priv
->interruptError
);
923 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
924 0, "enet_tx", dev
) < 0) {
925 if (netif_msg_intr(priv
))
926 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
927 dev
->name
, priv
->interruptTransmit
);
934 if (request_irq(priv
->interruptReceive
, gfar_receive
,
935 0, "enet_rx", dev
) < 0) {
936 if (netif_msg_intr(priv
))
937 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
938 dev
->name
, priv
->interruptReceive
);
944 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
945 0, "gfar_interrupt", dev
) < 0) {
946 if (netif_msg_intr(priv
))
947 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
948 dev
->name
, priv
->interruptError
);
955 phy_start(priv
->phydev
);
957 /* Configure the coalescing support */
958 if (priv
->txcoalescing
)
959 gfar_write(®s
->txic
,
960 mk_ic_value(priv
->txcount
, priv
->txtime
));
962 gfar_write(®s
->txic
, 0);
964 if (priv
->rxcoalescing
)
965 gfar_write(®s
->rxic
,
966 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
968 gfar_write(®s
->rxic
, 0);
970 if (priv
->rx_csum_enable
)
971 rctrl
|= RCTRL_CHECKSUMMING
;
973 if (priv
->extended_hash
) {
974 rctrl
|= RCTRL_EXTHASH
;
976 gfar_clear_exact_match(dev
);
980 if (priv
->vlan_enable
)
984 rctrl
&= ~RCTRL_PAL_MASK
;
985 rctrl
|= RCTRL_PADDING(priv
->padding
);
988 /* Init rctrl based on our settings */
989 gfar_write(&priv
->regs
->rctrl
, rctrl
);
991 if (dev
->features
& NETIF_F_IP_CSUM
)
992 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
994 /* Set the extraction length and index */
995 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
996 ATTRELI_EI(priv
->rx_stash_index
);
998 gfar_write(&priv
->regs
->attreli
, attrs
);
1000 /* Start with defaults, and add stashing or locking
1001 * depending on the approprate variables */
1002 attrs
= ATTR_INIT_SETTINGS
;
1004 if (priv
->bd_stash_en
)
1005 attrs
|= ATTR_BDSTASH
;
1007 if (priv
->rx_stash_size
!= 0)
1008 attrs
|= ATTR_BUFSTASH
;
1010 gfar_write(&priv
->regs
->attr
, attrs
);
1012 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1013 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1014 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1016 /* Start the controller */
1022 free_irq(priv
->interruptTransmit
, dev
);
1024 free_irq(priv
->interruptError
, dev
);
1028 free_skb_resources(priv
);
1030 dma_free_coherent(&dev
->dev
,
1031 sizeof(struct txbd8
)*priv
->tx_ring_size
1032 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1034 gfar_read(®s
->tbase0
));
1039 /* Called when something needs to use the ethernet device */
1040 /* Returns 0 for success. */
1041 static int gfar_enet_open(struct net_device
*dev
)
1043 struct gfar_private
*priv
= netdev_priv(dev
);
1046 napi_enable(&priv
->napi
);
1048 /* Initialize a bunch of registers */
1049 init_registers(dev
);
1051 gfar_set_mac_address(dev
);
1053 err
= init_phy(dev
);
1056 napi_disable(&priv
->napi
);
1060 err
= startup_gfar(dev
);
1062 napi_disable(&priv
->napi
);
1066 netif_start_queue(dev
);
1071 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
1073 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
1075 memset(fcb
, 0, GMAC_FCB_LEN
);
1080 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1084 /* If we're here, it's a IP packet with a TCP or UDP
1085 * payload. We set it to checksum, using a pseudo-header
1088 flags
= TXFCB_DEFAULT
;
1090 /* Tell the controller what the protocol is */
1091 /* And provide the already calculated phcs */
1092 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1094 fcb
->phcs
= udp_hdr(skb
)->check
;
1096 fcb
->phcs
= tcp_hdr(skb
)->check
;
1098 /* l3os is the distance between the start of the
1099 * frame (skb->data) and the start of the IP hdr.
1100 * l4os is the distance between the start of the
1101 * l3 hdr and the l4 hdr */
1102 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1103 fcb
->l4os
= skb_network_header_len(skb
);
1108 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1110 fcb
->flags
|= TXFCB_VLN
;
1111 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1114 /* This is called by the kernel when a frame is ready for transmission. */
1115 /* It is pointed to by the dev->hard_start_xmit function pointer */
1116 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1118 struct gfar_private
*priv
= netdev_priv(dev
);
1119 struct txfcb
*fcb
= NULL
;
1120 struct txbd8
*txbdp
;
1122 unsigned long flags
;
1124 /* Update transmit stats */
1125 dev
->stats
.tx_bytes
+= skb
->len
;
1128 spin_lock_irqsave(&priv
->txlock
, flags
);
1130 /* Point at the first free tx descriptor */
1131 txbdp
= priv
->cur_tx
;
1133 /* Clear all but the WRAP status flags */
1134 status
= txbdp
->status
& TXBD_WRAP
;
1136 /* Set up checksumming */
1137 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1138 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1139 fcb
= gfar_add_fcb(skb
, txbdp
);
1141 gfar_tx_checksum(skb
, fcb
);
1144 if (priv
->vlan_enable
&&
1145 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1146 if (unlikely(NULL
== fcb
)) {
1147 fcb
= gfar_add_fcb(skb
, txbdp
);
1151 gfar_tx_vlan(skb
, fcb
);
1154 /* Set buffer length and pointer */
1155 txbdp
->length
= skb
->len
;
1156 txbdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1157 skb
->len
, DMA_TO_DEVICE
);
1159 /* Save the skb pointer so we can free it later */
1160 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1162 /* Update the current skb pointer (wrapping if this was the last) */
1164 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1166 /* Flag the BD as interrupt-causing */
1167 status
|= TXBD_INTERRUPT
;
1169 /* Flag the BD as ready to go, last in frame, and */
1170 /* in need of CRC */
1171 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1173 dev
->trans_start
= jiffies
;
1175 /* The powerpc-specific eieio() is used, as wmb() has too strong
1176 * semantics (it requires synchronization between cacheable and
1177 * uncacheable mappings, which eieio doesn't provide and which we
1178 * don't need), thus requiring a more expensive sync instruction. At
1179 * some point, the set of architecture-independent barrier functions
1180 * should be expanded to include weaker barriers.
1184 txbdp
->status
= status
;
1186 /* If this was the last BD in the ring, the next one */
1187 /* is at the beginning of the ring */
1188 if (txbdp
->status
& TXBD_WRAP
)
1189 txbdp
= priv
->tx_bd_base
;
1193 /* If the next BD still needs to be cleaned up, then the bds
1194 are full. We need to tell the kernel to stop sending us stuff. */
1195 if (txbdp
== priv
->dirty_tx
) {
1196 netif_stop_queue(dev
);
1198 dev
->stats
.tx_fifo_errors
++;
1201 /* Update the current txbd to the next one */
1202 priv
->cur_tx
= txbdp
;
1204 /* Tell the DMA to go go go */
1205 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1208 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1213 /* Stops the kernel queue, and halts the controller */
1214 static int gfar_close(struct net_device
*dev
)
1216 struct gfar_private
*priv
= netdev_priv(dev
);
1218 napi_disable(&priv
->napi
);
1220 cancel_work_sync(&priv
->reset_task
);
1223 /* Disconnect from the PHY */
1224 phy_disconnect(priv
->phydev
);
1225 priv
->phydev
= NULL
;
1227 netif_stop_queue(dev
);
1232 /* Changes the mac address if the controller is not running. */
1233 static int gfar_set_mac_address(struct net_device
*dev
)
1235 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1241 /* Enables and disables VLAN insertion/extraction */
1242 static void gfar_vlan_rx_register(struct net_device
*dev
,
1243 struct vlan_group
*grp
)
1245 struct gfar_private
*priv
= netdev_priv(dev
);
1246 unsigned long flags
;
1249 spin_lock_irqsave(&priv
->rxlock
, flags
);
1254 /* Enable VLAN tag insertion */
1255 tempval
= gfar_read(&priv
->regs
->tctrl
);
1256 tempval
|= TCTRL_VLINS
;
1258 gfar_write(&priv
->regs
->tctrl
, tempval
);
1260 /* Enable VLAN tag extraction */
1261 tempval
= gfar_read(&priv
->regs
->rctrl
);
1262 tempval
|= RCTRL_VLEX
;
1263 gfar_write(&priv
->regs
->rctrl
, tempval
);
1265 /* Disable VLAN tag insertion */
1266 tempval
= gfar_read(&priv
->regs
->tctrl
);
1267 tempval
&= ~TCTRL_VLINS
;
1268 gfar_write(&priv
->regs
->tctrl
, tempval
);
1270 /* Disable VLAN tag extraction */
1271 tempval
= gfar_read(&priv
->regs
->rctrl
);
1272 tempval
&= ~RCTRL_VLEX
;
1273 gfar_write(&priv
->regs
->rctrl
, tempval
);
1276 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1279 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1281 int tempsize
, tempval
;
1282 struct gfar_private
*priv
= netdev_priv(dev
);
1283 int oldsize
= priv
->rx_buffer_size
;
1284 int frame_size
= new_mtu
+ ETH_HLEN
;
1286 if (priv
->vlan_enable
)
1287 frame_size
+= VLAN_HLEN
;
1289 if (gfar_uses_fcb(priv
))
1290 frame_size
+= GMAC_FCB_LEN
;
1292 frame_size
+= priv
->padding
;
1294 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1295 if (netif_msg_drv(priv
))
1296 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1302 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1303 INCREMENTAL_BUFFER_SIZE
;
1305 /* Only stop and start the controller if it isn't already
1306 * stopped, and we changed something */
1307 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1310 priv
->rx_buffer_size
= tempsize
;
1314 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1315 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1317 /* If the mtu is larger than the max size for standard
1318 * ethernet frames (ie, a jumbo frame), then set maccfg2
1319 * to allow huge frames, and to check the length */
1320 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1322 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1323 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1325 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1327 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1329 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1335 /* gfar_reset_task gets scheduled when a packet has not been
1336 * transmitted after a set amount of time.
1337 * For now, assume that clearing out all the structures, and
1338 * starting over will fix the problem.
1340 static void gfar_reset_task(struct work_struct
*work
)
1342 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
1344 struct net_device
*dev
= priv
->dev
;
1346 if (dev
->flags
& IFF_UP
) {
1351 netif_tx_schedule_all(dev
);
1354 static void gfar_timeout(struct net_device
*dev
)
1356 struct gfar_private
*priv
= netdev_priv(dev
);
1358 dev
->stats
.tx_errors
++;
1359 schedule_work(&priv
->reset_task
);
1362 /* Interrupt Handler for Transmit complete */
1363 static int gfar_clean_tx_ring(struct net_device
*dev
)
1366 struct gfar_private
*priv
= netdev_priv(dev
);
1369 bdp
= priv
->dirty_tx
;
1370 while ((bdp
->status
& TXBD_READY
) == 0) {
1371 /* If dirty_tx and cur_tx are the same, then either the */
1372 /* ring is empty or full now (it could only be full in the beginning, */
1373 /* obviously). If it is empty, we are done. */
1374 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1379 /* Deferred means some collisions occurred during transmit, */
1380 /* but we eventually sent the packet. */
1381 if (bdp
->status
& TXBD_DEF
)
1382 dev
->stats
.collisions
++;
1384 /* Free the sk buffer associated with this TxBD */
1385 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1387 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1389 (priv
->skb_dirtytx
+
1390 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1392 /* Clean BD length for empty detection */
1395 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1396 if (bdp
->status
& TXBD_WRAP
)
1397 bdp
= priv
->tx_bd_base
;
1401 /* Move dirty_tx to be the next bd */
1402 priv
->dirty_tx
= bdp
;
1404 /* We freed a buffer, so now we can restart transmission */
1405 if (netif_queue_stopped(dev
))
1406 netif_wake_queue(dev
);
1407 } /* while ((bdp->status & TXBD_READY) == 0) */
1409 dev
->stats
.tx_packets
+= howmany
;
1414 /* Interrupt Handler for Transmit complete */
1415 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1417 struct net_device
*dev
= (struct net_device
*) dev_id
;
1418 struct gfar_private
*priv
= netdev_priv(dev
);
1421 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1424 spin_lock(&priv
->txlock
);
1426 gfar_clean_tx_ring(dev
);
1428 /* If we are coalescing the interrupts, reset the timer */
1429 /* Otherwise, clear it */
1430 if (likely(priv
->txcoalescing
)) {
1431 gfar_write(&priv
->regs
->txic
, 0);
1432 gfar_write(&priv
->regs
->txic
,
1433 mk_ic_value(priv
->txcount
, priv
->txtime
));
1436 spin_unlock(&priv
->txlock
);
1441 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1442 struct sk_buff
*skb
)
1444 struct gfar_private
*priv
= netdev_priv(dev
);
1445 u32
* status_len
= (u32
*)bdp
;
1448 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1449 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1451 flags
= RXBD_EMPTY
| RXBD_INTERRUPT
;
1453 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1458 *status_len
= (u32
)flags
<< 16;
1462 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1464 unsigned int alignamount
;
1465 struct gfar_private
*priv
= netdev_priv(dev
);
1466 struct sk_buff
*skb
= NULL
;
1468 /* We have to allocate the skb, so keep trying till we succeed */
1469 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1474 alignamount
= RXBUF_ALIGNMENT
-
1475 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1477 /* We need the data buffer to be aligned properly. We will reserve
1478 * as many bytes as needed to align the data properly
1480 skb_reserve(skb
, alignamount
);
1485 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1487 struct gfar_private
*priv
= netdev_priv(dev
);
1488 struct net_device_stats
*stats
= &dev
->stats
;
1489 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1491 /* If the packet was truncated, none of the other errors
1493 if (status
& RXBD_TRUNCATED
) {
1494 stats
->rx_length_errors
++;
1500 /* Count the errors, if there were any */
1501 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1502 stats
->rx_length_errors
++;
1504 if (status
& RXBD_LARGE
)
1509 if (status
& RXBD_NONOCTET
) {
1510 stats
->rx_frame_errors
++;
1511 estats
->rx_nonoctet
++;
1513 if (status
& RXBD_CRCERR
) {
1514 estats
->rx_crcerr
++;
1515 stats
->rx_crc_errors
++;
1517 if (status
& RXBD_OVERRUN
) {
1518 estats
->rx_overrun
++;
1519 stats
->rx_crc_errors
++;
1523 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1525 struct net_device
*dev
= (struct net_device
*) dev_id
;
1526 struct gfar_private
*priv
= netdev_priv(dev
);
1530 /* Clear IEVENT, so interrupts aren't called again
1531 * because of the packets that have already arrived */
1532 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1534 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1535 tempval
= gfar_read(&priv
->regs
->imask
);
1536 tempval
&= IMASK_RTX_DISABLED
;
1537 gfar_write(&priv
->regs
->imask
, tempval
);
1539 __netif_rx_schedule(dev
, &priv
->napi
);
1541 if (netif_msg_rx_err(priv
))
1542 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1543 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1544 gfar_read(&priv
->regs
->imask
));
1550 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1552 /* If valid headers were found, and valid sums
1553 * were verified, then we tell the kernel that no
1554 * checksumming is necessary. Otherwise, it is */
1555 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1556 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1558 skb
->ip_summed
= CHECKSUM_NONE
;
1562 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1564 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1566 /* Remove the FCB from the skb */
1567 skb_pull(skb
, GMAC_FCB_LEN
);
1572 /* gfar_process_frame() -- handle one incoming packet if skb
1574 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1577 struct gfar_private
*priv
= netdev_priv(dev
);
1578 struct rxfcb
*fcb
= NULL
;
1581 if (netif_msg_rx_err(priv
))
1582 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1583 dev
->stats
.rx_dropped
++;
1584 priv
->extra_stats
.rx_skbmissing
++;
1588 /* Prep the skb for the packet */
1589 skb_put(skb
, length
);
1591 /* Grab the FCB if there is one */
1592 if (gfar_uses_fcb(priv
))
1593 fcb
= gfar_get_fcb(skb
);
1595 /* Remove the padded bytes, if there are any */
1597 skb_pull(skb
, priv
->padding
);
1599 if (priv
->rx_csum_enable
)
1600 gfar_rx_checksum(skb
, fcb
);
1602 /* Tell the skb what kind of packet this is */
1603 skb
->protocol
= eth_type_trans(skb
, dev
);
1605 /* Send the packet up the stack */
1606 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
))) {
1607 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
,
1610 ret
= netif_receive_skb(skb
);
1612 if (NET_RX_DROP
== ret
)
1613 priv
->extra_stats
.kernel_dropped
++;
1619 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1620 * until the budget/quota has been reached. Returns the number
1623 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1626 struct sk_buff
*skb
;
1629 struct gfar_private
*priv
= netdev_priv(dev
);
1631 /* Get the first full descriptor */
1634 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1635 struct sk_buff
*newskb
;
1638 /* Add another skb for the future */
1639 newskb
= gfar_new_skb(dev
);
1641 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1643 /* We drop the frame if we failed to allocate a new buffer */
1644 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1645 bdp
->status
& RXBD_ERR
)) {
1646 count_errors(bdp
->status
, dev
);
1648 if (unlikely(!newskb
))
1652 dma_unmap_single(&priv
->dev
->dev
,
1654 priv
->rx_buffer_size
,
1657 dev_kfree_skb_any(skb
);
1660 /* Increment the number of packets */
1661 dev
->stats
.rx_packets
++;
1664 /* Remove the FCS from the packet length */
1665 pkt_len
= bdp
->length
- 4;
1667 gfar_process_frame(dev
, skb
, pkt_len
);
1669 dev
->stats
.rx_bytes
+= pkt_len
;
1672 dev
->last_rx
= jiffies
;
1674 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1676 /* Setup the new bdp */
1677 gfar_new_rxbdp(dev
, bdp
, newskb
);
1679 /* Update to the next pointer */
1680 if (bdp
->status
& RXBD_WRAP
)
1681 bdp
= priv
->rx_bd_base
;
1685 /* update to point at the next skb */
1687 (priv
->skb_currx
+ 1) &
1688 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1691 /* Update the current rxbd pointer to be the next one */
1697 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1699 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1700 struct net_device
*dev
= priv
->dev
;
1702 unsigned long flags
;
1704 /* If we fail to get the lock, don't bother with the TX BDs */
1705 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1706 gfar_clean_tx_ring(dev
);
1707 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1710 howmany
= gfar_clean_rx_ring(dev
, budget
);
1712 if (howmany
< budget
) {
1713 netif_rx_complete(dev
, napi
);
1715 /* Clear the halt bit in RSTAT */
1716 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1718 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1720 /* If we are coalescing interrupts, update the timer */
1721 /* Otherwise, clear it */
1722 if (likely(priv
->rxcoalescing
)) {
1723 gfar_write(&priv
->regs
->rxic
, 0);
1724 gfar_write(&priv
->regs
->rxic
,
1725 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1732 #ifdef CONFIG_NET_POLL_CONTROLLER
1734 * Polling 'interrupt' - used by things like netconsole to send skbs
1735 * without having to re-enable interrupts. It's not called while
1736 * the interrupt routine is executing.
1738 static void gfar_netpoll(struct net_device
*dev
)
1740 struct gfar_private
*priv
= netdev_priv(dev
);
1742 /* If the device has multiple interrupts, run tx/rx */
1743 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1744 disable_irq(priv
->interruptTransmit
);
1745 disable_irq(priv
->interruptReceive
);
1746 disable_irq(priv
->interruptError
);
1747 gfar_interrupt(priv
->interruptTransmit
, dev
);
1748 enable_irq(priv
->interruptError
);
1749 enable_irq(priv
->interruptReceive
);
1750 enable_irq(priv
->interruptTransmit
);
1752 disable_irq(priv
->interruptTransmit
);
1753 gfar_interrupt(priv
->interruptTransmit
, dev
);
1754 enable_irq(priv
->interruptTransmit
);
1759 /* The interrupt handler for devices with one interrupt */
1760 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1762 struct net_device
*dev
= dev_id
;
1763 struct gfar_private
*priv
= netdev_priv(dev
);
1765 /* Save ievent for future reference */
1766 u32 events
= gfar_read(&priv
->regs
->ievent
);
1768 /* Check for reception */
1769 if (events
& IEVENT_RX_MASK
)
1770 gfar_receive(irq
, dev_id
);
1772 /* Check for transmit completion */
1773 if (events
& IEVENT_TX_MASK
)
1774 gfar_transmit(irq
, dev_id
);
1776 /* Check for errors */
1777 if (events
& IEVENT_ERR_MASK
)
1778 gfar_error(irq
, dev_id
);
1783 /* Called every time the controller might need to be made
1784 * aware of new link state. The PHY code conveys this
1785 * information through variables in the phydev structure, and this
1786 * function converts those variables into the appropriate
1787 * register values, and can bring down the device if needed.
1789 static void adjust_link(struct net_device
*dev
)
1791 struct gfar_private
*priv
= netdev_priv(dev
);
1792 struct gfar __iomem
*regs
= priv
->regs
;
1793 unsigned long flags
;
1794 struct phy_device
*phydev
= priv
->phydev
;
1797 spin_lock_irqsave(&priv
->txlock
, flags
);
1799 u32 tempval
= gfar_read(®s
->maccfg2
);
1800 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1802 /* Now we make sure that we can be in full duplex mode.
1803 * If not, we operate in half-duplex mode. */
1804 if (phydev
->duplex
!= priv
->oldduplex
) {
1806 if (!(phydev
->duplex
))
1807 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1809 tempval
|= MACCFG2_FULL_DUPLEX
;
1811 priv
->oldduplex
= phydev
->duplex
;
1814 if (phydev
->speed
!= priv
->oldspeed
) {
1816 switch (phydev
->speed
) {
1819 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1824 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1826 /* Reduced mode distinguishes
1827 * between 10 and 100 */
1828 if (phydev
->speed
== SPEED_100
)
1829 ecntrl
|= ECNTRL_R100
;
1831 ecntrl
&= ~(ECNTRL_R100
);
1834 if (netif_msg_link(priv
))
1836 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1837 dev
->name
, phydev
->speed
);
1841 priv
->oldspeed
= phydev
->speed
;
1844 gfar_write(®s
->maccfg2
, tempval
);
1845 gfar_write(®s
->ecntrl
, ecntrl
);
1847 if (!priv
->oldlink
) {
1851 } else if (priv
->oldlink
) {
1855 priv
->oldduplex
= -1;
1858 if (new_state
&& netif_msg_link(priv
))
1859 phy_print_status(phydev
);
1861 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1864 /* Update the hash table based on the current list of multicast
1865 * addresses we subscribe to. Also, change the promiscuity of
1866 * the device based on the flags (this function is called
1867 * whenever dev->flags is changed */
1868 static void gfar_set_multi(struct net_device
*dev
)
1870 struct dev_mc_list
*mc_ptr
;
1871 struct gfar_private
*priv
= netdev_priv(dev
);
1872 struct gfar __iomem
*regs
= priv
->regs
;
1875 if(dev
->flags
& IFF_PROMISC
) {
1876 /* Set RCTRL to PROM */
1877 tempval
= gfar_read(®s
->rctrl
);
1878 tempval
|= RCTRL_PROM
;
1879 gfar_write(®s
->rctrl
, tempval
);
1881 /* Set RCTRL to not PROM */
1882 tempval
= gfar_read(®s
->rctrl
);
1883 tempval
&= ~(RCTRL_PROM
);
1884 gfar_write(®s
->rctrl
, tempval
);
1887 if(dev
->flags
& IFF_ALLMULTI
) {
1888 /* Set the hash to rx all multicast frames */
1889 gfar_write(®s
->igaddr0
, 0xffffffff);
1890 gfar_write(®s
->igaddr1
, 0xffffffff);
1891 gfar_write(®s
->igaddr2
, 0xffffffff);
1892 gfar_write(®s
->igaddr3
, 0xffffffff);
1893 gfar_write(®s
->igaddr4
, 0xffffffff);
1894 gfar_write(®s
->igaddr5
, 0xffffffff);
1895 gfar_write(®s
->igaddr6
, 0xffffffff);
1896 gfar_write(®s
->igaddr7
, 0xffffffff);
1897 gfar_write(®s
->gaddr0
, 0xffffffff);
1898 gfar_write(®s
->gaddr1
, 0xffffffff);
1899 gfar_write(®s
->gaddr2
, 0xffffffff);
1900 gfar_write(®s
->gaddr3
, 0xffffffff);
1901 gfar_write(®s
->gaddr4
, 0xffffffff);
1902 gfar_write(®s
->gaddr5
, 0xffffffff);
1903 gfar_write(®s
->gaddr6
, 0xffffffff);
1904 gfar_write(®s
->gaddr7
, 0xffffffff);
1909 /* zero out the hash */
1910 gfar_write(®s
->igaddr0
, 0x0);
1911 gfar_write(®s
->igaddr1
, 0x0);
1912 gfar_write(®s
->igaddr2
, 0x0);
1913 gfar_write(®s
->igaddr3
, 0x0);
1914 gfar_write(®s
->igaddr4
, 0x0);
1915 gfar_write(®s
->igaddr5
, 0x0);
1916 gfar_write(®s
->igaddr6
, 0x0);
1917 gfar_write(®s
->igaddr7
, 0x0);
1918 gfar_write(®s
->gaddr0
, 0x0);
1919 gfar_write(®s
->gaddr1
, 0x0);
1920 gfar_write(®s
->gaddr2
, 0x0);
1921 gfar_write(®s
->gaddr3
, 0x0);
1922 gfar_write(®s
->gaddr4
, 0x0);
1923 gfar_write(®s
->gaddr5
, 0x0);
1924 gfar_write(®s
->gaddr6
, 0x0);
1925 gfar_write(®s
->gaddr7
, 0x0);
1927 /* If we have extended hash tables, we need to
1928 * clear the exact match registers to prepare for
1930 if (priv
->extended_hash
) {
1931 em_num
= GFAR_EM_NUM
+ 1;
1932 gfar_clear_exact_match(dev
);
1939 if(dev
->mc_count
== 0)
1942 /* Parse the list, and set the appropriate bits */
1943 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1945 gfar_set_mac_for_addr(dev
, idx
,
1949 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1957 /* Clears each of the exact match registers to zero, so they
1958 * don't interfere with normal reception */
1959 static void gfar_clear_exact_match(struct net_device
*dev
)
1962 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1964 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1965 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1968 /* Set the appropriate hash bit for the given addr */
1969 /* The algorithm works like so:
1970 * 1) Take the Destination Address (ie the multicast address), and
1971 * do a CRC on it (little endian), and reverse the bits of the
1973 * 2) Use the 8 most significant bits as a hash into a 256-entry
1974 * table. The table is controlled through 8 32-bit registers:
1975 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1976 * gaddr7. This means that the 3 most significant bits in the
1977 * hash index which gaddr register to use, and the 5 other bits
1978 * indicate which bit (assuming an IBM numbering scheme, which
1979 * for PowerPC (tm) is usually the case) in the register holds
1981 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1984 struct gfar_private
*priv
= netdev_priv(dev
);
1985 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1986 int width
= priv
->hash_width
;
1987 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1988 u8 whichreg
= result
>> (32 - width
+ 5);
1989 u32 value
= (1 << (31-whichbit
));
1991 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1993 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1999 /* There are multiple MAC Address register pairs on some controllers
2000 * This function sets the numth pair to a given address
2002 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
2004 struct gfar_private
*priv
= netdev_priv(dev
);
2006 char tmpbuf
[MAC_ADDR_LEN
];
2008 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
2012 /* Now copy it into the mac registers backwards, cuz */
2013 /* little endian is silly */
2014 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2015 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2017 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2019 tempval
= *((u32
*) (tmpbuf
+ 4));
2021 gfar_write(macptr
+1, tempval
);
2024 /* GFAR error interrupt handler */
2025 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2027 struct net_device
*dev
= dev_id
;
2028 struct gfar_private
*priv
= netdev_priv(dev
);
2030 /* Save ievent for future reference */
2031 u32 events
= gfar_read(&priv
->regs
->ievent
);
2034 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2036 /* Magic Packet is not an error. */
2037 if ((priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2038 (events
& IEVENT_MAG
))
2039 events
&= ~IEVENT_MAG
;
2042 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2043 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2044 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2046 /* Update the error counters */
2047 if (events
& IEVENT_TXE
) {
2048 dev
->stats
.tx_errors
++;
2050 if (events
& IEVENT_LC
)
2051 dev
->stats
.tx_window_errors
++;
2052 if (events
& IEVENT_CRL
)
2053 dev
->stats
.tx_aborted_errors
++;
2054 if (events
& IEVENT_XFUN
) {
2055 if (netif_msg_tx_err(priv
))
2056 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2057 "packet dropped.\n", dev
->name
);
2058 dev
->stats
.tx_dropped
++;
2059 priv
->extra_stats
.tx_underrun
++;
2061 /* Reactivate the Tx Queues */
2062 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2064 if (netif_msg_tx_err(priv
))
2065 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2067 if (events
& IEVENT_BSY
) {
2068 dev
->stats
.rx_errors
++;
2069 priv
->extra_stats
.rx_bsy
++;
2071 gfar_receive(irq
, dev_id
);
2073 if (netif_msg_rx_err(priv
))
2074 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2075 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2077 if (events
& IEVENT_BABR
) {
2078 dev
->stats
.rx_errors
++;
2079 priv
->extra_stats
.rx_babr
++;
2081 if (netif_msg_rx_err(priv
))
2082 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2084 if (events
& IEVENT_EBERR
) {
2085 priv
->extra_stats
.eberr
++;
2086 if (netif_msg_rx_err(priv
))
2087 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2089 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2090 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2092 if (events
& IEVENT_BABT
) {
2093 priv
->extra_stats
.tx_babt
++;
2094 if (netif_msg_tx_err(priv
))
2095 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2100 /* work with hotplug and coldplug */
2101 MODULE_ALIAS("platform:fsl-gianfar");
2103 /* Structure for a device driver */
2104 static struct platform_driver gfar_driver
= {
2105 .probe
= gfar_probe
,
2106 .remove
= gfar_remove
,
2107 .suspend
= gfar_suspend
,
2108 .resume
= gfar_resume
,
2110 .name
= "fsl-gianfar",
2111 .owner
= THIS_MODULE
,
2115 static int __init
gfar_init(void)
2117 int err
= gfar_mdio_init();
2122 err
= platform_driver_register(&gfar_driver
);
2130 static void __exit
gfar_exit(void)
2132 platform_driver_unregister(&gfar_driver
);
2136 module_init(gfar_init
);
2137 module_exit(gfar_exit
);