2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __devinit
quirk_passive_release(struct pci_dev
*dev
)
28 struct pci_dev
*d
= NULL
;
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
34 pci_read_config_byte(d
, 0x82, &dlc
);
36 printk(KERN_ERR
"PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d
));
38 pci_write_config_byte(d
, 0x82, dlc
);
42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
45 but VIA don't answer queries. If you happen to have good contacts at VIA
46 ask them for me please -- Alan
48 This appears to be BIOS not version dependent. So presumably there is a
50 int isa_dma_bridge_buggy
; /* Exported */
52 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
54 if (!isa_dma_bridge_buggy
) {
55 isa_dma_bridge_buggy
=1;
56 printk(KERN_INFO
"Activating ISA DMA hang workarounds.\n");
60 * Its not totally clear which chipsets are the problematic ones
61 * We know 82C586 and 82C596 variants are affected.
63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
74 * Chipsets where PCI->PCI transfers vanish or hang
76 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
78 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
79 printk(KERN_INFO
"Disabling direct PCI/PCI transfers.\n");
80 pci_pci_problems
|= PCIPCI_FAIL
;
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
87 * Triton requires workarounds to be used by the drivers
89 static void __devinit
quirk_triton(struct pci_dev
*dev
)
91 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
92 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
93 pci_pci_problems
|= PCIPCI_TRITON
;
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
102 * VIA Apollo KT133 needs PCI latency patch
103 * Made according to a windows driver based patch by George E. Breese
104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
106 * the info on which Mr Breese based his work.
108 * Updated based on further information from the site and also on
109 * information provided by VIA
111 static void __devinit
quirk_vialatency(struct pci_dev
*dev
)
116 /* Ok we have a potential problem chipset here. Now see if we have
117 a buggy southbridge */
119 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
121 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
123 /* Check for buggy part revisions */
124 if (rev
< 0x40 || rev
> 0x42)
127 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
128 if (p
==NULL
) /* No problem parts */
130 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
131 /* Check for buggy part revisions */
132 if (rev
< 0x10 || rev
> 0x12)
137 * Ok we have the problem. Now set the PCI master grant to
138 * occur every master grant. The apparent bug is that under high
139 * PCI load (quite common in Linux of course) you can get data
140 * loss when the CPU is held off the bus for 3 bus master requests
141 * This happens to include the IDE controllers....
143 * VIA only apply this fix when an SB Live! is present but under
144 * both Linux and Windows this isnt enough, and we have seen
145 * corruption without SB Live! but with things like 3 UDMA IDE
146 * controllers. So we ignore that bit of the VIA recommendation..
149 pci_read_config_byte(dev
, 0x76, &busarb
);
150 /* Set bit 4 and bi 5 of byte 76 to 0x01
151 "Master priority rotation on every PCI master grant */
154 pci_write_config_byte(dev
, 0x76, busarb
);
155 printk(KERN_INFO
"Applying VIA southbridge workaround.\n");
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
164 * VIA Apollo VP3 needs ETBF on BT848/878
166 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
168 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
169 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
170 pci_pci_problems
|= PCIPCI_VIAETBF
;
173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
175 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
177 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
178 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
179 pci_pci_problems
|= PCIPCI_VSFX
;
182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
185 * Ali Magik requires workarounds to be used by the drivers
186 * that DMA to AGP space. Latency must be set to 0xA and triton
187 * workaround applied too
188 * [Info kindly provided by ALi]
190 static void __init
quirk_alimagik(struct pci_dev
*dev
)
192 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
193 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
194 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
201 * Natoma has some interesting boundary conditions with Zoran stuff
204 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
206 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
207 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems
|= PCIPCI_NATOMA
;
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
219 * This chip can cause PCI parity errors if config register 0xA0 is read
220 * while DMAs are occurring.
222 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
224 dev
->cfg_size
= 0xA0;
226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
230 * If it's needed, re-allocate the region.
232 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
234 struct resource
*r
= &dev
->resource
[0];
236 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
244 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
245 unsigned size
, int nr
, const char *name
)
249 struct pci_bus_region bus_region
;
250 struct resource
*res
= dev
->resource
+ nr
;
252 res
->name
= pci_name(dev
);
254 res
->end
= region
+ size
- 1;
255 res
->flags
= IORESOURCE_IO
;
257 /* Convert from PCI bus to resource space. */
258 bus_region
.start
= res
->start
;
259 bus_region
.end
= res
->end
;
260 pcibios_bus_to_resource(dev
, res
, &bus_region
);
262 pci_claim_resource(dev
, nr
);
263 printk("PCI quirk: region %04x-%04x claimed by %s\n", region
, region
+ size
- 1, name
);
268 * ATI Northbridge setups MCE the processor if you even
269 * read somewhere between 0x3b0->0x3bb or read 0x3d3
271 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
273 printk(KERN_INFO
"ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
274 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
275 request_region(0x3b0, 0x0C, "RadeonIGP");
276 request_region(0x3d3, 0x01, "RadeonIGP");
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
281 * Let's make the southbridge information explicit instead
282 * of having to worry about people probing the ACPI areas,
283 * for example.. (Yes, it happens, and if you read the wrong
284 * ACPI register it will put the machine to sleep with no
285 * way of waking it up again. Bummer).
287 * ALI M7101: Two IO regions pointed to by words at
288 * 0xE0 (64 bytes of ACPI registers)
289 * 0xE2 (32 bytes of SMB registers)
291 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
295 pci_read_config_word(dev
, 0xE0, ®ion
);
296 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
297 pci_read_config_word(dev
, 0xE2, ®ion
);
298 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
302 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
305 u32 mask
, size
, base
;
307 pci_read_config_dword(dev
, port
, &devres
);
308 if ((devres
& enable
) != enable
)
310 mask
= (devres
>> 16) & 15;
311 base
= devres
& 0xffff;
314 unsigned bit
= size
>> 1;
315 if ((bit
& mask
) == bit
)
320 * For now we only print it out. Eventually we'll want to
321 * reserve it (at least if it's in the 0x1000+ range), but
322 * let's get enough confirmation reports first.
325 printk("%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
328 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
331 u32 mask
, size
, base
;
333 pci_read_config_dword(dev
, port
, &devres
);
334 if ((devres
& enable
) != enable
)
336 base
= devres
& 0xffff0000;
337 mask
= (devres
& 0x3f) << 16;
340 unsigned bit
= size
>> 1;
341 if ((bit
& mask
) == bit
)
346 * For now we only print it out. Eventually we'll want to
347 * reserve it, but let's get enough confirmation reports first.
350 printk("%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
354 * PIIX4 ACPI: Two IO regions pointed to by longwords at
355 * 0x40 (64 bytes of ACPI registers)
356 * 0x90 (32 bytes of SMB registers)
357 * and a few strange programmable PIIX4 device resources.
359 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
363 pci_read_config_dword(dev
, 0x40, ®ion
);
364 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
365 pci_read_config_dword(dev
, 0x90, ®ion
);
366 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
368 /* Device resource A has enables for some of the other ones */
369 pci_read_config_dword(dev
, 0x5c, &res_a
);
371 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
372 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
374 /* Device resource D is just bitfields for static resources */
376 /* Device 12 enabled? */
377 if (res_a
& (1 << 29)) {
378 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
379 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
381 /* Device 13 enabled? */
382 if (res_a
& (1 << 30)) {
383 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
384 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
386 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
387 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
389 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
392 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
393 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
394 * 0x58 (64 bytes of GPIO I/O space)
396 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
400 pci_read_config_dword(dev
, 0x40, ®ion
);
401 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH4 ACPI/GPIO/TCO");
403 pci_read_config_dword(dev
, 0x58, ®ion
);
404 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH4 GPIO");
406 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
407 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
418 * VIA ACPI: One IO region pointed to by longword at
419 * 0x48 or 0x20 (256 bytes of ACPI registers)
421 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
426 pci_read_config_byte(dev
, PCI_CLASS_REVISION
, &rev
);
428 pci_read_config_dword(dev
, 0x48, ®ion
);
429 region
&= PCI_BASE_ADDRESS_IO_MASK
;
430 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
433 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
436 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
437 * 0x48 (256 bytes of ACPI registers)
438 * 0x70 (128 bytes of hardware monitoring register)
439 * 0x90 (16 bytes of SMB registers)
441 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
446 quirk_vt82c586_acpi(dev
);
448 pci_read_config_word(dev
, 0x70, &hm
);
449 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
450 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c868 HW-mon");
452 pci_read_config_dword(dev
, 0x90, &smb
);
453 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
454 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c868 SMB");
456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
459 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
460 * 0x88 (128 bytes of power management registers)
461 * 0xd0 (16 bytes of SMB registers)
463 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
467 pci_read_config_word(dev
, 0x88, &pm
);
468 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
469 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
471 pci_read_config_word(dev
, 0xd0, &smb
);
472 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
473 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
478 #ifdef CONFIG_X86_IO_APIC
480 #include <asm/io_apic.h>
483 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
484 * devices to the external APIC.
486 * TODO: When we have device-specific interrupt routers,
487 * this code will go away from quirks.
489 static void __devinit
quirk_via_ioapic(struct pci_dev
*dev
)
494 tmp
= 0; /* nothing routed to external APIC */
496 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
498 printk(KERN_INFO
"PCI: %sbling Via external APIC routing\n",
499 tmp
== 0 ? "Disa" : "Ena");
501 /* Offset 0x58: External APIC IRQ output control */
502 pci_write_config_byte (dev
, 0x58, tmp
);
504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
507 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
508 * This leads to doubled level interrupt rates.
509 * Set this bit to get rid of cycle wastage.
510 * Otherwise uncritical.
512 static void __devinit
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
515 #define BYPASS_APIC_DEASSERT 8
517 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
518 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
519 printk(KERN_INFO
"PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
520 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
526 * The AMD io apic can hang the box when an apic irq is masked.
527 * We check all revs >= B0 (yet not in the pre production!) as the bug
528 * is currently marked NoFix
530 * We have multiple reports of hangs with this chipset that went away with
531 * noapic specified. For the moment we assume its the errata. We may be wrong
532 * of course. However the advice is demonstrably good even if so..
534 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
538 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
540 printk(KERN_WARNING
"I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
541 printk(KERN_WARNING
" : booting with the \"noapic\" option.\n");
544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
546 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
548 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
555 #define AMD8131_revA0 0x01
556 #define AMD8131_revB0 0x11
557 #define AMD8131_MISC 0x40
558 #define AMD8131_NIOAMODE_BIT 0
559 static void __init
quirk_amd_8131_ioapic(struct pci_dev
*dev
)
561 unsigned char revid
, tmp
;
564 printk(KERN_WARNING
"PCI: MSI quirk detected. pci_msi_quirk set.\n");
569 pci_read_config_byte(dev
, PCI_REVISION_ID
, &revid
);
570 if (revid
== AMD8131_revA0
|| revid
== AMD8131_revB0
) {
571 printk(KERN_INFO
"Fixing up AMD8131 IOAPIC mode\n");
572 pci_read_config_byte( dev
, AMD8131_MISC
, &tmp
);
573 tmp
&= ~(1 << AMD8131_NIOAMODE_BIT
);
574 pci_write_config_byte( dev
, AMD8131_MISC
, tmp
);
577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_APIC
, quirk_amd_8131_ioapic
);
579 static void __init
quirk_svw_msi(struct pci_dev
*dev
)
582 printk(KERN_WARNING
"PCI: MSI quirk detected. pci_msi_quirk set.\n");
584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_svw_msi
);
585 #endif /* CONFIG_X86_IO_APIC */
589 * FIXME: it is questionable that quirk_via_acpi
590 * is needed. It shows up as an ISA bridge, and does not
591 * support the PCI_INTERRUPT_LINE register at all. Therefore
592 * it seems like setting the pci_dev's 'irq' to the
593 * value of the ACPI SCI interrupt is only done for convenience.
596 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
599 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
602 pci_read_config_byte(d
, 0x42, &irq
);
604 if (irq
&& (irq
!= 2))
607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
611 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
612 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
613 * when written, it makes an internal connection to the PIC.
614 * For these devices, this register is defined to be 4 bits wide.
615 * Normally this is fine. However for IO-APIC motherboards, or
616 * non-x86 architectures (yes Via exists on PPC among other places),
617 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
618 * interrupts delivered properly.
620 static void quirk_via_irq(struct pci_dev
*dev
)
624 new_irq
= dev
->irq
& 0xf;
625 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
626 if (new_irq
!= irq
) {
627 printk(KERN_INFO
"PCI: Via IRQ fixup for %s, from %d to %d\n",
628 pci_name(dev
), irq
, new_irq
);
629 udelay(15); /* unknown if delay really needed */
630 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
633 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_irq
);
636 * PIIX3 USB: We have to disable USB interrupts that are
637 * hardwired to PIRQD# and may be shared with an
640 * Legacy Support Register (LEGSUP):
641 * bit13: USB PIRQ Enable (USBPIRQDEN),
642 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
644 * We mask out all r/wc bits, too.
646 static void __devinit
quirk_piix3_usb(struct pci_dev
*dev
)
650 pci_read_config_word(dev
, 0xc0, &legsup
);
652 pci_write_config_word(dev
, 0xc0, legsup
);
654 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_2
, quirk_piix3_usb
);
655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_2
, quirk_piix3_usb
);
658 * VIA VT82C598 has its device ID settable and many BIOSes
659 * set it to the ID of VT82C597 for backward compatibility.
660 * We need to switch it off to be able to recognize the real
663 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
665 pci_write_config_byte(dev
, 0xfc, 0);
666 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
671 * CardBus controllers have a legacy base address that enables them
672 * to respond as i82365 pcmcia controllers. We don't want them to
673 * do this even if the Linux CardBus driver is not loaded, because
674 * the Linux i82365 driver does not (and should not) handle CardBus.
676 static void __devinit
quirk_cardbus_legacy(struct pci_dev
*dev
)
678 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
680 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
682 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
685 * Following the PCI ordering rules is optional on the AMD762. I'm not
686 * sure what the designers were smoking but let's not inhale...
688 * To be fair to AMD, it follows the spec by default, its BIOS people
691 static void __devinit
quirk_amd_ordering(struct pci_dev
*dev
)
694 pci_read_config_dword(dev
, 0x4C, &pcic
);
697 printk(KERN_WARNING
"BIOS failed to enable PCI standards compliance, fixing this error.\n");
698 pci_write_config_dword(dev
, 0x4C, pcic
);
699 pci_read_config_dword(dev
, 0x84, &pcic
);
700 pcic
|= (1<<23); /* Required in this mode */
701 pci_write_config_dword(dev
, 0x84, pcic
);
704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
707 * DreamWorks provided workaround for Dunord I-3000 problem
709 * This card decodes and responds to addresses not apparently
710 * assigned to it. We force a larger allocation to ensure that
711 * nothing gets put too close to it.
713 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
715 struct resource
*r
= &dev
->resource
[1];
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
722 * i82380FB mobile docking controller: its PCI-to-PCI bridge
723 * is subtractive decoding (transparent), and does indicate this
724 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
727 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
729 dev
->transparent
= 1;
731 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
732 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
735 * Common misconfiguration of the MediaGX/Geode PCI master that will
736 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
737 * datasheets found at http://www.national.com/ds/GX for info on what
738 * these bits do. <christer@weinigel.se>
740 static void __init
quirk_mediagx_master(struct pci_dev
*dev
)
743 pci_read_config_byte(dev
, 0x41, ®
);
746 printk(KERN_INFO
"PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
747 pci_write_config_byte(dev
, 0x41, reg
);
750 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
753 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
754 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
755 * secondary channels respectively). If the device reports Compatible mode
756 * but does use BAR0-3 for address decoding, we assume that firmware has
757 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
758 * Exceptions (if they exist) must be handled in chip/architecture specific
761 * Note: for non x86 people. You may need an arch specific quirk to handle
762 * moving IDE devices to native mode as well. Some plug in card devices power
763 * up in compatible mode and assume the BIOS will adjust them.
765 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
766 * we do now ? We don't want is pci_enable_device to come along
767 * and assign new resources. Both approaches work for that.
769 static void __devinit
quirk_ide_bases(struct pci_dev
*dev
)
771 struct resource
*res
;
772 int first_bar
= 2, last_bar
= 0;
774 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
777 res
= &dev
->resource
[0];
779 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
780 if (!(dev
->class & 1) && (res
[0].flags
|| res
[1].flags
)) {
781 res
[0].start
= res
[0].end
= res
[0].flags
= 0;
782 res
[1].start
= res
[1].end
= res
[1].flags
= 0;
787 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
788 if (!(dev
->class & 4) && (res
[2].flags
|| res
[3].flags
)) {
789 res
[2].start
= res
[2].end
= res
[2].flags
= 0;
790 res
[3].start
= res
[3].end
= res
[3].flags
= 0;
797 printk(KERN_INFO
"PCI: Ignoring BAR%d-%d of IDE controller %s\n",
798 first_bar
, last_bar
, pci_name(dev
));
800 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, quirk_ide_bases
);
803 * Ensure C0 rev restreaming is off. This is normally done by
804 * the BIOS but in the odd case it is not the results are corruption
805 * hence the presence of a Linux check
807 static void __init
quirk_disable_pxb(struct pci_dev
*pdev
)
812 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
813 if (rev
!= 0x04) /* Only C0 requires this */
815 pci_read_config_word(pdev
, 0x40, &config
);
816 if (config
& (1<<6)) {
818 pci_write_config_word(pdev
, 0x40, config
);
819 printk(KERN_INFO
"PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
826 * Serverworks CSB5 IDE does not fully support native mode
828 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
831 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
835 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
836 /* need to re-assign BARs for compat mode */
837 quirk_ide_bases(pdev
);
840 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
843 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
845 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
849 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
851 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
852 printk(KERN_INFO
"PCI: IDE mode mismatch; forcing legacy mode\n");
855 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
856 /* need to re-assign BARs for compat mode */
857 quirk_ide_bases(pdev
);
860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
862 /* This was originally an Alpha specific thing, but it really fits here.
863 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
865 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
867 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
872 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
873 * is not activated. The myth is that Asus said that they do not want the
874 * users to be irritated by just another PCI Device in the Win98 device
875 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
876 * package 2.7.0 for details)
878 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
879 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
880 * becomes necessary to do this tweak in two steps -- I've chosen the Host
883 static int __initdata asus_hides_smbus
= 0;
885 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
887 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
888 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
889 switch(dev
->subsystem_device
) {
890 case 0x8025: /* P4B-LX */
891 case 0x8070: /* P4B */
892 case 0x8088: /* P4B533 */
893 case 0x1626: /* L3C notebook */
894 asus_hides_smbus
= 1;
896 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
897 switch(dev
->subsystem_device
) {
898 case 0x80b1: /* P4GE-V */
899 case 0x80b2: /* P4PE */
900 case 0x8093: /* P4B533-V */
901 asus_hides_smbus
= 1;
903 if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
904 switch(dev
->subsystem_device
) {
905 case 0x8030: /* P4T533 */
906 asus_hides_smbus
= 1;
908 if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
909 switch (dev
->subsystem_device
) {
910 case 0x8070: /* P4G8X Deluxe */
911 asus_hides_smbus
= 1;
913 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
914 switch (dev
->subsystem_device
) {
915 case 0x1751: /* M2N notebook */
916 case 0x1821: /* M5N notebook */
917 asus_hides_smbus
= 1;
919 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
920 switch (dev
->subsystem_device
) {
921 case 0x184b: /* W1N notebook */
922 case 0x186a: /* M6Ne notebook */
923 asus_hides_smbus
= 1;
925 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
926 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
927 switch(dev
->subsystem_device
) {
928 case 0x088C: /* HP Compaq nc8000 */
929 case 0x0890: /* HP Compaq nc6000 */
930 asus_hides_smbus
= 1;
932 if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
933 switch (dev
->subsystem_device
) {
934 case 0x12bc: /* HP D330L */
935 asus_hides_smbus
= 1;
937 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_TOSHIBA
)) {
938 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
939 switch(dev
->subsystem_device
) {
940 case 0x0001: /* Toshiba Satellite A40 */
941 asus_hides_smbus
= 1;
943 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
944 switch(dev
->subsystem_device
) {
945 case 0x0001: /* Toshiba Tecra M2 */
946 asus_hides_smbus
= 1;
948 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
949 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
950 switch(dev
->subsystem_device
) {
951 case 0xC00C: /* Samsung P35 notebook */
952 asus_hides_smbus
= 1;
954 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
955 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
956 switch(dev
->subsystem_device
) {
957 case 0x0058: /* Compaq Evo N620c */
958 asus_hides_smbus
= 1;
962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
964 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
966 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
970 static void __init
asus_hides_smbus_lpc(struct pci_dev
*dev
)
974 if (likely(!asus_hides_smbus
))
977 pci_read_config_word(dev
, 0xF2, &val
);
979 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
980 pci_read_config_word(dev
, 0xF2, &val
);
982 printk(KERN_INFO
"PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
984 printk(KERN_INFO
"PCI: Enabled i801 SMBus device\n");
987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
994 * SiS 96x south bridge: BIOS typically hides SMBus device...
996 static void __init
quirk_sis_96x_smbus(struct pci_dev
*dev
)
999 printk(KERN_INFO
"Enabling SiS 96x SMBus.\n");
1000 pci_read_config_byte(dev
, 0x77, &val
);
1001 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1002 pci_read_config_byte(dev
, 0x77, &val
);
1006 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
1007 #define UHCI_USBCMD 0 /* command register */
1008 #define UHCI_USBSTS 2 /* status register */
1009 #define UHCI_USBINTR 4 /* interrupt register */
1010 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
1011 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
1012 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
1013 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
1014 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
1016 #define OHCI_CONTROL 0x04
1017 #define OHCI_CMDSTATUS 0x08
1018 #define OHCI_INTRSTATUS 0x0c
1019 #define OHCI_INTRENABLE 0x10
1020 #define OHCI_INTRDISABLE 0x14
1021 #define OHCI_OCR (1 << 3) /* ownership change request */
1022 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
1023 #define OHCI_INTR_OC (1 << 30) /* ownership change */
1025 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
1026 #define EHCI_USBCMD 0 /* command register */
1027 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
1028 #define EHCI_USBSTS 4 /* status register */
1029 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
1030 #define EHCI_USBINTR 8 /* interrupt register */
1031 #define EHCI_USBLEGSUP 0 /* legacy support register */
1032 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
1033 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
1034 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
1035 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
1037 int usb_early_handoff __devinitdata
= 0;
1038 static int __init
usb_handoff_early(char *str
)
1040 usb_early_handoff
= 1;
1043 __setup("usb-handoff", usb_handoff_early
);
1045 static void __devinit
quirk_usb_handoff_uhci(struct pci_dev
*pdev
)
1047 unsigned long base
= 0;
1048 int wait_time
, delta
;
1052 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++)
1053 if ((pci_resource_flags(pdev
, i
) & IORESOURCE_IO
)) {
1054 base
= pci_resource_start(pdev
, i
);
1064 sts
= inw(base
+ UHCI_USBSTS
);
1065 val
= inw(base
+ UHCI_USBCMD
);
1066 val
&= ~(u16
)(UHCI_USBCMD_RUN
| UHCI_USBCMD_CONFIGURE
);
1067 outw(val
, base
+ UHCI_USBCMD
);
1070 * wait while it stops if it was running
1072 if ((sts
& UHCI_USBSTS_HALTED
) == 0)
1078 outw(0x1f, base
+ UHCI_USBSTS
);
1081 val
= inw(base
+ UHCI_USBSTS
);
1082 if (val
& UHCI_USBSTS_HALTED
)
1084 } while (wait_time
> 0);
1088 * disable interrupts & legacy support
1090 outw(0, base
+ UHCI_USBINTR
);
1091 outw(0x1f, base
+ UHCI_USBSTS
);
1092 pci_read_config_word(pdev
, UHCI_USBLEGSUP
, &val
);
1094 pci_write_config_word(pdev
, UHCI_USBLEGSUP
, UHCI_USBLEGSUP_DEFAULT
);
1098 static void __devinit
quirk_usb_handoff_ohci(struct pci_dev
*pdev
)
1103 base
= ioremap_nocache(pci_resource_start(pdev
, 0),
1104 pci_resource_len(pdev
, 0));
1105 if (base
== NULL
) return;
1107 if (readl(base
+ OHCI_CONTROL
) & OHCI_CTRL_IR
) {
1108 wait_time
= 500; /* 0.5 seconds */
1109 writel(OHCI_INTR_OC
, base
+ OHCI_INTRENABLE
);
1110 writel(OHCI_OCR
, base
+ OHCI_CMDSTATUS
);
1111 while (wait_time
> 0 &&
1112 readl(base
+ OHCI_CONTROL
) & OHCI_CTRL_IR
) {
1119 * disable interrupts
1121 writel(~(u32
)0, base
+ OHCI_INTRDISABLE
);
1122 writel(~(u32
)0, base
+ OHCI_INTRSTATUS
);
1127 static void __devinit
quirk_usb_disable_ehci(struct pci_dev
*pdev
)
1129 int wait_time
, delta
;
1130 void __iomem
*base
, *op_reg_base
;
1131 u32 hcc_params
, val
, temp
;
1134 base
= ioremap_nocache(pci_resource_start(pdev
, 0),
1135 pci_resource_len(pdev
, 0));
1136 if (base
== NULL
) return;
1138 cap_length
= readb(base
);
1139 op_reg_base
= base
+ cap_length
;
1140 hcc_params
= readl(base
+ EHCI_HCC_PARAMS
);
1141 hcc_params
= (hcc_params
>> 8) & 0xff;
1143 pci_read_config_dword(pdev
,
1144 hcc_params
+ EHCI_USBLEGSUP
,
1146 if (((val
& 0xff) == 1) && (val
& EHCI_USBLEGSUP_BIOS
)) {
1148 * Ok, BIOS is in smm mode, try to hand off...
1150 pci_read_config_dword(pdev
,
1151 hcc_params
+ EHCI_USBLEGCTLSTS
,
1153 pci_write_config_dword(pdev
,
1154 hcc_params
+ EHCI_USBLEGCTLSTS
,
1155 temp
| EHCI_USBLEGCTLSTS_SOOE
);
1156 val
|= EHCI_USBLEGSUP_OS
;
1157 pci_write_config_dword(pdev
,
1158 hcc_params
+ EHCI_USBLEGSUP
,
1165 pci_read_config_dword(pdev
,
1166 hcc_params
+ EHCI_USBLEGSUP
,
1168 } while (wait_time
&& (val
& EHCI_USBLEGSUP_BIOS
));
1171 * well, possibly buggy BIOS...
1173 printk(KERN_WARNING
"EHCI early BIOS handoff "
1174 "failed (BIOS bug ?)\n");
1175 pci_write_config_dword(pdev
,
1176 hcc_params
+ EHCI_USBLEGSUP
,
1178 pci_write_config_dword(pdev
,
1179 hcc_params
+ EHCI_USBLEGCTLSTS
,
1186 * halt EHCI & disable its interrupts in any case
1188 val
= readl(op_reg_base
+ EHCI_USBSTS
);
1189 if ((val
& EHCI_USBSTS_HALTED
) == 0) {
1190 val
= readl(op_reg_base
+ EHCI_USBCMD
);
1191 val
&= ~EHCI_USBCMD_RUN
;
1192 writel(val
, op_reg_base
+ EHCI_USBCMD
);
1197 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
1200 val
= readl(op_reg_base
+ EHCI_USBSTS
);
1201 if ((val
== ~(u32
)0) || (val
& EHCI_USBSTS_HALTED
)) {
1204 } while (wait_time
> 0);
1206 writel(0, op_reg_base
+ EHCI_USBINTR
);
1207 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
1216 static void __devinit
quirk_usb_early_handoff(struct pci_dev
*pdev
)
1218 if (!usb_early_handoff
)
1221 if (pdev
->class == ((PCI_CLASS_SERIAL_USB
<< 8) | 0x00)) { /* UHCI */
1222 quirk_usb_handoff_uhci(pdev
);
1223 } else if (pdev
->class == ((PCI_CLASS_SERIAL_USB
<< 8) | 0x10)) { /* OHCI */
1224 quirk_usb_handoff_ohci(pdev
);
1225 } else if (pdev
->class == ((PCI_CLASS_SERIAL_USB
<< 8) | 0x20)) { /* EHCI */
1226 quirk_usb_disable_ehci(pdev
);
1231 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, quirk_usb_early_handoff
);
1234 * ... This is further complicated by the fact that some SiS96x south
1235 * bridges pretend to be 85C503/5513 instead. In that case see if we
1236 * spotted a compatible north bridge to make sure.
1237 * (pci_find_device doesn't work yet)
1239 * We can also enable the sis96x bit in the discovery register..
1241 static int __devinitdata sis_96x_compatible
= 0;
1243 #define SIS_DETECT_REGISTER 0x40
1245 static void __init
quirk_sis_503(struct pci_dev
*dev
)
1250 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1251 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1252 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1253 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1254 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1258 /* Make people aware that we changed the config.. */
1259 printk(KERN_WARNING
"Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid
, sis_96x_compatible
);
1262 * Ok, it now shows up as a 96x.. The 96x quirks are after
1263 * the 503 quirk in the quirk table, so they'll automatically
1264 * run and enable things like the SMBus device
1266 dev
->device
= devid
;
1269 static void __init
quirk_sis_96x_compatible(struct pci_dev
*dev
)
1271 sis_96x_compatible
= 1;
1273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_645
, quirk_sis_96x_compatible
);
1274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_646
, quirk_sis_96x_compatible
);
1275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_648
, quirk_sis_96x_compatible
);
1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_650
, quirk_sis_96x_compatible
);
1277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_651
, quirk_sis_96x_compatible
);
1278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_735
, quirk_sis_96x_compatible
);
1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1287 #ifdef CONFIG_X86_IO_APIC
1288 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1292 if ((pdev
->class >> 8) != 0xff00)
1295 /* the first BAR is the location of the IO APIC...we must
1296 * not touch this (and it's already covered by the fixmap), so
1297 * forcibly insert it into the resource tree */
1298 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1299 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1301 /* The next five BARs all seem to be rubbish, so just clean
1303 for (i
=1; i
< 6; i
++) {
1304 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1311 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1312 static void __devinit
quirk_intel_ide_combined(struct pci_dev
*pdev
)
1318 * Narrow down to Intel SATA PCI devices.
1320 switch (pdev
->device
) {
1321 /* PCI ids taken from drivers/scsi/ata_piix.c */
1331 case 0x2680: /* ESB2 */
1339 /* we do not handle this PCI device */
1344 * Read combined mode register.
1346 pci_read_config_byte(pdev
, 0x90, &tmp
); /* combined mode reg */
1349 tmp
&= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1350 if (tmp
== 0x4) /* bits 10x */
1351 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1352 else if (tmp
== 0x6) /* bits 11x */
1353 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1355 return; /* not in combined mode */
1357 WARN_ON((ich
!= 6) && (ich
!= 7));
1358 tmp
&= 0x3; /* interesting bits 1:0 */
1360 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1361 else if (tmp
& (1 << 1))
1362 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1364 return; /* not in combined mode */
1368 * Read programming interface register.
1369 * (Tells us if it's legacy or native mode)
1371 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1373 /* if SATA port is in native mode, we're ok. */
1377 /* SATA port is in legacy mode. Reserve port so that
1378 * IDE driver does not attempt to use it. If request_region
1379 * fails, it will be obvious at boot time, so we don't bother
1380 * checking return values.
1382 if (comb
== (1 << 0))
1383 request_region(0x1f0, 8, "libata"); /* port 0 */
1385 request_region(0x170, 8, "libata"); /* port 1 */
1387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_intel_ide_combined
);
1388 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1393 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1403 * It's possible for the MSI to get corrupted if shpc and acpi
1404 * are used together on certain PXH-based systems.
1406 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1408 disable_msi_mode(dev
, pci_find_capability(dev
, PCI_CAP_ID_MSI
),
1412 printk(KERN_WARNING
"PCI: PXH quirk detected, "
1413 "disabling MSI for SHPC device\n");
1415 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1416 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1417 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1418 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1419 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1422 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1424 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1425 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1428 * These Netmos parts are multiport serial devices with optional
1429 * parallel ports. Even when parallel ports are present, they
1430 * are identified as class SERIAL, which means the serial driver
1431 * will claim them. To prevent this, mark them as class OTHER.
1432 * These combo devices should be claimed by parport_serial.
1434 * The subdevice ID is of the form 0x00PS, where <P> is the number
1435 * of parallel ports and <S> is the number of serial ports.
1437 switch (dev
->device
) {
1438 case PCI_DEVICE_ID_NETMOS_9735
:
1439 case PCI_DEVICE_ID_NETMOS_9745
:
1440 case PCI_DEVICE_ID_NETMOS_9835
:
1441 case PCI_DEVICE_ID_NETMOS_9845
:
1442 case PCI_DEVICE_ID_NETMOS_9855
:
1443 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1445 printk(KERN_INFO
"PCI: Netmos %04x (%u parallel, "
1446 "%u serial); changing class SERIAL to OTHER "
1447 "(use parport_serial)\n",
1448 dev
->device
, num_parallel
, num_serial
);
1449 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1450 (dev
->class & 0xff);
1454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1456 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
, struct pci_fixup
*end
)
1459 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
1460 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
1461 pr_debug("PCI: Calling quirk %p for %s\n", f
->hook
, pci_name(dev
));
1468 extern struct pci_fixup __start_pci_fixups_early
[];
1469 extern struct pci_fixup __end_pci_fixups_early
[];
1470 extern struct pci_fixup __start_pci_fixups_header
[];
1471 extern struct pci_fixup __end_pci_fixups_header
[];
1472 extern struct pci_fixup __start_pci_fixups_final
[];
1473 extern struct pci_fixup __end_pci_fixups_final
[];
1474 extern struct pci_fixup __start_pci_fixups_enable
[];
1475 extern struct pci_fixup __end_pci_fixups_enable
[];
1478 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
1480 struct pci_fixup
*start
, *end
;
1483 case pci_fixup_early
:
1484 start
= __start_pci_fixups_early
;
1485 end
= __end_pci_fixups_early
;
1488 case pci_fixup_header
:
1489 start
= __start_pci_fixups_header
;
1490 end
= __end_pci_fixups_header
;
1493 case pci_fixup_final
:
1494 start
= __start_pci_fixups_final
;
1495 end
= __end_pci_fixups_final
;
1498 case pci_fixup_enable
:
1499 start
= __start_pci_fixups_enable
;
1500 end
= __end_pci_fixups_enable
;
1504 /* stupid compiler warning, you would think with an enum... */
1507 pci_do_fixups(dev
, start
, end
);
1510 EXPORT_SYMBOL(pcie_mch_quirk
);
1511 #ifdef CONFIG_HOTPLUG
1512 EXPORT_SYMBOL(pci_fixup_device
);