arch/cris/arch-v32/kernel/time.c

   1 /* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $
   2  *
   3  *  linux/arch/cris/arch-v32/kernel/time.c
   4  *
   5  *  Copyright (C) 2003 Axis Communications AB
   6  *
   7  */
   8
   9 #include <linux/timex.h>
  10 #include <linux/time.h>
  11 #include <linux/jiffies.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/swap.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/threads.h>
  17 #include <asm/types.h>
  18 #include <asm/signal.h>
  19 #include <asm/io.h>
  20 #include <asm/delay.h>
  21 #include <asm/rtc.h>
  22 #include <asm/irq.h>
  23
  24 #include <asm/arch/hwregs/reg_map.h>
  25 #include <asm/arch/hwregs/reg_rdwr.h>
  26 #include <asm/arch/hwregs/timer_defs.h>
  27 #include <asm/arch/hwregs/intr_vect_defs.h>
  28
  29 /* Watchdog defines */
  30 #define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
  31 #define ETRAX_WD_HZ       763 /* watchdog counts at 763 Hz */
  32 #define ETRAX_WD_CNT      ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */
  33
  34 unsigned long timer_regs[NR_CPUS] =
  35 {
  36   regi_timer,
  37 #ifdef CONFIG_SMP
  38   regi_timer2
  39 #endif
  40 };
  41
  42 extern void update_xtime_from_cmos(void);
  43 extern int set_rtc_mmss(unsigned long nowtime);
  44 extern int setup_irq(int, struct irqaction *);
  45 extern int have_rtc;
  46
  47 unsigned long get_ns_in_jiffie(void)
  48 {
  49         reg_timer_r_tmr0_data data;
  50         unsigned long ns;
  51
  52         data = REG_RD(timer, regi_timer, r_tmr0_data);
  53         ns = (TIMER0_DIV - data) * 10;
  54         return ns;
  55 }
  56
  57 unsigned long do_slow_gettimeoffset(void)
  58 {
  59         unsigned long count;
  60         unsigned long usec_count = 0;
  61
  62         static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
  63         static unsigned long jiffies_p = 0;
  64
  65         /*
  66          * cache volatile jiffies temporarily; we have IRQs turned off.
  67          */
  68         unsigned long jiffies_t;
  69
  70         /* The timer interrupt comes from Etrax timer 0. In order to get
  71          * better precision, we check the current value. It might have
  72          * underflowed already though.
  73          */
  74
  75         count = REG_RD(timer, regi_timer, r_tmr0_data);
  76         jiffies_t = jiffies;
  77
  78         /*
  79          * avoiding timer inconsistencies (they are rare, but they happen)...
  80          * there are one problem that must be avoided here:
  81          *  1. the timer counter underflows
  82          */
  83         if( jiffies_t == jiffies_p ) {
  84                 if( count > count_p ) {
  85                         /* Timer wrapped, use new count and prescale
  86                          * increase the time corresponding to one jiffie
  87                          */
  88                         usec_count = 1000000/HZ;
  89                 }
  90         } else
  91                 jiffies_p = jiffies_t;
  92         count_p = count;
  93         /* Convert timer value to usec */
  94         /* 100 MHz timer, divide by 100 to get usec */
  95         usec_count +=  (TIMER0_DIV - count) / 100;
  96         return usec_count;
  97 }
  98
  99 /* From timer MDS describing the hardware watchdog:
 100  * 4.3.1 Watchdog Operation
 101  * The watchdog timer is an 8-bit timer with a configurable start value.
 102  * Once started the watchdog counts downwards with a frequency of 763 Hz
 103  * (100/131072 MHz). When the watchdog counts down to 1, it generates an
 104  * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
 105  * chip.
 106  */
 107 /* This gives us 1.3 ms to do something useful when the NMI comes */
 108
 109 /* right now, starting the watchdog is the same as resetting it */
 110 #define start_watchdog reset_watchdog
 111
 112 #if defined(CONFIG_ETRAX_WATCHDOG)
 113 static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 114 #endif
 115
 116 /* number of pages to consider "out of memory". it is normal that the memory
 117  * is used though, so put this really low.
 118  */
 119
 120 #define WATCHDOG_MIN_FREE_PAGES 8
 121
 122 void
 123 reset_watchdog(void)
 124 {
 125 #if defined(CONFIG_ETRAX_WATCHDOG)
 126         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 127
 128         /* only keep watchdog happy as long as we have memory left! */
 129         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 130                 /* reset the watchdog with the inverse of the old key */
 131                 watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
 132                 wd_ctrl.cnt = ETRAX_WD_CNT;
 133                 wd_ctrl.cmd = regk_timer_start;
 134                 wd_ctrl.key = watchdog_key;
 135                 REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
 136         }
 137 #endif
 138 }
 139
 140 /* stop the watchdog - we still need the correct key */
 141
 142 void
 143 stop_watchdog(void)
 144 {
 145 #if defined(CONFIG_ETRAX_WATCHDOG)
 146         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 147         watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
 148         wd_ctrl.cnt = ETRAX_WD_CNT;
 149         wd_ctrl.cmd = regk_timer_stop;
 150         wd_ctrl.key = watchdog_key;
 151         REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
 152 #endif
 153 }
 154
 155 extern void show_registers(struct pt_regs *regs);
 156
 157 void
 158 handle_watchdog_bite(struct pt_regs* regs)
 159 {
 160 #if defined(CONFIG_ETRAX_WATCHDOG)
 161         extern int cause_of_death;
 162
 163         raw_printk("Watchdog bite\n");
 164
 165         /* Check if forced restart or unexpected watchdog */
 166         if (cause_of_death == 0xbedead) {
 167                 while(1);
 168         }
 169
 170         /* Unexpected watchdog, stop the watchdog and dump registers*/
 171         stop_watchdog();
 172         raw_printk("Oops: bitten by watchdog\n");
 173         show_registers(regs);
 174 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
 175         reset_watchdog();
 176 #endif
 177         while(1) /* nothing */;
 178 #endif
 179 }
 180
 181 /* last time the cmos clock got updated */
 182 static long last_rtc_update = 0;
 183
 184 /*
 185  * timer_interrupt() needs to keep up the real-time clock,
 186  * as well as call the "do_timer()" routine every clocktick
 187  */
 188
 189 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
 190
 191 extern void cris_do_profile(struct pt_regs *regs);
 192
 193 static inline irqreturn_t
 194 timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 195 {
 196         int cpu = smp_processor_id();
 197         reg_timer_r_masked_intr masked_intr;
 198         reg_timer_rw_ack_intr ack_intr = { 0 };
 199
 200         /* Check if the timer interrupt is for us (a tmr0 int) */
 201         masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
 202         if (!masked_intr.tmr0)
 203                 return IRQ_NONE;
 204
 205         /* acknowledge the timer irq */
 206         ack_intr.tmr0 = 1;
 207         REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
 208
 209         /* reset watchdog otherwise it resets us! */
 210         reset_watchdog();
 211
 212         /* Update statistics. */
 213         update_process_times(user_mode(regs));
 214
 215         cris_do_profile(regs); /* Save profiling information */
 216
 217         /* The master CPU is responsible for the time keeping. */
 218         if (cpu != 0)
 219                 return IRQ_HANDLED;
 220
 221         /* call the real timer interrupt handler */
 222         do_timer(1);
 223
 224         /*
 225          * If we have an externally synchronized Linux clock, then update
 226          * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 227          * called as close as possible to 500 ms before the new second starts.
 228          *
 229          * The division here is not time critical since it will run once in
 230          * 11 minutes
 231          */
 232         if ((time_status & STA_UNSYNC) == 0 &&
 233             xtime.tv_sec > last_rtc_update + 660 &&
 234             (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
 235             (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
 236                 if (set_rtc_mmss(xtime.tv_sec) == 0)
 237                         last_rtc_update = xtime.tv_sec;
 238                 else
 239                         last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
 240         }
 241         return IRQ_HANDLED;
 242 }
 243
 244 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 245  * it needs to be IRQF_DISABLED to make the jiffies update work properly
 246  */
 247
 248 static struct irqaction irq_timer  = {
 249         .mask = timer_interrupt,
 250         .flags = IRQF_SHARED | IRQF_DISABLED,
 251         .mask = CPU_MASK_NONE,
 252         .name = "timer"
 253 };
 254
 255 void __init
 256 cris_timer_init(void)
 257 {
 258         int cpu = smp_processor_id();
 259         reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
 260         reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
 261         reg_timer_rw_intr_mask timer_intr_mask;
 262
 263         /* Setup the etrax timers
 264          * Base frequency is 100MHz, divider 1000000 -> 100 HZ
 265          * We use timer0, so timer1 is free.
 266          * The trig timer is used by the fasttimer API if enabled.
 267          */
 268
 269         tmr0_ctrl.op = regk_timer_ld;
 270         tmr0_ctrl.freq = regk_timer_f100;
 271         REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
 272         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
 273         tmr0_ctrl.op = regk_timer_run;
 274         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
 275
 276         /* enable the timer irq */
 277         timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
 278         timer_intr_mask.tmr0 = 1;
 279         REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
 280 }
 281
 282 void __init
 283 time_init(void)
 284 {
 285         reg_intr_vect_rw_mask intr_mask;
 286
 287         /* probe for the RTC and read it if it exists
 288          * Before the RTC can be probed the loops_per_usec variable needs
 289          * to be initialized to make usleep work. A better value for
 290          * loops_per_usec is calculated by the kernel later once the
 291          * clock has started.
 292          */
 293         loops_per_usec = 50;
 294
 295         if(RTC_INIT() < 0) {
 296                 /* no RTC, start at 1980 */
 297                 xtime.tv_sec = 0;
 298                 xtime.tv_nsec = 0;
 299                 have_rtc = 0;
 300         } else {
 301                 /* get the current time */
 302                 have_rtc = 1;
 303                 update_xtime_from_cmos();
 304         }
 305
 306         /*
 307          * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
 308          * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
 309          */
 310         set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
 311
 312         /* Start CPU local timer */
 313         cris_timer_init();
 314
 315         /* enable the timer irq in global config */
 316         intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
 317         intr_mask.timer = 1;
 318         REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
 319
 320         /* now actually register the timer irq handler that calls timer_interrupt() */
 321
 322         setup_irq(TIMER_INTR_VECT, &irq_timer);
 323
 324         /* enable watchdog if we should use one */
 325
 326 #if defined(CONFIG_ETRAX_WATCHDOG)
 327         printk("Enabling watchdog...\n");
 328         start_watchdog();
 329
 330         /* If we use the hardware watchdog, we want to trap it as an NMI
 331            and dump registers before it resets us.  For this to happen, we
 332            must set the "m" NMI enable flag (which once set, is unset only
 333            when an NMI is taken).
 334
 335            The same goes for the external NMI, but that doesn't have any
 336            driver or infrastructure support yet.  */
 337         {
 338           unsigned long flags;
 339           local_save_flags(flags);
 340           flags |= (1<<30); /* NMI M flag is at bit 30 */
 341           local_irq_restore(flags);
 342         }
 343 #endif
 344 }