2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
31 #include <asm/system.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/sstate.h>
50 #include <asm/mdesc.h>
51 #include <asm/cpudata.h>
53 #define MAX_PHYS_ADDRESS (1UL << 42UL)
54 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
55 #define KPTE_BITMAP_BYTES \
56 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
58 unsigned long kern_linear_pte_xor
[2] __read_mostly
;
60 /* A bitmap, one bit for every 256MB of physical memory. If the bit
61 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
62 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
64 unsigned long kpte_linear_bitmap
[KPTE_BITMAP_BYTES
/ sizeof(unsigned long)];
66 #ifndef CONFIG_DEBUG_PAGEALLOC
67 /* A special kernel TSB for 4MB and 256MB linear mappings.
68 * Space is allocated for this right after the trap table
69 * in arch/sparc64/kernel/head.S
71 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
76 static struct linux_prom64_registers pavail
[MAX_BANKS
] __initdata
;
77 static int pavail_ents __initdata
;
79 static int cmp_p64(const void *a
, const void *b
)
81 const struct linux_prom64_registers
*x
= a
, *y
= b
;
83 if (x
->phys_addr
> y
->phys_addr
)
85 if (x
->phys_addr
< y
->phys_addr
)
90 static void __init
read_obp_memory(const char *property
,
91 struct linux_prom64_registers
*regs
,
94 int node
= prom_finddevice("/memory");
95 int prop_size
= prom_getproplen(node
, property
);
98 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
99 if (ents
> MAX_BANKS
) {
100 prom_printf("The machine has more %s property entries than "
101 "this kernel can support (%d).\n",
102 property
, MAX_BANKS
);
106 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
108 prom_printf("Couldn't get %s property from /memory.\n");
112 /* Sanitize what we got from the firmware, by page aligning
115 for (i
= 0; i
< ents
; i
++) {
116 unsigned long base
, size
;
118 base
= regs
[i
].phys_addr
;
119 size
= regs
[i
].reg_size
;
122 if (base
& ~PAGE_MASK
) {
123 unsigned long new_base
= PAGE_ALIGN(base
);
125 size
-= new_base
- base
;
126 if ((long) size
< 0L)
131 /* If it is empty, simply get rid of it.
132 * This simplifies the logic of the other
133 * functions that process these arrays.
135 memmove(®s
[i
], ®s
[i
+ 1],
136 (ents
- i
- 1) * sizeof(regs
[0]));
141 regs
[i
].phys_addr
= base
;
142 regs
[i
].reg_size
= size
;
147 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
151 unsigned long *sparc64_valid_addr_bitmap __read_mostly
;
153 /* Kernel physical address base and size in bytes. */
154 unsigned long kern_base __read_mostly
;
155 unsigned long kern_size __read_mostly
;
157 /* Initial ramdisk setup */
158 extern unsigned long sparc_ramdisk_image64
;
159 extern unsigned int sparc_ramdisk_image
;
160 extern unsigned int sparc_ramdisk_size
;
162 struct page
*mem_map_zero __read_mostly
;
163 EXPORT_SYMBOL(mem_map_zero
);
165 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
167 unsigned long sparc64_kern_pri_context __read_mostly
;
168 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
169 unsigned long sparc64_kern_sec_context __read_mostly
;
171 int num_kernel_image_mappings
;
173 #ifdef CONFIG_DEBUG_DCFLUSH
174 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
176 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
180 inline void flush_dcache_page_impl(struct page
*page
)
182 BUG_ON(tlb_type
== hypervisor
);
183 #ifdef CONFIG_DEBUG_DCFLUSH
184 atomic_inc(&dcpage_flushes
);
187 #ifdef DCACHE_ALIASING_POSSIBLE
188 __flush_dcache_page(page_address(page
),
189 ((tlb_type
== spitfire
) &&
190 page_mapping(page
) != NULL
));
192 if (page_mapping(page
) != NULL
&&
193 tlb_type
== spitfire
)
194 __flush_icache_page(__pa(page_address(page
)));
198 #define PG_dcache_dirty PG_arch_1
199 #define PG_dcache_cpu_shift 32UL
200 #define PG_dcache_cpu_mask \
201 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
203 #define dcache_dirty_cpu(page) \
204 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
206 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
208 unsigned long mask
= this_cpu
;
209 unsigned long non_cpu_bits
;
211 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
212 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
214 __asm__
__volatile__("1:\n\t"
216 "and %%g7, %1, %%g1\n\t"
217 "or %%g1, %0, %%g1\n\t"
218 "casx [%2], %%g7, %%g1\n\t"
220 "membar #StoreLoad | #StoreStore\n\t"
221 "bne,pn %%xcc, 1b\n\t"
224 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
228 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
230 unsigned long mask
= (1UL << PG_dcache_dirty
);
232 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
235 "srlx %%g7, %4, %%g1\n\t"
236 "and %%g1, %3, %%g1\n\t"
238 "bne,pn %%icc, 2f\n\t"
239 " andn %%g7, %1, %%g1\n\t"
240 "casx [%2], %%g7, %%g1\n\t"
242 "membar #StoreLoad | #StoreStore\n\t"
243 "bne,pn %%xcc, 1b\n\t"
247 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
248 "i" (PG_dcache_cpu_mask
),
249 "i" (PG_dcache_cpu_shift
)
253 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
255 unsigned long tsb_addr
= (unsigned long) ent
;
257 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
258 tsb_addr
= __pa(tsb_addr
);
260 __tsb_insert(tsb_addr
, tag
, pte
);
263 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
264 unsigned long _PAGE_SZBITS __read_mostly
;
266 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
268 struct mm_struct
*mm
;
270 unsigned long tag
, flags
;
271 unsigned long tsb_index
, tsb_hash_shift
;
273 if (tlb_type
!= hypervisor
) {
274 unsigned long pfn
= pte_pfn(pte
);
275 unsigned long pg_flags
;
278 if (pfn_valid(pfn
) &&
279 (page
= pfn_to_page(pfn
), page_mapping(page
)) &&
280 ((pg_flags
= page
->flags
) & (1UL << PG_dcache_dirty
))) {
281 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
283 int this_cpu
= get_cpu();
285 /* This is just to optimize away some function calls
289 flush_dcache_page_impl(page
);
291 smp_flush_dcache_page_impl(page
, cpu
);
293 clear_dcache_dirty_cpu(page
, cpu
);
301 tsb_index
= MM_TSB_BASE
;
302 tsb_hash_shift
= PAGE_SHIFT
;
304 spin_lock_irqsave(&mm
->context
.lock
, flags
);
306 #ifdef CONFIG_HUGETLB_PAGE
307 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
) {
308 if ((tlb_type
== hypervisor
&&
309 (pte_val(pte
) & _PAGE_SZALL_4V
) == _PAGE_SZHUGE_4V
) ||
310 (tlb_type
!= hypervisor
&&
311 (pte_val(pte
) & _PAGE_SZALL_4U
) == _PAGE_SZHUGE_4U
)) {
312 tsb_index
= MM_TSB_HUGE
;
313 tsb_hash_shift
= HPAGE_SHIFT
;
318 tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
319 tsb
+= ((address
>> tsb_hash_shift
) &
320 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
321 tag
= (address
>> 22UL);
322 tsb_insert(tsb
, tag
, pte_val(pte
));
324 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
327 void flush_dcache_page(struct page
*page
)
329 struct address_space
*mapping
;
332 if (tlb_type
== hypervisor
)
335 /* Do not bother with the expensive D-cache flush if it
336 * is merely the zero page. The 'bigcore' testcase in GDB
337 * causes this case to run millions of times.
339 if (page
== ZERO_PAGE(0))
342 this_cpu
= get_cpu();
344 mapping
= page_mapping(page
);
345 if (mapping
&& !mapping_mapped(mapping
)) {
346 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
348 int dirty_cpu
= dcache_dirty_cpu(page
);
350 if (dirty_cpu
== this_cpu
)
352 smp_flush_dcache_page_impl(page
, dirty_cpu
);
354 set_dcache_dirty(page
, this_cpu
);
356 /* We could delay the flush for the !page_mapping
357 * case too. But that case is for exec env/arg
358 * pages and those are %99 certainly going to get
359 * faulted into the tlb (and thus flushed) anyways.
361 flush_dcache_page_impl(page
);
368 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
370 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
371 if (tlb_type
== spitfire
) {
374 /* This code only runs on Spitfire cpus so this is
375 * why we can assume _PAGE_PADDR_4U.
377 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
378 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
380 if (kaddr
>= PAGE_OFFSET
)
381 paddr
= kaddr
& mask
;
383 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
384 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
385 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
386 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
388 paddr
= pte_val(*ptep
) & mask
;
390 __flush_icache_page(paddr
);
395 void mmu_info(struct seq_file
*m
)
397 if (tlb_type
== cheetah
)
398 seq_printf(m
, "MMU Type\t: Cheetah\n");
399 else if (tlb_type
== cheetah_plus
)
400 seq_printf(m
, "MMU Type\t: Cheetah+\n");
401 else if (tlb_type
== spitfire
)
402 seq_printf(m
, "MMU Type\t: Spitfire\n");
403 else if (tlb_type
== hypervisor
)
404 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
406 seq_printf(m
, "MMU Type\t: ???\n");
408 #ifdef CONFIG_DEBUG_DCFLUSH
409 seq_printf(m
, "DCPageFlushes\t: %d\n",
410 atomic_read(&dcpage_flushes
));
412 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
413 atomic_read(&dcpage_flushes_xcall
));
414 #endif /* CONFIG_SMP */
415 #endif /* CONFIG_DEBUG_DCFLUSH */
418 struct linux_prom_translation
{
424 /* Exported for kernel TLB miss handling in ktlb.S */
425 struct linux_prom_translation prom_trans
[512] __read_mostly
;
426 unsigned int prom_trans_ents __read_mostly
;
428 /* Exported for SMP bootup purposes. */
429 unsigned long kern_locked_tte_data
;
431 /* The obp translations are saved based on 8k pagesize, since obp can
432 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
433 * HI_OBP_ADDRESS range are handled in ktlb.S.
435 static inline int in_obp_range(unsigned long vaddr
)
437 return (vaddr
>= LOW_OBP_ADDRESS
&&
438 vaddr
< HI_OBP_ADDRESS
);
441 static int cmp_ptrans(const void *a
, const void *b
)
443 const struct linux_prom_translation
*x
= a
, *y
= b
;
445 if (x
->virt
> y
->virt
)
447 if (x
->virt
< y
->virt
)
452 /* Read OBP translations property into 'prom_trans[]'. */
453 static void __init
read_obp_translations(void)
455 int n
, node
, ents
, first
, last
, i
;
457 node
= prom_finddevice("/virtual-memory");
458 n
= prom_getproplen(node
, "translations");
459 if (unlikely(n
== 0 || n
== -1)) {
460 prom_printf("prom_mappings: Couldn't get size.\n");
463 if (unlikely(n
> sizeof(prom_trans
))) {
464 prom_printf("prom_mappings: Size %Zd is too big.\n", n
);
468 if ((n
= prom_getproperty(node
, "translations",
469 (char *)&prom_trans
[0],
470 sizeof(prom_trans
))) == -1) {
471 prom_printf("prom_mappings: Couldn't get property.\n");
475 n
= n
/ sizeof(struct linux_prom_translation
);
479 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
482 /* Now kick out all the non-OBP entries. */
483 for (i
= 0; i
< ents
; i
++) {
484 if (in_obp_range(prom_trans
[i
].virt
))
488 for (; i
< ents
; i
++) {
489 if (!in_obp_range(prom_trans
[i
].virt
))
494 for (i
= 0; i
< (last
- first
); i
++) {
495 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
496 struct linux_prom_translation
*dest
= &prom_trans
[i
];
500 for (; i
< ents
; i
++) {
501 struct linux_prom_translation
*dest
= &prom_trans
[i
];
502 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
505 prom_trans_ents
= last
- first
;
507 if (tlb_type
== spitfire
) {
508 /* Clear diag TTE bits. */
509 for (i
= 0; i
< prom_trans_ents
; i
++)
510 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
514 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
518 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
521 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
522 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
527 static unsigned long kern_large_tte(unsigned long paddr
);
529 static void __init
remap_kernel(void)
531 unsigned long phys_page
, tte_vaddr
, tte_data
;
532 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
534 tte_vaddr
= (unsigned long) KERNBASE
;
535 phys_page
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
536 tte_data
= kern_large_tte(phys_page
);
538 kern_locked_tte_data
= tte_data
;
540 /* Now lock us into the TLBs via Hypervisor or OBP. */
541 if (tlb_type
== hypervisor
) {
542 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
543 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
544 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
545 tte_vaddr
+= 0x400000;
546 tte_data
+= 0x400000;
549 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
550 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
551 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
552 tte_vaddr
+= 0x400000;
553 tte_data
+= 0x400000;
555 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
557 if (tlb_type
== cheetah_plus
) {
558 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
559 CTX_CHEETAH_PLUS_NUC
);
560 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
561 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
566 static void __init
inherit_prom_mappings(void)
568 /* Now fixup OBP's idea about where we really are mapped. */
569 printk("Remapping the kernel... ");
574 void prom_world(int enter
)
577 set_fs((mm_segment_t
) { get_thread_current_ds() });
579 __asm__
__volatile__("flushw");
582 void __flush_dcache_range(unsigned long start
, unsigned long end
)
586 if (tlb_type
== spitfire
) {
589 for (va
= start
; va
< end
; va
+= 32) {
590 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
594 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
597 for (va
= start
; va
< end
; va
+= 32)
598 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
602 "i" (ASI_DCACHE_INVALIDATE
));
606 /* get_new_mmu_context() uses "cache + 1". */
607 DEFINE_SPINLOCK(ctx_alloc_lock
);
608 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
609 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
610 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
611 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
613 /* Caller does TLB context flushing on local CPU if necessary.
614 * The caller also ensures that CTX_VALID(mm->context) is false.
616 * We must be careful about boundary cases so that we never
617 * let the user have CTX 0 (nucleus) or we ever use a CTX
618 * version of zero (and thus NO_CONTEXT would not be caught
619 * by version mis-match tests in mmu_context.h).
621 * Always invoked with interrupts disabled.
623 void get_new_mmu_context(struct mm_struct
*mm
)
625 unsigned long ctx
, new_ctx
;
626 unsigned long orig_pgsz_bits
;
630 spin_lock_irqsave(&ctx_alloc_lock
, flags
);
631 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
632 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
633 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
635 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
636 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
637 if (new_ctx
>= ctx
) {
639 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
642 new_ctx
= CTX_FIRST_VERSION
;
644 /* Don't call memset, for 16 entries that's just
647 mmu_context_bmap
[0] = 3;
648 mmu_context_bmap
[1] = 0;
649 mmu_context_bmap
[2] = 0;
650 mmu_context_bmap
[3] = 0;
651 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
652 mmu_context_bmap
[i
+ 0] = 0;
653 mmu_context_bmap
[i
+ 1] = 0;
654 mmu_context_bmap
[i
+ 2] = 0;
655 mmu_context_bmap
[i
+ 3] = 0;
661 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
662 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
664 tlb_context_cache
= new_ctx
;
665 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
666 spin_unlock_irqrestore(&ctx_alloc_lock
, flags
);
668 if (unlikely(new_version
))
669 smp_new_mmu_context_version();
672 static int numa_enabled
= 1;
673 static int numa_debug
;
675 static int __init
early_numa(char *p
)
680 if (strstr(p
, "off"))
683 if (strstr(p
, "debug"))
688 early_param("numa", early_numa
);
690 #define numadbg(f, a...) \
691 do { if (numa_debug) \
692 printk(KERN_INFO f, ## a); \
695 static void __init
find_ramdisk(unsigned long phys_base
)
697 #ifdef CONFIG_BLK_DEV_INITRD
698 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
699 unsigned long ramdisk_image
;
701 /* Older versions of the bootloader only supported a
702 * 32-bit physical address for the ramdisk image
703 * location, stored at sparc_ramdisk_image. Newer
704 * SILO versions set sparc_ramdisk_image to zero and
705 * provide a full 64-bit physical address at
706 * sparc_ramdisk_image64.
708 ramdisk_image
= sparc_ramdisk_image
;
710 ramdisk_image
= sparc_ramdisk_image64
;
712 /* Another bootloader quirk. The bootloader normalizes
713 * the physical address to KERNBASE, so we have to
714 * factor that back out and add in the lowest valid
715 * physical page address to get the true physical address.
717 ramdisk_image
-= KERNBASE
;
718 ramdisk_image
+= phys_base
;
720 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
721 ramdisk_image
, sparc_ramdisk_size
);
723 initrd_start
= ramdisk_image
;
724 initrd_end
= ramdisk_image
+ sparc_ramdisk_size
;
726 lmb_reserve(initrd_start
, sparc_ramdisk_size
);
728 initrd_start
+= PAGE_OFFSET
;
729 initrd_end
+= PAGE_OFFSET
;
734 struct node_mem_mask
{
737 unsigned long bootmem_paddr
;
739 static struct node_mem_mask node_masks
[MAX_NUMNODES
];
740 static int num_node_masks
;
742 int numa_cpu_lookup_table
[NR_CPUS
];
743 cpumask_t numa_cpumask_lookup_table
[MAX_NUMNODES
];
745 #ifdef CONFIG_NEED_MULTIPLE_NODES
747 struct mdesc_mblock
{
750 u64 offset
; /* RA-to-PA */
752 static struct mdesc_mblock
*mblocks
;
753 static int num_mblocks
;
755 static unsigned long ra_to_pa(unsigned long addr
)
759 for (i
= 0; i
< num_mblocks
; i
++) {
760 struct mdesc_mblock
*m
= &mblocks
[i
];
762 if (addr
>= m
->base
&&
763 addr
< (m
->base
+ m
->size
)) {
771 static int find_node(unsigned long addr
)
775 addr
= ra_to_pa(addr
);
776 for (i
= 0; i
< num_node_masks
; i
++) {
777 struct node_mem_mask
*p
= &node_masks
[i
];
779 if ((addr
& p
->mask
) == p
->val
)
785 static unsigned long nid_range(unsigned long start
, unsigned long end
,
788 *nid
= find_node(start
);
790 while (start
< end
) {
791 int n
= find_node(start
);
801 static unsigned long nid_range(unsigned long start
, unsigned long end
,
809 /* This must be invoked after performing all of the necessary
810 * add_active_range() calls for 'nid'. We need to be able to get
811 * correct data from get_pfn_range_for_nid().
813 static void __init
allocate_node_data(int nid
)
815 unsigned long paddr
, num_pages
, start_pfn
, end_pfn
;
816 struct pglist_data
*p
;
818 #ifdef CONFIG_NEED_MULTIPLE_NODES
819 paddr
= lmb_alloc_nid(sizeof(struct pglist_data
),
820 SMP_CACHE_BYTES
, nid
, nid_range
);
822 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid
);
825 NODE_DATA(nid
) = __va(paddr
);
826 memset(NODE_DATA(nid
), 0, sizeof(struct pglist_data
));
828 NODE_DATA(nid
)->bdata
= &bootmem_node_data
[nid
];
833 get_pfn_range_for_nid(nid
, &start_pfn
, &end_pfn
);
834 p
->node_start_pfn
= start_pfn
;
835 p
->node_spanned_pages
= end_pfn
- start_pfn
;
837 if (p
->node_spanned_pages
) {
838 num_pages
= bootmem_bootmap_pages(p
->node_spanned_pages
);
840 paddr
= lmb_alloc_nid(num_pages
<< PAGE_SHIFT
, PAGE_SIZE
, nid
,
843 prom_printf("Cannot allocate bootmap for nid[%d]\n",
847 node_masks
[nid
].bootmem_paddr
= paddr
;
851 static void init_node_masks_nonnuma(void)
855 numadbg("Initializing tables for non-numa.\n");
857 node_masks
[0].mask
= node_masks
[0].val
= 0;
860 for (i
= 0; i
< NR_CPUS
; i
++)
861 numa_cpu_lookup_table
[i
] = 0;
863 numa_cpumask_lookup_table
[0] = CPU_MASK_ALL
;
866 #ifdef CONFIG_NEED_MULTIPLE_NODES
867 struct pglist_data
*node_data
[MAX_NUMNODES
];
869 EXPORT_SYMBOL(numa_cpu_lookup_table
);
870 EXPORT_SYMBOL(numa_cpumask_lookup_table
);
871 EXPORT_SYMBOL(node_data
);
873 struct mdesc_mlgroup
{
879 static struct mdesc_mlgroup
*mlgroups
;
880 static int num_mlgroups
;
882 static int scan_pio_for_cfg_handle(struct mdesc_handle
*md
, u64 pio
,
887 mdesc_for_each_arc(arc
, md
, pio
, MDESC_ARC_TYPE_FWD
) {
888 u64 target
= mdesc_arc_target(md
, arc
);
891 val
= mdesc_get_property(md
, target
,
893 if (val
&& *val
== cfg_handle
)
899 static int scan_arcs_for_cfg_handle(struct mdesc_handle
*md
, u64 grp
,
902 u64 arc
, candidate
, best_latency
= ~(u64
)0;
904 candidate
= MDESC_NODE_NULL
;
905 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
906 u64 target
= mdesc_arc_target(md
, arc
);
907 const char *name
= mdesc_node_name(md
, target
);
910 if (strcmp(name
, "pio-latency-group"))
913 val
= mdesc_get_property(md
, target
, "latency", NULL
);
917 if (*val
< best_latency
) {
923 if (candidate
== MDESC_NODE_NULL
)
926 return scan_pio_for_cfg_handle(md
, candidate
, cfg_handle
);
929 int of_node_to_nid(struct device_node
*dp
)
931 const struct linux_prom64_registers
*regs
;
932 struct mdesc_handle
*md
;
940 regs
= of_get_property(dp
, "reg", NULL
);
944 cfg_handle
= (regs
->phys_addr
>> 32UL) & 0x0fffffff;
950 mdesc_for_each_node_by_name(md
, grp
, "group") {
951 if (!scan_arcs_for_cfg_handle(md
, grp
, cfg_handle
)) {
963 static void add_node_ranges(void)
967 for (i
= 0; i
< lmb
.memory
.cnt
; i
++) {
968 unsigned long size
= lmb_size_bytes(&lmb
.memory
, i
);
969 unsigned long start
, end
;
971 start
= lmb
.memory
.region
[i
].base
;
973 while (start
< end
) {
974 unsigned long this_end
;
977 this_end
= nid_range(start
, end
, &nid
);
979 numadbg("Adding active range nid[%d] "
980 "start[%lx] end[%lx]\n",
981 nid
, start
, this_end
);
983 add_active_range(nid
,
985 this_end
>> PAGE_SHIFT
);
992 static int __init
grab_mlgroups(struct mdesc_handle
*md
)
998 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group")
1003 paddr
= lmb_alloc(count
* sizeof(struct mdesc_mlgroup
),
1008 mlgroups
= __va(paddr
);
1009 num_mlgroups
= count
;
1012 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group") {
1013 struct mdesc_mlgroup
*m
= &mlgroups
[count
++];
1018 val
= mdesc_get_property(md
, node
, "latency", NULL
);
1020 val
= mdesc_get_property(md
, node
, "address-match", NULL
);
1022 val
= mdesc_get_property(md
, node
, "address-mask", NULL
);
1025 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1026 "match[%lx] mask[%lx]\n",
1027 count
- 1, m
->node
, m
->latency
, m
->match
, m
->mask
);
1033 static int __init
grab_mblocks(struct mdesc_handle
*md
)
1035 unsigned long paddr
;
1039 mdesc_for_each_node_by_name(md
, node
, "mblock")
1044 paddr
= lmb_alloc(count
* sizeof(struct mdesc_mblock
),
1049 mblocks
= __va(paddr
);
1050 num_mblocks
= count
;
1053 mdesc_for_each_node_by_name(md
, node
, "mblock") {
1054 struct mdesc_mblock
*m
= &mblocks
[count
++];
1057 val
= mdesc_get_property(md
, node
, "base", NULL
);
1059 val
= mdesc_get_property(md
, node
, "size", NULL
);
1061 val
= mdesc_get_property(md
, node
,
1062 "address-congruence-offset", NULL
);
1065 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1066 count
- 1, m
->base
, m
->size
, m
->offset
);
1072 static void __init
numa_parse_mdesc_group_cpus(struct mdesc_handle
*md
,
1073 u64 grp
, cpumask_t
*mask
)
1079 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_BACK
) {
1080 u64 target
= mdesc_arc_target(md
, arc
);
1081 const char *name
= mdesc_node_name(md
, target
);
1084 if (strcmp(name
, "cpu"))
1086 id
= mdesc_get_property(md
, target
, "id", NULL
);
1088 cpu_set(*id
, *mask
);
1092 static struct mdesc_mlgroup
* __init
find_mlgroup(u64 node
)
1096 for (i
= 0; i
< num_mlgroups
; i
++) {
1097 struct mdesc_mlgroup
*m
= &mlgroups
[i
];
1098 if (m
->node
== node
)
1104 static int __init
numa_attach_mlgroup(struct mdesc_handle
*md
, u64 grp
,
1107 struct mdesc_mlgroup
*candidate
= NULL
;
1108 u64 arc
, best_latency
= ~(u64
)0;
1109 struct node_mem_mask
*n
;
1111 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1112 u64 target
= mdesc_arc_target(md
, arc
);
1113 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1116 if (m
->latency
< best_latency
) {
1118 best_latency
= m
->latency
;
1124 if (num_node_masks
!= index
) {
1125 printk(KERN_ERR
"Inconsistent NUMA state, "
1126 "index[%d] != num_node_masks[%d]\n",
1127 index
, num_node_masks
);
1131 n
= &node_masks
[num_node_masks
++];
1133 n
->mask
= candidate
->mask
;
1134 n
->val
= candidate
->match
;
1136 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1137 index
, n
->mask
, n
->val
, candidate
->latency
);
1142 static int __init
numa_parse_mdesc_group(struct mdesc_handle
*md
, u64 grp
,
1148 numa_parse_mdesc_group_cpus(md
, grp
, &mask
);
1150 for_each_cpu_mask(cpu
, mask
)
1151 numa_cpu_lookup_table
[cpu
] = index
;
1152 numa_cpumask_lookup_table
[index
] = mask
;
1155 printk(KERN_INFO
"NUMA GROUP[%d]: cpus [ ", index
);
1156 for_each_cpu_mask(cpu
, mask
)
1161 return numa_attach_mlgroup(md
, grp
, index
);
1164 static int __init
numa_parse_mdesc(void)
1166 struct mdesc_handle
*md
= mdesc_grab();
1170 node
= mdesc_node_by_name(md
, MDESC_NODE_NULL
, "latency-groups");
1171 if (node
== MDESC_NODE_NULL
) {
1176 err
= grab_mblocks(md
);
1180 err
= grab_mlgroups(md
);
1185 mdesc_for_each_node_by_name(md
, node
, "group") {
1186 err
= numa_parse_mdesc_group(md
, node
, count
);
1194 for (i
= 0; i
< num_node_masks
; i
++) {
1195 allocate_node_data(i
);
1205 static int __init
numa_parse_sun4u(void)
1210 static int __init
bootmem_init_numa(void)
1214 numadbg("bootmem_init_numa()\n");
1217 if (tlb_type
== hypervisor
)
1218 err
= numa_parse_mdesc();
1220 err
= numa_parse_sun4u();
1227 static int bootmem_init_numa(void)
1234 static void __init
bootmem_init_nonnuma(void)
1236 unsigned long top_of_ram
= lmb_end_of_DRAM();
1237 unsigned long total_ram
= lmb_phys_mem_size();
1240 numadbg("bootmem_init_nonnuma()\n");
1242 printk(KERN_INFO
"Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1243 top_of_ram
, total_ram
);
1244 printk(KERN_INFO
"Memory hole size: %ldMB\n",
1245 (top_of_ram
- total_ram
) >> 20);
1247 init_node_masks_nonnuma();
1249 for (i
= 0; i
< lmb
.memory
.cnt
; i
++) {
1250 unsigned long size
= lmb_size_bytes(&lmb
.memory
, i
);
1251 unsigned long start_pfn
, end_pfn
;
1256 start_pfn
= lmb
.memory
.region
[i
].base
>> PAGE_SHIFT
;
1257 end_pfn
= start_pfn
+ lmb_size_pages(&lmb
.memory
, i
);
1258 add_active_range(0, start_pfn
, end_pfn
);
1261 allocate_node_data(0);
1266 static void __init
reserve_range_in_node(int nid
, unsigned long start
,
1269 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1271 while (start
< end
) {
1272 unsigned long this_end
;
1275 this_end
= nid_range(start
, end
, &n
);
1277 numadbg(" MATCH reserving range [%lx:%lx]\n",
1279 reserve_bootmem_node(NODE_DATA(nid
), start
,
1280 (this_end
- start
), BOOTMEM_DEFAULT
);
1282 numadbg(" NO MATCH, advancing start to %lx\n",
1289 static void __init
trim_reserved_in_node(int nid
)
1293 numadbg(" trim_reserved_in_node(%d)\n", nid
);
1295 for (i
= 0; i
< lmb
.reserved
.cnt
; i
++) {
1296 unsigned long start
= lmb
.reserved
.region
[i
].base
;
1297 unsigned long size
= lmb_size_bytes(&lmb
.reserved
, i
);
1298 unsigned long end
= start
+ size
;
1300 reserve_range_in_node(nid
, start
, end
);
1304 static void __init
bootmem_init_one_node(int nid
)
1306 struct pglist_data
*p
;
1308 numadbg("bootmem_init_one_node(%d)\n", nid
);
1312 if (p
->node_spanned_pages
) {
1313 unsigned long paddr
= node_masks
[nid
].bootmem_paddr
;
1314 unsigned long end_pfn
;
1316 end_pfn
= p
->node_start_pfn
+ p
->node_spanned_pages
;
1318 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1319 nid
, paddr
>> PAGE_SHIFT
, p
->node_start_pfn
, end_pfn
);
1321 init_bootmem_node(p
, paddr
>> PAGE_SHIFT
,
1322 p
->node_start_pfn
, end_pfn
);
1324 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1326 free_bootmem_with_active_regions(nid
, end_pfn
);
1328 trim_reserved_in_node(nid
);
1330 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1332 sparse_memory_present_with_active_regions(nid
);
1336 static unsigned long __init
bootmem_init(unsigned long phys_base
)
1338 unsigned long end_pfn
;
1341 end_pfn
= lmb_end_of_DRAM() >> PAGE_SHIFT
;
1342 max_pfn
= max_low_pfn
= end_pfn
;
1343 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
1345 if (bootmem_init_numa() < 0)
1346 bootmem_init_nonnuma();
1348 /* XXX cpu notifier XXX */
1350 for_each_online_node(nid
)
1351 bootmem_init_one_node(nid
);
1358 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
1359 static int pall_ents __initdata
;
1361 #ifdef CONFIG_DEBUG_PAGEALLOC
1362 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
1363 unsigned long pend
, pgprot_t prot
)
1365 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
1366 unsigned long vend
= PAGE_OFFSET
+ pend
;
1367 unsigned long alloc_bytes
= 0UL;
1369 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
1370 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1375 while (vstart
< vend
) {
1376 unsigned long this_end
, paddr
= __pa(vstart
);
1377 pgd_t
*pgd
= pgd_offset_k(vstart
);
1382 pud
= pud_offset(pgd
, vstart
);
1383 if (pud_none(*pud
)) {
1386 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1387 alloc_bytes
+= PAGE_SIZE
;
1388 pud_populate(&init_mm
, pud
, new);
1391 pmd
= pmd_offset(pud
, vstart
);
1392 if (!pmd_present(*pmd
)) {
1395 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1396 alloc_bytes
+= PAGE_SIZE
;
1397 pmd_populate_kernel(&init_mm
, pmd
, new);
1400 pte
= pte_offset_kernel(pmd
, vstart
);
1401 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1402 if (this_end
> vend
)
1405 while (vstart
< this_end
) {
1406 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1408 vstart
+= PAGE_SIZE
;
1417 extern unsigned int kvmap_linear_patch
[1];
1418 #endif /* CONFIG_DEBUG_PAGEALLOC */
1420 static void __init
mark_kpte_bitmap(unsigned long start
, unsigned long end
)
1422 const unsigned long shift_256MB
= 28;
1423 const unsigned long mask_256MB
= ((1UL << shift_256MB
) - 1UL);
1424 const unsigned long size_256MB
= (1UL << shift_256MB
);
1426 while (start
< end
) {
1429 remains
= end
- start
;
1430 if (remains
< size_256MB
)
1433 if (start
& mask_256MB
) {
1434 start
= (start
+ size_256MB
) & ~mask_256MB
;
1438 while (remains
>= size_256MB
) {
1439 unsigned long index
= start
>> shift_256MB
;
1441 __set_bit(index
, kpte_linear_bitmap
);
1443 start
+= size_256MB
;
1444 remains
-= size_256MB
;
1449 static void __init
init_kpte_bitmap(void)
1453 for (i
= 0; i
< pall_ents
; i
++) {
1454 unsigned long phys_start
, phys_end
;
1456 phys_start
= pall
[i
].phys_addr
;
1457 phys_end
= phys_start
+ pall
[i
].reg_size
;
1459 mark_kpte_bitmap(phys_start
, phys_end
);
1463 static void __init
kernel_physical_mapping_init(void)
1465 #ifdef CONFIG_DEBUG_PAGEALLOC
1466 unsigned long i
, mem_alloced
= 0UL;
1468 for (i
= 0; i
< pall_ents
; i
++) {
1469 unsigned long phys_start
, phys_end
;
1471 phys_start
= pall
[i
].phys_addr
;
1472 phys_end
= phys_start
+ pall
[i
].reg_size
;
1474 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1478 printk("Allocated %ld bytes for kernel page tables.\n",
1481 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1482 flushi(&kvmap_linear_patch
[0]);
1488 #ifdef CONFIG_DEBUG_PAGEALLOC
1489 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1491 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1492 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1494 kernel_map_range(phys_start
, phys_end
,
1495 (enable
? PAGE_KERNEL
: __pgprot(0)));
1497 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1498 PAGE_OFFSET
+ phys_end
);
1500 /* we should perform an IPI and flush all tlbs,
1501 * but that can deadlock->flush only current cpu.
1503 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1504 PAGE_OFFSET
+ phys_end
);
1508 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1512 for (i
= 0; i
< pavail_ents
; i
++) {
1513 if (pavail
[i
].reg_size
>= size
)
1514 return pavail
[i
].phys_addr
;
1520 static void __init
tsb_phys_patch(void)
1522 struct tsb_ldquad_phys_patch_entry
*pquad
;
1523 struct tsb_phys_patch_entry
*p
;
1525 pquad
= &__tsb_ldquad_phys_patch
;
1526 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1527 unsigned long addr
= pquad
->addr
;
1529 if (tlb_type
== hypervisor
)
1530 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1532 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1534 __asm__
__volatile__("flush %0"
1541 p
= &__tsb_phys_patch
;
1542 while (p
< &__tsb_phys_patch_end
) {
1543 unsigned long addr
= p
->addr
;
1545 *(unsigned int *) addr
= p
->insn
;
1547 __asm__
__volatile__("flush %0"
1555 /* Don't mark as init, we give this to the Hypervisor. */
1556 #ifndef CONFIG_DEBUG_PAGEALLOC
1557 #define NUM_KTSB_DESCR 2
1559 #define NUM_KTSB_DESCR 1
1561 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1562 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
1564 static void __init
sun4v_ktsb_init(void)
1566 unsigned long ktsb_pa
;
1568 /* First KTSB for PAGE_SIZE mappings. */
1569 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1571 switch (PAGE_SIZE
) {
1574 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1575 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1579 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1580 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1584 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1585 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1588 case 4 * 1024 * 1024:
1589 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1590 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1594 ktsb_descr
[0].assoc
= 1;
1595 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1596 ktsb_descr
[0].ctx_idx
= 0;
1597 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1598 ktsb_descr
[0].resv
= 0;
1600 #ifndef CONFIG_DEBUG_PAGEALLOC
1601 /* Second KTSB for 4MB/256MB mappings. */
1602 ktsb_pa
= (kern_base
+
1603 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1605 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1606 ktsb_descr
[1].pgsz_mask
= (HV_PGSZ_MASK_4MB
|
1607 HV_PGSZ_MASK_256MB
);
1608 ktsb_descr
[1].assoc
= 1;
1609 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1610 ktsb_descr
[1].ctx_idx
= 0;
1611 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1612 ktsb_descr
[1].resv
= 0;
1616 void __cpuinit
sun4v_ktsb_register(void)
1618 unsigned long pa
, ret
;
1620 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1622 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
1624 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1625 "errors with %lx\n", pa
, ret
);
1630 /* paging_init() sets up the page tables */
1632 extern void central_probe(void);
1634 static unsigned long last_valid_pfn
;
1635 pgd_t swapper_pg_dir
[2048];
1637 static void sun4u_pgprot_init(void);
1638 static void sun4v_pgprot_init(void);
1640 /* Dummy function */
1641 void __init
setup_per_cpu_areas(void)
1645 void __init
paging_init(void)
1647 unsigned long end_pfn
, shift
, phys_base
;
1648 unsigned long real_end
, i
;
1650 /* These build time checkes make sure that the dcache_dirty_cpu()
1651 * page->flags usage will work.
1653 * When a page gets marked as dcache-dirty, we store the
1654 * cpu number starting at bit 32 in the page->flags. Also,
1655 * functions like clear_dcache_dirty_cpu use the cpu mask
1656 * in 13-bit signed-immediate instruction fields.
1660 * Page flags must not reach into upper 32 bits that are used
1661 * for the cpu number
1663 BUILD_BUG_ON(NR_PAGEFLAGS
> 32);
1666 * The bit fields placed in the high range must not reach below
1667 * the 32 bit boundary. Otherwise we cannot place the cpu field
1668 * at the 32 bit boundary.
1670 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
1671 ilog2(roundup_pow_of_two(NR_CPUS
)) > 32);
1673 BUILD_BUG_ON(NR_CPUS
> 4096);
1675 kern_base
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
1676 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
1680 /* Invalidate both kernel TSBs. */
1681 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
1682 #ifndef CONFIG_DEBUG_PAGEALLOC
1683 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
1686 if (tlb_type
== hypervisor
)
1687 sun4v_pgprot_init();
1689 sun4u_pgprot_init();
1691 if (tlb_type
== cheetah_plus
||
1692 tlb_type
== hypervisor
)
1695 if (tlb_type
== hypervisor
) {
1696 sun4v_patch_tlb_handlers();
1702 /* Find available physical memory...
1704 * Read it twice in order to work around a bug in openfirmware.
1705 * The call to grab this table itself can cause openfirmware to
1706 * allocate memory, which in turn can take away some space from
1707 * the list of available memory. Reading it twice makes sure
1708 * we really do get the final value.
1710 read_obp_translations();
1711 read_obp_memory("reg", &pall
[0], &pall_ents
);
1712 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1713 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1715 phys_base
= 0xffffffffffffffffUL
;
1716 for (i
= 0; i
< pavail_ents
; i
++) {
1717 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
1718 lmb_add(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
1721 lmb_reserve(kern_base
, kern_size
);
1723 find_ramdisk(phys_base
);
1725 if (cmdline_memory_size
)
1726 lmb_enforce_memory_limit(phys_base
+ cmdline_memory_size
);
1731 set_bit(0, mmu_context_bmap
);
1733 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
1735 real_end
= (unsigned long)_end
;
1736 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << 22);
1737 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1738 num_kernel_image_mappings
);
1740 /* Set kernel pgd to upper alias so physical page computations
1743 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
1745 memset(swapper_low_pmd_dir
, 0, sizeof(swapper_low_pmd_dir
));
1747 /* Now can init the kernel/bad page tables. */
1748 pud_set(pud_offset(&swapper_pg_dir
[0], 0),
1749 swapper_low_pmd_dir
+ (shift
/ sizeof(pgd_t
)));
1751 inherit_prom_mappings();
1755 /* Ok, we can use our TLB miss and window trap handlers safely. */
1760 if (tlb_type
== hypervisor
)
1761 sun4v_ktsb_register();
1763 /* We must setup the per-cpu areas before we pull in the
1764 * PROM and the MDESC. The code there fills in cpu and
1765 * other information into per-cpu data structures.
1767 real_setup_per_cpu_areas();
1769 prom_build_devicetree();
1771 if (tlb_type
== hypervisor
)
1774 /* Setup bootmem... */
1775 last_valid_pfn
= end_pfn
= bootmem_init(phys_base
);
1777 #ifndef CONFIG_NEED_MULTIPLE_NODES
1778 max_mapnr
= last_valid_pfn
;
1780 kernel_physical_mapping_init();
1783 unsigned long max_zone_pfns
[MAX_NR_ZONES
];
1785 memset(max_zone_pfns
, 0, sizeof(max_zone_pfns
));
1787 max_zone_pfns
[ZONE_NORMAL
] = end_pfn
;
1789 free_area_init_nodes(max_zone_pfns
);
1792 printk("Booting Linux...\n");
1798 int __init
page_in_phys_avail(unsigned long paddr
)
1804 for (i
= 0; i
< pavail_ents
; i
++) {
1805 unsigned long start
, end
;
1807 start
= pavail
[i
].phys_addr
;
1808 end
= start
+ pavail
[i
].reg_size
;
1810 if (paddr
>= start
&& paddr
< end
)
1813 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
1815 #ifdef CONFIG_BLK_DEV_INITRD
1816 if (paddr
>= __pa(initrd_start
) &&
1817 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
1824 static struct linux_prom64_registers pavail_rescan
[MAX_BANKS
] __initdata
;
1825 static int pavail_rescan_ents __initdata
;
1827 /* Certain OBP calls, such as fetching "available" properties, can
1828 * claim physical memory. So, along with initializing the valid
1829 * address bitmap, what we do here is refetch the physical available
1830 * memory list again, and make sure it provides at least as much
1831 * memory as 'pavail' does.
1833 static void setup_valid_addr_bitmap_from_pavail(void)
1837 read_obp_memory("available", &pavail_rescan
[0], &pavail_rescan_ents
);
1839 for (i
= 0; i
< pavail_ents
; i
++) {
1840 unsigned long old_start
, old_end
;
1842 old_start
= pavail
[i
].phys_addr
;
1843 old_end
= old_start
+ pavail
[i
].reg_size
;
1844 while (old_start
< old_end
) {
1847 for (n
= 0; n
< pavail_rescan_ents
; n
++) {
1848 unsigned long new_start
, new_end
;
1850 new_start
= pavail_rescan
[n
].phys_addr
;
1851 new_end
= new_start
+
1852 pavail_rescan
[n
].reg_size
;
1854 if (new_start
<= old_start
&&
1855 new_end
>= (old_start
+ PAGE_SIZE
)) {
1856 set_bit(old_start
>> 22,
1857 sparc64_valid_addr_bitmap
);
1862 prom_printf("mem_init: Lost memory in pavail\n");
1863 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1864 pavail
[i
].phys_addr
,
1865 pavail
[i
].reg_size
);
1866 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1867 pavail_rescan
[i
].phys_addr
,
1868 pavail_rescan
[i
].reg_size
);
1869 prom_printf("mem_init: Cannot continue, aborting.\n");
1873 old_start
+= PAGE_SIZE
;
1878 void __init
mem_init(void)
1880 unsigned long codepages
, datapages
, initpages
;
1881 unsigned long addr
, last
;
1884 i
= last_valid_pfn
>> ((22 - PAGE_SHIFT
) + 6);
1886 sparc64_valid_addr_bitmap
= (unsigned long *) alloc_bootmem(i
<< 3);
1887 if (sparc64_valid_addr_bitmap
== NULL
) {
1888 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1891 memset(sparc64_valid_addr_bitmap
, 0, i
<< 3);
1893 addr
= PAGE_OFFSET
+ kern_base
;
1894 last
= PAGE_ALIGN(kern_size
) + addr
;
1895 while (addr
< last
) {
1896 set_bit(__pa(addr
) >> 22, sparc64_valid_addr_bitmap
);
1900 setup_valid_addr_bitmap_from_pavail();
1902 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
1904 #ifdef CONFIG_NEED_MULTIPLE_NODES
1905 for_each_online_node(i
) {
1906 if (NODE_DATA(i
)->node_spanned_pages
!= 0) {
1908 free_all_bootmem_node(NODE_DATA(i
));
1912 totalram_pages
= free_all_bootmem();
1915 /* We subtract one to account for the mem_map_zero page
1918 totalram_pages
-= 1;
1919 num_physpages
= totalram_pages
;
1922 * Set up the zero page, mark it reserved, so that page count
1923 * is not manipulated when freeing the page from user ptes.
1925 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
1926 if (mem_map_zero
== NULL
) {
1927 prom_printf("paging_init: Cannot alloc zero page.\n");
1930 SetPageReserved(mem_map_zero
);
1932 codepages
= (((unsigned long) _etext
) - ((unsigned long) _start
));
1933 codepages
= PAGE_ALIGN(codepages
) >> PAGE_SHIFT
;
1934 datapages
= (((unsigned long) _edata
) - ((unsigned long) _etext
));
1935 datapages
= PAGE_ALIGN(datapages
) >> PAGE_SHIFT
;
1936 initpages
= (((unsigned long) __init_end
) - ((unsigned long) __init_begin
));
1937 initpages
= PAGE_ALIGN(initpages
) >> PAGE_SHIFT
;
1939 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1940 nr_free_pages() << (PAGE_SHIFT
-10),
1941 codepages
<< (PAGE_SHIFT
-10),
1942 datapages
<< (PAGE_SHIFT
-10),
1943 initpages
<< (PAGE_SHIFT
-10),
1944 PAGE_OFFSET
, (last_valid_pfn
<< PAGE_SHIFT
));
1946 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1947 cheetah_ecache_flush_init();
1950 void free_initmem(void)
1952 unsigned long addr
, initend
;
1955 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1957 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
1958 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
1959 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
1964 ((unsigned long) __va(kern_base
)) -
1965 ((unsigned long) KERNBASE
));
1966 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
1967 p
= virt_to_page(page
);
1969 ClearPageReserved(p
);
1977 #ifdef CONFIG_BLK_DEV_INITRD
1978 void free_initrd_mem(unsigned long start
, unsigned long end
)
1981 printk ("Freeing initrd memory: %ldk freed\n", (end
- start
) >> 10);
1982 for (; start
< end
; start
+= PAGE_SIZE
) {
1983 struct page
*p
= virt_to_page(start
);
1985 ClearPageReserved(p
);
1994 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1995 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1996 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1997 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1998 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1999 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2001 pgprot_t PAGE_KERNEL __read_mostly
;
2002 EXPORT_SYMBOL(PAGE_KERNEL
);
2004 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
2005 pgprot_t PAGE_COPY __read_mostly
;
2007 pgprot_t PAGE_SHARED __read_mostly
;
2008 EXPORT_SYMBOL(PAGE_SHARED
);
2010 pgprot_t PAGE_EXEC __read_mostly
;
2011 unsigned long pg_iobits __read_mostly
;
2013 unsigned long _PAGE_IE __read_mostly
;
2014 EXPORT_SYMBOL(_PAGE_IE
);
2016 unsigned long _PAGE_E __read_mostly
;
2017 EXPORT_SYMBOL(_PAGE_E
);
2019 unsigned long _PAGE_CACHE __read_mostly
;
2020 EXPORT_SYMBOL(_PAGE_CACHE
);
2022 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2024 #define VMEMMAP_CHUNK_SHIFT 22
2025 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
2026 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
2027 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2029 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2030 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2031 unsigned long vmemmap_table
[VMEMMAP_SIZE
];
2033 int __meminit
vmemmap_populate(struct page
*start
, unsigned long nr
, int node
)
2035 unsigned long vstart
= (unsigned long) start
;
2036 unsigned long vend
= (unsigned long) (start
+ nr
);
2037 unsigned long phys_start
= (vstart
- VMEMMAP_BASE
);
2038 unsigned long phys_end
= (vend
- VMEMMAP_BASE
);
2039 unsigned long addr
= phys_start
& VMEMMAP_CHUNK_MASK
;
2040 unsigned long end
= VMEMMAP_ALIGN(phys_end
);
2041 unsigned long pte_base
;
2043 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2044 _PAGE_CP_4U
| _PAGE_CV_4U
|
2045 _PAGE_P_4U
| _PAGE_W_4U
);
2046 if (tlb_type
== hypervisor
)
2047 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2048 _PAGE_CP_4V
| _PAGE_CV_4V
|
2049 _PAGE_P_4V
| _PAGE_W_4V
);
2051 for (; addr
< end
; addr
+= VMEMMAP_CHUNK
) {
2052 unsigned long *vmem_pp
=
2053 vmemmap_table
+ (addr
>> VMEMMAP_CHUNK_SHIFT
);
2056 if (!(*vmem_pp
& _PAGE_VALID
)) {
2057 block
= vmemmap_alloc_block(1UL << 22, node
);
2061 *vmem_pp
= pte_base
| __pa(block
);
2063 printk(KERN_INFO
"[%p-%p] page_structs=%lu "
2064 "node=%d entry=%lu/%lu\n", start
, block
, nr
,
2066 addr
>> VMEMMAP_CHUNK_SHIFT
,
2067 VMEMMAP_SIZE
>> VMEMMAP_CHUNK_SHIFT
);
2072 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2074 static void prot_init_common(unsigned long page_none
,
2075 unsigned long page_shared
,
2076 unsigned long page_copy
,
2077 unsigned long page_readonly
,
2078 unsigned long page_exec_bit
)
2080 PAGE_COPY
= __pgprot(page_copy
);
2081 PAGE_SHARED
= __pgprot(page_shared
);
2083 protection_map
[0x0] = __pgprot(page_none
);
2084 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
2085 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
2086 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
2087 protection_map
[0x4] = __pgprot(page_readonly
);
2088 protection_map
[0x5] = __pgprot(page_readonly
);
2089 protection_map
[0x6] = __pgprot(page_copy
);
2090 protection_map
[0x7] = __pgprot(page_copy
);
2091 protection_map
[0x8] = __pgprot(page_none
);
2092 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
2093 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
2094 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
2095 protection_map
[0xc] = __pgprot(page_readonly
);
2096 protection_map
[0xd] = __pgprot(page_readonly
);
2097 protection_map
[0xe] = __pgprot(page_shared
);
2098 protection_map
[0xf] = __pgprot(page_shared
);
2101 static void __init
sun4u_pgprot_init(void)
2103 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2104 unsigned long page_exec_bit
;
2106 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2107 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2108 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2110 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2111 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2112 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2113 _PAGE_EXEC_4U
| _PAGE_L_4U
);
2114 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4U
);
2116 _PAGE_IE
= _PAGE_IE_4U
;
2117 _PAGE_E
= _PAGE_E_4U
;
2118 _PAGE_CACHE
= _PAGE_CACHE_4U
;
2120 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
2121 __ACCESS_BITS_4U
| _PAGE_E_4U
);
2123 #ifdef CONFIG_DEBUG_PAGEALLOC
2124 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4U
) ^
2127 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
2130 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
2131 _PAGE_P_4U
| _PAGE_W_4U
);
2133 /* XXX Should use 256MB on Panther. XXX */
2134 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
2136 _PAGE_SZBITS
= _PAGE_SZBITS_4U
;
2137 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
2138 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
2139 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
2142 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
2143 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2144 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
2145 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2146 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2147 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2148 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2150 page_exec_bit
= _PAGE_EXEC_4U
;
2152 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2156 static void __init
sun4v_pgprot_init(void)
2158 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2159 unsigned long page_exec_bit
;
2161 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
2162 _PAGE_CACHE_4V
| _PAGE_P_4V
|
2163 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
2165 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
2166 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4V
);
2168 _PAGE_IE
= _PAGE_IE_4V
;
2169 _PAGE_E
= _PAGE_E_4V
;
2170 _PAGE_CACHE
= _PAGE_CACHE_4V
;
2172 #ifdef CONFIG_DEBUG_PAGEALLOC
2173 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
2176 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
2179 kern_linear_pte_xor
[0] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
2180 _PAGE_P_4V
| _PAGE_W_4V
);
2182 #ifdef CONFIG_DEBUG_PAGEALLOC
2183 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
2186 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
2189 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
2190 _PAGE_P_4V
| _PAGE_W_4V
);
2192 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
2193 __ACCESS_BITS_4V
| _PAGE_E_4V
);
2195 _PAGE_SZBITS
= _PAGE_SZBITS_4V
;
2196 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
2197 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
2198 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
2199 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
2201 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| _PAGE_CACHE_4V
;
2202 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2203 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
2204 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2205 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2206 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2207 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2209 page_exec_bit
= _PAGE_EXEC_4V
;
2211 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2215 unsigned long pte_sz_bits(unsigned long sz
)
2217 if (tlb_type
== hypervisor
) {
2221 return _PAGE_SZ8K_4V
;
2223 return _PAGE_SZ64K_4V
;
2225 return _PAGE_SZ512K_4V
;
2226 case 4 * 1024 * 1024:
2227 return _PAGE_SZ4MB_4V
;
2233 return _PAGE_SZ8K_4U
;
2235 return _PAGE_SZ64K_4U
;
2237 return _PAGE_SZ512K_4U
;
2238 case 4 * 1024 * 1024:
2239 return _PAGE_SZ4MB_4U
;
2244 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
2248 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
2249 pte_val(pte
) |= (((unsigned long)space
) << 32);
2250 pte_val(pte
) |= pte_sz_bits(page_size
);
2255 static unsigned long kern_large_tte(unsigned long paddr
)
2259 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2260 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
2261 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
2262 if (tlb_type
== hypervisor
)
2263 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2264 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_P_4V
|
2265 _PAGE_EXEC_4V
| _PAGE_W_4V
);
2270 /* If not locked, zap it. */
2271 void __flush_tlb_all(void)
2273 unsigned long pstate
;
2276 __asm__
__volatile__("flushw\n\t"
2277 "rdpr %%pstate, %0\n\t"
2278 "wrpr %0, %1, %%pstate"
2281 if (tlb_type
== hypervisor
) {
2282 sun4v_mmu_demap_all();
2283 } else if (tlb_type
== spitfire
) {
2284 for (i
= 0; i
< 64; i
++) {
2285 /* Spitfire Errata #32 workaround */
2286 /* NOTE: Always runs on spitfire, so no
2287 * cheetah+ page size encodings.
2289 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2293 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2295 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
2296 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2299 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
2300 spitfire_put_dtlb_data(i
, 0x0UL
);
2303 /* Spitfire Errata #32 workaround */
2304 /* NOTE: Always runs on spitfire, so no
2305 * cheetah+ page size encodings.
2307 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2311 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2313 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
2314 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2317 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
2318 spitfire_put_itlb_data(i
, 0x0UL
);
2321 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
2322 cheetah_flush_dtlb_all();
2323 cheetah_flush_itlb_all();
2325 __asm__
__volatile__("wrpr %0, 0, %%pstate"