arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h

   1 /*
   2  * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
   3  */
   4
   5 #ifndef __ASM_ARCH_EP93XX_REGS_H
   6 #define __ASM_ARCH_EP93XX_REGS_H
   7
   8 /*
   9  * EP93xx Physical Memory Map:
  10  *
  11  * The ASDO pin is sampled at system reset to select a synchronous or
  12  * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
  13  * the synchronous boot mode is selected.  When ASDO is "0" (i.e
  14  * pulled-down) the asynchronous boot mode is selected.
  15  *
  16  * In synchronous boot mode nSDCE3 is decoded starting at physical address
  17  * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
  18  * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
  19  * decoded at 0xf0000000.
  20  *
  21  * There is known errata for the EP93xx dealing with External Memory
  22  * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
  23  * Guidelines" for more information.  This document can be found at:
  24  *
  25  *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
  26  */
  27
  28 #define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
  29 #define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
  30 #define EP93XX_CS1_PHYS_BASE            0x10000000
  31 #define EP93XX_CS2_PHYS_BASE            0x20000000
  32 #define EP93XX_CS3_PHYS_BASE            0x30000000
  33 #define EP93XX_PCMCIA_PHYS_BASE         0x40000000
  34 #define EP93XX_CS6_PHYS_BASE            0x60000000
  35 #define EP93XX_CS7_PHYS_BASE            0x70000000
  36 #define EP93XX_SDCE0_PHYS_BASE          0xc0000000
  37 #define EP93XX_SDCE1_PHYS_BASE          0xd0000000
  38 #define EP93XX_SDCE2_PHYS_BASE          0xe0000000
  39 #define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
  40 #define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
  41
  42 /*
  43  * EP93xx linux memory map:
  44  *
  45  * virt         phys            size
  46  * fe800000                     5M              per-platform mappings
  47  * fed00000     80800000        2M              APB
  48  * fef00000     80000000        1M              AHB
  49  */
  50
  51 #define EP93XX_AHB_PHYS_BASE            0x80000000
  52 #define EP93XX_AHB_VIRT_BASE            0xfef00000
  53 #define EP93XX_AHB_SIZE                 0x00100000
  54
  55 #define EP93XX_APB_PHYS_BASE            0x80800000
  56 #define EP93XX_APB_VIRT_BASE            0xfed00000
  57 #define EP93XX_APB_SIZE                 0x00200000
  58
  59
  60 /* AHB peripherals */
  61 #define EP93XX_DMA_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00000000)
  62
  63 #define EP93XX_ETHERNET_BASE            (EP93XX_AHB_VIRT_BASE + 0x00010000)
  64 #define EP93XX_ETHERNET_PHYS_BASE       (EP93XX_AHB_PHYS_BASE + 0x00010000)
  65
  66 #define EP93XX_USB_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00020000)
  67 #define EP93XX_USB_PHYS_BASE            (EP93XX_AHB_PHYS_BASE + 0x00020000)
  68
  69 #define EP93XX_RASTER_BASE              (EP93XX_AHB_VIRT_BASE + 0x00030000)
  70
  71 #define EP93XX_GRAPHICS_ACCEL_BASE      (EP93XX_AHB_VIRT_BASE + 0x00040000)
  72
  73 #define EP93XX_SDRAM_CONTROLLER_BASE    (EP93XX_AHB_VIRT_BASE + 0x00060000)
  74
  75 #define EP93XX_PCMCIA_CONTROLLER_BASE   (EP93XX_AHB_VIRT_BASE + 0x00080000)
  76
  77 #define EP93XX_BOOT_ROM_BASE            (EP93XX_AHB_VIRT_BASE + 0x00090000)
  78
  79 #define EP93XX_IDE_BASE                 (EP93XX_AHB_VIRT_BASE + 0x000a0000)
  80
  81 #define EP93XX_VIC1_BASE                (EP93XX_AHB_VIRT_BASE + 0x000b0000)
  82
  83 #define EP93XX_VIC2_BASE                (EP93XX_AHB_VIRT_BASE + 0x000c0000)
  84
  85
  86 /* APB peripherals */
  87 #define EP93XX_TIMER_BASE               (EP93XX_APB_VIRT_BASE + 0x00010000)
  88 #define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
  89 #define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
  90 #define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
  91 #define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
  92 #define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
  93 #define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
  94 #define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
  95 #define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
  96 #define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
  97 #define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
  98 #define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
  99 #define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
 100 #define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
 101 #define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
 102 #define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
 103
 104 #define EP93XX_I2S_BASE                 (EP93XX_APB_VIRT_BASE + 0x00020000)
 105
 106 #define EP93XX_SECURITY_BASE            (EP93XX_APB_VIRT_BASE + 0x00030000)
 107
 108 #define EP93XX_GPIO_BASE                (EP93XX_APB_VIRT_BASE + 0x00040000)
 109 #define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
 110 #define EP93XX_GPIO_F_INT_TYPE1         EP93XX_GPIO_REG(0x4c)
 111 #define EP93XX_GPIO_F_INT_TYPE2         EP93XX_GPIO_REG(0x50)
 112 #define EP93XX_GPIO_F_INT_ACK           EP93XX_GPIO_REG(0x54)
 113 #define EP93XX_GPIO_F_INT_ENABLE        EP93XX_GPIO_REG(0x58)
 114 #define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
 115 #define EP93XX_GPIO_A_INT_TYPE1         EP93XX_GPIO_REG(0x90)
 116 #define EP93XX_GPIO_A_INT_TYPE2         EP93XX_GPIO_REG(0x94)
 117 #define EP93XX_GPIO_A_INT_ACK           EP93XX_GPIO_REG(0x98)
 118 #define EP93XX_GPIO_A_INT_ENABLE        EP93XX_GPIO_REG(0x9c)
 119 #define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
 120 #define EP93XX_GPIO_B_INT_TYPE1         EP93XX_GPIO_REG(0xac)
 121 #define EP93XX_GPIO_B_INT_TYPE2         EP93XX_GPIO_REG(0xb0)
 122 #define EP93XX_GPIO_B_INT_ACK           EP93XX_GPIO_REG(0xb4)
 123 #define EP93XX_GPIO_B_INT_ENABLE        EP93XX_GPIO_REG(0xb8)
 124 #define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
 125
 126 #define EP93XX_AAC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00080000)
 127
 128 #define EP93XX_SPI_BASE                 (EP93XX_APB_VIRT_BASE + 0x000a0000)
 129
 130 #define EP93XX_IRDA_BASE                (EP93XX_APB_VIRT_BASE + 0x000b0000)
 131
 132 #define EP93XX_UART1_BASE               (EP93XX_APB_VIRT_BASE + 0x000c0000)
 133 #define EP93XX_UART1_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000c0000)
 134
 135 #define EP93XX_UART2_BASE               (EP93XX_APB_VIRT_BASE + 0x000d0000)
 136 #define EP93XX_UART2_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000d0000)
 137
 138 #define EP93XX_UART3_BASE               (EP93XX_APB_VIRT_BASE + 0x000e0000)
 139 #define EP93XX_UART3_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000e0000)
 140
 141 #define EP93XX_KEY_MATRIX_BASE          (EP93XX_APB_VIRT_BASE + 0x000f0000)
 142
 143 #define EP93XX_ADC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00100000)
 144 #define EP93XX_TOUCHSCREEN_BASE         (EP93XX_APB_VIRT_BASE + 0x00100000)
 145
 146 #define EP93XX_PWM_BASE                 (EP93XX_APB_VIRT_BASE + 0x00110000)
 147
 148 #define EP93XX_RTC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00120000)
 149
 150 #define EP93XX_SYSCON_BASE              (EP93XX_APB_VIRT_BASE + 0x00130000)
 151 #define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
 152 #define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
 153 #define EP93XX_SYSCON_CLOCK_CONTROL     EP93XX_SYSCON_REG(0x04)
 154 #define EP93XX_SYSCON_CLOCK_UARTBAUD    0x20000000
 155 #define EP93XX_SYSCON_CLOCK_USH_EN      0x10000000
 156 #define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
 157 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
 158 #define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
 159 #define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
 160 #define EP93XX_SYSCON_DEVICE_CONFIG     EP93XX_SYSCON_REG(0x80)
 161 #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       0x00800000
 162 #define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
 163
 164 #define EP93XX_WATCHDOG_BASE            (EP93XX_APB_VIRT_BASE + 0x00140000)
 165
 166
 167 #endif