arch/m68k/mm/memory.c

   1 /*
   2  *  linux/arch/m68k/mm/memory.c
   3  *
   4  *  Copyright (C) 1995  Hamish Macdonald
   5  */
   6
   7 #include <linux/mm.h>
   8 #include <linux/kernel.h>
   9 #include <linux/string.h>
  10 #include <linux/types.h>
  11 #include <linux/slab.h>
  12 #include <linux/init.h>
  13 #include <linux/pagemap.h>
  14
  15 #include <asm/setup.h>
  16 #include <asm/segment.h>
  17 #include <asm/page.h>
  18 #include <asm/pgalloc.h>
  19 #include <asm/system.h>
  20 #include <asm/traps.h>
  21 #include <asm/machdep.h>
  22
  23
  24 /* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
  25    struct page instead of separately kmalloced struct.  Stolen from
  26    arch/sparc/mm/srmmu.c ... */
  27
  28 typedef struct list_head ptable_desc;
  29 static LIST_HEAD(ptable_list);
  30
  31 #define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
  32 #define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
  33 #define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
  34
  35 #define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
  36
  37 void __init init_pointer_table(unsigned long ptable)
  38 {
  39         ptable_desc *dp;
  40         unsigned long page = ptable & PAGE_MASK;
  41         unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
  42
  43         dp = PD_PTABLE(page);
  44         if (!(PD_MARKBITS(dp) & mask)) {
  45                 PD_MARKBITS(dp) = 0xff;
  46                 list_add(dp, &ptable_list);
  47         }
  48
  49         PD_MARKBITS(dp) &= ~mask;
  50 #ifdef DEBUG
  51         printk("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
  52 #endif
  53
  54         /* unreserve the page so it's possible to free that page */
  55         PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
  56         init_page_count(PD_PAGE(dp));
  57
  58         return;
  59 }
  60
  61 pmd_t *get_pointer_table (void)
  62 {
  63         ptable_desc *dp = ptable_list.next;
  64         unsigned char mask = PD_MARKBITS (dp);
  65         unsigned char tmp;
  66         unsigned int off;
  67
  68         /*
  69          * For a pointer table for a user process address space, a
  70          * table is taken from a page allocated for the purpose.  Each
  71          * page can hold 8 pointer tables.  The page is remapped in
  72          * virtual address space to be noncacheable.
  73          */
  74         if (mask == 0) {
  75                 void *page;
  76                 ptable_desc *new;
  77
  78                 if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
  79                         return NULL;
  80
  81                 flush_tlb_kernel_page(page);
  82                 nocache_page(page);
  83
  84                 new = PD_PTABLE(page);
  85                 PD_MARKBITS(new) = 0xfe;
  86                 list_add_tail(new, dp);
  87
  88                 return (pmd_t *)page;
  89         }
  90
  91         for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
  92                 ;
  93         PD_MARKBITS(dp) = mask & ~tmp;
  94         if (!PD_MARKBITS(dp)) {
  95                 /* move to end of list */
  96                 list_move_tail(dp, &ptable_list);
  97         }
  98         return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
  99 }
 100
 101 int free_pointer_table (pmd_t *ptable)
 102 {
 103         ptable_desc *dp;
 104         unsigned long page = (unsigned long)ptable & PAGE_MASK;
 105         unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
 106
 107         dp = PD_PTABLE(page);
 108         if (PD_MARKBITS (dp) & mask)
 109                 panic ("table already free!");
 110
 111         PD_MARKBITS (dp) |= mask;
 112
 113         if (PD_MARKBITS(dp) == 0xff) {
 114                 /* all tables in page are free, free page */
 115                 list_del(dp);
 116                 cache_page((void *)page);
 117                 free_page (page);
 118                 return 1;
 119         } else if (ptable_list.next != dp) {
 120                 /*
 121                  * move this descriptor to the front of the list, since
 122                  * it has one or more free tables.
 123                  */
 124                 list_move(dp, &ptable_list);
 125         }
 126         return 0;
 127 }
 128
 129 #ifdef DEBUG_INVALID_PTOV
 130 int mm_inv_cnt = 5;
 131 #endif
 132
 133 #ifndef CONFIG_SINGLE_MEMORY_CHUNK
 134 /*
 135  * The following two routines map from a physical address to a kernel
 136  * virtual address and vice versa.
 137  */
 138 unsigned long mm_vtop(unsigned long vaddr)
 139 {
 140         int i=0;
 141         unsigned long voff = (unsigned long)vaddr - PAGE_OFFSET;
 142
 143         do {
 144                 if (voff < m68k_memory[i].size) {
 145 #ifdef DEBUGPV
 146                         printk ("VTOP(%p)=%lx\n", vaddr,
 147                                 m68k_memory[i].addr + voff);
 148 #endif
 149                         return m68k_memory[i].addr + voff;
 150                 }
 151                 voff -= m68k_memory[i].size;
 152         } while (++i < m68k_num_memory);
 153
 154         /* As a special case allow `__pa(high_memory)'.  */
 155         if (voff == 0)
 156                 return m68k_memory[i-1].addr + m68k_memory[i-1].size;
 157
 158         return -1;
 159 }
 160 #endif
 161
 162 #ifndef CONFIG_SINGLE_MEMORY_CHUNK
 163 unsigned long mm_ptov (unsigned long paddr)
 164 {
 165         int i = 0;
 166         unsigned long poff, voff = PAGE_OFFSET;
 167
 168         do {
 169                 poff = paddr - m68k_memory[i].addr;
 170                 if (poff < m68k_memory[i].size) {
 171 #ifdef DEBUGPV
 172                         printk ("PTOV(%lx)=%lx\n", paddr, poff + voff);
 173 #endif
 174                         return poff + voff;
 175                 }
 176                 voff += m68k_memory[i].size;
 177         } while (++i < m68k_num_memory);
 178
 179 #ifdef DEBUG_INVALID_PTOV
 180         if (mm_inv_cnt > 0) {
 181                 mm_inv_cnt--;
 182                 printk("Invalid use of phys_to_virt(0x%lx) at 0x%p!\n",
 183                         paddr, __builtin_return_address(0));
 184         }
 185 #endif
 186         return -1;
 187 }
 188 #endif
 189
 190 /* invalidate page in both caches */
 191 static inline void clear040(unsigned long paddr)
 192 {
 193         asm volatile (
 194                 "nop\n\t"
 195                 ".chip 68040\n\t"
 196                 "cinvp %%bc,(%0)\n\t"
 197                 ".chip 68k"
 198                 : : "a" (paddr));
 199 }
 200
 201 /* invalidate page in i-cache */
 202 static inline void cleari040(unsigned long paddr)
 203 {
 204         asm volatile (
 205                 "nop\n\t"
 206                 ".chip 68040\n\t"
 207                 "cinvp %%ic,(%0)\n\t"
 208                 ".chip 68k"
 209                 : : "a" (paddr));
 210 }
 211
 212 /* push page in both caches */
 213 /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
 214 static inline void push040(unsigned long paddr)
 215 {
 216         asm volatile (
 217                 "nop\n\t"
 218                 ".chip 68040\n\t"
 219                 "cpushp %%bc,(%0)\n\t"
 220                 ".chip 68k"
 221                 : : "a" (paddr));
 222 }
 223
 224 /* push and invalidate page in both caches, must disable ints
 225  * to avoid invalidating valid data */
 226 static inline void pushcl040(unsigned long paddr)
 227 {
 228         unsigned long flags;
 229
 230         local_irq_save(flags);
 231         push040(paddr);
 232         if (CPU_IS_060)
 233                 clear040(paddr);
 234         local_irq_restore(flags);
 235 }
 236
 237 /*
 238  * 040: Hit every page containing an address in the range paddr..paddr+len-1.
 239  * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
 240  * Hit every page until there is a page or less to go. Hit the next page,
 241  * and the one after that if the range hits it.
 242  */
 243 /* ++roman: A little bit more care is required here: The CINVP instruction
 244  * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
 245  * and the end of the region must be treated differently if they are not
 246  * exactly at the beginning or end of a page boundary. Else, maybe too much
 247  * data becomes invalidated and thus lost forever. CPUSHP does what we need:
 248  * it invalidates the page after pushing dirty data to memory. (Thanks to Jes
 249  * for discovering the problem!)
 250  */
 251 /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
 252  * the DPI bit in the CACR; would it cause problems with temporarily changing
 253  * this?). So we have to push first and then additionally to invalidate.
 254  */
 255
 256
 257 /*
 258  * cache_clear() semantics: Clear any cache entries for the area in question,
 259  * without writing back dirty entries first. This is useful if the data will
 260  * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
 261  * _physical_ address.
 262  */
 263
 264 void cache_clear (unsigned long paddr, int len)
 265 {
 266     if (CPU_IS_040_OR_060) {
 267         int tmp;
 268
 269         /*
 270          * We need special treatment for the first page, in case it
 271          * is not page-aligned. Page align the addresses to work
 272          * around bug I17 in the 68060.
 273          */
 274         if ((tmp = -paddr & (PAGE_SIZE - 1))) {
 275             pushcl040(paddr & PAGE_MASK);
 276             if ((len -= tmp) <= 0)
 277                 return;
 278             paddr += tmp;
 279         }
 280         tmp = PAGE_SIZE;
 281         paddr &= PAGE_MASK;
 282         while ((len -= tmp) >= 0) {
 283             clear040(paddr);
 284             paddr += tmp;
 285         }
 286         if ((len += tmp))
 287             /* a page boundary gets crossed at the end */
 288             pushcl040(paddr);
 289     }
 290     else /* 68030 or 68020 */
 291         asm volatile ("movec %/cacr,%/d0\n\t"
 292                       "oriw %0,%/d0\n\t"
 293                       "movec %/d0,%/cacr"
 294                       : : "i" (FLUSH_I_AND_D)
 295                       : "d0");
 296 #ifdef CONFIG_M68K_L2_CACHE
 297     if(mach_l2_flush)
 298         mach_l2_flush(0);
 299 #endif
 300 }
 301
 302
 303 /*
 304  * cache_push() semantics: Write back any dirty cache data in the given area,
 305  * and invalidate the range in the instruction cache. It needs not (but may)
 306  * invalidate those entries also in the data cache. The range is defined by a
 307  * _physical_ address.
 308  */
 309
 310 void cache_push (unsigned long paddr, int len)
 311 {
 312     if (CPU_IS_040_OR_060) {
 313         int tmp = PAGE_SIZE;
 314
 315         /*
 316          * on 68040 or 68060, push cache lines for pages in the range;
 317          * on the '040 this also invalidates the pushed lines, but not on
 318          * the '060!
 319          */
 320         len += paddr & (PAGE_SIZE - 1);
 321
 322         /*
 323          * Work around bug I17 in the 68060 affecting some instruction
 324          * lines not being invalidated properly.
 325          */
 326         paddr &= PAGE_MASK;
 327
 328         do {
 329             push040(paddr);
 330             paddr += tmp;
 331         } while ((len -= tmp) > 0);
 332     }
 333     /*
 334      * 68030/68020 have no writeback cache. On the other hand,
 335      * cache_push is actually a superset of cache_clear (the lines
 336      * get written back and invalidated), so we should make sure
 337      * to perform the corresponding actions. After all, this is getting
 338      * called in places where we've just loaded code, or whatever, so
 339      * flushing the icache is appropriate; flushing the dcache shouldn't
 340      * be required.
 341      */
 342     else /* 68030 or 68020 */
 343         asm volatile ("movec %/cacr,%/d0\n\t"
 344                       "oriw %0,%/d0\n\t"
 345                       "movec %/d0,%/cacr"
 346                       : : "i" (FLUSH_I)
 347                       : "d0");
 348 #ifdef CONFIG_M68K_L2_CACHE
 349     if(mach_l2_flush)
 350         mach_l2_flush(1);
 351 #endif
 352 }
 353
 354 #ifndef CONFIG_SINGLE_MEMORY_CHUNK
 355 int mm_end_of_chunk (unsigned long addr, int len)
 356 {
 357         int i;
 358
 359         for (i = 0; i < m68k_num_memory; i++)
 360                 if (m68k_memory[i].addr + m68k_memory[i].size == addr + len)
 361                         return 1;
 362         return 0;
 363 }
 364 #endif