2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
44 #include <mach_apic.h>
46 int disable_apic_timer __cpuinitdata
;
47 static int apic_calibrate_pmtmr __initdata
;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok
;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
55 * Debug level, exported for io_apic.c
59 static struct resource lapic_resource
= {
61 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
64 static unsigned int calibration_result
;
66 static int lapic_next_event(unsigned long delta
,
67 struct clock_event_device
*evt
);
68 static void lapic_timer_setup(enum clock_event_mode mode
,
69 struct clock_event_device
*evt
);
70 static void lapic_timer_broadcast(cpumask_t mask
);
71 static void apic_pm_activate(void);
73 static struct clock_event_device lapic_clockevent
= {
75 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
76 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
78 .set_mode
= lapic_timer_setup
,
79 .set_next_event
= lapic_next_event
,
80 .broadcast
= lapic_timer_broadcast
,
84 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
86 static unsigned long apic_phys
;
88 unsigned long mp_lapic_addr
;
91 * Get the LAPIC version
93 static inline int lapic_get_version(void)
95 return GET_APIC_VERSION(apic_read(APIC_LVR
));
99 * Check, if the APIC is integrated or a seperate chip
101 static inline int lapic_is_integrated(void)
107 * Check, whether this is a modern or a first generation APIC
109 static int modern_apic(void)
111 /* AMD systems use old APIC versions, so check the CPU */
112 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
113 boot_cpu_data
.x86
>= 0xf)
115 return lapic_get_version() >= 0x14;
118 void apic_wait_icr_idle(void)
120 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
124 u32
safe_apic_wait_icr_idle(void)
131 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
135 } while (timeout
++ < 1000);
141 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
143 void __cpuinit
enable_NMI_through_LVT0(void)
147 /* unmask and set to NMI */
149 apic_write(APIC_LVT0
, v
);
153 * lapic_get_maxlvt - get the maximum number of local vector table entries
155 int lapic_get_maxlvt(void)
157 unsigned int v
, maxlvt
;
159 v
= apic_read(APIC_LVR
);
160 maxlvt
= GET_APIC_MAXLVT(v
);
165 * This function sets up the local APIC timer, with a timeout of
166 * 'clocks' APIC bus clock. During calibration we actually call
167 * this function twice on the boot CPU, once with a bogus timeout
168 * value, second time for real. The other (noncalibrating) CPUs
169 * call this function only once, with the real, calibrated value.
171 * We do reads before writes even if unnecessary, to get around the
172 * P5 APIC double write bug.
175 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
177 unsigned int lvtt_value
, tmp_value
;
179 lvtt_value
= LOCAL_TIMER_VECTOR
;
181 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
183 lvtt_value
|= APIC_LVT_MASKED
;
185 apic_write(APIC_LVTT
, lvtt_value
);
190 tmp_value
= apic_read(APIC_TDCR
);
191 apic_write(APIC_TDCR
, (tmp_value
192 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
196 apic_write(APIC_TMICT
, clocks
);
200 * Setup extended LVT, AMD specific (K8, family 10h)
202 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
203 * MCE interrupts are supported. Thus MCE offset must be set to 0.
206 #define APIC_EILVT_LVTOFF_MCE 0
207 #define APIC_EILVT_LVTOFF_IBS 1
209 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
211 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
212 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
217 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
219 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
220 return APIC_EILVT_LVTOFF_MCE
;
223 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
225 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
226 return APIC_EILVT_LVTOFF_IBS
;
230 * Program the next event, relative to now
232 static int lapic_next_event(unsigned long delta
,
233 struct clock_event_device
*evt
)
235 apic_write(APIC_TMICT
, delta
);
240 * Setup the lapic timer in periodic or oneshot mode
242 static void lapic_timer_setup(enum clock_event_mode mode
,
243 struct clock_event_device
*evt
)
248 /* Lapic used as dummy for broadcast ? */
249 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
252 local_irq_save(flags
);
255 case CLOCK_EVT_MODE_PERIODIC
:
256 case CLOCK_EVT_MODE_ONESHOT
:
257 __setup_APIC_LVTT(calibration_result
,
258 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
260 case CLOCK_EVT_MODE_UNUSED
:
261 case CLOCK_EVT_MODE_SHUTDOWN
:
262 v
= apic_read(APIC_LVTT
);
263 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
264 apic_write(APIC_LVTT
, v
);
266 case CLOCK_EVT_MODE_RESUME
:
267 /* Nothing to do here */
271 local_irq_restore(flags
);
275 * Local APIC timer broadcast function
277 static void lapic_timer_broadcast(cpumask_t mask
)
280 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
285 * Setup the local APIC timer for this CPU. Copy the initilized values
286 * of the boot CPU and register the clock event in the framework.
288 static void setup_APIC_timer(void)
290 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
292 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
293 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
295 clockevents_register_device(levt
);
299 * In this function we calibrate APIC bus clocks to the external
300 * timer. Unfortunately we cannot use jiffies and the timer irq
301 * to calibrate, since some later bootup code depends on getting
302 * the first irq? Ugh.
304 * We want to do the calibration only once since we
305 * want to have local timer irqs syncron. CPUs connected
306 * by the same APIC bus have the very same bus frequency.
307 * And we want to have irqs off anyways, no accidental
311 #define TICK_COUNT 100000000
313 static void __init
calibrate_APIC_clock(void)
315 unsigned apic
, apic_start
;
316 unsigned long tsc
, tsc_start
;
322 * Put whatever arbitrary (but long enough) timeout
323 * value into the APIC clock, we just want to get the
324 * counter running for calibration.
326 * No interrupt enable !
328 __setup_APIC_LVTT(250000000, 0, 0);
330 apic_start
= apic_read(APIC_TMCCT
);
331 #ifdef CONFIG_X86_PM_TIMER
332 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
333 pmtimer_wait(5000); /* 5ms wait */
334 apic
= apic_read(APIC_TMCCT
);
335 result
= (apic_start
- apic
) * 1000L / 5;
342 apic
= apic_read(APIC_TMCCT
);
344 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
345 (apic_start
- apic
) < TICK_COUNT
);
347 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
353 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
355 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
356 result
/ 1000 / 1000, result
/ 1000 % 1000);
358 /* Calculate the scaled math multiplication factor */
359 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
, 32);
360 lapic_clockevent
.max_delta_ns
=
361 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
362 lapic_clockevent
.min_delta_ns
=
363 clockevent_delta2ns(0xF, &lapic_clockevent
);
365 calibration_result
= result
/ HZ
;
369 * Setup the boot APIC
371 * Calibrate and verify the result.
373 void __init
setup_boot_APIC_clock(void)
376 * The local apic timer can be disabled via the kernel commandline.
377 * Register the lapic timer as a dummy clock event source on SMP
378 * systems, so the broadcast mechanism is used. On UP systems simply
381 if (disable_apic_timer
) {
382 printk(KERN_INFO
"Disabling APIC timer\n");
383 /* No broadcast on UP ! */
384 if (num_possible_cpus() > 1) {
385 lapic_clockevent
.mult
= 1;
391 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
392 calibrate_APIC_clock();
395 * Do a sanity check on the APIC calibration result
397 if (calibration_result
< (1000000 / HZ
)) {
399 "APIC frequency too slow, disabling apic timer\n");
400 /* No broadcast on UP ! */
401 if (num_possible_cpus() > 1)
407 * If nmi_watchdog is set to IO_APIC, we need the
408 * PIT/HPET going. Otherwise register lapic as a dummy
411 if (nmi_watchdog
!= NMI_IO_APIC
)
412 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
414 printk(KERN_WARNING
"APIC timer registered as dummy,"
415 " due to nmi_watchdog=1!\n");
421 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
422 * C1E flag only in the secondary CPU, so when we detect the wreckage
423 * we already have enabled the boot CPU local apic timer. Check, if
424 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
425 * set the DUMMY flag again and force the broadcast mode in the
428 void __cpuinit
check_boot_apic_timer_broadcast(void)
430 if (!disable_apic_timer
||
431 (lapic_clockevent
.features
& CLOCK_EVT_FEAT_DUMMY
))
434 printk(KERN_INFO
"AMD C1E detected late. Force timer broadcast.\n");
435 lapic_clockevent
.features
|= CLOCK_EVT_FEAT_DUMMY
;
438 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
439 &boot_cpu_physical_apicid
);
443 void __cpuinit
setup_secondary_APIC_clock(void)
445 check_boot_apic_timer_broadcast();
450 * The guts of the apic timer interrupt
452 static void local_apic_timer_interrupt(void)
454 int cpu
= smp_processor_id();
455 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
458 * Normally we should not be here till LAPIC has been initialized but
459 * in some cases like kdump, its possible that there is a pending LAPIC
460 * timer interrupt from previous kernel's context and is delivered in
461 * new kernel the moment interrupts are enabled.
463 * Interrupts are enabled early and LAPIC is setup much later, hence
464 * its possible that when we get here evt->event_handler is NULL.
465 * Check for event_handler being NULL and discard the interrupt as
468 if (!evt
->event_handler
) {
470 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
472 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
477 * the NMI deadlock-detector uses this.
479 add_pda(apic_timer_irqs
, 1);
481 evt
->event_handler(evt
);
485 * Local APIC timer interrupt. This is the most natural way for doing
486 * local interrupts, but local timer interrupts can be emulated by
487 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
489 * [ if a single-CPU system runs an SMP kernel then we call the local
490 * interrupt as well. Thus we cannot inline the local irq ... ]
492 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
494 struct pt_regs
*old_regs
= set_irq_regs(regs
);
497 * NOTE! We'd better ACK the irq immediately,
498 * because timer handling can be slow.
502 * update_process_times() expects us to have done irq_enter().
503 * Besides, if we don't timer interrupts ignore the global
504 * interrupt lock, which is the WrongThing (tm) to do.
508 local_apic_timer_interrupt();
510 set_irq_regs(old_regs
);
513 int setup_profiling_timer(unsigned int multiplier
)
520 * Local APIC start and shutdown
524 * clear_local_APIC - shutdown the local APIC
526 * This is called, when a CPU is disabled and before rebooting, so the state of
527 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
528 * leftovers during boot.
530 void clear_local_APIC(void)
532 int maxlvt
= lapic_get_maxlvt();
535 /* APIC hasn't been mapped yet */
539 maxlvt
= lapic_get_maxlvt();
541 * Masking an LVT entry can trigger a local APIC error
542 * if the vector is zero. Mask LVTERR first to prevent this.
545 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
546 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
549 * Careful: we have to set masks only first to deassert
550 * any level-triggered sources.
552 v
= apic_read(APIC_LVTT
);
553 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
554 v
= apic_read(APIC_LVT0
);
555 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
556 v
= apic_read(APIC_LVT1
);
557 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
559 v
= apic_read(APIC_LVTPC
);
560 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
564 * Clean APIC state for other OSs:
566 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
567 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
568 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
570 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
572 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
573 apic_write(APIC_ESR
, 0);
578 * disable_local_APIC - clear and disable the local APIC
580 void disable_local_APIC(void)
587 * Disable APIC (implies clearing of registers
590 value
= apic_read(APIC_SPIV
);
591 value
&= ~APIC_SPIV_APIC_ENABLED
;
592 apic_write(APIC_SPIV
, value
);
595 void lapic_shutdown(void)
602 local_irq_save(flags
);
604 disable_local_APIC();
606 local_irq_restore(flags
);
610 * This is to verify that we're looking at a real local APIC.
611 * Check these against your board if the CPUs aren't getting
612 * started for no apparent reason.
614 int __init
verify_local_APIC(void)
616 unsigned int reg0
, reg1
;
619 * The version register is read-only in a real APIC.
621 reg0
= apic_read(APIC_LVR
);
622 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
623 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
624 reg1
= apic_read(APIC_LVR
);
625 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
628 * The two version reads above should print the same
629 * numbers. If the second one is different, then we
630 * poke at a non-APIC.
636 * Check if the version looks reasonably.
638 reg1
= GET_APIC_VERSION(reg0
);
639 if (reg1
== 0x00 || reg1
== 0xff)
641 reg1
= lapic_get_maxlvt();
642 if (reg1
< 0x02 || reg1
== 0xff)
646 * The ID register is read/write in a real APIC.
648 reg0
= apic_read(APIC_ID
);
649 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
650 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
651 reg1
= apic_read(APIC_ID
);
652 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
653 apic_write(APIC_ID
, reg0
);
654 if (reg1
!= (reg0
^ APIC_ID_MASK
))
658 * The next two are just to see if we have sane values.
659 * They're only really relevant if we're in Virtual Wire
660 * compatibility mode, but most boxes are anymore.
662 reg0
= apic_read(APIC_LVT0
);
663 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
664 reg1
= apic_read(APIC_LVT1
);
665 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
671 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
673 void __init
sync_Arb_IDs(void)
675 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
682 apic_wait_icr_idle();
684 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
685 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
690 * An initial setup of the virtual wire mode.
692 void __init
init_bsp_APIC(void)
697 * Don't do the setup now if we have a SMP BIOS as the
698 * through-I/O-APIC virtual wire mode might be active.
700 if (smp_found_config
|| !cpu_has_apic
)
703 value
= apic_read(APIC_LVR
);
706 * Do not trust the local APIC being empty at bootup.
713 value
= apic_read(APIC_SPIV
);
714 value
&= ~APIC_VECTOR_MASK
;
715 value
|= APIC_SPIV_APIC_ENABLED
;
716 value
|= APIC_SPIV_FOCUS_DISABLED
;
717 value
|= SPURIOUS_APIC_VECTOR
;
718 apic_write(APIC_SPIV
, value
);
721 * Set up the virtual wire mode.
723 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
725 apic_write(APIC_LVT1
, value
);
729 * setup_local_APIC - setup the local APIC
731 void __cpuinit
setup_local_APIC(void)
736 value
= apic_read(APIC_LVR
);
738 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
741 * Double-check whether this APIC is really registered.
742 * This is meaningless in clustered apic mode, so we skip it.
744 if (!apic_id_registered())
748 * Intel recommends to set DFR, LDR and TPR before enabling
749 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
750 * document number 292116). So here it goes...
755 * Set Task Priority to 'accept all'. We never change this
758 value
= apic_read(APIC_TASKPRI
);
759 value
&= ~APIC_TPRI_MASK
;
760 apic_write(APIC_TASKPRI
, value
);
763 * After a crash, we no longer service the interrupts and a pending
764 * interrupt from previous kernel might still have ISR bit set.
766 * Most probably by now CPU has serviced that pending interrupt and
767 * it might not have done the ack_APIC_irq() because it thought,
768 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
769 * does not clear the ISR bit and cpu thinks it has already serivced
770 * the interrupt. Hence a vector might get locked. It was noticed
771 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
773 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
774 value
= apic_read(APIC_ISR
+ i
*0x10);
775 for (j
= 31; j
>= 0; j
--) {
782 * Now that we are all set up, enable the APIC
784 value
= apic_read(APIC_SPIV
);
785 value
&= ~APIC_VECTOR_MASK
;
789 value
|= APIC_SPIV_APIC_ENABLED
;
791 /* We always use processor focus */
794 * Set spurious IRQ vector
796 value
|= SPURIOUS_APIC_VECTOR
;
797 apic_write(APIC_SPIV
, value
);
802 * set up through-local-APIC on the BP's LINT0. This is not
803 * strictly necessary in pure symmetric-IO mode, but sometimes
804 * we delegate interrupts to the 8259A.
807 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
809 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
810 if (!smp_processor_id() && !value
) {
811 value
= APIC_DM_EXTINT
;
812 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
815 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
816 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
819 apic_write(APIC_LVT0
, value
);
822 * only the BP should see the LINT1 NMI signal, obviously.
824 if (!smp_processor_id())
827 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
828 apic_write(APIC_LVT1
, value
);
831 void __cpuinit
lapic_setup_esr(void)
833 unsigned maxlvt
= lapic_get_maxlvt();
835 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
837 * spec says clear errors after enabling vector.
840 apic_write(APIC_ESR
, 0);
843 void __cpuinit
end_local_APIC_setup(void)
846 nmi_watchdog_default();
847 setup_apic_nmi_watchdog(NULL
);
852 * Detect and enable local APICs on non-SMP boards.
853 * Original code written by Keir Fraser.
854 * On AMD64 we trust the BIOS - if it says no APIC it is likely
855 * not correctly set up (usually the APIC timer won't work etc.)
857 static int __init
detect_init_APIC(void)
860 printk(KERN_INFO
"No local APIC present\n");
864 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
865 boot_cpu_physical_apicid
= 0;
869 void __init
early_init_lapic_mapping(void)
871 unsigned long apic_phys
;
874 * If no local APIC can be found then go out
875 * : it means there is no mpatable and MADT
877 if (!smp_found_config
)
880 apic_phys
= mp_lapic_addr
;
882 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
883 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
884 APIC_BASE
, apic_phys
);
887 * Fetch the APIC ID of the BSP in case we have a
888 * default configuration (or the MP table is broken).
890 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
894 * init_apic_mappings - initialize APIC mappings
896 void __init
init_apic_mappings(void)
899 * If no local APIC can be found then set up a fake all
900 * zeroes page to simulate the local APIC and another
901 * one for the IO-APIC.
903 if (!smp_found_config
&& detect_init_APIC()) {
904 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
905 apic_phys
= __pa(apic_phys
);
907 apic_phys
= mp_lapic_addr
;
909 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
910 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
911 APIC_BASE
, apic_phys
);
914 * Fetch the APIC ID of the BSP in case we have a
915 * default configuration (or the MP table is broken).
917 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
921 * This initializes the IO-APIC and APIC hardware if this is
924 int __init
APIC_init_uniprocessor(void)
927 printk(KERN_INFO
"Apic disabled\n");
932 printk(KERN_INFO
"Apic disabled by BIOS\n");
938 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
939 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
944 * Now enable IO-APICs, actually call clear_IO_APIC
945 * We need clear_IO_APIC before enabling vector on BP
947 if (!skip_ioapic_setup
&& nr_ioapics
)
950 end_local_APIC_setup();
952 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
956 setup_boot_APIC_clock();
957 check_nmi_watchdog();
962 * Local APIC interrupts
966 * This interrupt should _never_ happen with our APIC/SMP architecture
968 asmlinkage
void smp_spurious_interrupt(void)
974 * Check if this really is a spurious interrupt and ACK it
975 * if it is a vectored one. Just in case...
976 * Spurious interrupts should not be ACKed.
978 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
979 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
982 add_pda(irq_spurious_count
, 1);
987 * This interrupt should never happen with our APIC/SMP architecture
989 asmlinkage
void smp_error_interrupt(void)
995 /* First tickle the hardware, only then report what went on. -- REW */
996 v
= apic_read(APIC_ESR
);
997 apic_write(APIC_ESR
, 0);
998 v1
= apic_read(APIC_ESR
);
1000 atomic_inc(&irq_err_count
);
1002 /* Here is what the APIC error bits mean:
1005 2: Send accept error
1006 3: Receive accept error
1008 5: Send illegal vector
1009 6: Received illegal vector
1010 7: Illegal register address
1012 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1013 smp_processor_id(), v
, v1
);
1017 void disconnect_bsp_APIC(int virt_wire_setup
)
1019 /* Go back to Virtual Wire compatibility mode */
1020 unsigned long value
;
1022 /* For the spurious interrupt use vector F, and enable it */
1023 value
= apic_read(APIC_SPIV
);
1024 value
&= ~APIC_VECTOR_MASK
;
1025 value
|= APIC_SPIV_APIC_ENABLED
;
1027 apic_write(APIC_SPIV
, value
);
1029 if (!virt_wire_setup
) {
1031 * For LVT0 make it edge triggered, active high,
1032 * external and enabled
1034 value
= apic_read(APIC_LVT0
);
1035 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1036 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1037 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1038 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1039 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1040 apic_write(APIC_LVT0
, value
);
1043 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1046 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1047 value
= apic_read(APIC_LVT1
);
1048 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1049 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1050 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1051 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1052 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1053 apic_write(APIC_LVT1
, value
);
1062 /* 'active' is true if the local APIC was enabled by us and
1063 not the BIOS; this signifies that we are also responsible
1064 for disabling it before entering apm/acpi suspend */
1066 /* r/w apic fields */
1067 unsigned int apic_id
;
1068 unsigned int apic_taskpri
;
1069 unsigned int apic_ldr
;
1070 unsigned int apic_dfr
;
1071 unsigned int apic_spiv
;
1072 unsigned int apic_lvtt
;
1073 unsigned int apic_lvtpc
;
1074 unsigned int apic_lvt0
;
1075 unsigned int apic_lvt1
;
1076 unsigned int apic_lvterr
;
1077 unsigned int apic_tmict
;
1078 unsigned int apic_tdcr
;
1079 unsigned int apic_thmr
;
1082 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1084 unsigned long flags
;
1087 if (!apic_pm_state
.active
)
1090 maxlvt
= lapic_get_maxlvt();
1092 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1093 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1094 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1095 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1096 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1097 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1099 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1100 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1101 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1102 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1103 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1104 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1105 #ifdef CONFIG_X86_MCE_INTEL
1107 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1109 local_irq_save(flags
);
1110 disable_local_APIC();
1111 local_irq_restore(flags
);
1115 static int lapic_resume(struct sys_device
*dev
)
1118 unsigned long flags
;
1121 if (!apic_pm_state
.active
)
1124 maxlvt
= lapic_get_maxlvt();
1126 local_irq_save(flags
);
1127 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1128 l
&= ~MSR_IA32_APICBASE_BASE
;
1129 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1130 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1131 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1132 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1133 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1134 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1135 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1136 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1137 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1138 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1139 #ifdef CONFIG_X86_MCE_INTEL
1141 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1144 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1145 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1146 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1147 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1148 apic_write(APIC_ESR
, 0);
1149 apic_read(APIC_ESR
);
1150 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1151 apic_write(APIC_ESR
, 0);
1152 apic_read(APIC_ESR
);
1153 local_irq_restore(flags
);
1157 static struct sysdev_class lapic_sysclass
= {
1159 .resume
= lapic_resume
,
1160 .suspend
= lapic_suspend
,
1163 static struct sys_device device_lapic
= {
1165 .cls
= &lapic_sysclass
,
1168 static void __cpuinit
apic_pm_activate(void)
1170 apic_pm_state
.active
= 1;
1173 static int __init
init_lapic_sysfs(void)
1179 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1181 error
= sysdev_class_register(&lapic_sysclass
);
1183 error
= sysdev_register(&device_lapic
);
1186 device_initcall(init_lapic_sysfs
);
1188 #else /* CONFIG_PM */
1190 static void apic_pm_activate(void) { }
1192 #endif /* CONFIG_PM */
1195 * apic_is_clustered_box() -- Check if we can expect good TSC
1197 * Thus far, the major user of this is IBM's Summit2 series:
1199 * Clustered boxes may have unsynced TSC problems if they are
1200 * multi-chassis. Use available data to take a good guess.
1201 * If in doubt, go HPET.
1203 __cpuinit
int apic_is_clustered_box(void)
1205 int i
, clusters
, zeros
;
1207 u16
*bios_cpu_apicid
;
1208 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1211 * there is not this kind of box with AMD CPU yet.
1212 * Some AMD box with quadcore cpu and 8 sockets apicid
1213 * will be [4, 0x23] or [8, 0x27] could be thought to
1214 * vsmp box still need checking...
1216 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1219 bios_cpu_apicid
= x86_bios_cpu_apicid_early_ptr
;
1220 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1222 for (i
= 0; i
< NR_CPUS
; i
++) {
1223 /* are we being called early in kernel startup? */
1224 if (bios_cpu_apicid
) {
1225 id
= bios_cpu_apicid
[i
];
1227 else if (i
< nr_cpu_ids
) {
1229 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1236 if (id
!= BAD_APICID
)
1237 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1240 /* Problem: Partially populated chassis may not have CPUs in some of
1241 * the APIC clusters they have been allocated. Only present CPUs have
1242 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1243 * Since clusters are allocated sequentially, count zeros only if
1244 * they are bounded by ones.
1248 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1249 if (test_bit(i
, clustermap
)) {
1250 clusters
+= 1 + zeros
;
1256 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1257 * not guaranteed to be synced between boards
1259 if (is_vsmp_box() && clusters
> 1)
1263 * If clusters > 2, then should be multi-chassis.
1264 * May have to revisit this when multi-core + hyperthreaded CPUs come
1265 * out, but AFAIK this will work even for them.
1267 return (clusters
> 2);
1271 * APIC command line parameters
1273 static int __init
apic_set_verbosity(char *str
)
1276 skip_ioapic_setup
= 0;
1280 if (strcmp("debug", str
) == 0)
1281 apic_verbosity
= APIC_DEBUG
;
1282 else if (strcmp("verbose", str
) == 0)
1283 apic_verbosity
= APIC_VERBOSE
;
1285 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1286 " use apic=verbose or apic=debug\n", str
);
1292 early_param("apic", apic_set_verbosity
);
1294 static __init
int setup_disableapic(char *str
)
1297 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1300 early_param("disableapic", setup_disableapic
);
1302 /* same as disableapic, for compatibility */
1303 static __init
int setup_nolapic(char *str
)
1305 return setup_disableapic(str
);
1307 early_param("nolapic", setup_nolapic
);
1309 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1311 local_apic_timer_c2_ok
= 1;
1314 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1316 static __init
int setup_noapictimer(char *str
)
1318 if (str
[0] != ' ' && str
[0] != 0)
1320 disable_apic_timer
= 1;
1323 __setup("noapictimer", setup_noapictimer
);
1325 static __init
int setup_apicpmtimer(char *s
)
1327 apic_calibrate_pmtmr
= 1;
1331 __setup("apicpmtimer", setup_apicpmtimer
);
1333 static int __init
lapic_insert_resource(void)
1338 /* Put local APIC into the resource map. */
1339 lapic_resource
.start
= apic_phys
;
1340 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1341 insert_resource(&iomem_resource
, &lapic_resource
);
1347 * need call insert after e820_reserve_resources()
1348 * that is using request_resource
1350 late_initcall(lapic_insert_resource
);