1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
35 static s32
ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw
*hw
);
36 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
37 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
38 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
39 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
40 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
41 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
43 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
44 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
45 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
46 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
47 static u16
ixgbe_calc_eeprom_checksum(struct ixgbe_hw
*hw
);
49 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
);
50 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
);
51 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
52 static void ixgbe_add_mc_addr(struct ixgbe_hw
*hw
, u8
*mc_addr
);
53 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
);
56 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
57 * @hw: pointer to hardware structure
59 * Starts the hardware by filling the bus info structure and media type, clears
60 * all on chip counters, initializes receive address registers, multicast
61 * table, VLAN filter table, calls routine to set up link and flow control
62 * settings, and leaves transmit and receive units disabled and uninitialized
64 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
68 /* Set the media type */
69 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
71 /* Identify the PHY */
72 hw
->phy
.ops
.identify(hw
);
75 * Store MAC address from RAR0, clear receive address registers, and
76 * clear the multicast table
78 hw
->mac
.ops
.init_rx_addrs(hw
);
80 /* Clear the VLAN filter table */
81 hw
->mac
.ops
.clear_vfta(hw
);
84 hw
->mac
.ops
.setup_link(hw
);
86 /* Clear statistics registers */
87 hw
->mac
.ops
.clear_hw_cntrs(hw
);
89 /* Set No Snoop Disable */
90 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
91 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
92 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
93 IXGBE_WRITE_FLUSH(hw
);
95 /* Clear adapter stopped flag */
96 hw
->adapter_stopped
= false;
102 * ixgbe_init_hw_generic - Generic hardware initialization
103 * @hw: pointer to hardware structure
105 * Initialize the hardware by resetting the hardware, filling the bus info
106 * structure and media type, clears all on chip counters, initializes receive
107 * address registers, multicast table, VLAN filter table, calls routine to set
108 * up link and flow control settings, and leaves transmit and receive units
109 * disabled and uninitialized
111 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
113 /* Reset the hardware */
114 hw
->mac
.ops
.reset_hw(hw
);
117 hw
->mac
.ops
.start_hw(hw
);
123 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
124 * @hw: pointer to hardware structure
126 * Clears all hardware statistics counters by reading them from the hardware
127 * Statistics counters are clear on read.
129 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
133 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
134 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
135 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
136 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
137 for (i
= 0; i
< 8; i
++)
138 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
140 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
141 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
142 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
143 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
144 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
145 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
146 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
148 for (i
= 0; i
< 8; i
++) {
149 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
150 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
151 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
152 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
155 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
156 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
157 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
158 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
159 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
160 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
161 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
162 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
163 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
164 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
165 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
166 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
167 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
168 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
169 for (i
= 0; i
< 8; i
++)
170 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
171 IXGBE_READ_REG(hw
, IXGBE_RUC
);
172 IXGBE_READ_REG(hw
, IXGBE_RFC
);
173 IXGBE_READ_REG(hw
, IXGBE_ROC
);
174 IXGBE_READ_REG(hw
, IXGBE_RJC
);
175 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
176 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
177 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
178 IXGBE_READ_REG(hw
, IXGBE_TORL
);
179 IXGBE_READ_REG(hw
, IXGBE_TORH
);
180 IXGBE_READ_REG(hw
, IXGBE_TPR
);
181 IXGBE_READ_REG(hw
, IXGBE_TPT
);
182 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
183 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
184 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
185 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
186 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
187 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
188 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
189 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
190 for (i
= 0; i
< 16; i
++) {
191 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
192 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
193 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
194 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
201 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
202 * @hw: pointer to hardware structure
203 * @pba_num: stores the part number from the EEPROM
205 * Reads the part number from the EEPROM.
207 s32
ixgbe_read_pba_num_generic(struct ixgbe_hw
*hw
, u32
*pba_num
)
212 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
214 hw_dbg(hw
, "NVM Read Error\n");
217 *pba_num
= (u32
)(data
<< 16);
219 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &data
);
221 hw_dbg(hw
, "NVM Read Error\n");
230 * ixgbe_get_mac_addr_generic - Generic get MAC address
231 * @hw: pointer to hardware structure
232 * @mac_addr: Adapter MAC address
234 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
235 * A reset of the adapter must be performed prior to calling this function
236 * in order for the MAC address to have been loaded from the EEPROM into RAR0
238 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
244 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
245 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
247 for (i
= 0; i
< 4; i
++)
248 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
250 for (i
= 0; i
< 2; i
++)
251 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
257 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
258 * @hw: pointer to hardware structure
260 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
261 * disables transmit and receive units. The adapter_stopped flag is used by
262 * the shared code and drivers to determine if the adapter is in a stopped
263 * state and should not touch the hardware.
265 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
267 u32 number_of_queues
;
272 * Set the adapter_stopped flag so other driver functions stop touching
275 hw
->adapter_stopped
= true;
277 /* Disable the receive unit */
278 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
279 reg_val
&= ~(IXGBE_RXCTRL_RXEN
);
280 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, reg_val
);
281 IXGBE_WRITE_FLUSH(hw
);
284 /* Clear interrupt mask to stop from interrupts being generated */
285 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
287 /* Clear any pending interrupts */
288 IXGBE_READ_REG(hw
, IXGBE_EICR
);
290 /* Disable the transmit unit. Each queue must be disabled. */
291 number_of_queues
= hw
->mac
.max_tx_queues
;
292 for (i
= 0; i
< number_of_queues
; i
++) {
293 reg_val
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
294 if (reg_val
& IXGBE_TXDCTL_ENABLE
) {
295 reg_val
&= ~IXGBE_TXDCTL_ENABLE
;
296 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), reg_val
);
301 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
302 * access and verify no pending requests
304 if (ixgbe_disable_pcie_master(hw
) != 0)
305 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
311 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
312 * @hw: pointer to hardware structure
313 * @index: led number to turn on
315 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
317 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
319 /* To turn on the LED, set mode to ON. */
320 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
321 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
322 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
323 IXGBE_WRITE_FLUSH(hw
);
329 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
330 * @hw: pointer to hardware structure
331 * @index: led number to turn off
333 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
335 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
337 /* To turn off the LED, set mode to OFF. */
338 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
339 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
340 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
341 IXGBE_WRITE_FLUSH(hw
);
347 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
348 * @hw: pointer to hardware structure
350 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
351 * ixgbe_hw struct in order to set up EEPROM access.
353 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
355 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
359 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
360 eeprom
->type
= ixgbe_eeprom_none
;
361 /* Set default semaphore delay to 10ms which is a well
363 eeprom
->semaphore_delay
= 10;
366 * Check for EEPROM present first.
367 * If not present leave as none
369 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
370 if (eec
& IXGBE_EEC_PRES
) {
371 eeprom
->type
= ixgbe_eeprom_spi
;
374 * SPI EEPROM is assumed here. This code would need to
375 * change if a future EEPROM is not SPI.
377 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
378 IXGBE_EEC_SIZE_SHIFT
);
379 eeprom
->word_size
= 1 << (eeprom_size
+
380 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
383 if (eec
& IXGBE_EEC_ADDR_SIZE
)
384 eeprom
->address_bits
= 16;
386 eeprom
->address_bits
= 8;
387 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: "
388 "%d\n", eeprom
->type
, eeprom
->word_size
,
389 eeprom
->address_bits
);
396 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
397 * @hw: pointer to hardware structure
398 * @offset: offset within the EEPROM to be read
399 * @data: read 16 bit value from EEPROM
401 * Reads 16 bit value from EEPROM through bit-bang method
403 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
408 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
410 hw
->eeprom
.ops
.init_params(hw
);
412 if (offset
>= hw
->eeprom
.word_size
) {
413 status
= IXGBE_ERR_EEPROM
;
417 /* Prepare the EEPROM for reading */
418 status
= ixgbe_acquire_eeprom(hw
);
421 if (ixgbe_ready_eeprom(hw
) != 0) {
422 ixgbe_release_eeprom(hw
);
423 status
= IXGBE_ERR_EEPROM
;
428 ixgbe_standby_eeprom(hw
);
431 * Some SPI eeproms use the 8th address bit embedded in the
434 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
435 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
437 /* Send the READ command (opcode + addr) */
438 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
439 IXGBE_EEPROM_OPCODE_BITS
);
440 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
441 hw
->eeprom
.address_bits
);
444 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
445 *data
= (word_in
>> 8) | (word_in
<< 8);
447 /* End this read operation */
448 ixgbe_release_eeprom(hw
);
456 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
457 * @hw: pointer to hardware structure
458 * @offset: offset of word in the EEPROM to read
459 * @data: word read from the EEPROM
461 * Reads a 16 bit word from the EEPROM using the EERD register.
463 s32
ixgbe_read_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
468 hw
->eeprom
.ops
.init_params(hw
);
470 if (offset
>= hw
->eeprom
.word_size
) {
471 status
= IXGBE_ERR_EEPROM
;
475 eerd
= (offset
<< IXGBE_EEPROM_READ_ADDR_SHIFT
) +
476 IXGBE_EEPROM_READ_REG_START
;
478 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
479 status
= ixgbe_poll_eeprom_eerd_done(hw
);
482 *data
= (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
483 IXGBE_EEPROM_READ_REG_DATA
);
485 hw_dbg(hw
, "Eeprom read timed out\n");
492 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
493 * @hw: pointer to hardware structure
495 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
497 static s32
ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw
*hw
)
501 s32 status
= IXGBE_ERR_EEPROM
;
503 for (i
= 0; i
< IXGBE_EERD_ATTEMPTS
; i
++) {
504 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
505 if (reg
& IXGBE_EEPROM_READ_REG_DONE
) {
515 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
516 * @hw: pointer to hardware structure
518 * Prepares EEPROM for access using bit-bang method. This function should
519 * be called before issuing a command to the EEPROM.
521 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
527 if (ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
528 status
= IXGBE_ERR_SWFW_SYNC
;
531 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
533 /* Request EEPROM Access */
534 eec
|= IXGBE_EEC_REQ
;
535 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
537 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
538 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
539 if (eec
& IXGBE_EEC_GNT
)
544 /* Release if grant not acquired */
545 if (!(eec
& IXGBE_EEC_GNT
)) {
546 eec
&= ~IXGBE_EEC_REQ
;
547 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
548 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
550 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
551 status
= IXGBE_ERR_EEPROM
;
555 /* Setup EEPROM for Read/Write */
557 /* Clear CS and SK */
558 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
559 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
560 IXGBE_WRITE_FLUSH(hw
);
567 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
568 * @hw: pointer to hardware structure
570 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
572 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
574 s32 status
= IXGBE_ERR_EEPROM
;
579 /* Set timeout value based on size of EEPROM */
580 timeout
= hw
->eeprom
.word_size
+ 1;
582 /* Get SMBI software semaphore between device drivers first */
583 for (i
= 0; i
< timeout
; i
++) {
585 * If the SMBI bit is 0 when we read it, then the bit will be
586 * set and we have the semaphore
588 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
589 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
596 /* Now get the semaphore between SW/FW through the SWESMBI bit */
598 for (i
= 0; i
< timeout
; i
++) {
599 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
601 /* Set the SW EEPROM semaphore bit to request access */
602 swsm
|= IXGBE_SWSM_SWESMBI
;
603 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
606 * If we set the bit successfully then we got the
609 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
610 if (swsm
& IXGBE_SWSM_SWESMBI
)
617 * Release semaphores and return error if SW EEPROM semaphore
618 * was not granted because we don't have access to the EEPROM
621 hw_dbg(hw
, "Driver can't access the Eeprom - Semaphore "
623 ixgbe_release_eeprom_semaphore(hw
);
624 status
= IXGBE_ERR_EEPROM
;
632 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
633 * @hw: pointer to hardware structure
635 * This function clears hardware semaphore bits.
637 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
641 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
643 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
644 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
645 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
646 IXGBE_WRITE_FLUSH(hw
);
650 * ixgbe_ready_eeprom - Polls for EEPROM ready
651 * @hw: pointer to hardware structure
653 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
660 * Read "Status Register" repeatedly until the LSB is cleared. The
661 * EEPROM will signal that the command has been completed by clearing
662 * bit 0 of the internal status register. If it's not cleared within
663 * 5 milliseconds, then error out.
665 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
666 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
667 IXGBE_EEPROM_OPCODE_BITS
);
668 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
669 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
673 ixgbe_standby_eeprom(hw
);
677 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
678 * devices (and only 0-5mSec on 5V devices)
680 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
681 hw_dbg(hw
, "SPI EEPROM Status error\n");
682 status
= IXGBE_ERR_EEPROM
;
689 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
690 * @hw: pointer to hardware structure
692 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
696 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
698 /* Toggle CS to flush commands */
700 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
701 IXGBE_WRITE_FLUSH(hw
);
703 eec
&= ~IXGBE_EEC_CS
;
704 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
705 IXGBE_WRITE_FLUSH(hw
);
710 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
711 * @hw: pointer to hardware structure
712 * @data: data to send to the EEPROM
713 * @count: number of bits to shift out
715 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
722 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
725 * Mask is used to shift "count" bits of "data" out to the EEPROM
726 * one bit at a time. Determine the starting bit based on count
728 mask
= 0x01 << (count
- 1);
730 for (i
= 0; i
< count
; i
++) {
732 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
733 * "1", and then raising and then lowering the clock (the SK
734 * bit controls the clock input to the EEPROM). A "0" is
735 * shifted out to the EEPROM by setting "DI" to "0" and then
736 * raising and then lowering the clock.
741 eec
&= ~IXGBE_EEC_DI
;
743 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
744 IXGBE_WRITE_FLUSH(hw
);
748 ixgbe_raise_eeprom_clk(hw
, &eec
);
749 ixgbe_lower_eeprom_clk(hw
, &eec
);
752 * Shift mask to signify next bit of data to shift in to the
758 /* We leave the "DI" bit set to "0" when we leave this routine. */
759 eec
&= ~IXGBE_EEC_DI
;
760 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
761 IXGBE_WRITE_FLUSH(hw
);
765 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
766 * @hw: pointer to hardware structure
768 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
775 * In order to read a register from the EEPROM, we need to shift
776 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
777 * the clock input to the EEPROM (setting the SK bit), and then reading
778 * the value of the "DO" bit. During this "shifting in" process the
779 * "DI" bit should always be clear.
781 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
783 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
785 for (i
= 0; i
< count
; i
++) {
787 ixgbe_raise_eeprom_clk(hw
, &eec
);
789 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
791 eec
&= ~(IXGBE_EEC_DI
);
792 if (eec
& IXGBE_EEC_DO
)
795 ixgbe_lower_eeprom_clk(hw
, &eec
);
802 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
803 * @hw: pointer to hardware structure
804 * @eec: EEC register's current value
806 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
809 * Raise the clock input to the EEPROM
810 * (setting the SK bit), then delay
812 *eec
= *eec
| IXGBE_EEC_SK
;
813 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
814 IXGBE_WRITE_FLUSH(hw
);
819 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
820 * @hw: pointer to hardware structure
821 * @eecd: EECD's current value
823 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
826 * Lower the clock input to the EEPROM (clearing the SK bit), then
829 *eec
= *eec
& ~IXGBE_EEC_SK
;
830 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
831 IXGBE_WRITE_FLUSH(hw
);
836 * ixgbe_release_eeprom - Release EEPROM, release semaphores
837 * @hw: pointer to hardware structure
839 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
843 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
845 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
846 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
848 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
849 IXGBE_WRITE_FLUSH(hw
);
853 /* Stop requesting EEPROM access */
854 eec
&= ~IXGBE_EEC_REQ
;
855 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
857 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
861 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
862 * @hw: pointer to hardware structure
864 static u16
ixgbe_calc_eeprom_checksum(struct ixgbe_hw
*hw
)
873 /* Include 0x0-0x3F in the checksum */
874 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
875 if (hw
->eeprom
.ops
.read(hw
, i
, &word
) != 0) {
876 hw_dbg(hw
, "EEPROM read failed\n");
882 /* Include all data from pointers except for the fw pointer */
883 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
884 hw
->eeprom
.ops
.read(hw
, i
, &pointer
);
886 /* Make sure the pointer seems valid */
887 if (pointer
!= 0xFFFF && pointer
!= 0) {
888 hw
->eeprom
.ops
.read(hw
, pointer
, &length
);
890 if (length
!= 0xFFFF && length
!= 0) {
891 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
892 hw
->eeprom
.ops
.read(hw
, j
, &word
);
899 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
905 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
906 * @hw: pointer to hardware structure
907 * @checksum_val: calculated checksum
909 * Performs checksum calculation and validates the EEPROM checksum. If the
910 * caller does not need checksum_val, the value can be NULL.
912 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
917 u16 read_checksum
= 0;
920 * Read the first word from the EEPROM. If this times out or fails, do
921 * not continue or we could be in for a very long wait while every
924 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
927 checksum
= ixgbe_calc_eeprom_checksum(hw
);
929 hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
932 * Verify read checksum from EEPROM is the same as
933 * calculated checksum
935 if (read_checksum
!= checksum
)
936 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
938 /* If the user cares, return the calculated checksum */
940 *checksum_val
= checksum
;
942 hw_dbg(hw
, "EEPROM read failed\n");
949 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
950 * @hw: pointer to hardware structure
952 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
958 * Read the first word from the EEPROM. If this times out or fails, do
959 * not continue or we could be in for a very long wait while every
962 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
965 checksum
= ixgbe_calc_eeprom_checksum(hw
);
966 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
,
969 hw_dbg(hw
, "EEPROM read failed\n");
976 * ixgbe_validate_mac_addr - Validate MAC address
977 * @mac_addr: pointer to MAC address.
979 * Tests a MAC address to ensure it is a valid Individual Address
981 s32
ixgbe_validate_mac_addr(u8
*mac_addr
)
985 /* Make sure it is not a multicast address */
986 if (IXGBE_IS_MULTICAST(mac_addr
))
987 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
988 /* Not a broadcast address */
989 else if (IXGBE_IS_BROADCAST(mac_addr
))
990 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
991 /* Reject the zero address */
992 else if (mac_addr
[0] == 0 && mac_addr
[1] == 0 && mac_addr
[2] == 0 &&
993 mac_addr
[3] == 0 && mac_addr
[4] == 0 && mac_addr
[5] == 0)
994 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1000 * ixgbe_set_rar_generic - Set Rx address register
1001 * @hw: pointer to hardware structure
1002 * @index: Receive address register to write
1003 * @addr: Address to put into receive address register
1004 * @vmdq: VMDq "set" or "pool" index
1005 * @enable_addr: set flag that address is active
1007 * Puts an ethernet address into a receive address register.
1009 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1012 u32 rar_low
, rar_high
;
1013 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1015 /* setup VMDq pool selection before this RAR gets enabled */
1016 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1018 /* Make sure we are using a valid rar index range */
1019 if (index
< rar_entries
) {
1021 * HW expects these in little endian so we reverse the byte
1022 * order from network order (big endian) to little endian
1024 rar_low
= ((u32
)addr
[0] |
1025 ((u32
)addr
[1] << 8) |
1026 ((u32
)addr
[2] << 16) |
1027 ((u32
)addr
[3] << 24));
1029 * Some parts put the VMDq setting in the extra RAH bits,
1030 * so save everything except the lower 16 bits that hold part
1031 * of the address and the address valid bit.
1033 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1034 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1035 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1037 if (enable_addr
!= 0)
1038 rar_high
|= IXGBE_RAH_AV
;
1040 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1041 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1043 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1050 * ixgbe_clear_rar_generic - Remove Rx address register
1051 * @hw: pointer to hardware structure
1052 * @index: Receive address register to write
1054 * Clears an ethernet address from a receive address register.
1056 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1059 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1061 /* Make sure we are using a valid rar index range */
1062 if (index
< rar_entries
) {
1064 * Some parts put the VMDq setting in the extra RAH bits,
1065 * so save everything except the lower 16 bits that hold part
1066 * of the address and the address valid bit.
1068 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1069 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1071 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1072 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1074 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1077 /* clear VMDq pool/queue selection for this RAR */
1078 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1084 * ixgbe_enable_rar - Enable Rx address register
1085 * @hw: pointer to hardware structure
1086 * @index: index into the RAR table
1088 * Enables the select receive address register.
1090 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
)
1094 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1095 rar_high
|= IXGBE_RAH_AV
;
1096 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1100 * ixgbe_disable_rar - Disable Rx address register
1101 * @hw: pointer to hardware structure
1102 * @index: index into the RAR table
1104 * Disables the select receive address register.
1106 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
)
1110 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1111 rar_high
&= (~IXGBE_RAH_AV
);
1112 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1116 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1117 * @hw: pointer to hardware structure
1119 * Places the MAC address in receive address register 0 and clears the rest
1120 * of the receive address registers. Clears the multicast table. Assumes
1121 * the receiver is in reset when the routine is called.
1123 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1126 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1129 * If the current mac address is valid, assume it is a software override
1130 * to the permanent address.
1131 * Otherwise, use the permanent address from the eeprom.
1133 if (ixgbe_validate_mac_addr(hw
->mac
.addr
) ==
1134 IXGBE_ERR_INVALID_MAC_ADDR
) {
1135 /* Get the MAC address from the RAR0 for later reference */
1136 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1138 hw_dbg(hw
, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1139 hw
->mac
.addr
[0], hw
->mac
.addr
[1],
1141 hw_dbg(hw
, "%.2X %.2X %.2X\n", hw
->mac
.addr
[3],
1142 hw
->mac
.addr
[4], hw
->mac
.addr
[5]);
1144 /* Setup the receive address. */
1145 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1146 hw_dbg(hw
, " New MAC Addr =%.2X %.2X %.2X ",
1147 hw
->mac
.addr
[0], hw
->mac
.addr
[1],
1149 hw_dbg(hw
, "%.2X %.2X %.2X\n", hw
->mac
.addr
[3],
1150 hw
->mac
.addr
[4], hw
->mac
.addr
[5]);
1152 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1154 hw
->addr_ctrl
.overflow_promisc
= 0;
1156 hw
->addr_ctrl
.rar_used_count
= 1;
1158 /* Zero out the other receive addresses. */
1159 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1160 for (i
= 1; i
< rar_entries
; i
++) {
1161 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1162 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1166 hw
->addr_ctrl
.mc_addr_in_rar_count
= 0;
1167 hw
->addr_ctrl
.mta_in_use
= 0;
1168 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1170 hw_dbg(hw
, " Clearing MTA\n");
1171 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1172 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1174 if (hw
->mac
.ops
.init_uta_tables
)
1175 hw
->mac
.ops
.init_uta_tables(hw
);
1181 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1182 * @hw: pointer to hardware structure
1183 * @addr: new address
1185 * Adds it to unused receive address register or goes into promiscuous mode.
1187 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
)
1189 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1192 hw_dbg(hw
, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1193 addr
[0], addr
[1], addr
[2], addr
[3], addr
[4], addr
[5]);
1196 * Place this address in the RAR if there is room,
1197 * else put the controller into promiscuous mode
1199 if (hw
->addr_ctrl
.rar_used_count
< rar_entries
) {
1200 rar
= hw
->addr_ctrl
.rar_used_count
-
1201 hw
->addr_ctrl
.mc_addr_in_rar_count
;
1202 hw
->mac
.ops
.set_rar(hw
, rar
, addr
, vmdq
, IXGBE_RAH_AV
);
1203 hw_dbg(hw
, "Added a secondary address to RAR[%d]\n", rar
);
1204 hw
->addr_ctrl
.rar_used_count
++;
1206 hw
->addr_ctrl
.overflow_promisc
++;
1209 hw_dbg(hw
, "ixgbe_add_uc_addr Complete\n");
1213 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1214 * @hw: pointer to hardware structure
1215 * @addr_list: the list of new addresses
1216 * @addr_count: number of addresses
1217 * @next: iterator function to walk the address list
1219 * The given list replaces any existing list. Clears the secondary addrs from
1220 * receive address registers. Uses unused receive address registers for the
1221 * first secondary addresses, and falls back to promiscuous mode as needed.
1223 * Drivers using secondary unicast addresses must set user_set_promisc when
1224 * manually putting the device into promiscuous mode.
1226 s32
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw
*hw
, u8
*addr_list
,
1227 u32 addr_count
, ixgbe_mc_addr_itr next
)
1231 u32 old_promisc_setting
= hw
->addr_ctrl
.overflow_promisc
;
1237 * Clear accounting of old secondary address list,
1238 * don't count RAR[0]
1240 uc_addr_in_use
= hw
->addr_ctrl
.rar_used_count
-
1241 hw
->addr_ctrl
.mc_addr_in_rar_count
- 1;
1242 hw
->addr_ctrl
.rar_used_count
-= uc_addr_in_use
;
1243 hw
->addr_ctrl
.overflow_promisc
= 0;
1245 /* Zero out the other receive addresses */
1246 hw_dbg(hw
, "Clearing RAR[1-%d]\n", uc_addr_in_use
);
1247 for (i
= 1; i
<= uc_addr_in_use
; i
++) {
1248 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1249 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1252 /* Add the new addresses */
1253 for (i
= 0; i
< addr_count
; i
++) {
1254 hw_dbg(hw
, " Adding the secondary addresses:\n");
1255 addr
= next(hw
, &addr_list
, &vmdq
);
1256 ixgbe_add_uc_addr(hw
, addr
, vmdq
);
1259 if (hw
->addr_ctrl
.overflow_promisc
) {
1260 /* enable promisc if not already in overflow or set by user */
1261 if (!old_promisc_setting
&& !hw
->addr_ctrl
.user_set_promisc
) {
1262 hw_dbg(hw
, " Entering address overflow promisc mode\n");
1263 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1264 fctrl
|= IXGBE_FCTRL_UPE
;
1265 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1268 /* only disable if set by overflow, not by user */
1269 if (old_promisc_setting
&& !hw
->addr_ctrl
.user_set_promisc
) {
1270 hw_dbg(hw
, " Leaving address overflow promisc mode\n");
1271 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1272 fctrl
&= ~IXGBE_FCTRL_UPE
;
1273 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1277 hw_dbg(hw
, "ixgbe_update_uc_addr_list_generic Complete\n");
1282 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1283 * @hw: pointer to hardware structure
1284 * @mc_addr: the multicast address
1286 * Extracts the 12 bits, from a multicast address, to determine which
1287 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1288 * incoming rx multicast addresses, to determine the bit-vector to check in
1289 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1290 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1291 * to mc_filter_type.
1293 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1297 switch (hw
->mac
.mc_filter_type
) {
1298 case 0: /* use bits [47:36] of the address */
1299 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1301 case 1: /* use bits [46:35] of the address */
1302 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1304 case 2: /* use bits [45:34] of the address */
1305 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1307 case 3: /* use bits [43:32] of the address */
1308 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1310 default: /* Invalid mc_filter_type */
1311 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1315 /* vector can only be 12-bits or boundary will be exceeded */
1321 * ixgbe_set_mta - Set bit-vector in multicast table
1322 * @hw: pointer to hardware structure
1323 * @hash_value: Multicast address hash value
1325 * Sets the bit-vector in the multicast table.
1327 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1334 hw
->addr_ctrl
.mta_in_use
++;
1336 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1337 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1340 * The MTA is a register array of 128 32-bit registers. It is treated
1341 * like an array of 4096 bits. We want to set bit
1342 * BitArray[vector_value]. So we figure out what register the bit is
1343 * in, read it, OR in the new bit, then write back the new value. The
1344 * register is determined by the upper 7 bits of the vector value and
1345 * the bit within that register are determined by the lower 5 bits of
1348 vector_reg
= (vector
>> 5) & 0x7F;
1349 vector_bit
= vector
& 0x1F;
1350 mta_reg
= IXGBE_READ_REG(hw
, IXGBE_MTA(vector_reg
));
1351 mta_reg
|= (1 << vector_bit
);
1352 IXGBE_WRITE_REG(hw
, IXGBE_MTA(vector_reg
), mta_reg
);
1356 * ixgbe_add_mc_addr - Adds a multicast address.
1357 * @hw: pointer to hardware structure
1358 * @mc_addr: new multicast address
1360 * Adds it to unused receive address register or to the multicast table.
1362 static void ixgbe_add_mc_addr(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1364 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1367 hw_dbg(hw
, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
1368 mc_addr
[0], mc_addr
[1], mc_addr
[2],
1369 mc_addr
[3], mc_addr
[4], mc_addr
[5]);
1372 * Place this multicast address in the RAR if there is room,
1373 * else put it in the MTA
1375 if (hw
->addr_ctrl
.rar_used_count
< rar_entries
) {
1376 /* use RAR from the end up for multicast */
1377 rar
= rar_entries
- hw
->addr_ctrl
.mc_addr_in_rar_count
- 1;
1378 hw
->mac
.ops
.set_rar(hw
, rar
, mc_addr
, 0, IXGBE_RAH_AV
);
1379 hw_dbg(hw
, "Added a multicast address to RAR[%d]\n", rar
);
1380 hw
->addr_ctrl
.rar_used_count
++;
1381 hw
->addr_ctrl
.mc_addr_in_rar_count
++;
1383 ixgbe_set_mta(hw
, mc_addr
);
1386 hw_dbg(hw
, "ixgbe_add_mc_addr Complete\n");
1390 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1391 * @hw: pointer to hardware structure
1392 * @mc_addr_list: the list of new multicast addresses
1393 * @mc_addr_count: number of addresses
1394 * @next: iterator function to walk the multicast address list
1396 * The given list replaces any existing list. Clears the MC addrs from receive
1397 * address registers and the multicast table. Uses unused receive address
1398 * registers for the first multicast addresses, and hashes the rest into the
1401 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
, u8
*mc_addr_list
,
1402 u32 mc_addr_count
, ixgbe_mc_addr_itr next
)
1405 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1409 * Set the new number of MC addresses that we are being requested to
1412 hw
->addr_ctrl
.num_mc_addrs
= mc_addr_count
;
1413 hw
->addr_ctrl
.rar_used_count
-= hw
->addr_ctrl
.mc_addr_in_rar_count
;
1414 hw
->addr_ctrl
.mc_addr_in_rar_count
= 0;
1415 hw
->addr_ctrl
.mta_in_use
= 0;
1417 /* Zero out the other receive addresses. */
1418 hw_dbg(hw
, "Clearing RAR[%d-%d]\n", hw
->addr_ctrl
.rar_used_count
,
1420 for (i
= hw
->addr_ctrl
.rar_used_count
; i
< rar_entries
; i
++) {
1421 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1422 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1426 hw_dbg(hw
, " Clearing MTA\n");
1427 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1428 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1430 /* Add the new addresses */
1431 for (i
= 0; i
< mc_addr_count
; i
++) {
1432 hw_dbg(hw
, " Adding the multicast addresses:\n");
1433 ixgbe_add_mc_addr(hw
, next(hw
, &mc_addr_list
, &vmdq
));
1437 if (hw
->addr_ctrl
.mta_in_use
> 0)
1438 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
1439 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
1441 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
1446 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1447 * @hw: pointer to hardware structure
1449 * Enables multicast address in RAR and the use of the multicast hash table.
1451 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
1454 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1455 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1457 if (a
->mc_addr_in_rar_count
> 0)
1458 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1459 i
< rar_entries
; i
++)
1460 ixgbe_enable_rar(hw
, i
);
1462 if (a
->mta_in_use
> 0)
1463 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
1464 hw
->mac
.mc_filter_type
);
1470 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1471 * @hw: pointer to hardware structure
1473 * Disables multicast address in RAR and the use of the multicast hash table.
1475 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
1478 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1479 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1481 if (a
->mc_addr_in_rar_count
> 0)
1482 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1483 i
< rar_entries
; i
++)
1484 ixgbe_disable_rar(hw
, i
);
1486 if (a
->mta_in_use
> 0)
1487 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1493 * ixgbe_disable_pcie_master - Disable PCI-express master access
1494 * @hw: pointer to hardware structure
1496 * Disables PCI-Express master access and verifies there are no pending
1497 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1498 * bit hasn't caused the master requests to be disabled, else 0
1499 * is returned signifying master requests disabled.
1501 s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
1505 u32 number_of_queues
;
1506 s32 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
1508 /* Disable the receive unit by stopping each queue */
1509 number_of_queues
= hw
->mac
.max_rx_queues
;
1510 for (i
= 0; i
< number_of_queues
; i
++) {
1511 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
1512 if (reg_val
& IXGBE_RXDCTL_ENABLE
) {
1513 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
1514 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
1518 reg_val
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
1519 reg_val
|= IXGBE_CTRL_GIO_DIS
;
1520 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, reg_val
);
1522 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
1523 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
)) {
1535 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
1536 * @hw: pointer to hardware structure
1537 * @mask: Mask to specify which semaphore to acquire
1539 * Acquires the SWFW semaphore thought the GSSR register for the specified
1540 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1542 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
1546 u32 fwmask
= mask
<< 5;
1550 if (ixgbe_get_eeprom_semaphore(hw
))
1551 return -IXGBE_ERR_SWFW_SYNC
;
1553 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
1554 if (!(gssr
& (fwmask
| swmask
)))
1558 * Firmware currently using resource (fwmask) or other software
1559 * thread currently using resource (swmask)
1561 ixgbe_release_eeprom_semaphore(hw
);
1567 hw_dbg(hw
, "Driver can't access resource, GSSR timeout.\n");
1568 return -IXGBE_ERR_SWFW_SYNC
;
1572 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
1574 ixgbe_release_eeprom_semaphore(hw
);
1579 * ixgbe_release_swfw_sync - Release SWFW semaphore
1580 * @hw: pointer to hardware structure
1581 * @mask: Mask to specify which semaphore to release
1583 * Releases the SWFW semaphore thought the GSSR register for the specified
1584 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1586 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
1591 ixgbe_get_eeprom_semaphore(hw
);
1593 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
1595 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
1597 ixgbe_release_eeprom_semaphore(hw
);