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Staging: brcm80211: s/int32/s32/
[linux-2.6/kvm.git] / drivers / staging / brcm80211 / brcmfmac / bcmsdh_sdmmc.c
blobe03e0d8fac0e7f008dfdf44f59ea895946c12a59
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include <typedefs.h>
17
18 #include <bcmdevs.h>
19 #include <bcmendian.h>
20 #include <bcmutils.h>
21 #include <osl.h>
22 #include <sdio.h> /* SDIO Device and Protocol Specs */
23 #include <sdioh.h> /* SDIO Host Controller Specification */
24 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
25 #include <sdiovar.h> /* ioctl/iovars */
26
27 #include <linux/mmc/core.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/sdio_ids.h>
30
31 #include <dngl_stats.h>
32 #include <dhd.h>
33
34 #if defined(CONFIG_PM_SLEEP)
35 #include <linux/suspend.h>
36 extern volatile bool dhd_mmc_suspend;
37 #endif
38 #include "bcmsdh_sdmmc.h"
39
40 extern int sdio_function_init(void);
41 extern void sdio_function_cleanup(void);
42
43 #if !defined(OOB_INTR_ONLY)
44 static void IRQHandler(struct sdio_func *func);
45 static void IRQHandlerF2(struct sdio_func *func);
46 #endif /* !defined(OOB_INTR_ONLY) */
47 static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr);
48 extern int sdio_reset_comm(struct mmc_card *card);
49
50 extern PBCMSDH_SDMMC_INSTANCE gInstance;
51
52 uint sd_sdmode = SDIOH_MODE_SD4; /* Use SD4 mode by default */
53 uint sd_f2_blocksize = 512; /* Default blocksize */
54
55 uint sd_divisor = 2; /* Default 48MHz/2 = 24MHz */
56
57 uint sd_power = 1; /* Default to SD Slot powered ON */
58 uint sd_clock = 1; /* Default to SD Clock turned ON */
59 uint sd_hiok = FALSE; /* Don't use hi-speed mode by default */
60 uint sd_msglevel = 0x01;
61 uint sd_use_dma = TRUE;
62 DHD_PM_RESUME_WAIT_INIT(sdioh_request_byte_wait);
63 DHD_PM_RESUME_WAIT_INIT(sdioh_request_word_wait);
64 DHD_PM_RESUME_WAIT_INIT(sdioh_request_packet_wait);
65 DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait);
66
67 #define DMA_ALIGN_MASK 0x03
68
69 int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
70 int regsize, u32 *data);
71
72 static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
73 {
74 int err_ret;
75 u32 fbraddr;
76 u8 func;
77
78 sd_trace(("%s\n", __func__));
79
80 /* Get the Card's common CIS address */
81 sd->com_cis_ptr = sdioh_sdmmc_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0);
82 sd->func_cis_ptr[0] = sd->com_cis_ptr;
83 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __func__,
84 sd->com_cis_ptr));
85
86 /* Get the Card's function CIS (for each function) */
87 for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
88 func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
89 sd->func_cis_ptr[func] =
90 sdioh_sdmmc_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr);
91 sd_info(("%s: Function %d CIS Ptr = 0x%x\n", __func__, func,
92 sd->func_cis_ptr[func]));
93 }
94
95 sd->func_cis_ptr[0] = sd->com_cis_ptr;
96 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __func__,
97 sd->com_cis_ptr));
98
99 /* Enable Function 1 */
100 sdio_claim_host(gInstance->func[1]);
101 err_ret = sdio_enable_func(gInstance->func[1]);
102 sdio_release_host(gInstance->func[1]);
103 if (err_ret) {
104 sd_err(("bcmsdh_sdmmc: Failed to enable F1 Err: 0x%08x",
105 err_ret));
106 }
107
108 return FALSE;
109 }
110
111 /*
112 * Public entry points & extern's
113 */
114 extern sdioh_info_t *sdioh_attach(osl_t *osh, void *bar0, uint irq)
115 {
116 sdioh_info_t *sd;
117 int err_ret;
118
119 sd_trace(("%s\n", __func__));
120
121 if (gInstance == NULL) {
122 sd_err(("%s: SDIO Device not present\n", __func__));
123 return NULL;
124 }
125
126 sd = (sdioh_info_t *) MALLOC(osh, sizeof(sdioh_info_t));
127 if (sd == NULL) {
128 sd_err(("sdioh_attach: out of memory, malloced %d bytes\n",
129 MALLOCED(osh)));
130 return NULL;
131 }
132 bzero((char *)sd, sizeof(sdioh_info_t));
133 sd->osh = osh;
134 if (sdioh_sdmmc_osinit(sd) != 0) {
135 sd_err(("%s:sdioh_sdmmc_osinit() failed\n", __func__));
136 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
137 return NULL;
138 }
139
140 sd->num_funcs = 2;
141 sd->sd_blockmode = TRUE;
142 sd->use_client_ints = TRUE;
143 sd->client_block_size[0] = 64;
144
145 gInstance->sd = sd;
146
147 /* Claim host controller */
148 sdio_claim_host(gInstance->func[1]);
149
150 sd->client_block_size[1] = 64;
151 err_ret = sdio_set_block_size(gInstance->func[1], 64);
152 if (err_ret)
153 sd_err(("bcmsdh_sdmmc: Failed to set F1 blocksize\n"));
154
155 /* Release host controller F1 */
156 sdio_release_host(gInstance->func[1]);
157
158 if (gInstance->func[2]) {
159 /* Claim host controller F2 */
160 sdio_claim_host(gInstance->func[2]);
161
162 sd->client_block_size[2] = sd_f2_blocksize;
163 err_ret =
164 sdio_set_block_size(gInstance->func[2], sd_f2_blocksize);
165 if (err_ret)
166 sd_err(("bcmsdh_sdmmc: Failed to set F2 blocksize "
167 "to %d\n", sd_f2_blocksize));
168
169 /* Release host controller F2 */
170 sdio_release_host(gInstance->func[2]);
171 }
172
173 sdioh_sdmmc_card_enablefuncs(sd);
174
175 sd_trace(("%s: Done\n", __func__));
176 return sd;
177 }
178
179 extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *sd)
180 {
181 sd_trace(("%s\n", __func__));
182
183 if (sd) {
184
185 /* Disable Function 2 */
186 sdio_claim_host(gInstance->func[2]);
187 sdio_disable_func(gInstance->func[2]);
188 sdio_release_host(gInstance->func[2]);
189
190 /* Disable Function 1 */
191 sdio_claim_host(gInstance->func[1]);
192 sdio_disable_func(gInstance->func[1]);
193 sdio_release_host(gInstance->func[1]);
194
195 /* deregister irq */
196 sdioh_sdmmc_osfree(sd);
197
198 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
199 }
200 return SDIOH_API_RC_SUCCESS;
201 }
202
203 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
204
205 extern SDIOH_API_RC sdioh_enable_func_intr(void)
206 {
207 u8 reg;
208 int err;
209
210 if (gInstance->func[0]) {
211 sdio_claim_host(gInstance->func[0]);
212
213 reg = sdio_readb(gInstance->func[0], SDIOD_CCCR_INTEN, &err);
214 if (err) {
215 sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n",
216 __func__, err));
217 sdio_release_host(gInstance->func[0]);
218 return SDIOH_API_RC_FAIL;
219 }
220
221 /* Enable F1 and F2 interrupts, set master enable */
222 reg |=
223 (INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN |
224 INTR_CTL_MASTER_EN);
225
226 sdio_writeb(gInstance->func[0], reg, SDIOD_CCCR_INTEN, &err);
227 sdio_release_host(gInstance->func[0]);
228
229 if (err) {
230 sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n",
231 __func__, err));
232 return SDIOH_API_RC_FAIL;
233 }
234 }
235
236 return SDIOH_API_RC_SUCCESS;
237 }
238
239 extern SDIOH_API_RC sdioh_disable_func_intr(void)
240 {
241 u8 reg;
242 int err;
243
244 if (gInstance->func[0]) {
245 sdio_claim_host(gInstance->func[0]);
246 reg = sdio_readb(gInstance->func[0], SDIOD_CCCR_INTEN, &err);
247 if (err) {
248 sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n",
249 __func__, err));
250 sdio_release_host(gInstance->func[0]);
251 return SDIOH_API_RC_FAIL;
252 }
253
254 reg &= ~(INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN);
255 /* Disable master interrupt with the last function interrupt */
256 if (!(reg & 0xFE))
257 reg = 0;
258 sdio_writeb(gInstance->func[0], reg, SDIOD_CCCR_INTEN, &err);
259
260 sdio_release_host(gInstance->func[0]);
261 if (err) {
262 sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n",
263 __func__, err));
264 return SDIOH_API_RC_FAIL;
265 }
266 }
267 return SDIOH_API_RC_SUCCESS;
268 }
269 #endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
270
271 /* Configure callback to client when we recieve client interrupt */
272 extern SDIOH_API_RC
273 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
274 {
275 sd_trace(("%s: Entering\n", __func__));
276 if (fn == NULL) {
277 sd_err(("%s: interrupt handler is NULL, not registering\n",
278 __func__));
279 return SDIOH_API_RC_FAIL;
280 }
281 #if !defined(OOB_INTR_ONLY)
282 sd->intr_handler = fn;
283 sd->intr_handler_arg = argh;
284 sd->intr_handler_valid = TRUE;
285
286 /* register and unmask irq */
287 if (gInstance->func[2]) {
288 sdio_claim_host(gInstance->func[2]);
289 sdio_claim_irq(gInstance->func[2], IRQHandlerF2);
290 sdio_release_host(gInstance->func[2]);
291 }
292
293 if (gInstance->func[1]) {
294 sdio_claim_host(gInstance->func[1]);
295 sdio_claim_irq(gInstance->func[1], IRQHandler);
296 sdio_release_host(gInstance->func[1]);
297 }
298 #elif defined(HW_OOB)
299 sdioh_enable_func_intr();
300 #endif /* defined(OOB_INTR_ONLY) */
301 return SDIOH_API_RC_SUCCESS;
302 }
303
304 extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *sd)
305 {
306 sd_trace(("%s: Entering\n", __func__));
307
308 #if !defined(OOB_INTR_ONLY)
309 if (gInstance->func[1]) {
310 /* register and unmask irq */
311 sdio_claim_host(gInstance->func[1]);
312 sdio_release_irq(gInstance->func[1]);
313 sdio_release_host(gInstance->func[1]);
314 }
315
316 if (gInstance->func[2]) {
317 /* Claim host controller F2 */
318 sdio_claim_host(gInstance->func[2]);
319 sdio_release_irq(gInstance->func[2]);
320 /* Release host controller F2 */
321 sdio_release_host(gInstance->func[2]);
322 }
323
324 sd->intr_handler_valid = FALSE;
325 sd->intr_handler = NULL;
326 sd->intr_handler_arg = NULL;
327 #elif defined(HW_OOB)
328 sdioh_disable_func_intr();
329 #endif /* !defined(OOB_INTR_ONLY) */
330 return SDIOH_API_RC_SUCCESS;
331 }
332
333 extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
334 {
335 sd_trace(("%s: Entering\n", __func__));
336 *onoff = sd->client_intr_enabled;
337 return SDIOH_API_RC_SUCCESS;
338 }
339
340 #if defined(DHD_DEBUG)
341 extern bool sdioh_interrupt_pending(sdioh_info_t *sd)
342 {
343 return 0;
344 }
345 #endif
346
347 uint sdioh_query_iofnum(sdioh_info_t *sd)
348 {
349 return sd->num_funcs;
350 }
351
352 /* IOVar table */
353 enum {
354 IOV_MSGLEVEL = 1,
355 IOV_BLOCKMODE,
356 IOV_BLOCKSIZE,
357 IOV_DMA,
358 IOV_USEINTS,
359 IOV_NUMINTS,
360 IOV_NUMLOCALINTS,
361 IOV_HOSTREG,
362 IOV_DEVREG,
363 IOV_DIVISOR,
364 IOV_SDMODE,
365 IOV_HISPEED,
366 IOV_HCIREGS,
367 IOV_POWER,
368 IOV_CLOCK,
369 IOV_RXCHAIN
370 };
371
372 const bcm_iovar_t sdioh_iovars[] = {
373 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0},
374 {"sd_blockmode", IOV_BLOCKMODE, 0, IOVT_BOOL, 0},
375 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0},/* ((fn << 16) |
376 size) */
377 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0},
378 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0},
379 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0},
380 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0},
381 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
382 ,
383 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
384 ,
385 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0}
386 ,
387 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0}
388 ,
389 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0}
390 ,
391 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100}
392 ,
393 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0}
394 ,
395 {"sd_rxchain", IOV_RXCHAIN, 0, IOVT_BOOL, 0}
396 ,
397 {NULL, 0, 0, 0, 0}
398 };
399
400 int
401 sdioh_iovar_op(sdioh_info_t *si, const char *name,
402 void *params, int plen, void *arg, int len, bool set)
403 {
404 const bcm_iovar_t *vi = NULL;
405 int bcmerror = 0;
406 int val_size;
407 s32 int_val = 0;
408 bool bool_val;
409 u32 actionid;
410
411 ASSERT(name);
412 ASSERT(len >= 0);
413
414 /* Get must have return space; Set does not take qualifiers */
415 ASSERT(set || (arg && len));
416 ASSERT(!set || (!params && !plen));
417
418 sd_trace(("%s: Enter (%s %s)\n", __func__, (set ? "set" : "get"),
419 name));
420
421 vi = bcm_iovar_lookup(sdioh_iovars, name);
422 if (vi == NULL) {
423 bcmerror = BCME_UNSUPPORTED;
424 goto exit;
425 }
426
427 bcmerror = bcm_iovar_lencheck(vi, arg, len, set);
428 if (bcmerror != 0)
429 goto exit;
430
431 /* Set up params so get and set can share the convenience variables */
432 if (params == NULL) {
433 params = arg;
434 plen = len;
435 }
436
437 if (vi->type == IOVT_VOID)
438 val_size = 0;
439 else if (vi->type == IOVT_BUFFER)
440 val_size = len;
441 else
442 val_size = sizeof(int);
443
444 if (plen >= (int)sizeof(int_val))
445 bcopy(params, &int_val, sizeof(int_val));
446
447 bool_val = (int_val != 0) ? TRUE : FALSE;
448
449 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
450 switch (actionid) {
451 case IOV_GVAL(IOV_MSGLEVEL):
452 int_val = (s32) sd_msglevel;
453 bcopy(&int_val, arg, val_size);
454 break;
455
456 case IOV_SVAL(IOV_MSGLEVEL):
457 sd_msglevel = int_val;
458 break;
459
460 case IOV_GVAL(IOV_BLOCKMODE):
461 int_val = (s32) si->sd_blockmode;
462 bcopy(&int_val, arg, val_size);
463 break;
464
465 case IOV_SVAL(IOV_BLOCKMODE):
466 si->sd_blockmode = (bool) int_val;
467 /* Haven't figured out how to make non-block mode with DMA */
468 break;
469
470 case IOV_GVAL(IOV_BLOCKSIZE):
471 if ((u32) int_val > si->num_funcs) {
472 bcmerror = BCME_BADARG;
473 break;
474 }
475 int_val = (s32) si->client_block_size[int_val];
476 bcopy(&int_val, arg, val_size);
477 break;
478
479 case IOV_SVAL(IOV_BLOCKSIZE):
480 {
481 uint func = ((u32) int_val >> 16);
482 uint blksize = (u16) int_val;
483 uint maxsize;
484
485 if (func > si->num_funcs) {
486 bcmerror = BCME_BADARG;
487 break;
488 }
489
490 switch (func) {
491 case 0:
492 maxsize = 32;
493 break;
494 case 1:
495 maxsize = BLOCK_SIZE_4318;
496 break;
497 case 2:
498 maxsize = BLOCK_SIZE_4328;
499 break;
500 default:
501 maxsize = 0;
502 }
503 if (blksize > maxsize) {
504 bcmerror = BCME_BADARG;
505 break;
506 }
507 if (!blksize)
508 blksize = maxsize;
509
510 /* Now set it */
511 si->client_block_size[func] = blksize;
512
513 break;
514 }
515
516 case IOV_GVAL(IOV_RXCHAIN):
517 int_val = FALSE;
518 bcopy(&int_val, arg, val_size);
519 break;
520
521 case IOV_GVAL(IOV_DMA):
522 int_val = (s32) si->sd_use_dma;
523 bcopy(&int_val, arg, val_size);
524 break;
525
526 case IOV_SVAL(IOV_DMA):
527 si->sd_use_dma = (bool) int_val;
528 break;
529
530 case IOV_GVAL(IOV_USEINTS):
531 int_val = (s32) si->use_client_ints;
532 bcopy(&int_val, arg, val_size);
533 break;
534
535 case IOV_SVAL(IOV_USEINTS):
536 si->use_client_ints = (bool) int_val;
537 if (si->use_client_ints)
538 si->intmask |= CLIENT_INTR;
539 else
540 si->intmask &= ~CLIENT_INTR;
541
542 break;
543
544 case IOV_GVAL(IOV_DIVISOR):
545 int_val = (u32) sd_divisor;
546 bcopy(&int_val, arg, val_size);
547 break;
548
549 case IOV_SVAL(IOV_DIVISOR):
550 sd_divisor = int_val;
551 break;
552
553 case IOV_GVAL(IOV_POWER):
554 int_val = (u32) sd_power;
555 bcopy(&int_val, arg, val_size);
556 break;
557
558 case IOV_SVAL(IOV_POWER):
559 sd_power = int_val;
560 break;
561
562 case IOV_GVAL(IOV_CLOCK):
563 int_val = (u32) sd_clock;
564 bcopy(&int_val, arg, val_size);
565 break;
566
567 case IOV_SVAL(IOV_CLOCK):
568 sd_clock = int_val;
569 break;
570
571 case IOV_GVAL(IOV_SDMODE):
572 int_val = (u32) sd_sdmode;
573 bcopy(&int_val, arg, val_size);
574 break;
575
576 case IOV_SVAL(IOV_SDMODE):
577 sd_sdmode = int_val;
578 break;
579
580 case IOV_GVAL(IOV_HISPEED):
581 int_val = (u32) sd_hiok;
582 bcopy(&int_val, arg, val_size);
583 break;
584
585 case IOV_SVAL(IOV_HISPEED):
586 sd_hiok = int_val;
587 break;
588
589 case IOV_GVAL(IOV_NUMINTS):
590 int_val = (s32) si->intrcount;
591 bcopy(&int_val, arg, val_size);
592 break;
593
594 case IOV_GVAL(IOV_NUMLOCALINTS):
595 int_val = (s32) 0;
596 bcopy(&int_val, arg, val_size);
597 break;
598
599 case IOV_GVAL(IOV_HOSTREG):
600 {
601 sdreg_t *sd_ptr = (sdreg_t *) params;
602
603 if (sd_ptr->offset < SD_SysAddr
604 || sd_ptr->offset > SD_MaxCurCap) {
605 sd_err(("%s: bad offset 0x%x\n", __func__,
606 sd_ptr->offset));
607 bcmerror = BCME_BADARG;
608 break;
609 }
610
611 sd_trace(("%s: rreg%d at offset %d\n", __func__,
612 (sd_ptr->offset & 1) ? 8
613 : ((sd_ptr->offset & 2) ? 16 : 32),
614 sd_ptr->offset));
615 if (sd_ptr->offset & 1)
616 int_val = 8; /* sdioh_sdmmc_rreg8(si,
617 sd_ptr->offset); */
618 else if (sd_ptr->offset & 2)
619 int_val = 16; /* sdioh_sdmmc_rreg16(si,
620 sd_ptr->offset); */
621 else
622 int_val = 32; /* sdioh_sdmmc_rreg(si,
623 sd_ptr->offset); */
624
625 bcopy(&int_val, arg, sizeof(int_val));
626 break;
627 }
628
629 case IOV_SVAL(IOV_HOSTREG):
630 {
631 sdreg_t *sd_ptr = (sdreg_t *) params;
632
633 if (sd_ptr->offset < SD_SysAddr
634 || sd_ptr->offset > SD_MaxCurCap) {
635 sd_err(("%s: bad offset 0x%x\n", __func__,
636 sd_ptr->offset));
637 bcmerror = BCME_BADARG;
638 break;
639 }
640
641 sd_trace(("%s: wreg%d value 0x%08x at offset %d\n",
642 __func__, sd_ptr->value,
643 (sd_ptr->offset & 1) ? 8
644 : ((sd_ptr->offset & 2) ? 16 : 32),
645 sd_ptr->offset));
646 break;
647 }
648
649 case IOV_GVAL(IOV_DEVREG):
650 {
651 sdreg_t *sd_ptr = (sdreg_t *) params;
652 u8 data = 0;
653
654 if (sdioh_cfg_read
655 (si, sd_ptr->func, sd_ptr->offset, &data)) {
656 bcmerror = BCME_SDIO_ERROR;
657 break;
658 }
659
660 int_val = (int)data;
661 bcopy(&int_val, arg, sizeof(int_val));
662 break;
663 }
664
665 case IOV_SVAL(IOV_DEVREG):
666 {
667 sdreg_t *sd_ptr = (sdreg_t *) params;
668 u8 data = (u8) sd_ptr->value;
669
670 if (sdioh_cfg_write
671 (si, sd_ptr->func, sd_ptr->offset, &data)) {
672 bcmerror = BCME_SDIO_ERROR;
673 break;
674 }
675 break;
676 }
677
678 default:
679 bcmerror = BCME_UNSUPPORTED;
680 break;
681 }
682 exit:
683
684 return bcmerror;
685 }
686
687 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
688
689 SDIOH_API_RC sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable)
690 {
691 SDIOH_API_RC status;
692 u8 data;
693
694 if (enable)
695 data = 3; /* enable hw oob interrupt */
696 else
697 data = 4; /* disable hw oob interrupt */
698 data |= 4; /* Active HIGH */
699
700 status = sdioh_request_byte(sd, SDIOH_WRITE, 0, 0xf2, &data);
701 return status;
702 }
703 #endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
704
705 extern SDIOH_API_RC
706 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
707 {
708 SDIOH_API_RC status;
709 /* No lock needed since sdioh_request_byte does locking */
710 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
711 return status;
712 }
713
714 extern SDIOH_API_RC
715 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
716 {
717 /* No lock needed since sdioh_request_byte does locking */
718 SDIOH_API_RC status;
719 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
720 return status;
721 }
722
723 static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr)
724 {
725 /* read 24 bits and return valid 17 bit addr */
726 int i;
727 u32 scratch, regdata;
728 u8 *ptr = (u8 *)&scratch;
729 for (i = 0; i < 3; i++) {
730 if ((sdioh_sdmmc_card_regread(sd, 0, regaddr, 1, &regdata)) !=
731 SUCCESS)
732 sd_err(("%s: Can't read!\n", __func__));
733
734 *ptr++ = (u8) regdata;
735 regaddr++;
736 }
737
738 /* Only the lower 17-bits are valid */
739 scratch = ltoh32(scratch);
740 scratch &= 0x0001FFFF;
741 return scratch;
742 }
743
744 extern SDIOH_API_RC
745 sdioh_cis_read(sdioh_info_t *sd, uint func, u8 *cisd, u32 length)
746 {
747 u32 count;
748 int offset;
749 u32 foo;
750 u8 *cis = cisd;
751
752 sd_trace(("%s: Func = %d\n", __func__, func));
753
754 if (!sd->func_cis_ptr[func]) {
755 bzero(cis, length);
756 sd_err(("%s: no func_cis_ptr[%d]\n", __func__, func));
757 return SDIOH_API_RC_FAIL;
758 }
759
760 sd_err(("%s: func_cis_ptr[%d]=0x%04x\n", __func__, func,
761 sd->func_cis_ptr[func]));
762
763 for (count = 0; count < length; count++) {
764 offset = sd->func_cis_ptr[func] + count;
765 if (sdioh_sdmmc_card_regread(sd, 0, offset, 1, &foo) < 0) {
766 sd_err(("%s: regread failed: Can't read CIS\n",
767 __func__));
768 return SDIOH_API_RC_FAIL;
769 }
770
771 *cis = (u8) (foo & 0xff);
772 cis++;
773 }
774
775 return SDIOH_API_RC_SUCCESS;
776 }
777
778 extern SDIOH_API_RC
779 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr,
780 u8 *byte)
781 {
782 int err_ret;
783
784 sd_info(("%s: rw=%d, func=%d, addr=0x%05x\n", __func__, rw, func,
785 regaddr));
786
787 DHD_PM_RESUME_WAIT(sdioh_request_byte_wait);
788 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
789 if (rw) { /* CMD52 Write */
790 if (func == 0) {
791 /* Can only directly write to some F0 registers.
792 * Handle F2 enable
793 * as a special case.
794 */
795 if (regaddr == SDIOD_CCCR_IOEN) {
796 if (gInstance->func[2]) {
797 sdio_claim_host(gInstance->func[2]);
798 if (*byte & SDIO_FUNC_ENABLE_2) {
799 /* Enable Function 2 */
800 err_ret =
801 sdio_enable_func
802 (gInstance->func[2]);
803 if (err_ret)
804 sd_err(("bcmsdh_sdmmc: enable F2 failed:%d",
805 err_ret));
806 } else {
807 /* Disable Function 2 */
808 err_ret =
809 sdio_disable_func
810 (gInstance->func[2]);
811 if (err_ret)
812 sd_err(("bcmsdh_sdmmc: Disab F2 failed:%d",
813 err_ret));
814 }
815 sdio_release_host(gInstance->func[2]);
816 }
817 }
818 #if defined(MMC_SDIO_ABORT)
819 /* to allow abort command through F1 */
820 else if (regaddr == SDIOD_CCCR_IOABORT) {
821 sdio_claim_host(gInstance->func[func]);
822 /*
823 * this sdio_f0_writeb() can be replaced
824 * with another api
825 * depending upon MMC driver change.
826 * As of this time, this is temporaray one
827 */
828 sdio_writeb(gInstance->func[func], *byte,
829 regaddr, &err_ret);
830 sdio_release_host(gInstance->func[func]);
831 }
832 #endif /* MMC_SDIO_ABORT */
833 else if (regaddr < 0xF0) {
834 sd_err(("bcmsdh_sdmmc: F0 Wr:0x%02x: write "
835 "disallowed\n", regaddr));
836 } else {
837 /* Claim host controller, perform F0 write,
838 and release */
839 sdio_claim_host(gInstance->func[func]);
840 sdio_f0_writeb(gInstance->func[func], *byte,
841 regaddr, &err_ret);
842 sdio_release_host(gInstance->func[func]);
843 }
844 } else {
845 /* Claim host controller, perform Fn write,
846 and release */
847 sdio_claim_host(gInstance->func[func]);
848 sdio_writeb(gInstance->func[func], *byte, regaddr,
849 &err_ret);
850 sdio_release_host(gInstance->func[func]);
851 }
852 } else { /* CMD52 Read */
853 /* Claim host controller, perform Fn read, and release */
854 sdio_claim_host(gInstance->func[func]);
855
856 if (func == 0) {
857 *byte =
858 sdio_f0_readb(gInstance->func[func], regaddr,
859 &err_ret);
860 } else {
861 *byte =
862 sdio_readb(gInstance->func[func], regaddr,
863 &err_ret);
864 }
865
866 sdio_release_host(gInstance->func[func]);
867 }
868
869 if (err_ret)
870 sd_err(("bcmsdh_sdmmc: Failed to %s byte F%d:@0x%05x=%02x, "
871 "Err: %d\n", rw ? "Write" : "Read", func, regaddr,
872 *byte, err_ret));
873
874 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
875 }
876
877 extern SDIOH_API_RC
878 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func,
879 uint addr, u32 *word, uint nbytes)
880 {
881 int err_ret = SDIOH_API_RC_FAIL;
882
883 if (func == 0) {
884 sd_err(("%s: Only CMD52 allowed to F0.\n", __func__));
885 return SDIOH_API_RC_FAIL;
886 }
887
888 sd_info(("%s: cmd_type=%d, rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
889 __func__, cmd_type, rw, func, addr, nbytes));
890
891 DHD_PM_RESUME_WAIT(sdioh_request_word_wait);
892 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
893 /* Claim host controller */
894 sdio_claim_host(gInstance->func[func]);
895
896 if (rw) { /* CMD52 Write */
897 if (nbytes == 4) {
898 sdio_writel(gInstance->func[func], *word, addr,
899 &err_ret);
900 } else if (nbytes == 2) {
901 sdio_writew(gInstance->func[func], (*word & 0xFFFF),
902 addr, &err_ret);
903 } else {
904 sd_err(("%s: Invalid nbytes: %d\n", __func__, nbytes));
905 }
906 } else { /* CMD52 Read */
907 if (nbytes == 4) {
908 *word =
909 sdio_readl(gInstance->func[func], addr, &err_ret);
910 } else if (nbytes == 2) {
911 *word =
912 sdio_readw(gInstance->func[func], addr,
913 &err_ret) & 0xFFFF;
914 } else {
915 sd_err(("%s: Invalid nbytes: %d\n", __func__, nbytes));
916 }
917 }
918
919 /* Release host controller */
920 sdio_release_host(gInstance->func[func]);
921
922 if (err_ret) {
923 sd_err(("bcmsdh_sdmmc: Failed to %s word, Err: 0x%08x",
924 rw ? "Write" : "Read", err_ret));
925 }
926
927 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
928 }
929
930 static SDIOH_API_RC
931 sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
932 uint addr, void *pkt)
933 {
934 bool fifo = (fix_inc == SDIOH_DATA_FIX);
935 u32 SGCount = 0;
936 int err_ret = 0;
937
938 void *pnext;
939
940 sd_trace(("%s: Enter\n", __func__));
941
942 ASSERT(pkt);
943 DHD_PM_RESUME_WAIT(sdioh_request_packet_wait);
944 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
945
946 /* Claim host controller */
947 sdio_claim_host(gInstance->func[func]);
948 for (pnext = pkt; pnext; pnext = PKTNEXT(pnext)) {
949 uint pkt_len = PKTLEN(pnext);
950 pkt_len += 3;
951 pkt_len &= 0xFFFFFFFC;
952
953 #ifdef CONFIG_MMC_MSM7X00A
954 if ((pkt_len % 64) == 32) {
955 sd_trace(("%s: Rounding up TX packet +=32\n",
956 __func__));
957 pkt_len += 32;
958 }
959 #endif /* CONFIG_MMC_MSM7X00A */
960 /* Make sure the packet is aligned properly.
961 * If it isn't, then this
962 * is the fault of sdioh_request_buffer() which
963 * is supposed to give
964 * us something we can work with.
965 */
966 ASSERT(((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) == 0);
967
968 if ((write) && (!fifo)) {
969 err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
970 ((u8 *) PKTDATA(pnext)),
971 pkt_len);
972 } else if (write) {
973 err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
974 ((u8 *) PKTDATA(pnext)),
975 pkt_len);
976 } else if (fifo) {
977 err_ret = sdio_readsb(gInstance->func[func],
978 ((u8 *) PKTDATA(pnext)),
979 addr, pkt_len);
980 } else {
981 err_ret = sdio_memcpy_fromio(gInstance->func[func],
982 ((u8 *) PKTDATA(pnext)),
983 addr, pkt_len);
984 }
985
986 if (err_ret) {
987 sd_err(("%s: %s FAILED %p[%d], addr=0x%05x, pkt_len=%d,"
988 "ERR=0x%08x\n", __func__,
989 (write) ? "TX" : "RX",
990 pnext, SGCount, addr, pkt_len, err_ret));
991 } else {
992 sd_trace(("%s: %s xfr'd %p[%d], addr=0x%05x, len=%d\n",
993 __func__,
994 (write) ? "TX" : "RX",
995 pnext, SGCount, addr, pkt_len));
996 }
997
998 if (!fifo)
999 addr += pkt_len;
1000 SGCount++;
1001
1002 }
1003
1004 /* Release host controller */
1005 sdio_release_host(gInstance->func[func]);
1006
1007 sd_trace(("%s: Exit\n", __func__));
1008 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
1009 }
1010
1011 /*
1012 * This function takes a buffer or packet, and fixes everything up
1013 * so that in the
1014 * end, a DMA-able packet is created.
1015 *
1016 * A buffer does not have an associated packet pointer,
1017 * and may or may not be aligned.
1018 * A packet may consist of a single packet, or a packet chain.
1019 * If it is a packet chain,
1020 * then all the packets in the chain must be properly aligned.
1021 * If the packet data is not
1022 * aligned, then there may only be one packet, and in this case,
1023 * it is copied to a new
1024 * aligned packet.
1025 *
1026 */
1027 extern SDIOH_API_RC
1028 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
1029 uint func, uint addr, uint reg_width, uint buflen_u,
1030 u8 *buffer, void *pkt)
1031 {
1032 SDIOH_API_RC Status;
1033 void *mypkt = NULL;
1034
1035 sd_trace(("%s: Enter\n", __func__));
1036
1037 DHD_PM_RESUME_WAIT(sdioh_request_buffer_wait);
1038 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
1039 /* Case 1: we don't have a packet. */
1040 if (pkt == NULL) {
1041 sd_data(("%s: Creating new %s Packet, len=%d\n",
1042 __func__, write ? "TX" : "RX", buflen_u));
1043 #ifdef DHD_USE_STATIC_BUF
1044 mypkt = PKTGET_STATIC(sd->osh, buflen_u, write ? TRUE : FALSE);
1045 #else
1046 mypkt = PKTGET(sd->osh, buflen_u, write ? TRUE : FALSE);
1047 #endif /* DHD_USE_STATIC_BUF */
1048 if (!mypkt) {
1049 sd_err(("%s: PKTGET failed: len %d\n",
1050 __func__, buflen_u));
1051 return SDIOH_API_RC_FAIL;
1052 }
1053
1054 /* For a write, copy the buffer data into the packet. */
1055 if (write)
1056 bcopy(buffer, PKTDATA(mypkt), buflen_u);
1057
1058 Status =
1059 sdioh_request_packet(sd, fix_inc, write, func, addr, mypkt);
1060
1061 /* For a read, copy the packet data back to the buffer. */
1062 if (!write)
1063 bcopy(PKTDATA(mypkt), buffer, buflen_u);
1064
1065 #ifdef DHD_USE_STATIC_BUF
1066 PKTFREE_STATIC(sd->osh, mypkt, write ? TRUE : FALSE);
1067 #else
1068 PKTFREE(sd->osh, mypkt, write ? TRUE : FALSE);
1069 #endif /* DHD_USE_STATIC_BUF */
1070 } else if (((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) != 0) {
1071 /* Case 2: We have a packet, but it is unaligned. */
1072
1073 /* In this case, we cannot have a chain. */
1074 ASSERT(PKTNEXT(pkt) == NULL);
1075
1076 sd_data(("%s: Creating aligned %s Packet, len=%d\n",
1077 __func__, write ? "TX" : "RX", PKTLEN(pkt)));
1078 #ifdef DHD_USE_STATIC_BUF
1079 mypkt = PKTGET_STATIC(sd->osh, PKTLEN(pkt),
1080 write ? TRUE : FALSE);
1081 #else
1082 mypkt = PKTGET(sd->osh, PKTLEN(pkt), write ? TRUE : FALSE);
1083 #endif /* DHD_USE_STATIC_BUF */
1084 if (!mypkt) {
1085 sd_err(("%s: PKTGET failed: len %d\n",
1086 __func__, PKTLEN(pkt)));
1087 return SDIOH_API_RC_FAIL;
1088 }
1089
1090 /* For a write, copy the buffer data into the packet. */
1091 if (write)
1092 bcopy(PKTDATA(pkt), PKTDATA(mypkt), PKTLEN(pkt));
1093
1094 Status =
1095 sdioh_request_packet(sd, fix_inc, write, func, addr, mypkt);
1096
1097 /* For a read, copy the packet data back to the buffer. */
1098 if (!write)
1099 bcopy(PKTDATA(mypkt), PKTDATA(pkt), PKTLEN(mypkt));
1100
1101 #ifdef DHD_USE_STATIC_BUF
1102 PKTFREE_STATIC(sd->osh, mypkt, write ? TRUE : FALSE);
1103 #else
1104 PKTFREE(sd->osh, mypkt, write ? TRUE : FALSE);
1105 #endif /* DHD_USE_STATIC_BUF */
1106 } else { /* case 3: We have a packet and
1107 it is aligned. */
1108 sd_data(("%s: Aligned %s Packet, direct DMA\n",
1109 __func__, write ? "Tx" : "Rx"));
1110 Status =
1111 sdioh_request_packet(sd, fix_inc, write, func, addr, pkt);
1112 }
1113
1114 return Status;
1115 }
1116
1117 /* this function performs "abort" for both of host & device */
1118 extern int sdioh_abort(sdioh_info_t *sd, uint func)
1119 {
1120 #if defined(MMC_SDIO_ABORT)
1121 char t_func = (char)func;
1122 #endif /* defined(MMC_SDIO_ABORT) */
1123 sd_trace(("%s: Enter\n", __func__));
1124
1125 #if defined(MMC_SDIO_ABORT)
1126 /* issue abort cmd52 command through F1 */
1127 sdioh_request_byte(sd, SD_IO_OP_WRITE, SDIO_FUNC_0, SDIOD_CCCR_IOABORT,
1128 &t_func);
1129 #endif /* defined(MMC_SDIO_ABORT) */
1130
1131 sd_trace(("%s: Exit\n", __func__));
1132 return SDIOH_API_RC_SUCCESS;
1133 }
1134
1135 /* Reset and re-initialize the device */
1136 int sdioh_sdio_reset(sdioh_info_t *si)
1137 {
1138 sd_trace(("%s: Enter\n", __func__));
1139 sd_trace(("%s: Exit\n", __func__));
1140 return SDIOH_API_RC_SUCCESS;
1141 }
1142
1143 /* Disable device interrupt */
1144 void sdioh_sdmmc_devintr_off(sdioh_info_t *sd)
1145 {
1146 sd_trace(("%s: %d\n", __func__, sd->use_client_ints));
1147 sd->intmask &= ~CLIENT_INTR;
1148 }
1149
1150 /* Enable device interrupt */
1151 void sdioh_sdmmc_devintr_on(sdioh_info_t *sd)
1152 {
1153 sd_trace(("%s: %d\n", __func__, sd->use_client_ints));
1154 sd->intmask |= CLIENT_INTR;
1155 }
1156
1157 /* Read client card reg */
1158 int
1159 sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
1160 int regsize, u32 *data)
1161 {
1162
1163 if ((func == 0) || (regsize == 1)) {
1164 u8 temp = 0;
1165
1166 sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
1167 *data = temp;
1168 *data &= 0xff;
1169 sd_data(("%s: byte read data=0x%02x\n", __func__, *data));
1170 } else {
1171 sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, data,
1172 regsize);
1173 if (regsize == 2)
1174 *data &= 0xffff;
1175
1176 sd_data(("%s: word read data=0x%08x\n", __func__, *data));
1177 }
1178
1179 return SUCCESS;
1180 }
1181
1182 #if !defined(OOB_INTR_ONLY)
1183 /* bcmsdh_sdmmc interrupt handler */
1184 static void IRQHandler(struct sdio_func *func)
1185 {
1186 sdioh_info_t *sd;
1187
1188 sd_trace(("bcmsdh_sdmmc: ***IRQHandler\n"));
1189 sd = gInstance->sd;
1190
1191 ASSERT(sd != NULL);
1192 sdio_release_host(gInstance->func[0]);
1193
1194 if (sd->use_client_ints) {
1195 sd->intrcount++;
1196 ASSERT(sd->intr_handler);
1197 ASSERT(sd->intr_handler_arg);
1198 (sd->intr_handler) (sd->intr_handler_arg);
1199 } else {
1200 sd_err(("bcmsdh_sdmmc: ***IRQHandler\n"));
1201
1202 sd_err(("%s: Not ready for intr: enabled %d, handler %p\n",
1203 __func__, sd->client_intr_enabled, sd->intr_handler));
1204 }
1205
1206 sdio_claim_host(gInstance->func[0]);
1207 }
1208
1209 /* bcmsdh_sdmmc interrupt handler for F2 (dummy handler) */
1210 static void IRQHandlerF2(struct sdio_func *func)
1211 {
1212 sdioh_info_t *sd;
1213
1214 sd_trace(("bcmsdh_sdmmc: ***IRQHandlerF2\n"));
1215
1216 sd = gInstance->sd;
1217
1218 ASSERT(sd != NULL);
1219 }
1220 #endif /* !defined(OOB_INTR_ONLY) */
1221
1222 #ifdef NOTUSED
1223 /* Write client card reg */
1224 static int
1225 sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, u32 regaddr,
1226 int regsize, u32 data)
1227 {
1228
1229 if ((func == 0) || (regsize == 1)) {
1230 u8 temp;
1231
1232 temp = data & 0xff;
1233 sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
1234 sd_data(("%s: byte write data=0x%02x\n", __func__, data));
1235 } else {
1236 if (regsize == 2)
1237 data &= 0xffff;
1238
1239 sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, &data,
1240 regsize);
1241
1242 sd_data(("%s: word write data=0x%08x\n", __func__, data));
1243 }
1244
1245 return SUCCESS;
1246 }
1247 #endif /* NOTUSED */
1248
1249 int sdioh_start(sdioh_info_t *si, int stage)
1250 {
1251 return 0;
1252 }
1253
1254 int sdioh_stop(sdioh_info_t *si)
1255 {
1256 return 0;
1257 }
kernel-based virtual machine