4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/uio_driver.h>
15 #include <linux/sh_timer.h>
16 #include <asm/clock.h>
18 static struct resource iic0_resources
[] = {
23 .flags
= IORESOURCE_MEM
,
28 .flags
= IORESOURCE_IRQ
,
32 static struct platform_device iic0_device
= {
33 .name
= "i2c-sh_mobile",
34 .id
= 0, /* "i2c0" clock */
35 .num_resources
= ARRAY_SIZE(iic0_resources
),
36 .resource
= iic0_resources
,
39 static struct resource iic1_resources
[] = {
44 .flags
= IORESOURCE_MEM
,
49 .flags
= IORESOURCE_IRQ
,
53 static struct platform_device iic1_device
= {
54 .name
= "i2c-sh_mobile",
55 .id
= 1, /* "i2c1" clock */
56 .num_resources
= ARRAY_SIZE(iic1_resources
),
57 .resource
= iic1_resources
,
60 static struct uio_info vpu_platform_data
= {
66 static struct resource vpu_resources
[] = {
71 .flags
= IORESOURCE_MEM
,
74 /* place holder for contiguous memory */
78 static struct platform_device vpu_device
= {
79 .name
= "uio_pdrv_genirq",
82 .platform_data
= &vpu_platform_data
,
84 .resource
= vpu_resources
,
85 .num_resources
= ARRAY_SIZE(vpu_resources
),
88 static struct uio_info veu_platform_data
= {
94 static struct resource veu_resources
[] = {
99 .flags
= IORESOURCE_MEM
,
102 /* place holder for contiguous memory */
106 static struct platform_device veu_device
= {
107 .name
= "uio_pdrv_genirq",
110 .platform_data
= &veu_platform_data
,
112 .resource
= veu_resources
,
113 .num_resources
= ARRAY_SIZE(veu_resources
),
116 static struct uio_info jpu_platform_data
= {
122 static struct resource jpu_resources
[] = {
127 .flags
= IORESOURCE_MEM
,
130 /* place holder for contiguous memory */
134 static struct platform_device jpu_device
= {
135 .name
= "uio_pdrv_genirq",
138 .platform_data
= &jpu_platform_data
,
140 .resource
= jpu_resources
,
141 .num_resources
= ARRAY_SIZE(jpu_resources
),
144 static struct sh_timer_config cmt_platform_data
= {
146 .channel_offset
= 0x60,
149 .clockevent_rating
= 125,
150 .clocksource_rating
= 200,
153 static struct resource cmt_resources
[] = {
158 .flags
= IORESOURCE_MEM
,
162 .flags
= IORESOURCE_IRQ
,
166 static struct platform_device cmt_device
= {
170 .platform_data
= &cmt_platform_data
,
172 .resource
= cmt_resources
,
173 .num_resources
= ARRAY_SIZE(cmt_resources
),
176 static struct plat_sci_port sci_platform_data
[] = {
178 .mapbase
= 0xffe00000,
179 .flags
= UPF_BOOT_AUTOCONF
,
181 .irqs
= { 80, 80, 80, 80 },
184 .mapbase
= 0xffe10000,
185 .flags
= UPF_BOOT_AUTOCONF
,
187 .irqs
= { 81, 81, 81, 81 },
190 .mapbase
= 0xffe20000,
191 .flags
= UPF_BOOT_AUTOCONF
,
193 .irqs
= { 82, 82, 82, 82 },
196 .mapbase
= 0xffe30000,
197 .flags
= UPF_BOOT_AUTOCONF
,
199 .irqs
= { 83, 83, 83, 83 },
206 static struct platform_device sci_device
= {
210 .platform_data
= sci_platform_data
,
214 static struct platform_device
*sh7343_devices
[] __initdata
= {
224 static int __init
sh7343_devices_setup(void)
226 clk_always_enable("uram0"); /* URAM */
227 clk_always_enable("xymem0"); /* XYMEM */
228 clk_always_enable("veu0"); /* VEU */
229 clk_always_enable("vpu0"); /* VPU */
230 clk_always_enable("jpu0"); /* JPU */
232 platform_resource_setup_memory(&vpu_device
, "vpu", 1 << 20);
233 platform_resource_setup_memory(&veu_device
, "veu", 2 << 20);
234 platform_resource_setup_memory(&jpu_device
, "jpu", 2 << 20);
236 return platform_add_devices(sh7343_devices
,
237 ARRAY_SIZE(sh7343_devices
));
239 __initcall(sh7343_devices_setup
);
241 static struct platform_device
*sh7343_early_devices
[] __initdata
= {
245 void __init
plat_early_device_setup(void)
247 early_platform_add_devices(sh7343_early_devices
,
248 ARRAY_SIZE(sh7343_early_devices
));
254 /* interrupt sources */
255 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
256 DMAC0
, DMAC1
, DMAC2
, DMAC3
,
257 VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
,
258 MFI
, VPU
, TPU
, Z3D4
, USBI0
, USBI1
,
259 MMC_ERR
, MMC_TRAN
, MMC_FSTAT
, MMC_FRDY
,
260 DMAC4
, DMAC5
, DMAC_DADERR
,
262 SCIF
, SCIF1
, SCIF2
, SCIF3
,
264 FLCTL_FLSTEI
, FLCTL_FLENDI
, FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
,
265 I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
,
266 I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
,
267 SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
,
269 SDHI0
, SDHI1
, SDHI2
, SDHI3
,
274 /* interrupt groups */
276 DMAC0123
, VIOVOU
, MMC
, DMAC45
, FLCTL
, I2C0
, I2C1
, SIM
, SDHI
, USB
,
279 static struct intc_vect vectors
[] __initdata
= {
280 INTC_VECT(IRQ0
, 0x600), INTC_VECT(IRQ1
, 0x620),
281 INTC_VECT(IRQ2
, 0x640), INTC_VECT(IRQ3
, 0x660),
282 INTC_VECT(IRQ4
, 0x680), INTC_VECT(IRQ5
, 0x6a0),
283 INTC_VECT(IRQ6
, 0x6c0), INTC_VECT(IRQ7
, 0x6e0),
284 INTC_VECT(I2C1_ALI
, 0x780), INTC_VECT(I2C1_TACKI
, 0x7a0),
285 INTC_VECT(I2C1_WAITI
, 0x7c0), INTC_VECT(I2C1_DTEI
, 0x7e0),
286 INTC_VECT(DMAC0
, 0x800), INTC_VECT(DMAC1
, 0x820),
287 INTC_VECT(DMAC2
, 0x840), INTC_VECT(DMAC3
, 0x860),
288 INTC_VECT(VIO_CEUI
, 0x880), INTC_VECT(VIO_BEUI
, 0x8a0),
289 INTC_VECT(VIO_VEUI
, 0x8c0), INTC_VECT(VOU
, 0x8e0),
290 INTC_VECT(MFI
, 0x900), INTC_VECT(VPU
, 0x980),
291 INTC_VECT(TPU
, 0x9a0), INTC_VECT(Z3D4
, 0x9e0),
292 INTC_VECT(USBI0
, 0xa20), INTC_VECT(USBI1
, 0xa40),
293 INTC_VECT(MMC_ERR
, 0xb00), INTC_VECT(MMC_TRAN
, 0xb20),
294 INTC_VECT(MMC_FSTAT
, 0xb40), INTC_VECT(MMC_FRDY
, 0xb60),
295 INTC_VECT(DMAC4
, 0xb80), INTC_VECT(DMAC5
, 0xba0),
296 INTC_VECT(DMAC_DADERR
, 0xbc0), INTC_VECT(KEYSC
, 0xbe0),
297 INTC_VECT(SCIF
, 0xc00), INTC_VECT(SCIF1
, 0xc20),
298 INTC_VECT(SCIF2
, 0xc40), INTC_VECT(SCIF3
, 0xc60),
299 INTC_VECT(SIOF0
, 0xc80), INTC_VECT(SIOF1
, 0xca0),
300 INTC_VECT(SIO
, 0xd00),
301 INTC_VECT(FLCTL_FLSTEI
, 0xd80), INTC_VECT(FLCTL_FLENDI
, 0xda0),
302 INTC_VECT(FLCTL_FLTREQ0I
, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I
, 0xde0),
303 INTC_VECT(I2C0_ALI
, 0xe00), INTC_VECT(I2C0_TACKI
, 0xe20),
304 INTC_VECT(I2C0_WAITI
, 0xe40), INTC_VECT(I2C0_DTEI
, 0xe60),
305 INTC_VECT(SDHI0
, 0xe80), INTC_VECT(SDHI1
, 0xea0),
306 INTC_VECT(SDHI2
, 0xec0), INTC_VECT(SDHI3
, 0xee0),
307 INTC_VECT(CMT
, 0xf00), INTC_VECT(TSIF
, 0xf20),
308 INTC_VECT(SIU
, 0xf80),
309 INTC_VECT(TMU0
, 0x400), INTC_VECT(TMU1
, 0x420),
310 INTC_VECT(TMU2
, 0x440),
311 INTC_VECT(JPU
, 0x560), INTC_VECT(LCDC
, 0x580),
314 static struct intc_group groups
[] __initdata
= {
315 INTC_GROUP(DMAC0123
, DMAC0
, DMAC1
, DMAC2
, DMAC3
),
316 INTC_GROUP(VIOVOU
, VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
),
317 INTC_GROUP(MMC
, MMC_FRDY
, MMC_FSTAT
, MMC_TRAN
, MMC_ERR
),
318 INTC_GROUP(DMAC45
, DMAC4
, DMAC5
, DMAC_DADERR
),
319 INTC_GROUP(FLCTL
, FLCTL_FLSTEI
, FLCTL_FLENDI
,
320 FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
),
321 INTC_GROUP(I2C0
, I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
),
322 INTC_GROUP(I2C1
, I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
),
323 INTC_GROUP(SIM
, SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
),
324 INTC_GROUP(SDHI
, SDHI0
, SDHI1
, SDHI2
, SDHI3
),
325 INTC_GROUP(USB
, USBI0
, USBI1
),
328 static struct intc_mask_reg mask_registers
[] __initdata
= {
329 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
330 { VOU
, VIO_VEUI
, VIO_BEUI
, VIO_CEUI
, DMAC3
, DMAC2
, DMAC1
, DMAC0
} },
331 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
332 { 0, 0, 0, VPU
, 0, 0, 0, MFI
} },
333 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
334 { SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
, 0, 0, 0, IRDA
} },
335 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
336 { 0, TMU2
, TMU1
, TMU0
, JPU
, 0, 0, LCDC
} },
337 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
338 { KEYSC
, DMAC_DADERR
, DMAC5
, DMAC4
, SCIF3
, SCIF2
, SCIF1
, SCIF
} },
339 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
340 { 0, 0, 0, SIO
, Z3D4
, 0, SIOF1
, SIOF0
} },
341 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
342 { I2C0_DTEI
, I2C0_WAITI
, I2C0_TACKI
, I2C0_ALI
,
343 FLCTL_FLTREQ1I
, FLCTL_FLTREQ0I
, FLCTL_FLENDI
, FLCTL_FLSTEI
} },
344 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
345 { SDHI3
, SDHI2
, SDHI1
, SDHI0
, 0, 0, 0, SIU
} },
346 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
347 { 0, 0, 0, CMT
, 0, USBI1
, USBI0
} },
348 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
349 { MMC_FRDY
, MMC_FSTAT
, MMC_TRAN
, MMC_ERR
} },
350 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
351 { I2C1_DTEI
, I2C1_WAITI
, I2C1_TACKI
, I2C1_ALI
, TPU
, 0, 0, TSIF
} },
352 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
353 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
356 static struct intc_prio_reg prio_registers
[] __initdata
= {
357 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0
, TMU1
, TMU2
} },
358 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU
, LCDC
, SIM
} },
359 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123
, VIOVOU
, MFI
, VPU
} },
360 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC
, DMAC45
, USB
, CMT
} },
361 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF
, SCIF1
, SCIF2
, SCIF3
} },
362 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0
, SIOF1
, FLCTL
, I2C0
} },
363 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO
, 0, TSIF
, I2C1
} },
364 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4
, 0, SIU
} },
365 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC
, 0, SDHI
} },
366 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU
} },
367 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
368 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
371 static struct intc_sense_reg sense_registers
[] __initdata
= {
372 { 0xa414001c, 16, 2, /* ICR1 */
373 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
376 static struct intc_mask_reg ack_registers
[] __initdata
= {
377 { 0xa4140024, 0, 8, /* INTREQ00 */
378 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
381 static DECLARE_INTC_DESC_ACK(intc_desc
, "sh7343", vectors
, groups
,
382 mask_registers
, prio_registers
, sense_registers
,
385 void __init
plat_irq_setup(void)
387 register_intc_controller(&intc_desc
);