1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
57 #include <linux/netdevice.h>
58 #include <linux/ethtool.h>
59 #include <linux/delay.h>
60 #include <linux/pci.h>
64 #define ICH_FLASH_GFPREG 0x0000
65 #define ICH_FLASH_HSFSTS 0x0004
66 #define ICH_FLASH_HSFCTL 0x0006
67 #define ICH_FLASH_FADDR 0x0008
68 #define ICH_FLASH_FDATA0 0x0010
69 #define ICH_FLASH_PR0 0x0074
71 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
74 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
75 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
77 #define ICH_CYCLE_READ 0
78 #define ICH_CYCLE_WRITE 2
79 #define ICH_CYCLE_ERASE 3
81 #define FLASH_GFPREG_BASE_MASK 0x1FFF
82 #define FLASH_SECTOR_ADDR_SHIFT 12
84 #define ICH_FLASH_SEG_SIZE_256 256
85 #define ICH_FLASH_SEG_SIZE_4K 4096
86 #define ICH_FLASH_SEG_SIZE_8K 8192
87 #define ICH_FLASH_SEG_SIZE_64K 65536
90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
92 #define E1000_ICH_MNG_IAMT_MODE 0x2
94 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
95 (ID_LED_DEF1_OFF2 << 8) | \
96 (ID_LED_DEF1_ON2 << 4) | \
99 #define E1000_ICH_NVM_SIG_WORD 0x13
100 #define E1000_ICH_NVM_SIG_MASK 0xC000
101 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
102 #define E1000_ICH_NVM_SIG_VALUE 0x80
104 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
106 #define E1000_FEXTNVM_SW_CONFIG 1
107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
109 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
111 #define E1000_ICH_RAR_ENTRIES 7
113 #define PHY_PAGE_SHIFT 5
114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
115 ((reg) & MAX_PHY_REG_ADDRESS))
116 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
117 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
121 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
123 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
125 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
126 /* Offset 04h HSFSTS */
127 union ich8_hws_flash_status
{
129 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
130 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
131 u16 dael
:1; /* bit 2 Direct Access error Log */
132 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
133 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
134 u16 reserved1
:2; /* bit 13:6 Reserved */
135 u16 reserved2
:6; /* bit 13:6 Reserved */
136 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
137 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
142 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
143 /* Offset 06h FLCTL */
144 union ich8_hws_flash_ctrl
{
145 struct ich8_hsflctl
{
146 u16 flcgo
:1; /* 0 Flash Cycle Go */
147 u16 flcycle
:2; /* 2:1 Flash Cycle */
148 u16 reserved
:5; /* 7:3 Reserved */
149 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
150 u16 flockdn
:6; /* 15:10 Reserved */
155 /* ICH Flash Region Access Permissions */
156 union ich8_hws_flash_regacc
{
158 u32 grra
:8; /* 0:7 GbE region Read Access */
159 u32 grwa
:8; /* 8:15 GbE region Write Access */
160 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
161 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
166 /* ICH Flash Protected Region */
167 union ich8_flash_protected_range
{
169 u32 base
:13; /* 0:12 Protected Range Base */
170 u32 reserved1
:2; /* 13:14 Reserved */
171 u32 rpe
:1; /* 15 Read Protection Enable */
172 u32 limit
:13; /* 16:28 Protected Range Limit */
173 u32 reserved2
:2; /* 29:30 Reserved */
174 u32 wpe
:1; /* 31 Write Protection Enable */
179 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
180 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
181 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
182 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
);
183 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
184 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
185 u32 offset
, u8 byte
);
186 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
188 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
190 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
192 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
193 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
194 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
195 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
196 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
197 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
198 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
199 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
200 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
201 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
202 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
204 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
206 return readw(hw
->flash_address
+ reg
);
209 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
211 return readl(hw
->flash_address
+ reg
);
214 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
216 writew(val
, hw
->flash_address
+ reg
);
219 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
221 writel(val
, hw
->flash_address
+ reg
);
224 #define er16flash(reg) __er16flash(hw, (reg))
225 #define er32flash(reg) __er32flash(hw, (reg))
226 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
227 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
230 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
231 * @hw: pointer to the HW structure
233 * Initialize family-specific PHY parameters and function pointers.
235 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
237 struct e1000_phy_info
*phy
= &hw
->phy
;
241 phy
->reset_delay_us
= 100;
243 phy
->ops
.check_polarity
= e1000_check_polarity_ife_ich8lan
;
244 phy
->ops
.read_phy_reg
= e1000_read_phy_reg_hv
;
245 phy
->ops
.write_phy_reg
= e1000_write_phy_reg_hv
;
246 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
248 phy
->id
= e1000_phy_unknown
;
249 e1000e_get_phy_id(hw
);
250 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
252 if (phy
->type
== e1000_phy_82577
) {
253 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
254 phy
->ops
.force_speed_duplex
=
255 e1000_phy_force_speed_duplex_82577
;
256 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
257 phy
->ops
.get_phy_info
= e1000_get_phy_info_82577
;
258 phy
->ops
.commit_phy
= e1000e_phy_sw_reset
;
265 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
266 * @hw: pointer to the HW structure
268 * Initialize family-specific PHY parameters and function pointers.
270 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
272 struct e1000_phy_info
*phy
= &hw
->phy
;
277 phy
->reset_delay_us
= 100;
280 * We may need to do this twice - once for IGP and if that fails,
281 * we'll set BM func pointers and try again
283 ret_val
= e1000e_determine_phy_address(hw
);
285 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
286 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
287 ret_val
= e1000e_determine_phy_address(hw
);
293 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
296 ret_val
= e1000e_get_phy_id(hw
);
303 case IGP03E1000_E_PHY_ID
:
304 phy
->type
= e1000_phy_igp_3
;
305 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
308 case IFE_PLUS_E_PHY_ID
:
310 phy
->type
= e1000_phy_ife
;
311 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
313 case BME1000_E_PHY_ID
:
314 phy
->type
= e1000_phy_bm
;
315 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
316 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
317 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
318 hw
->phy
.ops
.commit_phy
= e1000e_phy_sw_reset
;
321 return -E1000_ERR_PHY
;
325 phy
->ops
.check_polarity
= e1000_check_polarity_ife_ich8lan
;
331 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
332 * @hw: pointer to the HW structure
334 * Initialize family-specific NVM parameters and function
337 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
339 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
340 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
341 union ich8_hws_flash_status hsfsts
;
343 u32 sector_base_addr
;
347 /* Can't read flash registers if the register set isn't mapped. */
348 if (!hw
->flash_address
) {
349 hw_dbg(hw
, "ERROR: Flash registers not mapped\n");
350 return -E1000_ERR_CONFIG
;
353 nvm
->type
= e1000_nvm_flash_sw
;
355 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
358 * sector_X_addr is a "sector"-aligned address (4096 bytes)
359 * Add 1 to sector_end_addr since this sector is included in
362 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
363 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
365 /* flash_base_addr is byte-aligned */
366 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
369 * find total size of the NVM, then cut in half since the total
370 * size represents two separate NVM banks.
372 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
373 << FLASH_SECTOR_ADDR_SHIFT
;
374 nvm
->flash_bank_size
/= 2;
375 /* Adjust to word count */
376 nvm
->flash_bank_size
/= sizeof(u16
);
379 * Make sure the flash bank size does not overwrite the 4k
380 * sector ranges. We may have 64k allotted to us but we only care
381 * about the first 2 4k sectors. Therefore, if we have anything less
382 * than 64k set in the HSFSTS register, we will reduce the bank size
383 * down to 4k and let the rest remain unused. If berasesz == 3, then
384 * we are working in 64k mode. Otherwise we are not.
386 if (nvm
->flash_bank_size
> E1000_ICH8_SHADOW_RAM_WORDS
) {
387 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
388 if (hsfsts
.hsf_status
.berasesz
!= 3)
389 nvm
->flash_bank_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
392 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
394 /* Clear shadow ram */
395 for (i
= 0; i
< nvm
->word_size
; i
++) {
396 dev_spec
->shadow_ram
[i
].modified
= 0;
397 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
404 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
405 * @hw: pointer to the HW structure
407 * Initialize family-specific MAC parameters and function
410 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
412 struct e1000_hw
*hw
= &adapter
->hw
;
413 struct e1000_mac_info
*mac
= &hw
->mac
;
415 /* Set media type function pointer */
416 hw
->phy
.media_type
= e1000_media_type_copper
;
418 /* Set mta register count */
419 mac
->mta_reg_count
= 32;
420 /* Set rar entry count */
421 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
422 if (mac
->type
== e1000_ich8lan
)
423 mac
->rar_entry_count
--;
424 /* Set if manageability features are enabled. */
425 mac
->arc_subsystem_valid
= 1;
433 mac
->ops
.id_led_init
= e1000e_id_led_init
;
435 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
437 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
438 /* turn on/off LED */
439 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
440 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
444 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
446 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
448 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
449 /* turn on/off LED */
450 mac
->ops
.led_on
= e1000_led_on_pchlan
;
451 mac
->ops
.led_off
= e1000_led_off_pchlan
;
457 /* Enable PCS Lock-loss workaround for ICH8 */
458 if (mac
->type
== e1000_ich8lan
)
459 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, 1);
465 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
466 * @hw: pointer to the HW structure
468 * Checks to see of the link status of the hardware has changed. If a
469 * change in link status has been detected, then we read the PHY registers
470 * to get the current speed/duplex if link exists.
472 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
474 struct e1000_mac_info
*mac
= &hw
->mac
;
479 * We only want to go out to the PHY registers to see if Auto-Neg
480 * has completed and/or if our link status has changed. The
481 * get_link_status flag is set upon receiving a Link Status
482 * Change or Rx Sequence Error interrupt.
484 if (!mac
->get_link_status
) {
489 if (hw
->mac
.type
== e1000_pchlan
) {
490 ret_val
= e1000e_write_kmrn_reg(hw
,
491 E1000_KMRNCTRLSTA_K1_CONFIG
,
492 E1000_KMRNCTRLSTA_K1_ENABLE
);
498 * First we want to see if the MII Status Register reports
499 * link. If so, then we want to get the current speed/duplex
502 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
507 goto out
; /* No link detected */
509 mac
->get_link_status
= false;
511 if (hw
->phy
.type
== e1000_phy_82578
) {
512 ret_val
= e1000_link_stall_workaround_hv(hw
);
518 * Check if there was DownShift, must be checked
519 * immediately after link-up
521 e1000e_check_downshift(hw
);
524 * If we are forcing speed/duplex, then we simply return since
525 * we have already determined whether we have link or not.
528 ret_val
= -E1000_ERR_CONFIG
;
533 * Auto-Neg is enabled. Auto Speed Detection takes care
534 * of MAC speed/duplex configuration. So we only need to
535 * configure Collision Distance in the MAC.
537 e1000e_config_collision_dist(hw
);
540 * Configure Flow Control now that Auto-Neg has completed.
541 * First, we need to restore the desired flow control
542 * settings because we may have had to re-autoneg with a
543 * different link partner.
545 ret_val
= e1000e_config_fc_after_link_up(hw
);
547 hw_dbg(hw
, "Error configuring flow control\n");
553 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
555 struct e1000_hw
*hw
= &adapter
->hw
;
558 rc
= e1000_init_mac_params_ich8lan(adapter
);
562 rc
= e1000_init_nvm_params_ich8lan(hw
);
566 if (hw
->mac
.type
== e1000_pchlan
)
567 rc
= e1000_init_phy_params_pchlan(hw
);
569 rc
= e1000_init_phy_params_ich8lan(hw
);
573 if (adapter
->hw
.phy
.type
== e1000_phy_ife
) {
574 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
575 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
578 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
579 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
580 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
585 static DEFINE_MUTEX(nvm_mutex
);
588 * e1000_acquire_swflag_ich8lan - Acquire software control flag
589 * @hw: pointer to the HW structure
591 * Acquires the software control flag for performing NVM and PHY
592 * operations. This is a function pointer entry point only called by
593 * read/write routines for the PHY and NVM parts.
595 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
597 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
602 mutex_lock(&nvm_mutex
);
605 extcnf_ctrl
= er32(EXTCNF_CTRL
);
606 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
614 hw_dbg(hw
, "SW/FW/HW has locked the resource for too long.\n");
615 ret_val
= -E1000_ERR_CONFIG
;
619 timeout
= PHY_CFG_TIMEOUT
* 2;
621 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
622 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
625 extcnf_ctrl
= er32(EXTCNF_CTRL
);
626 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
634 hw_dbg(hw
, "Failed to acquire the semaphore.\n");
635 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
636 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
637 ret_val
= -E1000_ERR_CONFIG
;
643 mutex_unlock(&nvm_mutex
);
649 * e1000_release_swflag_ich8lan - Release software control flag
650 * @hw: pointer to the HW structure
652 * Releases the software control flag for performing NVM and PHY operations.
653 * This is a function pointer entry point only called by read/write
654 * routines for the PHY and NVM parts.
656 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
660 extcnf_ctrl
= er32(EXTCNF_CTRL
);
661 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
662 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
664 mutex_unlock(&nvm_mutex
);
668 * e1000_check_mng_mode_ich8lan - Checks management mode
669 * @hw: pointer to the HW structure
671 * This checks if the adapter has manageability enabled.
672 * This is a function pointer entry point only called by read/write
673 * routines for the PHY and NVM parts.
675 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
677 u32 fwsm
= er32(FWSM
);
679 return (fwsm
& E1000_FWSM_MODE_MASK
) ==
680 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
);
684 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
685 * @hw: pointer to the HW structure
687 * Checks if firmware is blocking the reset of the PHY.
688 * This is a function pointer entry point only called by
691 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
697 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
701 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
702 * @hw: pointer to the HW structure
704 * Forces the speed and duplex settings of the PHY.
705 * This is a function pointer entry point only called by
706 * PHY setup routines.
708 static s32
e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw
*hw
)
710 struct e1000_phy_info
*phy
= &hw
->phy
;
715 if (phy
->type
!= e1000_phy_ife
) {
716 ret_val
= e1000e_phy_force_speed_duplex_igp(hw
);
720 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &data
);
724 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
726 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, data
);
730 /* Disable MDI-X support for 10/100 */
731 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
735 data
&= ~IFE_PMC_AUTO_MDIX
;
736 data
&= ~IFE_PMC_FORCE_MDIX
;
738 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
742 hw_dbg(hw
, "IFE PMC: %X\n", data
);
746 if (phy
->autoneg_wait_to_complete
) {
747 hw_dbg(hw
, "Waiting for forced speed/duplex link on IFE phy.\n");
749 ret_val
= e1000e_phy_has_link_generic(hw
,
757 hw_dbg(hw
, "Link taking longer than expected.\n");
760 ret_val
= e1000e_phy_has_link_generic(hw
,
772 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
773 * done after every PHY reset.
775 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
779 if (hw
->mac
.type
!= e1000_pchlan
)
782 if (((hw
->phy
.type
== e1000_phy_82577
) &&
783 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
784 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
785 /* Disable generation of early preamble */
786 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
790 /* Preamble tuning for SSC */
791 ret_val
= e1e_wphy(hw
, PHY_REG(770, 16), 0xA204);
796 if (hw
->phy
.type
== e1000_phy_82578
) {
798 * Return registers to default by doing a soft reset then
799 * writing 0x3140 to the control register.
801 if (hw
->phy
.revision
< 2) {
802 e1000e_phy_sw_reset(hw
);
803 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, 0x3140);
808 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
812 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
813 hw
->phy
.ops
.release_phy(hw
);
819 * e1000_lan_init_done_ich8lan - Check for PHY config completion
820 * @hw: pointer to the HW structure
822 * Check the appropriate indication the MAC has finished configuring the
823 * PHY after a software reset.
825 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
827 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
829 /* Wait for basic configuration completes before proceeding */
832 data
&= E1000_STATUS_LAN_INIT_DONE
;
834 } while ((!data
) && --loop
);
837 * If basic configuration is incomplete before the above loop
838 * count reaches 0, loading the configuration from NVM will
839 * leave the PHY in a bad state possibly resulting in no link.
842 hw_dbg(hw
, "LAN_INIT_DONE not set, increase timeout\n");
844 /* Clear the Init Done bit for the next init event */
846 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
851 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
852 * @hw: pointer to the HW structure
855 * This is a function pointer entry point called by drivers
856 * or other shared routines.
858 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
860 struct e1000_phy_info
*phy
= &hw
->phy
;
862 u32 data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
864 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
866 ret_val
= e1000e_phy_hw_reset_generic(hw
);
870 /* Allow time for h/w to get to a quiescent state after reset */
873 if (hw
->mac
.type
== e1000_pchlan
) {
874 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
880 * Initialize the PHY from the NVM on ICH platforms. This
881 * is needed due to an issue where the NVM configuration is
882 * not properly autoloaded after power transitions.
883 * Therefore, after each PHY reset, we will load the
884 * configuration data out of the NVM manually.
886 if (hw
->mac
.type
== e1000_ich8lan
&& phy
->type
== e1000_phy_igp_3
) {
887 struct e1000_adapter
*adapter
= hw
->adapter
;
889 /* Check if SW needs configure the PHY */
890 if ((adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M_AMT
) ||
891 (adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M
))
892 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
894 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
896 data
= er32(FEXTNVM
);
897 if (!(data
& sw_cfg_mask
))
900 /* Wait for basic configuration completes before proceeding */
901 e1000_lan_init_done_ich8lan(hw
);
904 * Make sure HW does not configure LCD from PHY
905 * extended configuration before SW configuration
907 data
= er32(EXTCNF_CTRL
);
908 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
911 cnf_size
= er32(EXTCNF_SIZE
);
912 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
913 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
917 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
918 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
920 /* Configure LCD from extended configuration region. */
922 /* cnf_base_addr is in DWORD */
923 word_addr
= (u16
)(cnf_base_addr
<< 1);
925 for (i
= 0; i
< cnf_size
; i
++) {
926 ret_val
= e1000_read_nvm(hw
,
933 ret_val
= e1000_read_nvm(hw
,
934 (word_addr
+ i
* 2 + 1),
940 /* Save off the PHY page for future writes. */
941 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
946 reg_addr
|= phy_page
;
948 ret_val
= e1e_wphy(hw
, (u32
)reg_addr
, reg_data
);
958 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
959 * @hw: pointer to the HW structure
961 * Populates "phy" structure with various feature states.
962 * This function is only called by other family-specific
965 static s32
e1000_get_phy_info_ife_ich8lan(struct e1000_hw
*hw
)
967 struct e1000_phy_info
*phy
= &hw
->phy
;
972 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
977 hw_dbg(hw
, "Phy info is only valid if link is up\n");
978 return -E1000_ERR_CONFIG
;
981 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
984 phy
->polarity_correction
= (!(data
& IFE_PSC_AUTO_POLARITY_DISABLE
));
986 if (phy
->polarity_correction
) {
987 ret_val
= phy
->ops
.check_polarity(hw
);
991 /* Polarity is forced */
992 phy
->cable_polarity
= (data
& IFE_PSC_FORCE_POLARITY
)
993 ? e1000_rev_polarity_reversed
994 : e1000_rev_polarity_normal
;
997 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
1001 phy
->is_mdix
= (data
& IFE_PMC_MDIX_STATUS
);
1003 /* The following parameters are undefined for 10/100 operation. */
1004 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1005 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1006 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1012 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1013 * @hw: pointer to the HW structure
1015 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1016 * This is a function pointer entry point called by drivers
1017 * or other shared routines.
1019 static s32
e1000_get_phy_info_ich8lan(struct e1000_hw
*hw
)
1021 switch (hw
->phy
.type
) {
1023 return e1000_get_phy_info_ife_ich8lan(hw
);
1025 case e1000_phy_igp_3
:
1027 case e1000_phy_82578
:
1028 case e1000_phy_82577
:
1029 return e1000e_get_phy_info_igp(hw
);
1035 return -E1000_ERR_PHY_TYPE
;
1039 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1040 * @hw: pointer to the HW structure
1042 * Polarity is determined on the polarity reversal feature being enabled.
1043 * This function is only called by other family-specific
1046 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
)
1048 struct e1000_phy_info
*phy
= &hw
->phy
;
1050 u16 phy_data
, offset
, mask
;
1053 * Polarity is determined based on the reversal feature being enabled.
1055 if (phy
->polarity_correction
) {
1056 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
1057 mask
= IFE_PESC_POLARITY_REVERSED
;
1059 offset
= IFE_PHY_SPECIAL_CONTROL
;
1060 mask
= IFE_PSC_FORCE_POLARITY
;
1063 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1066 phy
->cable_polarity
= (phy_data
& mask
)
1067 ? e1000_rev_polarity_reversed
1068 : e1000_rev_polarity_normal
;
1074 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1075 * @hw: pointer to the HW structure
1076 * @active: TRUE to enable LPLU, FALSE to disable
1078 * Sets the LPLU D0 state according to the active flag. When
1079 * activating LPLU this function also disables smart speed
1080 * and vice versa. LPLU will not be activated unless the
1081 * device autonegotiation advertisement meets standards of
1082 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1083 * This is a function pointer entry point only called by
1084 * PHY setup routines.
1086 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1088 struct e1000_phy_info
*phy
= &hw
->phy
;
1093 if (phy
->type
== e1000_phy_ife
)
1096 phy_ctrl
= er32(PHY_CTRL
);
1099 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
1100 ew32(PHY_CTRL
, phy_ctrl
);
1102 if (phy
->type
!= e1000_phy_igp_3
)
1106 * Call gig speed drop workaround on LPLU before accessing
1109 if (hw
->mac
.type
== e1000_ich8lan
)
1110 e1000e_gig_downshift_workaround_ich8lan(hw
);
1112 /* When LPLU is enabled, we should disable SmartSpeed */
1113 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1114 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1115 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1119 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
1120 ew32(PHY_CTRL
, phy_ctrl
);
1122 if (phy
->type
!= e1000_phy_igp_3
)
1126 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1127 * during Dx states where the power conservation is most
1128 * important. During driver activity we should enable
1129 * SmartSpeed, so performance is maintained.
1131 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1132 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1137 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1138 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1142 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1143 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1148 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1149 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1160 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1161 * @hw: pointer to the HW structure
1162 * @active: TRUE to enable LPLU, FALSE to disable
1164 * Sets the LPLU D3 state according to the active flag. When
1165 * activating LPLU this function also disables smart speed
1166 * and vice versa. LPLU will not be activated unless the
1167 * device autonegotiation advertisement meets standards of
1168 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1169 * This is a function pointer entry point only called by
1170 * PHY setup routines.
1172 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1174 struct e1000_phy_info
*phy
= &hw
->phy
;
1179 phy_ctrl
= er32(PHY_CTRL
);
1182 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
1183 ew32(PHY_CTRL
, phy_ctrl
);
1185 if (phy
->type
!= e1000_phy_igp_3
)
1189 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1190 * during Dx states where the power conservation is most
1191 * important. During driver activity we should enable
1192 * SmartSpeed, so performance is maintained.
1194 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1195 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1200 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1201 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1205 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1206 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1211 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1212 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1217 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1218 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1219 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1220 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
1221 ew32(PHY_CTRL
, phy_ctrl
);
1223 if (phy
->type
!= e1000_phy_igp_3
)
1227 * Call gig speed drop workaround on LPLU before accessing
1230 if (hw
->mac
.type
== e1000_ich8lan
)
1231 e1000e_gig_downshift_workaround_ich8lan(hw
);
1233 /* When LPLU is enabled, we should disable SmartSpeed */
1234 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1238 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1239 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1246 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1247 * @hw: pointer to the HW structure
1248 * @bank: pointer to the variable that returns the active bank
1250 * Reads signature byte from the NVM using the flash access registers.
1251 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1253 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
1256 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1257 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
1258 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
1262 switch (hw
->mac
.type
) {
1266 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
1267 E1000_EECD_SEC1VAL_VALID_MASK
) {
1268 if (eecd
& E1000_EECD_SEC1VAL
)
1275 hw_dbg(hw
, "Unable to determine valid NVM bank via EEC - "
1276 "reading flash signature\n");
1279 /* set bank to 0 in case flash read fails */
1283 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
1287 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1288 E1000_ICH_NVM_SIG_VALUE
) {
1294 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
1299 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1300 E1000_ICH_NVM_SIG_VALUE
) {
1305 hw_dbg(hw
, "ERROR: No valid NVM bank present\n");
1306 return -E1000_ERR_NVM
;
1313 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1314 * @hw: pointer to the HW structure
1315 * @offset: The offset (in bytes) of the word(s) to read.
1316 * @words: Size of data to read in words
1317 * @data: Pointer to the word(s) to read at offset.
1319 * Reads a word(s) from the NVM using the flash access registers.
1321 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1324 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1325 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1331 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1333 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1334 return -E1000_ERR_NVM
;
1337 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1341 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1345 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
1346 act_offset
+= offset
;
1348 for (i
= 0; i
< words
; i
++) {
1349 if ((dev_spec
->shadow_ram
) &&
1350 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
1351 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
1353 ret_val
= e1000_read_flash_word_ich8lan(hw
,
1363 e1000_release_swflag_ich8lan(hw
);
1367 hw_dbg(hw
, "NVM read error: %d\n", ret_val
);
1373 * e1000_flash_cycle_init_ich8lan - Initialize flash
1374 * @hw: pointer to the HW structure
1376 * This function does initial flash setup so that a new read/write/erase cycle
1379 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
1381 union ich8_hws_flash_status hsfsts
;
1382 s32 ret_val
= -E1000_ERR_NVM
;
1385 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1387 /* Check if the flash descriptor is valid */
1388 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
1389 hw_dbg(hw
, "Flash descriptor invalid. "
1390 "SW Sequencing must be used.");
1391 return -E1000_ERR_NVM
;
1394 /* Clear FCERR and DAEL in hw status by writing 1 */
1395 hsfsts
.hsf_status
.flcerr
= 1;
1396 hsfsts
.hsf_status
.dael
= 1;
1398 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1401 * Either we should have a hardware SPI cycle in progress
1402 * bit to check against, in order to start a new cycle or
1403 * FDONE bit should be changed in the hardware so that it
1404 * is 1 after hardware reset, which can then be used as an
1405 * indication whether a cycle is in progress or has been
1409 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1411 * There is no cycle running at present,
1412 * so we can start a cycle
1413 * Begin by setting Flash Cycle Done.
1415 hsfsts
.hsf_status
.flcdone
= 1;
1416 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1420 * otherwise poll for sometime so the current
1421 * cycle has a chance to end before giving up.
1423 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
1424 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
1425 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1433 * Successful in waiting for previous cycle to timeout,
1434 * now set the Flash Cycle Done.
1436 hsfsts
.hsf_status
.flcdone
= 1;
1437 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1439 hw_dbg(hw
, "Flash controller busy, cannot get access");
1447 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1448 * @hw: pointer to the HW structure
1449 * @timeout: maximum time to wait for completion
1451 * This function starts a flash cycle and waits for its completion.
1453 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
1455 union ich8_hws_flash_ctrl hsflctl
;
1456 union ich8_hws_flash_status hsfsts
;
1457 s32 ret_val
= -E1000_ERR_NVM
;
1460 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1461 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1462 hsflctl
.hsf_ctrl
.flcgo
= 1;
1463 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1465 /* wait till FDONE bit is set to 1 */
1467 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1468 if (hsfsts
.hsf_status
.flcdone
== 1)
1471 } while (i
++ < timeout
);
1473 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
1480 * e1000_read_flash_word_ich8lan - Read word from flash
1481 * @hw: pointer to the HW structure
1482 * @offset: offset to data location
1483 * @data: pointer to the location for storing the data
1485 * Reads the flash word at offset into data. Offset is converted
1486 * to bytes before read.
1488 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1491 /* Must convert offset into bytes. */
1494 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
1498 * e1000_read_flash_byte_ich8lan - Read byte from flash
1499 * @hw: pointer to the HW structure
1500 * @offset: The offset of the byte to read.
1501 * @data: Pointer to a byte to store the value read.
1503 * Reads a single byte from the NVM using the flash access registers.
1505 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1511 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
1521 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1522 * @hw: pointer to the HW structure
1523 * @offset: The offset (in bytes) of the byte or word to read.
1524 * @size: Size of data to read, 1=byte 2=word
1525 * @data: Pointer to the word to store the value read.
1527 * Reads a byte or word from the NVM using the flash access registers.
1529 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1532 union ich8_hws_flash_status hsfsts
;
1533 union ich8_hws_flash_ctrl hsflctl
;
1534 u32 flash_linear_addr
;
1536 s32 ret_val
= -E1000_ERR_NVM
;
1539 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1540 return -E1000_ERR_NVM
;
1542 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1543 hw
->nvm
.flash_base_addr
;
1548 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1552 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1553 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1554 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
1555 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
1556 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1558 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1560 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1561 ICH_FLASH_READ_COMMAND_TIMEOUT
);
1564 * Check if FCERR is set to 1, if set to 1, clear it
1565 * and try the whole sequence a few more times, else
1566 * read in (shift in) the Flash Data0, the order is
1567 * least significant byte first msb to lsb
1570 flash_data
= er32flash(ICH_FLASH_FDATA0
);
1572 *data
= (u8
)(flash_data
& 0x000000FF);
1573 } else if (size
== 2) {
1574 *data
= (u16
)(flash_data
& 0x0000FFFF);
1579 * If we've gotten here, then things are probably
1580 * completely hosed, but if the error condition is
1581 * detected, it won't hurt to give it another try...
1582 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1584 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1585 if (hsfsts
.hsf_status
.flcerr
== 1) {
1586 /* Repeat for some time before giving up. */
1588 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
1589 hw_dbg(hw
, "Timeout error - flash cycle "
1590 "did not complete.");
1594 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1600 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1601 * @hw: pointer to the HW structure
1602 * @offset: The offset (in bytes) of the word(s) to write.
1603 * @words: Size of data to write in words
1604 * @data: Pointer to the word(s) to write at offset.
1606 * Writes a byte or word to the NVM using the flash access registers.
1608 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1611 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1612 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1616 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1618 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1619 return -E1000_ERR_NVM
;
1622 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1626 for (i
= 0; i
< words
; i
++) {
1627 dev_spec
->shadow_ram
[offset
+i
].modified
= 1;
1628 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
1631 e1000_release_swflag_ich8lan(hw
);
1637 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1638 * @hw: pointer to the HW structure
1640 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1641 * which writes the checksum to the shadow ram. The changes in the shadow
1642 * ram are then committed to the EEPROM by processing each bank at a time
1643 * checking for the modified bit and writing only the pending changes.
1644 * After a successful commit, the shadow ram is cleared and is ready for
1647 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1649 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1650 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1651 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
1655 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
1659 if (nvm
->type
!= e1000_nvm_flash_sw
)
1662 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1667 * We're writing to the opposite bank so if we're on bank 1,
1668 * write to bank 0 etc. We also need to erase the segment that
1669 * is going to be written
1671 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1673 e1000_release_swflag_ich8lan(hw
);
1678 new_bank_offset
= nvm
->flash_bank_size
;
1679 old_bank_offset
= 0;
1680 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
1682 e1000_release_swflag_ich8lan(hw
);
1686 old_bank_offset
= nvm
->flash_bank_size
;
1687 new_bank_offset
= 0;
1688 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
1690 e1000_release_swflag_ich8lan(hw
);
1695 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1697 * Determine whether to write the value stored
1698 * in the other NVM bank or a modified value stored
1701 if (dev_spec
->shadow_ram
[i
].modified
) {
1702 data
= dev_spec
->shadow_ram
[i
].value
;
1704 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
1712 * If the word is 0x13, then make sure the signature bits
1713 * (15:14) are 11b until the commit has completed.
1714 * This will allow us to write 10b which indicates the
1715 * signature is valid. We want to do this after the write
1716 * has completed so that we don't mark the segment valid
1717 * while the write is still in progress
1719 if (i
== E1000_ICH_NVM_SIG_WORD
)
1720 data
|= E1000_ICH_NVM_SIG_MASK
;
1722 /* Convert offset to bytes. */
1723 act_offset
= (i
+ new_bank_offset
) << 1;
1726 /* Write the bytes to the new bank. */
1727 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1734 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1742 * Don't bother writing the segment valid bits if sector
1743 * programming failed.
1746 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1747 hw_dbg(hw
, "Flash commit failed.\n");
1748 e1000_release_swflag_ich8lan(hw
);
1753 * Finally validate the new segment by setting bit 15:14
1754 * to 10b in word 0x13 , this can be done without an
1755 * erase as well since these bits are 11 to start with
1756 * and we need to change bit 14 to 0b
1758 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
1759 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
1761 e1000_release_swflag_ich8lan(hw
);
1765 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1769 e1000_release_swflag_ich8lan(hw
);
1774 * And invalidate the previously valid segment by setting
1775 * its signature word (0x13) high_byte to 0b. This can be
1776 * done without an erase because flash erase sets all bits
1777 * to 1's. We can write 1's to 0's without an erase
1779 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
1780 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
1782 e1000_release_swflag_ich8lan(hw
);
1786 /* Great! Everything worked, we can now clear the cached entries. */
1787 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1788 dev_spec
->shadow_ram
[i
].modified
= 0;
1789 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
1792 e1000_release_swflag_ich8lan(hw
);
1795 * Reload the EEPROM, or else modifications will not appear
1796 * until after the next adapter reset.
1798 e1000e_reload_nvm(hw
);
1803 hw_dbg(hw
, "NVM update error: %d\n", ret_val
);
1809 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1810 * @hw: pointer to the HW structure
1812 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1813 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1814 * calculated, in which case we need to calculate the checksum and set bit 6.
1816 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1822 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1823 * needs to be fixed. This bit is an indication that the NVM
1824 * was prepared by OEM software and did not calculate the
1825 * checksum...a likely scenario.
1827 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
1831 if ((data
& 0x40) == 0) {
1833 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
1836 ret_val
= e1000e_update_nvm_checksum(hw
);
1841 return e1000e_validate_nvm_checksum_generic(hw
);
1845 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1846 * @hw: pointer to the HW structure
1848 * To prevent malicious write/erase of the NVM, set it to be read-only
1849 * so that the hardware ignores all write/erase cycles of the NVM via
1850 * the flash control registers. The shadow-ram copy of the NVM will
1851 * still be updated, however any updates to this copy will not stick
1852 * across driver reloads.
1854 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
1856 union ich8_flash_protected_range pr0
;
1857 union ich8_hws_flash_status hsfsts
;
1861 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1865 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
1867 /* Write-protect GbE Sector of NVM */
1868 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
1869 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
1870 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
1871 pr0
.range
.wpe
= true;
1872 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
1875 * Lock down a subset of GbE Flash Control Registers, e.g.
1876 * PR0 to prevent the write-protection from being lifted.
1877 * Once FLOCKDN is set, the registers protected by it cannot
1878 * be written until FLOCKDN is cleared by a hardware reset.
1880 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1881 hsfsts
.hsf_status
.flockdn
= true;
1882 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1884 e1000_release_swflag_ich8lan(hw
);
1888 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1889 * @hw: pointer to the HW structure
1890 * @offset: The offset (in bytes) of the byte/word to read.
1891 * @size: Size of data to read, 1=byte 2=word
1892 * @data: The byte(s) to write to the NVM.
1894 * Writes one/two bytes to the NVM using the flash access registers.
1896 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1899 union ich8_hws_flash_status hsfsts
;
1900 union ich8_hws_flash_ctrl hsflctl
;
1901 u32 flash_linear_addr
;
1906 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
1907 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1908 return -E1000_ERR_NVM
;
1910 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1911 hw
->nvm
.flash_base_addr
;
1916 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1920 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1921 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1922 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
1923 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
1924 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1926 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1929 flash_data
= (u32
)data
& 0x00FF;
1931 flash_data
= (u32
)data
;
1933 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
1936 * check if FCERR is set to 1 , if set to 1, clear it
1937 * and try the whole sequence a few more times else done
1939 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1940 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
1945 * If we're here, then things are most likely
1946 * completely hosed, but if the error condition
1947 * is detected, it won't hurt to give it another
1948 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1950 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1951 if (hsfsts
.hsf_status
.flcerr
== 1)
1952 /* Repeat for some time before giving up. */
1954 if (hsfsts
.hsf_status
.flcdone
== 0) {
1955 hw_dbg(hw
, "Timeout error - flash cycle "
1956 "did not complete.");
1959 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1965 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1966 * @hw: pointer to the HW structure
1967 * @offset: The index of the byte to read.
1968 * @data: The byte to write to the NVM.
1970 * Writes a single byte to the NVM using the flash access registers.
1972 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1975 u16 word
= (u16
)data
;
1977 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
1981 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1982 * @hw: pointer to the HW structure
1983 * @offset: The offset of the byte to write.
1984 * @byte: The byte to write to the NVM.
1986 * Writes a single byte to the NVM using the flash access registers.
1987 * Goes through a retry algorithm before giving up.
1989 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
1990 u32 offset
, u8 byte
)
1993 u16 program_retries
;
1995 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1999 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
2000 hw_dbg(hw
, "Retrying Byte %2.2X at offset %u\n", byte
, offset
);
2002 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
2006 if (program_retries
== 100)
2007 return -E1000_ERR_NVM
;
2013 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2014 * @hw: pointer to the HW structure
2015 * @bank: 0 for first bank, 1 for second bank, etc.
2017 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2018 * bank N is 4096 * N + flash_reg_addr.
2020 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
2022 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2023 union ich8_hws_flash_status hsfsts
;
2024 union ich8_hws_flash_ctrl hsflctl
;
2025 u32 flash_linear_addr
;
2026 /* bank size is in 16bit words - adjust to bytes */
2027 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
2034 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2037 * Determine HW Sector size: Read BERASE bits of hw flash status
2039 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2040 * consecutive sectors. The start index for the nth Hw sector
2041 * can be calculated as = bank * 4096 + n * 256
2042 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2043 * The start index for the nth Hw sector can be calculated
2045 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2046 * (ich9 only, otherwise error condition)
2047 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2049 switch (hsfsts
.hsf_status
.berasesz
) {
2051 /* Hw sector size 256 */
2052 sector_size
= ICH_FLASH_SEG_SIZE_256
;
2053 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
2056 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
2060 if (hw
->mac
.type
== e1000_ich9lan
) {
2061 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
2062 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_8K
;
2064 return -E1000_ERR_NVM
;
2068 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
2072 return -E1000_ERR_NVM
;
2075 /* Start with the base address, then add the sector offset. */
2076 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
2077 flash_linear_addr
+= (bank
) ? (sector_size
* iteration
) : 0;
2079 for (j
= 0; j
< iteration
; j
++) {
2082 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2087 * Write a value 11 (block Erase) in Flash
2088 * Cycle field in hw flash control
2090 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2091 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
2092 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2095 * Write the last 24 bits of an index within the
2096 * block into Flash Linear address field in Flash
2099 flash_linear_addr
+= (j
* sector_size
);
2100 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2102 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2103 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
2108 * Check if FCERR is set to 1. If 1,
2109 * clear it and try the whole sequence
2110 * a few more times else Done
2112 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2113 if (hsfsts
.hsf_status
.flcerr
== 1)
2114 /* repeat for some time before giving up */
2116 else if (hsfsts
.hsf_status
.flcdone
== 0)
2118 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
2125 * e1000_valid_led_default_ich8lan - Set the default LED settings
2126 * @hw: pointer to the HW structure
2127 * @data: Pointer to the LED settings
2129 * Reads the LED default settings from the NVM to data. If the NVM LED
2130 * settings is all 0's or F's, set the LED default to a valid LED default
2133 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
2137 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
2139 hw_dbg(hw
, "NVM Read Error\n");
2143 if (*data
== ID_LED_RESERVED_0000
||
2144 *data
== ID_LED_RESERVED_FFFF
)
2145 *data
= ID_LED_DEFAULT_ICH8LAN
;
2151 * e1000_id_led_init_pchlan - store LED configurations
2152 * @hw: pointer to the HW structure
2154 * PCH does not control LEDs via the LEDCTL register, rather it uses
2155 * the PHY LED configuration register.
2157 * PCH also does not have an "always on" or "always off" mode which
2158 * complicates the ID feature. Instead of using the "on" mode to indicate
2159 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2160 * use "link_up" mode. The LEDs will still ID on request if there is no
2161 * link based on logic in e1000_led_[on|off]_pchlan().
2163 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
2165 struct e1000_mac_info
*mac
= &hw
->mac
;
2167 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
2168 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
2169 u16 data
, i
, temp
, shift
;
2171 /* Get default ID LED modes */
2172 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
2176 mac
->ledctl_default
= er32(LEDCTL
);
2177 mac
->ledctl_mode1
= mac
->ledctl_default
;
2178 mac
->ledctl_mode2
= mac
->ledctl_default
;
2180 for (i
= 0; i
< 4; i
++) {
2181 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
2184 case ID_LED_ON1_DEF2
:
2185 case ID_LED_ON1_ON2
:
2186 case ID_LED_ON1_OFF2
:
2187 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2188 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
2190 case ID_LED_OFF1_DEF2
:
2191 case ID_LED_OFF1_ON2
:
2192 case ID_LED_OFF1_OFF2
:
2193 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2194 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
2201 case ID_LED_DEF1_ON2
:
2202 case ID_LED_ON1_ON2
:
2203 case ID_LED_OFF1_ON2
:
2204 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2205 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
2207 case ID_LED_DEF1_OFF2
:
2208 case ID_LED_ON1_OFF2
:
2209 case ID_LED_OFF1_OFF2
:
2210 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2211 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
2224 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2225 * @hw: pointer to the HW structure
2227 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2228 * register, so the the bus width is hard coded.
2230 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
2232 struct e1000_bus_info
*bus
= &hw
->bus
;
2235 ret_val
= e1000e_get_bus_info_pcie(hw
);
2238 * ICH devices are "PCI Express"-ish. They have
2239 * a configuration space, but do not contain
2240 * PCI Express Capability registers, so bus width
2241 * must be hardcoded.
2243 if (bus
->width
== e1000_bus_width_unknown
)
2244 bus
->width
= e1000_bus_width_pcie_x1
;
2250 * e1000_reset_hw_ich8lan - Reset the hardware
2251 * @hw: pointer to the HW structure
2253 * Does a full reset of the hardware which includes a reset of the PHY and
2256 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
2262 * Prevent the PCI-E bus from sticking if there is no TLP connection
2263 * on the last TLP read/write transaction when MAC is reset.
2265 ret_val
= e1000e_disable_pcie_master(hw
);
2267 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
2270 hw_dbg(hw
, "Masking off all interrupts\n");
2271 ew32(IMC
, 0xffffffff);
2274 * Disable the Transmit and Receive units. Then delay to allow
2275 * any pending transactions to complete before we hit the MAC
2276 * with the global reset.
2279 ew32(TCTL
, E1000_TCTL_PSP
);
2284 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2285 if (hw
->mac
.type
== e1000_ich8lan
) {
2286 /* Set Tx and Rx buffer allocation to 8k apiece. */
2287 ew32(PBA
, E1000_PBA_8K
);
2288 /* Set Packet Buffer Size to 16k. */
2289 ew32(PBS
, E1000_PBS_16K
);
2294 if (!e1000_check_reset_block(hw
)) {
2295 /* Clear PHY Reset Asserted bit */
2296 if (hw
->mac
.type
>= e1000_pchlan
) {
2297 u32 status
= er32(STATUS
);
2298 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
2302 * PHY HW reset requires MAC CORE reset at the same
2303 * time to make sure the interface between MAC and the
2304 * external PHY is reset.
2306 ctrl
|= E1000_CTRL_PHY_RST
;
2308 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
2309 /* Whether or not the swflag was acquired, we need to reset the part */
2310 hw_dbg(hw
, "Issuing a global reset to ich8lan\n");
2311 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
2315 e1000_release_swflag_ich8lan(hw
);
2317 if (ctrl
& E1000_CTRL_PHY_RST
)
2318 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
2320 if (hw
->mac
.type
>= e1000_ich10lan
) {
2321 e1000_lan_init_done_ich8lan(hw
);
2323 ret_val
= e1000e_get_auto_rd_done(hw
);
2326 * When auto config read does not complete, do not
2327 * return with an error. This can happen in situations
2328 * where there is no eeprom and prevents getting link.
2330 hw_dbg(hw
, "Auto Read Done did not complete\n");
2335 * For PCH, this write will make sure that any noise
2336 * will be detected as a CRC error and be dropped rather than show up
2337 * as a bad packet to the DMA engine.
2339 if (hw
->mac
.type
== e1000_pchlan
)
2340 ew32(CRC_OFFSET
, 0x65656565);
2342 ew32(IMC
, 0xffffffff);
2345 kab
= er32(KABGTXD
);
2346 kab
|= E1000_KABGTXD_BGSQLBIAS
;
2349 if (hw
->mac
.type
== e1000_pchlan
)
2350 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
2356 * e1000_init_hw_ich8lan - Initialize the hardware
2357 * @hw: pointer to the HW structure
2359 * Prepares the hardware for transmit and receive by doing the following:
2360 * - initialize hardware bits
2361 * - initialize LED identification
2362 * - setup receive address registers
2363 * - setup flow control
2364 * - setup transmit descriptors
2365 * - clear statistics
2367 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
2369 struct e1000_mac_info
*mac
= &hw
->mac
;
2370 u32 ctrl_ext
, txdctl
, snoop
;
2374 e1000_initialize_hw_bits_ich8lan(hw
);
2376 /* Initialize identification LED */
2377 ret_val
= mac
->ops
.id_led_init(hw
);
2379 hw_dbg(hw
, "Error initializing identification LED\n");
2383 /* Setup the receive address. */
2384 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
2386 /* Zero out the Multicast HASH table */
2387 hw_dbg(hw
, "Zeroing the MTA\n");
2388 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
2389 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
2392 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2393 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2394 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2396 if (hw
->phy
.type
== e1000_phy_82578
) {
2397 hw
->phy
.ops
.read_phy_reg(hw
, BM_WUC
, &i
);
2398 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
2403 /* Setup link and flow control */
2404 ret_val
= e1000_setup_link_ich8lan(hw
);
2406 /* Set the transmit descriptor write-back policy for both queues */
2407 txdctl
= er32(TXDCTL(0));
2408 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2409 E1000_TXDCTL_FULL_TX_DESC_WB
;
2410 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2411 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2412 ew32(TXDCTL(0), txdctl
);
2413 txdctl
= er32(TXDCTL(1));
2414 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2415 E1000_TXDCTL_FULL_TX_DESC_WB
;
2416 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2417 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2418 ew32(TXDCTL(1), txdctl
);
2421 * ICH8 has opposite polarity of no_snoop bits.
2422 * By default, we should use snoop behavior.
2424 if (mac
->type
== e1000_ich8lan
)
2425 snoop
= PCIE_ICH8_SNOOP_ALL
;
2427 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
2428 e1000e_set_pcie_no_snoop(hw
, snoop
);
2430 ctrl_ext
= er32(CTRL_EXT
);
2431 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
2432 ew32(CTRL_EXT
, ctrl_ext
);
2435 * Clear all of the statistics registers (clear on read). It is
2436 * important that we do this after we have tried to establish link
2437 * because the symbol error count will increment wildly if there
2440 e1000_clear_hw_cntrs_ich8lan(hw
);
2445 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2446 * @hw: pointer to the HW structure
2448 * Sets/Clears required hardware bits necessary for correctly setting up the
2449 * hardware for transmit and receive.
2451 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
2455 /* Extended Device Control */
2456 reg
= er32(CTRL_EXT
);
2458 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2459 if (hw
->mac
.type
>= e1000_pchlan
)
2460 reg
|= E1000_CTRL_EXT_PHYPDEN
;
2461 ew32(CTRL_EXT
, reg
);
2463 /* Transmit Descriptor Control 0 */
2464 reg
= er32(TXDCTL(0));
2466 ew32(TXDCTL(0), reg
);
2468 /* Transmit Descriptor Control 1 */
2469 reg
= er32(TXDCTL(1));
2471 ew32(TXDCTL(1), reg
);
2473 /* Transmit Arbitration Control 0 */
2474 reg
= er32(TARC(0));
2475 if (hw
->mac
.type
== e1000_ich8lan
)
2476 reg
|= (1 << 28) | (1 << 29);
2477 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2480 /* Transmit Arbitration Control 1 */
2481 reg
= er32(TARC(1));
2482 if (er32(TCTL
) & E1000_TCTL_MULR
)
2486 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
2490 if (hw
->mac
.type
== e1000_ich8lan
) {
2498 * e1000_setup_link_ich8lan - Setup flow control and link settings
2499 * @hw: pointer to the HW structure
2501 * Determines which flow control settings to use, then configures flow
2502 * control. Calls the appropriate media-specific link configuration
2503 * function. Assuming the adapter has a valid link partner, a valid link
2504 * should be established. Assumes the hardware has previously been reset
2505 * and the transmitter and receiver are not enabled.
2507 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
2511 if (e1000_check_reset_block(hw
))
2515 * ICH parts do not have a word in the NVM to determine
2516 * the default flow control setting, so we explicitly
2519 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
2520 /* Workaround h/w hang when Tx flow control enabled */
2521 if (hw
->mac
.type
== e1000_pchlan
)
2522 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
2524 hw
->fc
.requested_mode
= e1000_fc_full
;
2528 * Save off the requested flow control mode for use later. Depending
2529 * on the link partner's capabilities, we may or may not use this mode.
2531 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2533 hw_dbg(hw
, "After fix-ups FlowControl is now = %x\n",
2534 hw
->fc
.current_mode
);
2536 /* Continue to configure the copper link. */
2537 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
2541 ew32(FCTTV
, hw
->fc
.pause_time
);
2542 if ((hw
->phy
.type
== e1000_phy_82578
) ||
2543 (hw
->phy
.type
== e1000_phy_82577
)) {
2544 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
2545 PHY_REG(BM_PORT_CTRL_PAGE
, 27),
2551 return e1000e_set_fc_watermarks(hw
);
2555 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2556 * @hw: pointer to the HW structure
2558 * Configures the kumeran interface to the PHY to wait the appropriate time
2559 * when polling the PHY, then call the generic setup_copper_link to finish
2560 * configuring the copper link.
2562 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
2569 ctrl
|= E1000_CTRL_SLU
;
2570 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
2574 * Set the mac to wait the maximum time between each iteration
2575 * and increase the max iterations when polling the phy;
2576 * this fixes erroneous timeouts at 10Mbps.
2578 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
2581 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
2585 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
2589 switch (hw
->phy
.type
) {
2590 case e1000_phy_igp_3
:
2591 ret_val
= e1000e_copper_link_setup_igp(hw
);
2596 case e1000_phy_82578
:
2597 ret_val
= e1000e_copper_link_setup_m88(hw
);
2601 case e1000_phy_82577
:
2602 ret_val
= e1000_copper_link_setup_82577(hw
);
2607 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, IFE_PHY_MDIX_CONTROL
,
2612 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
2614 switch (hw
->phy
.mdix
) {
2616 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
2619 reg_data
|= IFE_PMC_FORCE_MDIX
;
2623 reg_data
|= IFE_PMC_AUTO_MDIX
;
2626 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, IFE_PHY_MDIX_CONTROL
,
2634 return e1000e_setup_copper_link(hw
);
2638 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2639 * @hw: pointer to the HW structure
2640 * @speed: pointer to store current link speed
2641 * @duplex: pointer to store the current link duplex
2643 * Calls the generic get_speed_and_duplex to retrieve the current link
2644 * information and then calls the Kumeran lock loss workaround for links at
2647 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
2652 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
2656 if ((hw
->mac
.type
== e1000_pchlan
) && (*speed
== SPEED_1000
)) {
2657 ret_val
= e1000e_write_kmrn_reg(hw
,
2658 E1000_KMRNCTRLSTA_K1_CONFIG
,
2659 E1000_KMRNCTRLSTA_K1_DISABLE
);
2664 if ((hw
->mac
.type
== e1000_ich8lan
) &&
2665 (hw
->phy
.type
== e1000_phy_igp_3
) &&
2666 (*speed
== SPEED_1000
)) {
2667 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
2674 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2675 * @hw: pointer to the HW structure
2677 * Work-around for 82566 Kumeran PCS lock loss:
2678 * On link status change (i.e. PCI reset, speed change) and link is up and
2680 * 0) if workaround is optionally disabled do nothing
2681 * 1) wait 1ms for Kumeran link to come up
2682 * 2) check Kumeran Diagnostic register PCS lock loss bit
2683 * 3) if not set the link is locked (all is good), otherwise...
2685 * 5) repeat up to 10 times
2686 * Note: this is only called for IGP3 copper when speed is 1gb.
2688 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
2690 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2696 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
2700 * Make sure link is up before proceeding. If not just return.
2701 * Attempting this while link is negotiating fouled up link
2704 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2708 for (i
= 0; i
< 10; i
++) {
2709 /* read once to clear */
2710 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2713 /* and again to get new status */
2714 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2718 /* check for PCS lock */
2719 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
2722 /* Issue PHY reset */
2723 e1000_phy_hw_reset(hw
);
2726 /* Disable GigE link negotiation */
2727 phy_ctrl
= er32(PHY_CTRL
);
2728 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2729 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2730 ew32(PHY_CTRL
, phy_ctrl
);
2733 * Call gig speed drop workaround on Gig disable before accessing
2736 e1000e_gig_downshift_workaround_ich8lan(hw
);
2738 /* unable to acquire PCS lock */
2739 return -E1000_ERR_PHY
;
2743 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2744 * @hw: pointer to the HW structure
2745 * @state: boolean value used to set the current Kumeran workaround state
2747 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2748 * /disabled - FALSE).
2750 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
2753 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2755 if (hw
->mac
.type
!= e1000_ich8lan
) {
2756 hw_dbg(hw
, "Workaround applies to ICH8 only.\n");
2760 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
2764 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2765 * @hw: pointer to the HW structure
2767 * Workaround for 82566 power-down on D3 entry:
2768 * 1) disable gigabit link
2769 * 2) write VR power-down enable
2771 * Continue if successful, else issue LCD reset and repeat
2773 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
2779 if (hw
->phy
.type
!= e1000_phy_igp_3
)
2782 /* Try the workaround twice (if needed) */
2785 reg
= er32(PHY_CTRL
);
2786 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2787 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2788 ew32(PHY_CTRL
, reg
);
2791 * Call gig speed drop workaround on Gig disable before
2792 * accessing any PHY registers
2794 if (hw
->mac
.type
== e1000_ich8lan
)
2795 e1000e_gig_downshift_workaround_ich8lan(hw
);
2797 /* Write VR power-down enable */
2798 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2799 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2800 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
2802 /* Read it back and test */
2803 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2804 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2805 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
2808 /* Issue PHY reset and repeat at most one more time */
2810 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
2816 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2817 * @hw: pointer to the HW structure
2819 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2820 * LPLU, Gig disable, MDIC PHY reset):
2821 * 1) Set Kumeran Near-end loopback
2822 * 2) Clear Kumeran Near-end loopback
2823 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2825 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
2830 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
2831 (hw
->phy
.type
!= e1000_phy_igp_3
))
2834 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2838 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2839 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2843 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2844 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2849 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2850 * @hw: pointer to the HW structure
2852 * During S0 to Sx transition, it is possible the link remains at gig
2853 * instead of negotiating to a lower speed. Before going to Sx, set
2854 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2857 * Should only be called for applicable parts.
2859 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
2863 switch (hw
->mac
.type
) {
2865 case e1000_ich10lan
:
2867 phy_ctrl
= er32(PHY_CTRL
);
2868 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
|
2869 E1000_PHY_CTRL_GBE_DISABLE
;
2870 ew32(PHY_CTRL
, phy_ctrl
);
2872 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2873 if (hw
->mac
.type
== e1000_pchlan
)
2883 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2884 * @hw: pointer to the HW structure
2886 * Return the LED back to the default configuration.
2888 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
2890 if (hw
->phy
.type
== e1000_phy_ife
)
2891 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
2893 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
2898 * e1000_led_on_ich8lan - Turn LEDs on
2899 * @hw: pointer to the HW structure
2903 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
2905 if (hw
->phy
.type
== e1000_phy_ife
)
2906 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2907 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
2909 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
2914 * e1000_led_off_ich8lan - Turn LEDs off
2915 * @hw: pointer to the HW structure
2917 * Turn off the LEDs.
2919 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
2921 if (hw
->phy
.type
== e1000_phy_ife
)
2922 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2923 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
2925 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
2930 * e1000_setup_led_pchlan - Configures SW controllable LED
2931 * @hw: pointer to the HW structure
2933 * This prepares the SW controllable LED for use.
2935 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
2937 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
,
2938 (u16
)hw
->mac
.ledctl_mode1
);
2942 * e1000_cleanup_led_pchlan - Restore the default LED operation
2943 * @hw: pointer to the HW structure
2945 * Return the LED back to the default configuration.
2947 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
2949 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
,
2950 (u16
)hw
->mac
.ledctl_default
);
2954 * e1000_led_on_pchlan - Turn LEDs on
2955 * @hw: pointer to the HW structure
2959 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
2961 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
2965 * If no link, then turn LED on by setting the invert bit
2966 * for each LED that's mode is "link_up" in ledctl_mode2.
2968 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
2969 for (i
= 0; i
< 3; i
++) {
2970 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
2971 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
2972 E1000_LEDCTL_MODE_LINK_UP
)
2974 if (led
& E1000_PHY_LED0_IVRT
)
2975 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
2977 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
2981 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
, data
);
2985 * e1000_led_off_pchlan - Turn LEDs off
2986 * @hw: pointer to the HW structure
2988 * Turn off the LEDs.
2990 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
2992 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
2996 * If no link, then turn LED off by clearing the invert bit
2997 * for each LED that's mode is "link_up" in ledctl_mode1.
2999 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
3000 for (i
= 0; i
< 3; i
++) {
3001 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
3002 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
3003 E1000_LEDCTL_MODE_LINK_UP
)
3005 if (led
& E1000_PHY_LED0_IVRT
)
3006 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
3008 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
3012 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
, data
);
3016 * e1000_get_cfg_done_ich8lan - Read config done bit
3017 * @hw: pointer to the HW structure
3019 * Read the management control register for the config done bit for
3020 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3021 * to read the config done bit, so an error is *ONLY* logged and returns
3022 * 0. If we were to return with error, EEPROM-less silicon
3023 * would not be able to be reset or change link.
3025 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
3029 if (hw
->mac
.type
>= e1000_pchlan
) {
3030 u32 status
= er32(STATUS
);
3032 if (status
& E1000_STATUS_PHYRA
)
3033 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
3036 "PHY Reset Asserted not set - needs delay\n");
3039 e1000e_get_cfg_done(hw
);
3041 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3042 if ((hw
->mac
.type
!= e1000_ich10lan
) &&
3043 (hw
->mac
.type
!= e1000_pchlan
)) {
3044 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
3045 (hw
->phy
.type
== e1000_phy_igp_3
)) {
3046 e1000e_phy_init_script_igp3(hw
);
3049 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
3050 /* Maybe we should do a basic PHY config */
3051 hw_dbg(hw
, "EEPROM not present\n");
3052 return -E1000_ERR_CONFIG
;
3060 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3061 * @hw: pointer to the HW structure
3063 * Clears hardware counters specific to the silicon family and calls
3064 * clear_hw_cntrs_generic to clear all general purpose counters.
3066 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
3071 e1000e_clear_hw_cntrs_base(hw
);
3073 temp
= er32(ALGNERRC
);
3074 temp
= er32(RXERRC
);
3076 temp
= er32(CEXTERR
);
3078 temp
= er32(TSCTFC
);
3080 temp
= er32(MGTPRC
);
3081 temp
= er32(MGTPDC
);
3082 temp
= er32(MGTPTC
);
3085 temp
= er32(ICRXOC
);
3087 /* Clear PHY statistics registers */
3088 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3089 (hw
->phy
.type
== e1000_phy_82577
)) {
3090 hw
->phy
.ops
.read_phy_reg(hw
, HV_SCC_UPPER
, &phy_data
);
3091 hw
->phy
.ops
.read_phy_reg(hw
, HV_SCC_LOWER
, &phy_data
);
3092 hw
->phy
.ops
.read_phy_reg(hw
, HV_ECOL_UPPER
, &phy_data
);
3093 hw
->phy
.ops
.read_phy_reg(hw
, HV_ECOL_LOWER
, &phy_data
);
3094 hw
->phy
.ops
.read_phy_reg(hw
, HV_MCC_UPPER
, &phy_data
);
3095 hw
->phy
.ops
.read_phy_reg(hw
, HV_MCC_LOWER
, &phy_data
);
3096 hw
->phy
.ops
.read_phy_reg(hw
, HV_LATECOL_UPPER
, &phy_data
);
3097 hw
->phy
.ops
.read_phy_reg(hw
, HV_LATECOL_LOWER
, &phy_data
);
3098 hw
->phy
.ops
.read_phy_reg(hw
, HV_COLC_UPPER
, &phy_data
);
3099 hw
->phy
.ops
.read_phy_reg(hw
, HV_COLC_LOWER
, &phy_data
);
3100 hw
->phy
.ops
.read_phy_reg(hw
, HV_DC_UPPER
, &phy_data
);
3101 hw
->phy
.ops
.read_phy_reg(hw
, HV_DC_LOWER
, &phy_data
);
3102 hw
->phy
.ops
.read_phy_reg(hw
, HV_TNCRS_UPPER
, &phy_data
);
3103 hw
->phy
.ops
.read_phy_reg(hw
, HV_TNCRS_LOWER
, &phy_data
);
3107 static struct e1000_mac_operations ich8_mac_ops
= {
3108 .id_led_init
= e1000e_id_led_init
,
3109 .check_mng_mode
= e1000_check_mng_mode_ich8lan
,
3110 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
3111 /* cleanup_led dependent on mac type */
3112 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
3113 .get_bus_info
= e1000_get_bus_info_ich8lan
,
3114 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
3115 /* led_on dependent on mac type */
3116 /* led_off dependent on mac type */
3117 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
3118 .reset_hw
= e1000_reset_hw_ich8lan
,
3119 .init_hw
= e1000_init_hw_ich8lan
,
3120 .setup_link
= e1000_setup_link_ich8lan
,
3121 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
3122 /* id_led_init dependent on mac type */
3125 static struct e1000_phy_operations ich8_phy_ops
= {
3126 .acquire_phy
= e1000_acquire_swflag_ich8lan
,
3127 .check_reset_block
= e1000_check_reset_block_ich8lan
,
3129 .force_speed_duplex
= e1000_phy_force_speed_duplex_ich8lan
,
3130 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
3131 .get_cable_length
= e1000e_get_cable_length_igp_2
,
3132 .get_phy_info
= e1000_get_phy_info_ich8lan
,
3133 .read_phy_reg
= e1000e_read_phy_reg_igp
,
3134 .release_phy
= e1000_release_swflag_ich8lan
,
3135 .reset_phy
= e1000_phy_hw_reset_ich8lan
,
3136 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
3137 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
3138 .write_phy_reg
= e1000e_write_phy_reg_igp
,
3141 static struct e1000_nvm_operations ich8_nvm_ops
= {
3142 .acquire_nvm
= e1000_acquire_swflag_ich8lan
,
3143 .read_nvm
= e1000_read_nvm_ich8lan
,
3144 .release_nvm
= e1000_release_swflag_ich8lan
,
3145 .update_nvm
= e1000_update_nvm_checksum_ich8lan
,
3146 .valid_led_default
= e1000_valid_led_default_ich8lan
,
3147 .validate_nvm
= e1000_validate_nvm_checksum_ich8lan
,
3148 .write_nvm
= e1000_write_nvm_ich8lan
,
3151 struct e1000_info e1000_ich8_info
= {
3152 .mac
= e1000_ich8lan
,
3153 .flags
= FLAG_HAS_WOL
3155 | FLAG_RX_CSUM_ENABLED
3156 | FLAG_HAS_CTRLEXT_ON_LOAD
3161 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
3162 .get_variants
= e1000_get_variants_ich8lan
,
3163 .mac_ops
= &ich8_mac_ops
,
3164 .phy_ops
= &ich8_phy_ops
,
3165 .nvm_ops
= &ich8_nvm_ops
,
3168 struct e1000_info e1000_ich9_info
= {
3169 .mac
= e1000_ich9lan
,
3170 .flags
= FLAG_HAS_JUMBO_FRAMES
3173 | FLAG_RX_CSUM_ENABLED
3174 | FLAG_HAS_CTRLEXT_ON_LOAD
3180 .max_hw_frame_size
= DEFAULT_JUMBO
,
3181 .get_variants
= e1000_get_variants_ich8lan
,
3182 .mac_ops
= &ich8_mac_ops
,
3183 .phy_ops
= &ich8_phy_ops
,
3184 .nvm_ops
= &ich8_nvm_ops
,
3187 struct e1000_info e1000_ich10_info
= {
3188 .mac
= e1000_ich10lan
,
3189 .flags
= FLAG_HAS_JUMBO_FRAMES
3192 | FLAG_RX_CSUM_ENABLED
3193 | FLAG_HAS_CTRLEXT_ON_LOAD
3199 .max_hw_frame_size
= DEFAULT_JUMBO
,
3200 .get_variants
= e1000_get_variants_ich8lan
,
3201 .mac_ops
= &ich8_mac_ops
,
3202 .phy_ops
= &ich8_phy_ops
,
3203 .nvm_ops
= &ich8_nvm_ops
,
3206 struct e1000_info e1000_pch_info
= {
3207 .mac
= e1000_pchlan
,
3208 .flags
= FLAG_IS_ICH
3210 | FLAG_RX_CSUM_ENABLED
3211 | FLAG_HAS_CTRLEXT_ON_LOAD
3214 | FLAG_HAS_JUMBO_FRAMES
3217 .max_hw_frame_size
= 4096,
3218 .get_variants
= e1000_get_variants_ich8lan
,
3219 .mac_ops
= &ich8_mac_ops
,
3220 .phy_ops
= &ich8_phy_ops
,
3221 .nvm_ops
= &ich8_nvm_ops
,