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intel-iommu: fix for IOMMU early crash
[linux-2.6/kvm.git] / drivers / scsi / nsp32.c
blob28161dc95e0d7107613933da5186e50f265a0ded
1 /*
2 * NinjaSCSI-32Bi Cardbus, NinjaSCSI-32UDE PCI/CardBus SCSI driver
3 * Copyright (C) 2001, 2002, 2003
4 * YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>
5 * GOTO Masanori <gotom@debian.or.jp>, <gotom@debian.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 *
18 * Revision History:
19 * 1.0: Initial Release.
20 * 1.1: Add /proc SDTR status.
21 * Remove obsolete error handler nsp32_reset.
22 * Some clean up.
23 * 1.2: PowerPC (big endian) support.
24 */
25
26 #include <linux/version.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/timer.h>
33 #include <linux/ioport.h>
34 #include <linux/major.h>
35 #include <linux/blkdev.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/ctype.h>
40 #include <linux/dma-mapping.h>
41
42 #include <asm/dma.h>
43 #include <asm/system.h>
44 #include <asm/io.h>
45
46 #include <scsi/scsi.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <scsi/scsi_device.h>
49 #include <scsi/scsi_host.h>
50 #include <scsi/scsi_ioctl.h>
51
52 #include "nsp32.h"
53
54
55 /***********************************************************************
56 * Module parameters
57 */
58 static int trans_mode = 0; /* default: BIOS */
59 module_param (trans_mode, int, 0);
60 MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
61 #define ASYNC_MODE 1
62 #define ULTRA20M_MODE 2
63
64 static int auto_param = 0; /* default: ON */
65 module_param (auto_param, bool, 0);
66 MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
67
68 static int disc_priv = 1; /* default: OFF */
69 module_param (disc_priv, bool, 0);
70 MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
71
72 MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>");
73 MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module");
74 MODULE_LICENSE("GPL");
75
76 static const char *nsp32_release_version = "1.2";
77
78
79 /****************************************************************************
80 * Supported hardware
81 */
82 static struct pci_device_id nsp32_pci_table[] __devinitdata = {
83 {
84 .vendor = PCI_VENDOR_ID_IODATA,
85 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II,
86 .subvendor = PCI_ANY_ID,
87 .subdevice = PCI_ANY_ID,
88 .driver_data = MODEL_IODATA,
89 },
90 {
91 .vendor = PCI_VENDOR_ID_WORKBIT,
92 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME,
93 .subvendor = PCI_ANY_ID,
94 .subdevice = PCI_ANY_ID,
95 .driver_data = MODEL_KME,
96 },
97 {
98 .vendor = PCI_VENDOR_ID_WORKBIT,
99 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT,
100 .subvendor = PCI_ANY_ID,
101 .subdevice = PCI_ANY_ID,
102 .driver_data = MODEL_WORKBIT,
103 },
104 {
105 .vendor = PCI_VENDOR_ID_WORKBIT,
106 .device = PCI_DEVICE_ID_WORKBIT_STANDARD,
107 .subvendor = PCI_ANY_ID,
108 .subdevice = PCI_ANY_ID,
109 .driver_data = MODEL_PCI_WORKBIT,
110 },
111 {
112 .vendor = PCI_VENDOR_ID_WORKBIT,
113 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC,
114 .subvendor = PCI_ANY_ID,
115 .subdevice = PCI_ANY_ID,
116 .driver_data = MODEL_LOGITEC,
117 },
118 {
119 .vendor = PCI_VENDOR_ID_WORKBIT,
120 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC,
121 .subvendor = PCI_ANY_ID,
122 .subdevice = PCI_ANY_ID,
123 .driver_data = MODEL_PCI_LOGITEC,
124 },
125 {
126 .vendor = PCI_VENDOR_ID_WORKBIT,
127 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO,
128 .subvendor = PCI_ANY_ID,
129 .subdevice = PCI_ANY_ID,
130 .driver_data = MODEL_PCI_MELCO,
131 },
132 {
133 .vendor = PCI_VENDOR_ID_WORKBIT,
134 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II,
135 .subvendor = PCI_ANY_ID,
136 .subdevice = PCI_ANY_ID,
137 .driver_data = MODEL_PCI_MELCO,
138 },
139 {0,0,},
140 };
141 MODULE_DEVICE_TABLE(pci, nsp32_pci_table);
142
143 static nsp32_hw_data nsp32_data_base; /* probe <-> detect glue */
144
145
146 /*
147 * Period/AckWidth speed conversion table
148 *
149 * Note: This period/ackwidth speed table must be in descending order.
150 */
151 static nsp32_sync_table nsp32_sync_table_40M[] = {
152 /* {PNo, AW, SP, EP, SREQ smpl} Speed(MB/s) Period AckWidth */
153 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */
154 {0x2, 0, 0x0d, 0x18, SMPL_40M}, /* 13.3 : 75ns, 25ns */
155 {0x3, 1, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
156 {0x4, 1, 0x1a, 0x1f, SMPL_20M}, /* 8.0 : 125ns, 50ns */
157 {0x5, 2, 0x20, 0x25, SMPL_20M}, /* 6.7 : 150ns, 75ns */
158 {0x6, 2, 0x26, 0x31, SMPL_20M}, /* 5.7 : 175ns, 75ns */
159 {0x7, 3, 0x32, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
160 {0x8, 3, 0x33, 0x38, SMPL_10M}, /* 4.4 : 225ns, 100ns */
161 {0x9, 3, 0x39, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
162 };
163
164 static nsp32_sync_table nsp32_sync_table_20M[] = {
165 {0x1, 0, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
166 {0x2, 0, 0x1a, 0x25, SMPL_20M}, /* 6.7 : 150ns, 50ns */
167 {0x3, 1, 0x26, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
168 {0x4, 1, 0x33, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
169 {0x5, 2, 0x3f, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 150ns */
170 {0x6, 2, 0x4c, 0x57, SMPL_10M}, /* 2.8 : 350ns, 150ns */
171 {0x7, 3, 0x58, 0x64, SMPL_10M}, /* 2.5 : 400ns, 200ns */
172 {0x8, 3, 0x65, 0x70, SMPL_10M}, /* 2.2 : 450ns, 200ns */
173 {0x9, 3, 0x71, 0x7d, SMPL_10M}, /* 2.0 : 500ns, 200ns */
174 };
175
176 static nsp32_sync_table nsp32_sync_table_pci[] = {
177 {0x1, 0, 0x0c, 0x0f, SMPL_40M}, /* 16.6 : 60ns, 30ns */
178 {0x2, 0, 0x10, 0x16, SMPL_40M}, /* 11.1 : 90ns, 30ns */
179 {0x3, 1, 0x17, 0x1e, SMPL_20M}, /* 8.3 : 120ns, 60ns */
180 {0x4, 1, 0x1f, 0x25, SMPL_20M}, /* 6.7 : 150ns, 60ns */
181 {0x5, 2, 0x26, 0x2d, SMPL_20M}, /* 5.6 : 180ns, 90ns */
182 {0x6, 2, 0x2e, 0x34, SMPL_10M}, /* 4.8 : 210ns, 90ns */
183 {0x7, 3, 0x35, 0x3c, SMPL_10M}, /* 4.2 : 240ns, 120ns */
184 {0x8, 3, 0x3d, 0x43, SMPL_10M}, /* 3.7 : 270ns, 120ns */
185 {0x9, 3, 0x44, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 120ns */
186 };
187
188 /*
189 * function declaration
190 */
191 /* module entry point */
192 static int __devinit nsp32_probe (struct pci_dev *, const struct pci_device_id *);
193 static void __devexit nsp32_remove(struct pci_dev *);
194 static int __init init_nsp32 (void);
195 static void __exit exit_nsp32 (void);
196
197 /* struct struct scsi_host_template */
198 static int nsp32_proc_info (struct Scsi_Host *, char *, char **, off_t, int, int);
199
200 static int nsp32_detect (struct pci_dev *pdev);
201 static int nsp32_queuecommand(struct scsi_cmnd *,
202 void (*done)(struct scsi_cmnd *));
203 static const char *nsp32_info (struct Scsi_Host *);
204 static int nsp32_release (struct Scsi_Host *);
205
206 /* SCSI error handler */
207 static int nsp32_eh_abort (struct scsi_cmnd *);
208 static int nsp32_eh_bus_reset (struct scsi_cmnd *);
209 static int nsp32_eh_host_reset(struct scsi_cmnd *);
210
211 /* generate SCSI message */
212 static void nsp32_build_identify(struct scsi_cmnd *);
213 static void nsp32_build_nop (struct scsi_cmnd *);
214 static void nsp32_build_reject (struct scsi_cmnd *);
215 static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char, unsigned char);
216
217 /* SCSI message handler */
218 static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short);
219 static void nsp32_msgout_occur (struct scsi_cmnd *);
220 static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long, unsigned short);
221
222 static int nsp32_setup_sg_table (struct scsi_cmnd *);
223 static int nsp32_selection_autopara(struct scsi_cmnd *);
224 static int nsp32_selection_autoscsi(struct scsi_cmnd *);
225 static void nsp32_scsi_done (struct scsi_cmnd *);
226 static int nsp32_arbitration (struct scsi_cmnd *, unsigned int);
227 static int nsp32_reselection (struct scsi_cmnd *, unsigned char);
228 static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int);
229 static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short);
230
231 /* SCSI SDTR */
232 static void nsp32_analyze_sdtr (struct scsi_cmnd *);
233 static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *, unsigned char);
234 static void nsp32_set_async (nsp32_hw_data *, nsp32_target *);
235 static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *, unsigned char *, unsigned char *);
236 static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *, int, unsigned char);
237
238 /* SCSI bus status handler */
239 static void nsp32_wait_req (nsp32_hw_data *, int);
240 static void nsp32_wait_sack (nsp32_hw_data *, int);
241 static void nsp32_sack_assert (nsp32_hw_data *);
242 static void nsp32_sack_negate (nsp32_hw_data *);
243 static void nsp32_do_bus_reset(nsp32_hw_data *);
244
245 /* hardware interrupt handler */
246 static irqreturn_t do_nsp32_isr(int, void *);
247
248 /* initialize hardware */
249 static int nsp32hw_init(nsp32_hw_data *);
250
251 /* EEPROM handler */
252 static int nsp32_getprom_param (nsp32_hw_data *);
253 static int nsp32_getprom_at24 (nsp32_hw_data *);
254 static int nsp32_getprom_c16 (nsp32_hw_data *);
255 static void nsp32_prom_start (nsp32_hw_data *);
256 static void nsp32_prom_stop (nsp32_hw_data *);
257 static int nsp32_prom_read (nsp32_hw_data *, int);
258 static int nsp32_prom_read_bit (nsp32_hw_data *);
259 static void nsp32_prom_write_bit(nsp32_hw_data *, int);
260 static void nsp32_prom_set (nsp32_hw_data *, int, int);
261 static int nsp32_prom_get (nsp32_hw_data *, int);
262
263 /* debug/warning/info message */
264 static void nsp32_message (const char *, int, char *, char *, ...);
265 #ifdef NSP32_DEBUG
266 static void nsp32_dmessage(const char *, int, int, char *, ...);
267 #endif
268
269 /*
270 * max_sectors is currently limited up to 128.
271 */
272 static struct scsi_host_template nsp32_template = {
273 .proc_name = "nsp32",
274 .name = "Workbit NinjaSCSI-32Bi/UDE",
275 .proc_info = nsp32_proc_info,
276 .info = nsp32_info,
277 .queuecommand = nsp32_queuecommand,
278 .can_queue = 1,
279 .sg_tablesize = NSP32_SG_SIZE,
280 .max_sectors = 128,
281 .cmd_per_lun = 1,
282 .this_id = NSP32_HOST_SCSIID,
283 .use_clustering = DISABLE_CLUSTERING,
284 .use_sg_chaining = ENABLE_SG_CHAINING,
285 .eh_abort_handler = nsp32_eh_abort,
286 .eh_bus_reset_handler = nsp32_eh_bus_reset,
287 .eh_host_reset_handler = nsp32_eh_host_reset,
288 /* .highmem_io = 1, */
289 };
290
291 #include "nsp32_io.h"
292
293 /***********************************************************************
294 * debug, error print
295 */
296 #ifndef NSP32_DEBUG
297 # define NSP32_DEBUG_MASK 0x000000
298 # define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args)
299 # define nsp32_dbg(mask, args...) /* */
300 #else
301 # define NSP32_DEBUG_MASK 0xffffff
302 # define nsp32_msg(type, args...) \
303 nsp32_message (__FUNCTION__, __LINE__, (type), args)
304 # define nsp32_dbg(mask, args...) \
305 nsp32_dmessage(__FUNCTION__, __LINE__, (mask), args)
306 #endif
307
308 #define NSP32_DEBUG_QUEUECOMMAND BIT(0)
309 #define NSP32_DEBUG_REGISTER BIT(1)
310 #define NSP32_DEBUG_AUTOSCSI BIT(2)
311 #define NSP32_DEBUG_INTR BIT(3)
312 #define NSP32_DEBUG_SGLIST BIT(4)
313 #define NSP32_DEBUG_BUSFREE BIT(5)
314 #define NSP32_DEBUG_CDB_CONTENTS BIT(6)
315 #define NSP32_DEBUG_RESELECTION BIT(7)
316 #define NSP32_DEBUG_MSGINOCCUR BIT(8)
317 #define NSP32_DEBUG_EEPROM BIT(9)
318 #define NSP32_DEBUG_MSGOUTOCCUR BIT(10)
319 #define NSP32_DEBUG_BUSRESET BIT(11)
320 #define NSP32_DEBUG_RESTART BIT(12)
321 #define NSP32_DEBUG_SYNC BIT(13)
322 #define NSP32_DEBUG_WAIT BIT(14)
323 #define NSP32_DEBUG_TARGETFLAG BIT(15)
324 #define NSP32_DEBUG_PROC BIT(16)
325 #define NSP32_DEBUG_INIT BIT(17)
326 #define NSP32_SPECIAL_PRINT_REGISTER BIT(20)
327
328 #define NSP32_DEBUG_BUF_LEN 100
329
330 static void nsp32_message(const char *func, int line, char *type, char *fmt, ...)
331 {
332 va_list args;
333 char buf[NSP32_DEBUG_BUF_LEN];
334
335 va_start(args, fmt);
336 vsnprintf(buf, sizeof(buf), fmt, args);
337 va_end(args);
338
339 #ifndef NSP32_DEBUG
340 printk("%snsp32: %s\n", type, buf);
341 #else
342 printk("%snsp32: %s (%d): %s\n", type, func, line, buf);
343 #endif
344 }
345
346 #ifdef NSP32_DEBUG
347 static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...)
348 {
349 va_list args;
350 char buf[NSP32_DEBUG_BUF_LEN];
351
352 va_start(args, fmt);
353 vsnprintf(buf, sizeof(buf), fmt, args);
354 va_end(args);
355
356 if (mask & NSP32_DEBUG_MASK) {
357 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf);
358 }
359 }
360 #endif
361
362 #ifdef NSP32_DEBUG
363 # include "nsp32_debug.c"
364 #else
365 # define show_command(arg) /* */
366 # define show_busphase(arg) /* */
367 # define show_autophase(arg) /* */
368 #endif
369
370 /*
371 * IDENTIFY Message
372 */
373 static void nsp32_build_identify(struct scsi_cmnd *SCpnt)
374 {
375 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
376 int pos = data->msgout_len;
377 int mode = FALSE;
378
379 /* XXX: Auto DiscPriv detection is progressing... */
380 if (disc_priv == 0) {
381 /* mode = TRUE; */
382 }
383
384 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
385
386 data->msgout_len = pos;
387 }
388
389 /*
390 * SDTR Message Routine
391 */
392 static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt,
393 unsigned char period,
394 unsigned char offset)
395 {
396 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
397 int pos = data->msgout_len;
398
399 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
400 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
401 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
402 data->msgoutbuf[pos] = period; pos++;
403 data->msgoutbuf[pos] = offset; pos++;
404
405 data->msgout_len = pos;
406 }
407
408 /*
409 * No Operation Message
410 */
411 static void nsp32_build_nop(struct scsi_cmnd *SCpnt)
412 {
413 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
414 int pos = data->msgout_len;
415
416 if (pos != 0) {
417 nsp32_msg(KERN_WARNING,
418 "Some messages are already contained!");
419 return;
420 }
421
422 data->msgoutbuf[pos] = NOP; pos++;
423 data->msgout_len = pos;
424 }
425
426 /*
427 * Reject Message
428 */
429 static void nsp32_build_reject(struct scsi_cmnd *SCpnt)
430 {
431 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
432 int pos = data->msgout_len;
433
434 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
435 data->msgout_len = pos;
436 }
437
438 /*
439 * timer
440 */
441 #if 0
442 static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time)
443 {
444 unsigned int base = SCpnt->host->io_port;
445
446 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
447
448 if (time & (~TIMER_CNT_MASK)) {
449 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
450 }
451
452 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
453 }
454 #endif
455
456
457 /*
458 * set SCSI command and other parameter to asic, and start selection phase
459 */
460 static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt)
461 {
462 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
463 unsigned int base = SCpnt->device->host->io_port;
464 unsigned int host_id = SCpnt->device->host->this_id;
465 unsigned char target = scmd_id(SCpnt);
466 nsp32_autoparam *param = data->autoparam;
467 unsigned char phase;
468 int i, ret;
469 unsigned int msgout;
470 u16_le s;
471
472 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
473
474 /*
475 * check bus free
476 */
477 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
478 if (phase != BUSMON_BUS_FREE) {
479 nsp32_msg(KERN_WARNING, "bus busy");
480 show_busphase(phase & BUSMON_PHASE_MASK);
481 SCpnt->result = DID_BUS_BUSY << 16;
482 return FALSE;
483 }
484
485 /*
486 * message out
487 *
488 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
489 * over 3 messages needs another routine.
490 */
491 if (data->msgout_len == 0) {
492 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
493 SCpnt->result = DID_ERROR << 16;
494 return FALSE;
495 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
496 msgout = 0;
497 for (i = 0; i < data->msgout_len; i++) {
498 /*
499 * the sending order of the message is:
500 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
501 * MCNT 2: MSG#1 -> MSG#2
502 * MCNT 1: MSG#2
503 */
504 msgout >>= 8;
505 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
506 }
507 msgout |= MV_VALID; /* MV valid */
508 msgout |= (unsigned int)data->msgout_len; /* len */
509 } else {
510 /* data->msgout_len > 3 */
511 msgout = 0;
512 }
513
514 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n", nsp32_read2(base, SEL_TIME_OUT));
515 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
516
517 /*
518 * setup asic parameter
519 */
520 memset(param, 0, sizeof(nsp32_autoparam));
521
522 /* cdb */
523 for (i = 0; i < SCpnt->cmd_len; i++) {
524 param->cdb[4 * i] = SCpnt->cmnd[i];
525 }
526
527 /* outgoing messages */
528 param->msgout = cpu_to_le32(msgout);
529
530 /* syncreg, ackwidth, target id, SREQ sampling rate */
531 param->syncreg = data->cur_target->syncreg;
532 param->ackwidth = data->cur_target->ackwidth;
533 param->target_id = BIT(host_id) | BIT(target);
534 param->sample_reg = data->cur_target->sample_reg;
535
536 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg);
537
538 /* command control */
539 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER |
540 AUTOSCSI_START |
541 AUTO_MSGIN_00_OR_04 |
542 AUTO_MSGIN_02 |
543 AUTO_ATN );
544
545
546 /* transfer control */
547 s = 0;
548 switch (data->trans_method) {
549 case NSP32_TRANSFER_BUSMASTER:
550 s |= BM_START;
551 break;
552 case NSP32_TRANSFER_MMIO:
553 s |= CB_MMIO_MODE;
554 break;
555 case NSP32_TRANSFER_PIO:
556 s |= CB_IO_MODE;
557 break;
558 default:
559 nsp32_msg(KERN_ERR, "unknown trans_method");
560 break;
561 }
562 /*
563 * OR-ed BLIEND_MODE, FIFO intr is decreased, instead of PCI bus waits.
564 * For bus master transfer, it's taken off.
565 */
566 s |= (TRANSFER_GO | ALL_COUNTER_CLR);
567 param->transfer_control = cpu_to_le16(s);
568
569 /* sg table addr */
570 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
571
572 /*
573 * transfer parameter to ASIC
574 */
575 nsp32_write4(base, SGT_ADR, data->auto_paddr);
576 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER |
577 AUTO_PARAMETER );
578
579 /*
580 * Check arbitration
581 */
582 ret = nsp32_arbitration(SCpnt, base);
583
584 return ret;
585 }
586
587
588 /*
589 * Selection with AUTO SCSI (without AUTO PARAMETER)
590 */
591 static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt)
592 {
593 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
594 unsigned int base = SCpnt->device->host->io_port;
595 unsigned int host_id = SCpnt->device->host->this_id;
596 unsigned char target = scmd_id(SCpnt);
597 unsigned char phase;
598 int status;
599 unsigned short command = 0;
600 unsigned int msgout = 0;
601 unsigned short execph;
602 int i;
603
604 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
605
606 /*
607 * IRQ disable
608 */
609 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
610
611 /*
612 * check bus line
613 */
614 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
615 if(((phase & BUSMON_BSY) == 1) || (phase & BUSMON_SEL) == 1) {
616 nsp32_msg(KERN_WARNING, "bus busy");
617 SCpnt->result = DID_BUS_BUSY << 16;
618 status = 1;
619 goto out;
620 }
621
622 /*
623 * clear execph
624 */
625 execph = nsp32_read2(base, SCSI_EXECUTE_PHASE);
626
627 /*
628 * clear FIFO counter to set CDBs
629 */
630 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
631
632 /*
633 * set CDB0 - CDB15
634 */
635 for (i = 0; i < SCpnt->cmd_len; i++) {
636 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]);
637 }
638 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]);
639
640 /*
641 * set SCSIOUT LATCH(initiator)/TARGET(target) (OR-ed) ID
642 */
643 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target));
644
645 /*
646 * set SCSI MSGOUT REG
647 *
648 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
649 * over 3 messages needs another routine.
650 */
651 if (data->msgout_len == 0) {
652 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
653 SCpnt->result = DID_ERROR << 16;
654 status = 1;
655 goto out;
656 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
657 msgout = 0;
658 for (i = 0; i < data->msgout_len; i++) {
659 /*
660 * the sending order of the message is:
661 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
662 * MCNT 2: MSG#1 -> MSG#2
663 * MCNT 1: MSG#2
664 */
665 msgout >>= 8;
666 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
667 }
668 msgout |= MV_VALID; /* MV valid */
669 msgout |= (unsigned int)data->msgout_len; /* len */
670 nsp32_write4(base, SCSI_MSG_OUT, msgout);
671 } else {
672 /* data->msgout_len > 3 */
673 nsp32_write4(base, SCSI_MSG_OUT, 0);
674 }
675
676 /*
677 * set selection timeout(= 250ms)
678 */
679 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
680
681 /*
682 * set SREQ hazard killer sampling rate
683 *
684 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz.
685 * check other internal clock!
686 */
687 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
688
689 /*
690 * clear Arbit
691 */
692 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
693
694 /*
695 * set SYNCREG
696 * Don't set BM_START_ADR before setting this register.
697 */
698 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
699
700 /*
701 * set ACKWIDTH
702 */
703 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
704
705 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
706 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x",
707 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH),
708 nsp32_read4(base, SGT_ADR), nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
709 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x",
710 data->msgout_len, msgout);
711
712 /*
713 * set SGT ADDR (physical address)
714 */
715 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
716
717 /*
718 * set TRANSFER CONTROL REG
719 */
720 command = 0;
721 command |= (TRANSFER_GO | ALL_COUNTER_CLR);
722 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
723 if (scsi_bufflen(SCpnt) > 0) {
724 command |= BM_START;
725 }
726 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
727 command |= CB_MMIO_MODE;
728 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
729 command |= CB_IO_MODE;
730 }
731 nsp32_write2(base, TRANSFER_CONTROL, command);
732
733 /*
734 * start AUTO SCSI, kick off arbitration
735 */
736 command = (CLEAR_CDB_FIFO_POINTER |
737 AUTOSCSI_START |
738 AUTO_MSGIN_00_OR_04 |
739 AUTO_MSGIN_02 |
740 AUTO_ATN );
741 nsp32_write2(base, COMMAND_CONTROL, command);
742
743 /*
744 * Check arbitration
745 */
746 status = nsp32_arbitration(SCpnt, base);
747
748 out:
749 /*
750 * IRQ enable
751 */
752 nsp32_write2(base, IRQ_CONTROL, 0);
753
754 return status;
755 }
756
757
758 /*
759 * Arbitration Status Check
760 *
761 * Note: Arbitration counter is waited during ARBIT_GO is not lifting.
762 * Using udelay(1) consumes CPU time and system time, but
763 * arbitration delay time is defined minimal 2.4us in SCSI
764 * specification, thus udelay works as coarse grained wait timer.
765 */
766 static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base)
767 {
768 unsigned char arbit;
769 int status = TRUE;
770 int time = 0;
771
772 do {
773 arbit = nsp32_read1(base, ARBIT_STATUS);
774 time++;
775 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 &&
776 (time <= ARBIT_TIMEOUT_TIME));
777
778 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
779 "arbit: 0x%x, delay time: %d", arbit, time);
780
781 if (arbit & ARBIT_WIN) {
782 /* Arbitration succeeded */
783 SCpnt->result = DID_OK << 16;
784 nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */
785 } else if (arbit & ARBIT_FAIL) {
786 /* Arbitration failed */
787 SCpnt->result = DID_BUS_BUSY << 16;
788 status = FALSE;
789 } else {
790 /*
791 * unknown error or ARBIT_GO timeout,
792 * something lock up! guess no connection.
793 */
794 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout");
795 SCpnt->result = DID_NO_CONNECT << 16;
796 status = FALSE;
797 }
798
799 /*
800 * clear Arbit
801 */
802 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
803
804 return status;
805 }
806
807
808 /*
809 * reselection
810 *
811 * Note: This reselection routine is called from msgin_occur,
812 * reselection target id&lun must be already set.
813 * SCSI-2 says IDENTIFY implies RESTORE_POINTER operation.
814 */
815 static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun)
816 {
817 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
818 unsigned int host_id = SCpnt->device->host->this_id;
819 unsigned int base = SCpnt->device->host->io_port;
820 unsigned char tmpid, newid;
821
822 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter");
823
824 /*
825 * calculate reselected SCSI ID
826 */
827 tmpid = nsp32_read1(base, RESELECT_ID);
828 tmpid &= (~BIT(host_id));
829 newid = 0;
830 while (tmpid) {
831 if (tmpid & 1) {
832 break;
833 }
834 tmpid >>= 1;
835 newid++;
836 }
837
838 /*
839 * If reselected New ID:LUN is not existed
840 * or current nexus is not existed, unexpected
841 * reselection is occurred. Send reject message.
842 */
843 if (newid >= ARRAY_SIZE(data->lunt) || newlun >= ARRAY_SIZE(data->lunt[0])) {
844 nsp32_msg(KERN_WARNING, "unknown id/lun");
845 return FALSE;
846 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
847 nsp32_msg(KERN_WARNING, "no SCSI command is processing");
848 return FALSE;
849 }
850
851 data->cur_id = newid;
852 data->cur_lun = newlun;
853 data->cur_target = &(data->target[newid]);
854 data->cur_lunt = &(data->lunt[newid][newlun]);
855
856 /* reset SACK/SavedACK counter (or ALL clear?) */
857 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
858
859 return TRUE;
860 }
861
862
863 /*
864 * nsp32_setup_sg_table - build scatter gather list for transfer data
865 * with bus master.
866 *
867 * Note: NinjaSCSI-32Bi/UDE bus master can not transfer over 64KB at a time.
868 */
869 static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt)
870 {
871 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
872 struct scatterlist *sg;
873 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
874 int num, i;
875 u32_le l;
876
877 if (sgt == NULL) {
878 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null");
879 return FALSE;
880 }
881
882 num = scsi_dma_map(SCpnt);
883 if (!num)
884 return TRUE;
885 else if (num < 0)
886 return FALSE;
887 else {
888 scsi_for_each_sg(SCpnt, sg, num, i) {
889 /*
890 * Build nsp32_sglist, substitute sg dma addresses.
891 */
892 sgt[i].addr = cpu_to_le32(sg_dma_address(sg));
893 sgt[i].len = cpu_to_le32(sg_dma_len(sg));
894
895 if (le32_to_cpu(sgt[i].len) > 0x10000) {
896 nsp32_msg(KERN_ERR,
897 "can't transfer over 64KB at a time, size=0x%lx", le32_to_cpu(sgt[i].len));
898 return FALSE;
899 }
900 nsp32_dbg(NSP32_DEBUG_SGLIST,
901 "num 0x%x : addr 0x%lx len 0x%lx",
902 i,
903 le32_to_cpu(sgt[i].addr),
904 le32_to_cpu(sgt[i].len ));
905 }
906
907 /* set end mark */
908 l = le32_to_cpu(sgt[num-1].len);
909 sgt[num-1].len = cpu_to_le32(l | SGTEND);
910 }
911
912 return TRUE;
913 }
914
915 static int nsp32_queuecommand(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
916 {
917 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
918 nsp32_target *target;
919 nsp32_lunt *cur_lunt;
920 int ret;
921
922 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
923 "enter. target: 0x%x LUN: 0x%x cmnd: 0x%x cmndlen: 0x%x "
924 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x",
925 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0], SCpnt->cmd_len,
926 scsi_sg_count(SCpnt), scsi_sglist(SCpnt), scsi_bufflen(SCpnt));
927
928 if (data->CurrentSC != NULL) {
929 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request");
930 data->CurrentSC = NULL;
931 SCpnt->result = DID_NO_CONNECT << 16;
932 done(SCpnt);
933 return 0;
934 }
935
936 /* check target ID is not same as this initiator ID */
937 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) {
938 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "terget==host???");
939 SCpnt->result = DID_BAD_TARGET << 16;
940 done(SCpnt);
941 return 0;
942 }
943
944 /* check target LUN is allowable value */
945 if (SCpnt->device->lun >= MAX_LUN) {
946 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun");
947 SCpnt->result = DID_BAD_TARGET << 16;
948 done(SCpnt);
949 return 0;
950 }
951
952 show_command(SCpnt);
953
954 SCpnt->scsi_done = done;
955 data->CurrentSC = SCpnt;
956 SCpnt->SCp.Status = CHECK_CONDITION;
957 SCpnt->SCp.Message = 0;
958 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt));
959
960 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt);
961 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt);
962 SCpnt->SCp.buffer = NULL;
963 SCpnt->SCp.buffers_residual = 0;
964
965 /* initialize data */
966 data->msgout_len = 0;
967 data->msgin_len = 0;
968 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
969 cur_lunt->SCpnt = SCpnt;
970 cur_lunt->save_datp = 0;
971 cur_lunt->msgin03 = FALSE;
972 data->cur_lunt = cur_lunt;
973 data->cur_id = SCpnt->device->id;
974 data->cur_lun = SCpnt->device->lun;
975
976 ret = nsp32_setup_sg_table(SCpnt);
977 if (ret == FALSE) {
978 nsp32_msg(KERN_ERR, "SGT fail");
979 SCpnt->result = DID_ERROR << 16;
980 nsp32_scsi_done(SCpnt);
981 return 0;
982 }
983
984 /* Build IDENTIFY */
985 nsp32_build_identify(SCpnt);
986
987 /*
988 * If target is the first time to transfer after the reset
989 * (target don't have SDTR_DONE and SDTR_INITIATOR), sync
990 * message SDTR is needed to do synchronous transfer.
991 */
992 target = &data->target[scmd_id(SCpnt)];
993 data->cur_target = target;
994
995 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) {
996 unsigned char period, offset;
997
998 if (trans_mode != ASYNC_MODE) {
999 nsp32_set_max_sync(data, target, &period, &offset);
1000 nsp32_build_sdtr(SCpnt, period, offset);
1001 target->sync_flag |= SDTR_INITIATOR;
1002 } else {
1003 nsp32_set_async(data, target);
1004 target->sync_flag |= SDTR_DONE;
1005 }
1006
1007 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1008 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n",
1009 target->limit_entry, period, offset);
1010 } else if (target->sync_flag & SDTR_INITIATOR) {
1011 /*
1012 * It was negotiating SDTR with target, sending from the
1013 * initiator, but there are no chance to remove this flag.
1014 * Set async because we don't get proper negotiation.
1015 */
1016 nsp32_set_async(data, target);
1017 target->sync_flag &= ~SDTR_INITIATOR;
1018 target->sync_flag |= SDTR_DONE;
1019
1020 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1021 "SDTR_INITIATOR: fall back to async");
1022 } else if (target->sync_flag & SDTR_TARGET) {
1023 /*
1024 * It was negotiating SDTR with target, sending from target,
1025 * but there are no chance to remove this flag. Set async
1026 * because we don't get proper negotiation.
1027 */
1028 nsp32_set_async(data, target);
1029 target->sync_flag &= ~SDTR_TARGET;
1030 target->sync_flag |= SDTR_DONE;
1031
1032 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1033 "Unknown SDTR from target is reached, fall back to async.");
1034 }
1035
1036 nsp32_dbg(NSP32_DEBUG_TARGETFLAG,
1037 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x",
1038 SCpnt->device->id, target->sync_flag, target->syncreg,
1039 target->ackwidth);
1040
1041 /* Selection */
1042 if (auto_param == 0) {
1043 ret = nsp32_selection_autopara(SCpnt);
1044 } else {
1045 ret = nsp32_selection_autoscsi(SCpnt);
1046 }
1047
1048 if (ret != TRUE) {
1049 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail");
1050 nsp32_scsi_done(SCpnt);
1051 }
1052
1053 return 0;
1054 }
1055
1056 /* initialize asic */
1057 static int nsp32hw_init(nsp32_hw_data *data)
1058 {
1059 unsigned int base = data->BaseAddress;
1060 unsigned short irq_stat;
1061 unsigned long lc_reg;
1062 unsigned char power;
1063
1064 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE);
1065 if ((lc_reg & 0xff00) == 0) {
1066 lc_reg |= (0x20 << 8);
1067 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff);
1068 }
1069
1070 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1071 nsp32_write2(base, TRANSFER_CONTROL, 0);
1072 nsp32_write4(base, BM_CNT, 0);
1073 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1074
1075 do {
1076 irq_stat = nsp32_read2(base, IRQ_STATUS);
1077 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat);
1078 } while (irq_stat & IRQSTATUS_ANY_IRQ);
1079
1080 /*
1081 * Fill FIFO_FULL_SHLD, FIFO_EMPTY_SHLD. Below parameter is
1082 * designated by specification.
1083 */
1084 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1085 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1086 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40);
1087 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40);
1088 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1089 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10);
1090 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60);
1091 } else {
1092 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode");
1093 }
1094
1095 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x",
1096 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT),
1097 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT));
1098
1099 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1100 nsp32_index_write1(base, BM_CYCLE, MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD);
1101 nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */
1102
1103 /*
1104 * initialize MISC_WRRD register
1105 *
1106 * Note: Designated parameters is obeyed as following:
1107 * MISC_SCSI_DIRECTION_DETECTOR_SELECT: It must be set.
1108 * MISC_MASTER_TERMINATION_SELECT: It must be set.
1109 * MISC_BMREQ_NEGATE_TIMING_SEL: It should be set.
1110 * MISC_AUTOSEL_TIMING_SEL: It should be set.
1111 * MISC_BMSTOP_CHANGE2_NONDATA_PHASE: It should be set.
1112 * MISC_DELAYED_BMSTART: It's selected for safety.
1113 *
1114 * Note: If MISC_BMSTOP_CHANGE2_NONDATA_PHASE is set, then
1115 * we have to set TRANSFERCONTROL_BM_START as 0 and set
1116 * appropriate value before restarting bus master transfer.
1117 */
1118 nsp32_index_write2(base, MISC_WR,
1119 (SCSI_DIRECTION_DETECTOR_SELECT |
1120 DELAYED_BMSTART |
1121 MASTER_TERMINATION_SELECT |
1122 BMREQ_NEGATE_TIMING_SEL |
1123 AUTOSEL_TIMING_SEL |
1124 BMSTOP_CHANGE2_NONDATA_PHASE));
1125
1126 nsp32_index_write1(base, TERM_PWR_CONTROL, 0);
1127 power = nsp32_index_read1(base, TERM_PWR_CONTROL);
1128 if (!(power & SENSE)) {
1129 nsp32_msg(KERN_INFO, "term power on");
1130 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR);
1131 }
1132
1133 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1134 nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */
1135
1136 nsp32_write1(base, SYNC_REG, 0);
1137 nsp32_write1(base, ACK_WIDTH, 0);
1138 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
1139
1140 /*
1141 * enable to select designated IRQ (except for
1142 * IRQSELECT_SERR, IRQSELECT_PERR, IRQSELECT_BMCNTERR)
1143 */
1144 nsp32_index_write2(base, IRQ_SELECT, IRQSELECT_TIMER_IRQ |
1145 IRQSELECT_SCSIRESET_IRQ |
1146 IRQSELECT_FIFO_SHLD_IRQ |
1147 IRQSELECT_RESELECT_IRQ |
1148 IRQSELECT_PHASE_CHANGE_IRQ |
1149 IRQSELECT_AUTO_SCSI_SEQ_IRQ |
1150 // IRQSELECT_BMCNTERR_IRQ |
1151 IRQSELECT_TARGET_ABORT_IRQ |
1152 IRQSELECT_MASTER_ABORT_IRQ );
1153 nsp32_write2(base, IRQ_CONTROL, 0);
1154
1155 /* PCI LED off */
1156 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF);
1157 nsp32_index_write1(base, EXT_PORT, LED_OFF);
1158
1159 return TRUE;
1160 }
1161
1162
1163 /* interrupt routine */
1164 static irqreturn_t do_nsp32_isr(int irq, void *dev_id)
1165 {
1166 nsp32_hw_data *data = dev_id;
1167 unsigned int base = data->BaseAddress;
1168 struct scsi_cmnd *SCpnt = data->CurrentSC;
1169 unsigned short auto_stat, irq_stat, trans_stat;
1170 unsigned char busmon, busphase;
1171 unsigned long flags;
1172 int ret;
1173 int handled = 0;
1174 struct Scsi_Host *host = data->Host;
1175
1176 spin_lock_irqsave(host->host_lock, flags);
1177
1178 /*
1179 * IRQ check, then enable IRQ mask
1180 */
1181 irq_stat = nsp32_read2(base, IRQ_STATUS);
1182 nsp32_dbg(NSP32_DEBUG_INTR,
1183 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat);
1184 /* is this interrupt comes from Ninja asic? */
1185 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) {
1186 nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);
1187 goto out2;
1188 }
1189 handled = 1;
1190 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1191
1192 busmon = nsp32_read1(base, SCSI_BUS_MONITOR);
1193 busphase = busmon & BUSMON_PHASE_MASK;
1194
1195 trans_stat = nsp32_read2(base, TRANSFER_STATUS);
1196 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) {
1197 nsp32_msg(KERN_INFO, "card disconnect");
1198 if (data->CurrentSC != NULL) {
1199 nsp32_msg(KERN_INFO, "clean up current SCSI command");
1200 SCpnt->result = DID_BAD_TARGET << 16;
1201 nsp32_scsi_done(SCpnt);
1202 }
1203 goto out;
1204 }
1205
1206 /* Timer IRQ */
1207 if (irq_stat & IRQSTATUS_TIMER_IRQ) {
1208 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1209 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1210 goto out;
1211 }
1212
1213 /* SCSI reset */
1214 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) {
1215 nsp32_msg(KERN_INFO, "detected someone do bus reset");
1216 nsp32_do_bus_reset(data);
1217 if (SCpnt != NULL) {
1218 SCpnt->result = DID_RESET << 16;
1219 nsp32_scsi_done(SCpnt);
1220 }
1221 goto out;
1222 }
1223
1224 if (SCpnt == NULL) {
1225 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened");
1226 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1227 goto out;
1228 }
1229
1230 /*
1231 * AutoSCSI Interrupt.
1232 * Note: This interrupt is occurred when AutoSCSI is finished. Then
1233 * check SCSIEXECUTEPHASE, and do appropriate action. Each phases are
1234 * recorded when AutoSCSI sequencer has been processed.
1235 */
1236 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) {
1237 /* getting SCSI executed phase */
1238 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE);
1239 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1240
1241 /* Selection Timeout, go busfree phase. */
1242 if (auto_stat & SELECTION_TIMEOUT) {
1243 nsp32_dbg(NSP32_DEBUG_INTR,
1244 "selection timeout occurred");
1245
1246 SCpnt->result = DID_TIME_OUT << 16;
1247 nsp32_scsi_done(SCpnt);
1248 goto out;
1249 }
1250
1251 if (auto_stat & MSGOUT_PHASE) {
1252 /*
1253 * MsgOut phase was processed.
1254 * If MSG_IN_OCCUER is not set, then MsgOut phase is
1255 * completed. Thus, msgout_len must reset. Otherwise,
1256 * nothing to do here. If MSG_OUT_OCCUER is occurred,
1257 * then we will encounter the condition and check.
1258 */
1259 if (!(auto_stat & MSG_IN_OCCUER) &&
1260 (data->msgout_len <= 3)) {
1261 /*
1262 * !MSG_IN_OCCUER && msgout_len <=3
1263 * ---> AutoSCSI with MSGOUTreg is processed.
1264 */
1265 data->msgout_len = 0;
1266 };
1267
1268 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1269 }
1270
1271 if ((auto_stat & DATA_IN_PHASE) &&
1272 (scsi_get_resid(SCpnt) > 0) &&
1273 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) {
1274 printk( "auto+fifo\n");
1275 //nsp32_pio_read(SCpnt);
1276 }
1277
1278 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) {
1279 /* DATA_IN_PHASE/DATA_OUT_PHASE was processed. */
1280 nsp32_dbg(NSP32_DEBUG_INTR,
1281 "Data in/out phase processed");
1282
1283 /* read BMCNT, SGT pointer addr */
1284 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1285 nsp32_read4(base, BM_CNT));
1286 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1287 nsp32_read4(base, SGT_ADR));
1288 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1289 nsp32_read4(base, SACK_CNT));
1290 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1291 nsp32_read4(base, SAVED_SACK_CNT));
1292
1293 scsi_set_resid(SCpnt, 0); /* all data transfered! */
1294 }
1295
1296 /*
1297 * MsgIn Occur
1298 */
1299 if (auto_stat & MSG_IN_OCCUER) {
1300 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat);
1301 }
1302
1303 /*
1304 * MsgOut Occur
1305 */
1306 if (auto_stat & MSG_OUT_OCCUER) {
1307 nsp32_msgout_occur(SCpnt);
1308 }
1309
1310 /*
1311 * Bus Free Occur
1312 */
1313 if (auto_stat & BUS_FREE_OCCUER) {
1314 ret = nsp32_busfree_occur(SCpnt, auto_stat);
1315 if (ret == TRUE) {
1316 goto out;
1317 }
1318 }
1319
1320 if (auto_stat & STATUS_PHASE) {
1321 /*
1322 * Read CSB and substitute CSB for SCpnt->result
1323 * to save status phase stutas byte.
1324 * scsi error handler checks host_byte (DID_*:
1325 * low level driver to indicate status), then checks
1326 * status_byte (SCSI status byte).
1327 */
1328 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN);
1329 }
1330
1331 if (auto_stat & ILLEGAL_PHASE) {
1332 /* Illegal phase is detected. SACK is not back. */
1333 nsp32_msg(KERN_WARNING,
1334 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!");
1335
1336 /* TODO: currently we don't have any action... bus reset? */
1337
1338 /*
1339 * To send back SACK, assert, wait, and negate.
1340 */
1341 nsp32_sack_assert(data);
1342 nsp32_wait_req(data, NEGATE);
1343 nsp32_sack_negate(data);
1344
1345 }
1346
1347 if (auto_stat & COMMAND_PHASE) {
1348 /* nothing to do */
1349 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1350 }
1351
1352 if (auto_stat & AUTOSCSI_BUSY) {
1353 /* AutoSCSI is running */
1354 }
1355
1356 show_autophase(auto_stat);
1357 }
1358
1359 /* FIFO_SHLD_IRQ */
1360 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) {
1361 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1362
1363 switch(busphase) {
1364 case BUSPHASE_DATA_OUT:
1365 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1366
1367 //nsp32_pio_write(SCpnt);
1368
1369 break;
1370
1371 case BUSPHASE_DATA_IN:
1372 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1373
1374 //nsp32_pio_read(SCpnt);
1375
1376 break;
1377
1378 case BUSPHASE_STATUS:
1379 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1380
1381 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1382
1383 break;
1384 default:
1385 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1386 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1387 show_busphase(busphase);
1388 break;
1389 }
1390
1391 goto out;
1392 }
1393
1394 /* Phase Change IRQ */
1395 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) {
1396 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1397
1398 switch(busphase) {
1399 case BUSPHASE_MESSAGE_IN:
1400 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1401 nsp32_msgin_occur(SCpnt, irq_stat, 0);
1402 break;
1403 default:
1404 nsp32_msg(KERN_WARNING, "phase chg/other phase?");
1405 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n",
1406 irq_stat, trans_stat);
1407 show_busphase(busphase);
1408 break;
1409 }
1410 goto out;
1411 }
1412
1413 /* PCI_IRQ */
1414 if (irq_stat & IRQSTATUS_PCI_IRQ) {
1415 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1416 /* Do nothing */
1417 }
1418
1419 /* BMCNTERR_IRQ */
1420 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) {
1421 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! ");
1422 /*
1423 * TODO: To be implemented improving bus master
1424 * transfer reliablity when BMCNTERR is occurred in
1425 * AutoSCSI phase described in specification.
1426 */
1427 }
1428
1429 #if 0
1430 nsp32_dbg(NSP32_DEBUG_INTR,
1431 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1432 show_busphase(busphase);
1433 #endif
1434
1435 out:
1436 /* disable IRQ mask */
1437 nsp32_write2(base, IRQ_CONTROL, 0);
1438
1439 out2:
1440 spin_unlock_irqrestore(host->host_lock, flags);
1441
1442 nsp32_dbg(NSP32_DEBUG_INTR, "exit");
1443
1444 return IRQ_RETVAL(handled);
1445 }
1446
1447 #undef SPRINTF
1448 #define SPRINTF(args...) \
1449 do { \
1450 if(length > (pos - buffer)) { \
1451 pos += snprintf(pos, length - (pos - buffer) + 1, ## args); \
1452 nsp32_dbg(NSP32_DEBUG_PROC, "buffer=0x%p pos=0x%p length=%d %d\n", buffer, pos, length, length - (pos - buffer));\
1453 } \
1454 } while(0)
1455
1456 static int nsp32_proc_info(struct Scsi_Host *host, char *buffer, char **start,
1457 off_t offset, int length, int inout)
1458 {
1459 char *pos = buffer;
1460 int thislength;
1461 unsigned long flags;
1462 nsp32_hw_data *data;
1463 int hostno;
1464 unsigned int base;
1465 unsigned char mode_reg;
1466 int id, speed;
1467 long model;
1468
1469 /* Write is not supported, just return. */
1470 if (inout == TRUE) {
1471 return -EINVAL;
1472 }
1473
1474 hostno = host->host_no;
1475 data = (nsp32_hw_data *)host->hostdata;
1476 base = host->io_port;
1477
1478 SPRINTF("NinjaSCSI-32 status\n\n");
1479 SPRINTF("Driver version: %s, $Revision: 1.33 $\n", nsp32_release_version);
1480 SPRINTF("SCSI host No.: %d\n", hostno);
1481 SPRINTF("IRQ: %d\n", host->irq);
1482 SPRINTF("IO: 0x%lx-0x%lx\n", host->io_port, host->io_port + host->n_io_port - 1);
1483 SPRINTF("MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1);
1484 SPRINTF("sg_tablesize: %d\n", host->sg_tablesize);
1485 SPRINTF("Chip revision: 0x%x\n", (nsp32_read2(base, INDEX_REG) >> 8) & 0xff);
1486
1487 mode_reg = nsp32_index_read1(base, CHIP_MODE);
1488 model = data->pci_devid->driver_data;
1489
1490 #ifdef CONFIG_PM
1491 SPRINTF("Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no");
1492 #endif
1493 SPRINTF("OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]);
1494
1495 spin_lock_irqsave(&(data->Lock), flags);
1496 SPRINTF("CurrentSC: 0x%p\n\n", data->CurrentSC);
1497 spin_unlock_irqrestore(&(data->Lock), flags);
1498
1499
1500 SPRINTF("SDTR status\n");
1501 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1502
1503 SPRINTF("id %d: ", id);
1504
1505 if (id == host->this_id) {
1506 SPRINTF("----- NinjaSCSI-32 host adapter\n");
1507 continue;
1508 }
1509
1510 if (data->target[id].sync_flag == SDTR_DONE) {
1511 if (data->target[id].period == 0 &&
1512 data->target[id].offset == ASYNC_OFFSET ) {
1513 SPRINTF("async");
1514 } else {
1515 SPRINTF(" sync");
1516 }
1517 } else {
1518 SPRINTF(" none");
1519 }
1520
1521 if (data->target[id].period != 0) {
1522
1523 speed = 1000000 / (data->target[id].period * 4);
1524
1525 SPRINTF(" transfer %d.%dMB/s, offset %d",
1526 speed / 1000,
1527 speed % 1000,
1528 data->target[id].offset
1529 );
1530 }
1531 SPRINTF("\n");
1532 }
1533
1534
1535 thislength = pos - (buffer + offset);
1536
1537 if(thislength < 0) {
1538 *start = NULL;
1539 return 0;
1540 }
1541
1542
1543 thislength = min(thislength, length);
1544 *start = buffer + offset;
1545
1546 return thislength;
1547 }
1548 #undef SPRINTF
1549
1550
1551
1552 /*
1553 * Reset parameters and call scsi_done for data->cur_lunt.
1554 * Be careful setting SCpnt->result = DID_* before calling this function.
1555 */
1556 static void nsp32_scsi_done(struct scsi_cmnd *SCpnt)
1557 {
1558 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1559 unsigned int base = SCpnt->device->host->io_port;
1560
1561 scsi_dma_unmap(SCpnt);
1562
1563 /*
1564 * clear TRANSFERCONTROL_BM_START
1565 */
1566 nsp32_write2(base, TRANSFER_CONTROL, 0);
1567 nsp32_write4(base, BM_CNT, 0);
1568
1569 /*
1570 * call scsi_done
1571 */
1572 (*SCpnt->scsi_done)(SCpnt);
1573
1574 /*
1575 * reset parameters
1576 */
1577 data->cur_lunt->SCpnt = NULL;
1578 data->cur_lunt = NULL;
1579 data->cur_target = NULL;
1580 data->CurrentSC = NULL;
1581 }
1582
1583
1584 /*
1585 * Bus Free Occur
1586 *
1587 * Current Phase is BUSFREE. AutoSCSI is automatically execute BUSFREE phase
1588 * with ACK reply when below condition is matched:
1589 * MsgIn 00: Command Complete.
1590 * MsgIn 02: Save Data Pointer.
1591 * MsgIn 04: Diconnect.
1592 * In other case, unexpected BUSFREE is detected.
1593 */
1594 static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph)
1595 {
1596 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1597 unsigned int base = SCpnt->device->host->io_port;
1598
1599 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph);
1600 show_autophase(execph);
1601
1602 nsp32_write4(base, BM_CNT, 0);
1603 nsp32_write2(base, TRANSFER_CONTROL, 0);
1604
1605 /*
1606 * MsgIn 02: Save Data Pointer
1607 *
1608 * VALID:
1609 * Save Data Pointer is received. Adjust pointer.
1610 *
1611 * NO-VALID:
1612 * SCSI-3 says if Save Data Pointer is not received, then we restart
1613 * processing and we can't adjust any SCSI data pointer in next data
1614 * phase.
1615 */
1616 if (execph & MSGIN_02_VALID) {
1617 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid");
1618
1619 /*
1620 * Check sack_cnt/saved_sack_cnt, then adjust sg table if
1621 * needed.
1622 */
1623 if (!(execph & MSGIN_00_VALID) &&
1624 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) {
1625 unsigned int sacklen, s_sacklen;
1626
1627 /*
1628 * Read SACK count and SAVEDSACK count, then compare.
1629 */
1630 sacklen = nsp32_read4(base, SACK_CNT );
1631 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1632
1633 /*
1634 * If SAVEDSACKCNT == 0, it means SavedDataPointer is
1635 * come after data transfering.
1636 */
1637 if (s_sacklen > 0) {
1638 /*
1639 * Comparing between sack and savedsack to
1640 * check the condition of AutoMsgIn03.
1641 *
1642 * If they are same, set msgin03 == TRUE,
1643 * COMMANDCONTROL_AUTO_MSGIN_03 is enabled at
1644 * reselection. On the other hand, if they
1645 * aren't same, set msgin03 == FALSE, and
1646 * COMMANDCONTROL_AUTO_MSGIN_03 is disabled at
1647 * reselection.
1648 */
1649 if (sacklen != s_sacklen) {
1650 data->cur_lunt->msgin03 = FALSE;
1651 } else {
1652 data->cur_lunt->msgin03 = TRUE;
1653 }
1654
1655 nsp32_adjust_busfree(SCpnt, s_sacklen);
1656 }
1657 }
1658
1659 /* This value has not substitude with valid value yet... */
1660 //data->cur_lunt->save_datp = data->cur_datp;
1661 } else {
1662 /*
1663 * no processing.
1664 */
1665 }
1666
1667 if (execph & MSGIN_03_VALID) {
1668 /* MsgIn03 was valid to be processed. No need processing. */
1669 }
1670
1671 /*
1672 * target SDTR check
1673 */
1674 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1675 /*
1676 * SDTR negotiation pulled by the initiator has not
1677 * finished yet. Fall back to ASYNC mode.
1678 */
1679 nsp32_set_async(data, data->cur_target);
1680 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1681 data->cur_target->sync_flag |= SDTR_DONE;
1682 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1683 /*
1684 * SDTR negotiation pulled by the target has been
1685 * negotiating.
1686 */
1687 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) {
1688 /*
1689 * If valid message is received, then
1690 * negotiation is succeeded.
1691 */
1692 } else {
1693 /*
1694 * On the contrary, if unexpected bus free is
1695 * occurred, then negotiation is failed. Fall
1696 * back to ASYNC mode.
1697 */
1698 nsp32_set_async(data, data->cur_target);
1699 }
1700 data->cur_target->sync_flag &= ~SDTR_TARGET;
1701 data->cur_target->sync_flag |= SDTR_DONE;
1702 }
1703
1704 /*
1705 * It is always ensured by SCSI standard that initiator
1706 * switches into Bus Free Phase after
1707 * receiving message 00 (Command Complete), 04 (Disconnect).
1708 * It's the reason that processing here is valid.
1709 */
1710 if (execph & MSGIN_00_VALID) {
1711 /* MsgIn 00: Command Complete */
1712 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete");
1713
1714 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1715 SCpnt->SCp.Message = 0;
1716 nsp32_dbg(NSP32_DEBUG_BUSFREE,
1717 "normal end stat=0x%x resid=0x%x\n",
1718 SCpnt->SCp.Status, scsi_get_resid(SCpnt));
1719 SCpnt->result = (DID_OK << 16) |
1720 (SCpnt->SCp.Message << 8) |
1721 (SCpnt->SCp.Status << 0);
1722 nsp32_scsi_done(SCpnt);
1723 /* All operation is done */
1724 return TRUE;
1725 } else if (execph & MSGIN_04_VALID) {
1726 /* MsgIn 04: Disconnect */
1727 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1728 SCpnt->SCp.Message = 4;
1729
1730 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect");
1731 return TRUE;
1732 } else {
1733 /* Unexpected bus free */
1734 nsp32_msg(KERN_WARNING, "unexpected bus free occurred");
1735
1736 /* DID_ERROR? */
1737 //SCpnt->result = (DID_OK << 16) | (SCpnt->SCp.Message << 8) | (SCpnt->SCp.Status << 0);
1738 SCpnt->result = DID_ERROR << 16;
1739 nsp32_scsi_done(SCpnt);
1740 return TRUE;
1741 }
1742 return FALSE;
1743 }
1744
1745
1746 /*
1747 * nsp32_adjust_busfree - adjusting SG table
1748 *
1749 * Note: This driver adjust the SG table using SCSI ACK
1750 * counter instead of BMCNT counter!
1751 */
1752 static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen)
1753 {
1754 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1755 int old_entry = data->cur_entry;
1756 int new_entry;
1757 int sg_num = data->cur_lunt->sg_num;
1758 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1759 unsigned int restlen, sentlen;
1760 u32_le len, addr;
1761
1762 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt));
1763
1764 /* adjust saved SACK count with 4 byte start address boundary */
1765 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3;
1766
1767 /*
1768 * calculate new_entry from sack count and each sgt[].len
1769 * calculate the byte which is intent to send
1770 */
1771 sentlen = 0;
1772 for (new_entry = old_entry; new_entry < sg_num; new_entry++) {
1773 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND);
1774 if (sentlen > s_sacklen) {
1775 break;
1776 }
1777 }
1778
1779 /* all sgt is processed */
1780 if (new_entry == sg_num) {
1781 goto last;
1782 }
1783
1784 if (sentlen == s_sacklen) {
1785 /* XXX: confirm it's ok or not */
1786 /* In this case, it's ok because we are at
1787 the head element of the sg. restlen is correctly calculated. */
1788 }
1789
1790 /* calculate the rest length for transfering */
1791 restlen = sentlen - s_sacklen;
1792
1793 /* update adjusting current SG table entry */
1794 len = le32_to_cpu(sgt[new_entry].len);
1795 addr = le32_to_cpu(sgt[new_entry].addr);
1796 addr += (len - restlen);
1797 sgt[new_entry].addr = cpu_to_le32(addr);
1798 sgt[new_entry].len = cpu_to_le32(restlen);
1799
1800 /* set cur_entry with new_entry */
1801 data->cur_entry = new_entry;
1802
1803 return;
1804
1805 last:
1806 if (scsi_get_resid(SCpnt) < sentlen) {
1807 nsp32_msg(KERN_ERR, "resid underflow");
1808 }
1809
1810 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen);
1811 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt));
1812
1813 /* update hostdata and lun */
1814
1815 return;
1816 }
1817
1818
1819 /*
1820 * It's called MsgOut phase occur.
1821 * NinjaSCSI-32Bi/UDE automatically processes up to 3 messages in
1822 * message out phase. It, however, has more than 3 messages,
1823 * HBA creates the interrupt and we have to process by hand.
1824 */
1825 static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt)
1826 {
1827 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1828 unsigned int base = SCpnt->device->host->io_port;
1829 //unsigned short command;
1830 long new_sgtp;
1831 int i;
1832
1833 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1834 "enter: msgout_len: 0x%x", data->msgout_len);
1835
1836 /*
1837 * If MsgOut phase is occurred without having any
1838 * message, then No_Operation is sent (SCSI-2).
1839 */
1840 if (data->msgout_len == 0) {
1841 nsp32_build_nop(SCpnt);
1842 }
1843
1844 /*
1845 * Set SGTP ADDR current entry for restarting AUTOSCSI,
1846 * because SGTP is incremented next point.
1847 * There is few statement in the specification...
1848 */
1849 new_sgtp = data->cur_lunt->sglun_paddr +
1850 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
1851
1852 /*
1853 * send messages
1854 */
1855 for (i = 0; i < data->msgout_len; i++) {
1856 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1857 "%d : 0x%x", i, data->msgoutbuf[i]);
1858
1859 /*
1860 * Check REQ is asserted.
1861 */
1862 nsp32_wait_req(data, ASSERT);
1863
1864 if (i == (data->msgout_len - 1)) {
1865 /*
1866 * If the last message, set the AutoSCSI restart
1867 * before send back the ack message. AutoSCSI
1868 * restart automatically negate ATN signal.
1869 */
1870 //command = (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
1871 //nsp32_restart_autoscsi(SCpnt, command);
1872 nsp32_write2(base, COMMAND_CONTROL,
1873 (CLEAR_CDB_FIFO_POINTER |
1874 AUTO_COMMAND_PHASE |
1875 AUTOSCSI_RESTART |
1876 AUTO_MSGIN_00_OR_04 |
1877 AUTO_MSGIN_02 ));
1878 }
1879 /*
1880 * Write data with SACK, then wait sack is
1881 * automatically negated.
1882 */
1883 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1884 nsp32_wait_sack(data, NEGATE);
1885
1886 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n",
1887 nsp32_read1(base, SCSI_BUS_MONITOR));
1888 };
1889
1890 data->msgout_len = 0;
1891
1892 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit");
1893 }
1894
1895 /*
1896 * Restart AutoSCSI
1897 *
1898 * Note: Restarting AutoSCSI needs set:
1899 * SYNC_REG, ACK_WIDTH, SGT_ADR, TRANSFER_CONTROL
1900 */
1901 static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command)
1902 {
1903 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1904 unsigned int base = data->BaseAddress;
1905 unsigned short transfer = 0;
1906
1907 nsp32_dbg(NSP32_DEBUG_RESTART, "enter");
1908
1909 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1910 nsp32_msg(KERN_ERR, "Target or Lun is invalid");
1911 }
1912
1913 /*
1914 * set SYNC_REG
1915 * Don't set BM_START_ADR before setting this register.
1916 */
1917 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1918
1919 /*
1920 * set ACKWIDTH
1921 */
1922 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1923
1924 /*
1925 * set SREQ hazard killer sampling rate
1926 */
1927 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1928
1929 /*
1930 * set SGT ADDR (physical address)
1931 */
1932 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1933
1934 /*
1935 * set TRANSFER CONTROL REG
1936 */
1937 transfer = 0;
1938 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR);
1939 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1940 if (scsi_bufflen(SCpnt) > 0) {
1941 transfer |= BM_START;
1942 }
1943 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1944 transfer |= CB_MMIO_MODE;
1945 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1946 transfer |= CB_IO_MODE;
1947 }
1948 nsp32_write2(base, TRANSFER_CONTROL, transfer);
1949
1950 /*
1951 * restart AutoSCSI
1952 *
1953 * TODO: COMMANDCONTROL_AUTO_COMMAND_PHASE is needed ?
1954 */
1955 command |= (CLEAR_CDB_FIFO_POINTER |
1956 AUTO_COMMAND_PHASE |
1957 AUTOSCSI_RESTART );
1958 nsp32_write2(base, COMMAND_CONTROL, command);
1959
1960 nsp32_dbg(NSP32_DEBUG_RESTART, "exit");
1961 }
1962
1963
1964 /*
1965 * cannot run automatically message in occur
1966 */
1967 static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt,
1968 unsigned long irq_status,
1969 unsigned short execph)
1970 {
1971 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1972 unsigned int base = SCpnt->device->host->io_port;
1973 unsigned char msg;
1974 unsigned char msgtype;
1975 unsigned char newlun;
1976 unsigned short command = 0;
1977 int msgclear = TRUE;
1978 long new_sgtp;
1979 int ret;
1980
1981 /*
1982 * read first message
1983 * Use SCSIDATA_W_ACK instead of SCSIDATAIN, because the procedure
1984 * of Message-In have to be processed before sending back SCSI ACK.
1985 */
1986 msg = nsp32_read1(base, SCSI_DATA_IN);
1987 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1988 msgtype = data->msginbuf[0];
1989 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR,
1990 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x",
1991 data->msgin_len, msg, msgtype);
1992
1993 /*
1994 * TODO: We need checking whether bus phase is message in?
1995 */
1996
1997 /*
1998 * assert SCSI ACK
1999 */
2000 nsp32_sack_assert(data);
2001
2002 /*
2003 * processing IDENTIFY
2004 */
2005 if (msgtype & 0x80) {
2006 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) {
2007 /* Invalid (non reselect) phase */
2008 goto reject;
2009 }
2010
2011 newlun = msgtype & 0x1f; /* TODO: SPI-3 compliant? */
2012 ret = nsp32_reselection(SCpnt, newlun);
2013 if (ret == TRUE) {
2014 goto restart;
2015 } else {
2016 goto reject;
2017 }
2018 }
2019
2020 /*
2021 * processing messages except for IDENTIFY
2022 *
2023 * TODO: Messages are all SCSI-2 terminology. SCSI-3 compliance is TODO.
2024 */
2025 switch (msgtype) {
2026 /*
2027 * 1-byte message
2028 */
2029 case COMMAND_COMPLETE:
2030 case DISCONNECT:
2031 /*
2032 * These messages should not be occurred.
2033 * They should be processed on AutoSCSI sequencer.
2034 */
2035 nsp32_msg(KERN_WARNING,
2036 "unexpected message of AutoSCSI MsgIn: 0x%x", msg);
2037 break;
2038
2039 case RESTORE_POINTERS:
2040 /*
2041 * AutoMsgIn03 is disabled, and HBA gets this message.
2042 */
2043
2044 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) {
2045 unsigned int s_sacklen;
2046
2047 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
2048 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) {
2049 nsp32_adjust_busfree(SCpnt, s_sacklen);
2050 } else {
2051 /* No need to rewrite SGT */
2052 }
2053 }
2054 data->cur_lunt->msgin03 = FALSE;
2055
2056 /* Update with the new value */
2057
2058 /* reset SACK/SavedACK counter (or ALL clear?) */
2059 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2060
2061 /*
2062 * set new sg pointer
2063 */
2064 new_sgtp = data->cur_lunt->sglun_paddr +
2065 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2066 nsp32_write4(base, SGT_ADR, new_sgtp);
2067
2068 break;
2069
2070 case SAVE_POINTERS:
2071 /*
2072 * These messages should not be occurred.
2073 * They should be processed on AutoSCSI sequencer.
2074 */
2075 nsp32_msg (KERN_WARNING,
2076 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS");
2077
2078 break;
2079
2080 case MESSAGE_REJECT:
2081 /* If previous message_out is sending SDTR, and get
2082 message_reject from target, SDTR negotiation is failed */
2083 if (data->cur_target->sync_flag &
2084 (SDTR_INITIATOR | SDTR_TARGET)) {
2085 /*
2086 * Current target is negotiating SDTR, but it's
2087 * failed. Fall back to async transfer mode, and set
2088 * SDTR_DONE.
2089 */
2090 nsp32_set_async(data, data->cur_target);
2091 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2092 data->cur_target->sync_flag |= SDTR_DONE;
2093
2094 }
2095 break;
2096
2097 case LINKED_CMD_COMPLETE:
2098 case LINKED_FLG_CMD_COMPLETE:
2099 /* queue tag is not supported currently */
2100 nsp32_msg (KERN_WARNING,
2101 "unsupported message: 0x%x", msgtype);
2102 break;
2103
2104 case INITIATE_RECOVERY:
2105 /* staring ECA (Extended Contingent Allegiance) state. */
2106 /* This message is declined in SPI2 or later. */
2107
2108 goto reject;
2109
2110 /*
2111 * 2-byte message
2112 */
2113 case SIMPLE_QUEUE_TAG:
2114 case 0x23:
2115 /*
2116 * 0x23: Ignore_Wide_Residue is not declared in scsi.h.
2117 * No support is needed.
2118 */
2119 if (data->msgin_len >= 1) {
2120 goto reject;
2121 }
2122
2123 /* current position is 1-byte of 2 byte */
2124 msgclear = FALSE;
2125
2126 break;
2127
2128 /*
2129 * extended message
2130 */
2131 case EXTENDED_MESSAGE:
2132 if (data->msgin_len < 1) {
2133 /*
2134 * Current position does not reach 2-byte
2135 * (2-byte is extended message length).
2136 */
2137 msgclear = FALSE;
2138 break;
2139 }
2140
2141 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2142 /*
2143 * Current extended message has msginbuf[1] + 2
2144 * (msgin_len starts counting from 0, so buf[1] + 1).
2145 * If current message position is not finished,
2146 * continue receiving message.
2147 */
2148 msgclear = FALSE;
2149 break;
2150 }
2151
2152 /*
2153 * Reach here means regular length of each type of
2154 * extended messages.
2155 */
2156 switch (data->msginbuf[2]) {
2157 case EXTENDED_MODIFY_DATA_POINTER:
2158 /* TODO */
2159 goto reject; /* not implemented yet */
2160 break;
2161
2162 case EXTENDED_SDTR:
2163 /*
2164 * Exchange this message between initiator and target.
2165 */
2166 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2167 /*
2168 * received inappropriate message.
2169 */
2170 goto reject;
2171 break;
2172 }
2173
2174 nsp32_analyze_sdtr(SCpnt);
2175
2176 break;
2177
2178 case EXTENDED_EXTENDED_IDENTIFY:
2179 /* SCSI-I only, not supported. */
2180 goto reject; /* not implemented yet */
2181
2182 break;
2183
2184 case EXTENDED_WDTR:
2185 goto reject; /* not implemented yet */
2186
2187 break;
2188
2189 default:
2190 goto reject;
2191 }
2192 break;
2193
2194 default:
2195 goto reject;
2196 }
2197
2198 restart:
2199 if (msgclear == TRUE) {
2200 data->msgin_len = 0;
2201
2202 /*
2203 * If restarting AutoSCSI, but there are some message to out
2204 * (msgout_len > 0), set AutoATN, and set SCSIMSGOUT as 0
2205 * (MV_VALID = 0). When commandcontrol is written with
2206 * AutoSCSI restart, at the same time MsgOutOccur should be
2207 * happened (however, such situation is really possible...?).
2208 */
2209 if (data->msgout_len > 0) {
2210 nsp32_write4(base, SCSI_MSG_OUT, 0);
2211 command |= AUTO_ATN;
2212 }
2213
2214 /*
2215 * restart AutoSCSI
2216 * If it's failed, COMMANDCONTROL_AUTO_COMMAND_PHASE is needed.
2217 */
2218 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
2219
2220 /*
2221 * If current msgin03 is TRUE, then flag on.
2222 */
2223 if (data->cur_lunt->msgin03 == TRUE) {
2224 command |= AUTO_MSGIN_03;
2225 }
2226 data->cur_lunt->msgin03 = FALSE;
2227 } else {
2228 data->msgin_len++;
2229 }
2230
2231 /*
2232 * restart AutoSCSI
2233 */
2234 nsp32_restart_autoscsi(SCpnt, command);
2235
2236 /*
2237 * wait SCSI REQ negate for REQ-ACK handshake
2238 */
2239 nsp32_wait_req(data, NEGATE);
2240
2241 /*
2242 * negate SCSI ACK
2243 */
2244 nsp32_sack_negate(data);
2245
2246 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2247
2248 return;
2249
2250 reject:
2251 nsp32_msg(KERN_WARNING,
2252 "invalid or unsupported MessageIn, rejected. "
2253 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x",
2254 msg, data->msgin_len, msgtype);
2255 nsp32_build_reject(SCpnt);
2256 data->msgin_len = 0;
2257
2258 goto restart;
2259 }
2260
2261 /*
2262 *
2263 */
2264 static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt)
2265 {
2266 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2267 nsp32_target *target = data->cur_target;
2268 nsp32_sync_table *synct;
2269 unsigned char get_period = data->msginbuf[3];
2270 unsigned char get_offset = data->msginbuf[4];
2271 int entry;
2272 int syncnum;
2273
2274 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter");
2275
2276 synct = data->synct;
2277 syncnum = data->syncnum;
2278
2279 /*
2280 * If this inititor sent the SDTR message, then target responds SDTR,
2281 * initiator SYNCREG, ACKWIDTH from SDTR parameter.
2282 * Messages are not appropriate, then send back reject message.
2283 * If initiator did not send the SDTR, but target sends SDTR,
2284 * initiator calculator the appropriate parameter and send back SDTR.
2285 */
2286 if (target->sync_flag & SDTR_INITIATOR) {
2287 /*
2288 * Initiator sent SDTR, the target responds and
2289 * send back negotiation SDTR.
2290 */
2291 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR");
2292
2293 target->sync_flag &= ~SDTR_INITIATOR;
2294 target->sync_flag |= SDTR_DONE;
2295
2296 /*
2297 * offset:
2298 */
2299 if (get_offset > SYNC_OFFSET) {
2300 /*
2301 * Negotiation is failed, the target send back
2302 * unexpected offset value.
2303 */
2304 goto reject;
2305 }
2306
2307 if (get_offset == ASYNC_OFFSET) {
2308 /*
2309 * Negotiation is succeeded, the target want
2310 * to fall back into asynchronous transfer mode.
2311 */
2312 goto async;
2313 }
2314
2315 /*
2316 * period:
2317 * Check whether sync period is too short. If too short,
2318 * fall back to async mode. If it's ok, then investigate
2319 * the received sync period. If sync period is acceptable
2320 * between sync table start_period and end_period, then
2321 * set this I_T nexus as sent offset and period.
2322 * If it's not acceptable, send back reject and fall back
2323 * to async mode.
2324 */
2325 if (get_period < data->synct[0].period_num) {
2326 /*
2327 * Negotiation is failed, the target send back
2328 * unexpected period value.
2329 */
2330 goto reject;
2331 }
2332
2333 entry = nsp32_search_period_entry(data, target, get_period);
2334
2335 if (entry < 0) {
2336 /*
2337 * Target want to use long period which is not
2338 * acceptable NinjaSCSI-32Bi/UDE.
2339 */
2340 goto reject;
2341 }
2342
2343 /*
2344 * Set new sync table and offset in this I_T nexus.
2345 */
2346 nsp32_set_sync_entry(data, target, entry, get_offset);
2347 } else {
2348 /* Target send SDTR to initiator. */
2349 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR");
2350
2351 target->sync_flag |= SDTR_INITIATOR;
2352
2353 /* offset: */
2354 if (get_offset > SYNC_OFFSET) {
2355 /* send back as SYNC_OFFSET */
2356 get_offset = SYNC_OFFSET;
2357 }
2358
2359 /* period: */
2360 if (get_period < data->synct[0].period_num) {
2361 get_period = data->synct[0].period_num;
2362 }
2363
2364 entry = nsp32_search_period_entry(data, target, get_period);
2365
2366 if (get_offset == ASYNC_OFFSET || entry < 0) {
2367 nsp32_set_async(data, target);
2368 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET);
2369 } else {
2370 nsp32_set_sync_entry(data, target, entry, get_offset);
2371 nsp32_build_sdtr(SCpnt, get_period, get_offset);
2372 }
2373 }
2374
2375 target->period = get_period;
2376 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2377 return;
2378
2379 reject:
2380 /*
2381 * If the current message is unacceptable, send back to the target
2382 * with reject message.
2383 */
2384 nsp32_build_reject(SCpnt);
2385
2386 async:
2387 nsp32_set_async(data, target); /* set as ASYNC transfer mode */
2388
2389 target->period = 0;
2390 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async");
2391 return;
2392 }
2393
2394
2395 /*
2396 * Search config entry number matched in sync_table from given
2397 * target and speed period value. If failed to search, return negative value.
2398 */
2399 static int nsp32_search_period_entry(nsp32_hw_data *data,
2400 nsp32_target *target,
2401 unsigned char period)
2402 {
2403 int i;
2404
2405 if (target->limit_entry >= data->syncnum) {
2406 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!");
2407 target->limit_entry = 0;
2408 }
2409
2410 for (i = target->limit_entry; i < data->syncnum; i++) {
2411 if (period >= data->synct[i].start_period &&
2412 period <= data->synct[i].end_period) {
2413 break;
2414 }
2415 }
2416
2417 /*
2418 * Check given period value is over the sync_table value.
2419 * If so, return max value.
2420 */
2421 if (i == data->syncnum) {
2422 i = -1;
2423 }
2424
2425 return i;
2426 }
2427
2428
2429 /*
2430 * target <-> initiator use ASYNC transfer
2431 */
2432 static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2433 {
2434 unsigned char period = data->synct[target->limit_entry].period_num;
2435
2436 target->offset = ASYNC_OFFSET;
2437 target->period = 0;
2438 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET);
2439 target->ackwidth = 0;
2440 target->sample_reg = 0;
2441
2442 nsp32_dbg(NSP32_DEBUG_SYNC, "set async");
2443 }
2444
2445
2446 /*
2447 * target <-> initiator use maximum SYNC transfer
2448 */
2449 static void nsp32_set_max_sync(nsp32_hw_data *data,
2450 nsp32_target *target,
2451 unsigned char *period,
2452 unsigned char *offset)
2453 {
2454 unsigned char period_num, ackwidth;
2455
2456 period_num = data->synct[target->limit_entry].period_num;
2457 *period = data->synct[target->limit_entry].start_period;
2458 ackwidth = data->synct[target->limit_entry].ackwidth;
2459 *offset = SYNC_OFFSET;
2460
2461 target->syncreg = TO_SYNCREG(period_num, *offset);
2462 target->ackwidth = ackwidth;
2463 target->offset = *offset;
2464 target->sample_reg = 0; /* disable SREQ sampling */
2465 }
2466
2467
2468 /*
2469 * target <-> initiator use entry number speed
2470 */
2471 static void nsp32_set_sync_entry(nsp32_hw_data *data,
2472 nsp32_target *target,
2473 int entry,
2474 unsigned char offset)
2475 {
2476 unsigned char period, ackwidth, sample_rate;
2477
2478 period = data->synct[entry].period_num;
2479 ackwidth = data->synct[entry].ackwidth;
2480 offset = offset;
2481 sample_rate = data->synct[entry].sample_rate;
2482
2483 target->syncreg = TO_SYNCREG(period, offset);
2484 target->ackwidth = ackwidth;
2485 target->offset = offset;
2486 target->sample_reg = sample_rate | SAMPLING_ENABLE;
2487
2488 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync");
2489 }
2490
2491
2492 /*
2493 * It waits until SCSI REQ becomes assertion or negation state.
2494 *
2495 * Note: If nsp32_msgin_occur is called, we asserts SCSI ACK. Then
2496 * connected target responds SCSI REQ negation. We have to wait
2497 * SCSI REQ becomes negation in order to negate SCSI ACK signal for
2498 * REQ-ACK handshake.
2499 */
2500 static void nsp32_wait_req(nsp32_hw_data *data, int state)
2501 {
2502 unsigned int base = data->BaseAddress;
2503 int wait_time = 0;
2504 unsigned char bus, req_bit;
2505
2506 if (!((state == ASSERT) || (state == NEGATE))) {
2507 nsp32_msg(KERN_ERR, "unknown state designation");
2508 }
2509 /* REQ is BIT(5) */
2510 req_bit = (state == ASSERT ? BUSMON_REQ : 0);
2511
2512 do {
2513 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2514 if ((bus & BUSMON_REQ) == req_bit) {
2515 nsp32_dbg(NSP32_DEBUG_WAIT,
2516 "wait_time: %d", wait_time);
2517 return;
2518 }
2519 udelay(1);
2520 wait_time++;
2521 } while (wait_time < REQSACK_TIMEOUT_TIME);
2522
2523 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit);
2524 }
2525
2526 /*
2527 * It waits until SCSI SACK becomes assertion or negation state.
2528 */
2529 static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2530 {
2531 unsigned int base = data->BaseAddress;
2532 int wait_time = 0;
2533 unsigned char bus, ack_bit;
2534
2535 if (!((state == ASSERT) || (state == NEGATE))) {
2536 nsp32_msg(KERN_ERR, "unknown state designation");
2537 }
2538 /* ACK is BIT(4) */
2539 ack_bit = (state == ASSERT ? BUSMON_ACK : 0);
2540
2541 do {
2542 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2543 if ((bus & BUSMON_ACK) == ack_bit) {
2544 nsp32_dbg(NSP32_DEBUG_WAIT,
2545 "wait_time: %d", wait_time);
2546 return;
2547 }
2548 udelay(1);
2549 wait_time++;
2550 } while (wait_time < REQSACK_TIMEOUT_TIME);
2551
2552 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit);
2553 }
2554
2555 /*
2556 * assert SCSI ACK
2557 *
2558 * Note: SCSI ACK assertion needs with ACKENB=1, AUTODIRECTION=1.
2559 */
2560 static void nsp32_sack_assert(nsp32_hw_data *data)
2561 {
2562 unsigned int base = data->BaseAddress;
2563 unsigned char busctrl;
2564
2565 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2566 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB);
2567 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2568 }
2569
2570 /*
2571 * negate SCSI ACK
2572 */
2573 static void nsp32_sack_negate(nsp32_hw_data *data)
2574 {
2575 unsigned int base = data->BaseAddress;
2576 unsigned char busctrl;
2577
2578 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2579 busctrl &= ~BUSCTL_ACK;
2580 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2581 }
2582
2583
2584
2585 /*
2586 * Note: n_io_port is defined as 0x7f because I/O register port is
2587 * assigned as:
2588 * 0x800-0x8ff: memory mapped I/O port
2589 * 0x900-0xbff: (map same 0x800-0x8ff I/O port image repeatedly)
2590 * 0xc00-0xfff: CardBus status registers
2591 */
2592 static int nsp32_detect(struct pci_dev *pdev)
2593 {
2594 struct Scsi_Host *host; /* registered host structure */
2595 struct resource *res;
2596 nsp32_hw_data *data;
2597 int ret;
2598 int i, j;
2599
2600 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
2601
2602 /*
2603 * register this HBA as SCSI device
2604 */
2605 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data));
2606 if (host == NULL) {
2607 nsp32_msg (KERN_ERR, "failed to scsi register");
2608 goto err;
2609 }
2610
2611 /*
2612 * set nsp32_hw_data
2613 */
2614 data = (nsp32_hw_data *)host->hostdata;
2615
2616 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2617
2618 host->irq = data->IrqNumber;
2619 host->io_port = data->BaseAddress;
2620 host->unique_id = data->BaseAddress;
2621 host->n_io_port = data->NumAddress;
2622 host->base = (unsigned long)data->MmioAddress;
2623
2624 data->Host = host;
2625 spin_lock_init(&(data->Lock));
2626
2627 data->cur_lunt = NULL;
2628 data->cur_target = NULL;
2629
2630 /*
2631 * Bus master transfer mode is supported currently.
2632 */
2633 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2634
2635 /*
2636 * Set clock div, CLOCK_4 (HBA has own external clock, and
2637 * dividing * 100ns/4).
2638 * Currently CLOCK_4 has only tested, not for CLOCK_2/PCICLK yet.
2639 */
2640 data->clock = CLOCK_4;
2641
2642 /*
2643 * Select appropriate nsp32_sync_table and set I_CLOCKDIV.
2644 */
2645 switch (data->clock) {
2646 case CLOCK_4:
2647 /* If data->clock is CLOCK_4, then select 40M sync table. */
2648 data->synct = nsp32_sync_table_40M;
2649 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2650 break;
2651 case CLOCK_2:
2652 /* If data->clock is CLOCK_2, then select 20M sync table. */
2653 data->synct = nsp32_sync_table_20M;
2654 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2655 break;
2656 case PCICLK:
2657 /* If data->clock is PCICLK, then select pci sync table. */
2658 data->synct = nsp32_sync_table_pci;
2659 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2660 break;
2661 default:
2662 nsp32_msg(KERN_WARNING,
2663 "Invalid clock div is selected, set CLOCK_4.");
2664 /* Use default value CLOCK_4 */
2665 data->clock = CLOCK_4;
2666 data->synct = nsp32_sync_table_40M;
2667 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2668 }
2669
2670 /*
2671 * setup nsp32_lunt
2672 */
2673
2674 /*
2675 * setup DMA
2676 */
2677 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
2678 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask");
2679 goto scsi_unregister;
2680 }
2681
2682 /*
2683 * allocate autoparam DMA resource.
2684 */
2685 data->autoparam = pci_alloc_consistent(pdev, sizeof(nsp32_autoparam), &(data->auto_paddr));
2686 if (data->autoparam == NULL) {
2687 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2688 goto scsi_unregister;
2689 }
2690
2691 /*
2692 * allocate scatter-gather DMA resource.
2693 */
2694 data->sg_list = pci_alloc_consistent(pdev, NSP32_SG_TABLE_SIZE,
2695 &(data->sg_paddr));
2696 if (data->sg_list == NULL) {
2697 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2698 goto free_autoparam;
2699 }
2700
2701 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2702 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2703 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2704 nsp32_lunt tmp = {
2705 .SCpnt = NULL,
2706 .save_datp = 0,
2707 .msgin03 = FALSE,
2708 .sg_num = 0,
2709 .cur_entry = 0,
2710 .sglun = &(data->sg_list[offset]),
2711 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2712 };
2713
2714 data->lunt[i][j] = tmp;
2715 }
2716 }
2717
2718 /*
2719 * setup target
2720 */
2721 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2722 nsp32_target *target = &(data->target[i]);
2723
2724 target->limit_entry = 0;
2725 target->sync_flag = 0;
2726 nsp32_set_async(data, target);
2727 }
2728
2729 /*
2730 * EEPROM check
2731 */
2732 ret = nsp32_getprom_param(data);
2733 if (ret == FALSE) {
2734 data->resettime = 3; /* default 3 */
2735 }
2736
2737 /*
2738 * setup HBA
2739 */
2740 nsp32hw_init(data);
2741
2742 snprintf(data->info_str, sizeof(data->info_str),
2743 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x",
2744 host->irq, host->io_port, host->n_io_port);
2745
2746 /*
2747 * SCSI bus reset
2748 *
2749 * Note: It's important to reset SCSI bus in initialization phase.
2750 * NinjaSCSI-32Bi/UDE HBA EEPROM seems to exchange SDTR when
2751 * system is coming up, so SCSI devices connected to HBA is set as
2752 * un-asynchronous mode. It brings the merit that this HBA is
2753 * ready to start synchronous transfer without any preparation,
2754 * but we are difficult to control transfer speed. In addition,
2755 * it prevents device transfer speed from effecting EEPROM start-up
2756 * SDTR. NinjaSCSI-32Bi/UDE has the feature if EEPROM is set as
2757 * Auto Mode, then FAST-10M is selected when SCSI devices are
2758 * connected same or more than 4 devices. It should be avoided
2759 * depending on this specification. Thus, resetting the SCSI bus
2760 * restores all connected SCSI devices to asynchronous mode, then
2761 * this driver set SDTR safely later, and we can control all SCSI
2762 * device transfer mode.
2763 */
2764 nsp32_do_bus_reset(data);
2765
2766 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2767 if (ret < 0) {
2768 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 "
2769 "SCSI PCI controller. Interrupt: %d", host->irq);
2770 goto free_sg_list;
2771 }
2772
2773 /*
2774 * PCI IO register
2775 */
2776 res = request_region(host->io_port, host->n_io_port, "nsp32");
2777 if (res == NULL) {
2778 nsp32_msg(KERN_ERR,
2779 "I/O region 0x%lx+0x%lx is already used",
2780 data->BaseAddress, data->NumAddress);
2781 goto free_irq;
2782 }
2783
2784 ret = scsi_add_host(host, &pdev->dev);
2785 if (ret) {
2786 nsp32_msg(KERN_ERR, "failed to add scsi host");
2787 goto free_region;
2788 }
2789 scsi_scan_host(host);
2790 pci_set_drvdata(pdev, host);
2791 return 0;
2792
2793 free_region:
2794 release_region(host->io_port, host->n_io_port);
2795
2796 free_irq:
2797 free_irq(host->irq, data);
2798
2799 free_sg_list:
2800 pci_free_consistent(pdev, NSP32_SG_TABLE_SIZE,
2801 data->sg_list, data->sg_paddr);
2802
2803 free_autoparam:
2804 pci_free_consistent(pdev, sizeof(nsp32_autoparam),
2805 data->autoparam, data->auto_paddr);
2806
2807 scsi_unregister:
2808 scsi_host_put(host);
2809
2810 err:
2811 return 1;
2812 }
2813
2814 static int nsp32_release(struct Scsi_Host *host)
2815 {
2816 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2817
2818 if (data->autoparam) {
2819 pci_free_consistent(data->Pci, sizeof(nsp32_autoparam),
2820 data->autoparam, data->auto_paddr);
2821 }
2822
2823 if (data->sg_list) {
2824 pci_free_consistent(data->Pci, NSP32_SG_TABLE_SIZE,
2825 data->sg_list, data->sg_paddr);
2826 }
2827
2828 if (host->irq) {
2829 free_irq(host->irq, data);
2830 }
2831
2832 if (host->io_port && host->n_io_port) {
2833 release_region(host->io_port, host->n_io_port);
2834 }
2835
2836 if (data->MmioAddress) {
2837 iounmap(data->MmioAddress);
2838 }
2839
2840 return 0;
2841 }
2842
2843 static const char *nsp32_info(struct Scsi_Host *shpnt)
2844 {
2845 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2846
2847 return data->info_str;
2848 }
2849
2850
2851 /****************************************************************************
2852 * error handler
2853 */
2854 static int nsp32_eh_abort(struct scsi_cmnd *SCpnt)
2855 {
2856 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2857 unsigned int base = SCpnt->device->host->io_port;
2858
2859 nsp32_msg(KERN_WARNING, "abort");
2860
2861 if (data->cur_lunt->SCpnt == NULL) {
2862 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed");
2863 return FAILED;
2864 }
2865
2866 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2867 /* reset SDTR negotiation */
2868 data->cur_target->sync_flag = 0;
2869 nsp32_set_async(data, data->cur_target);
2870 }
2871
2872 nsp32_write2(base, TRANSFER_CONTROL, 0);
2873 nsp32_write2(base, BM_CNT, 0);
2874
2875 SCpnt->result = DID_ABORT << 16;
2876 nsp32_scsi_done(SCpnt);
2877
2878 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success");
2879 return SUCCESS;
2880 }
2881
2882 static int nsp32_eh_bus_reset(struct scsi_cmnd *SCpnt)
2883 {
2884 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2885 unsigned int base = SCpnt->device->host->io_port;
2886
2887 spin_lock_irq(SCpnt->device->host->host_lock);
2888
2889 nsp32_msg(KERN_INFO, "Bus Reset");
2890 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2891
2892 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2893 nsp32_do_bus_reset(data);
2894 nsp32_write2(base, IRQ_CONTROL, 0);
2895
2896 spin_unlock_irq(SCpnt->device->host->host_lock);
2897 return SUCCESS; /* SCSI bus reset is succeeded at any time. */
2898 }
2899
2900 static void nsp32_do_bus_reset(nsp32_hw_data *data)
2901 {
2902 unsigned int base = data->BaseAddress;
2903 unsigned short intrdat;
2904 int i;
2905
2906 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in");
2907
2908 /*
2909 * stop all transfer
2910 * clear TRANSFERCONTROL_BM_START
2911 * clear counter
2912 */
2913 nsp32_write2(base, TRANSFER_CONTROL, 0);
2914 nsp32_write4(base, BM_CNT, 0);
2915 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2916
2917 /*
2918 * fall back to asynchronous transfer mode
2919 * initialize SDTR negotiation flag
2920 */
2921 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2922 nsp32_target *target = &data->target[i];
2923
2924 target->sync_flag = 0;
2925 nsp32_set_async(data, target);
2926 }
2927
2928 /*
2929 * reset SCSI bus
2930 */
2931 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
2932 udelay(RESET_HOLD_TIME);
2933 nsp32_write1(base, SCSI_BUS_CONTROL, 0);
2934 for(i = 0; i < 5; i++) {
2935 intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */
2936 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat);
2937 }
2938
2939 data->CurrentSC = NULL;
2940 }
2941
2942 static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt)
2943 {
2944 struct Scsi_Host *host = SCpnt->device->host;
2945 unsigned int base = SCpnt->device->host->io_port;
2946 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2947
2948 nsp32_msg(KERN_INFO, "Host Reset");
2949 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2950
2951 spin_lock_irq(SCpnt->device->host->host_lock);
2952
2953 nsp32hw_init(data);
2954 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2955 nsp32_do_bus_reset(data);
2956 nsp32_write2(base, IRQ_CONTROL, 0);
2957
2958 spin_unlock_irq(SCpnt->device->host->host_lock);
2959 return SUCCESS; /* Host reset is succeeded at any time. */
2960 }
2961
2962
2963 /**************************************************************************
2964 * EEPROM handler
2965 */
2966
2967 /*
2968 * getting EEPROM parameter
2969 */
2970 static int nsp32_getprom_param(nsp32_hw_data *data)
2971 {
2972 int vendor = data->pci_devid->vendor;
2973 int device = data->pci_devid->device;
2974 int ret, val, i;
2975
2976 /*
2977 * EEPROM checking.
2978 */
2979 ret = nsp32_prom_read(data, 0x7e);
2980 if (ret != 0x55) {
2981 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret);
2982 return FALSE;
2983 }
2984 ret = nsp32_prom_read(data, 0x7f);
2985 if (ret != 0xaa) {
2986 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret);
2987 return FALSE;
2988 }
2989
2990 /*
2991 * check EEPROM type
2992 */
2993 if (vendor == PCI_VENDOR_ID_WORKBIT &&
2994 device == PCI_DEVICE_ID_WORKBIT_STANDARD) {
2995 ret = nsp32_getprom_c16(data);
2996 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2997 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) {
2998 ret = nsp32_getprom_at24(data);
2999 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
3000 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) {
3001 ret = nsp32_getprom_at24(data);
3002 } else {
3003 nsp32_msg(KERN_WARNING, "Unknown EEPROM");
3004 ret = FALSE;
3005 }
3006
3007 /* for debug : SPROM data full checking */
3008 for (i = 0; i <= 0x1f; i++) {
3009 val = nsp32_prom_read(data, i);
3010 nsp32_dbg(NSP32_DEBUG_EEPROM,
3011 "rom address 0x%x : 0x%x", i, val);
3012 }
3013
3014 return ret;
3015 }
3016
3017
3018 /*
3019 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map:
3020 *
3021 * ROMADDR
3022 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
3023 * Value 0x0: ASYNC, 0x0c: Ultra-20M, 0x19: Fast-10M
3024 * 0x07 : HBA Synchronous Transfer Period
3025 * Value 0: AutoSync, 1: Manual Setting
3026 * 0x08 - 0x0f : Not Used? (0x0)
3027 * 0x10 : Bus Termination
3028 * Value 0: Auto[ON], 1: ON, 2: OFF
3029 * 0x11 : Not Used? (0)
3030 * 0x12 : Bus Reset Delay Time (0x03)
3031 * 0x13 : Bootable CD Support
3032 * Value 0: Disable, 1: Enable
3033 * 0x14 : Device Scan
3034 * Bit 7 6 5 4 3 2 1 0
3035 * | <----------------->
3036 * | SCSI ID: Value 0: Skip, 1: YES
3037 * |-> Value 0: ALL scan, Value 1: Manual
3038 * 0x15 - 0x1b : Not Used? (0)
3039 * 0x1c : Constant? (0x01) (clock div?)
3040 * 0x1d - 0x7c : Not Used (0xff)
3041 * 0x7d : Not Used? (0xff)
3042 * 0x7e : Constant (0x55), Validity signature
3043 * 0x7f : Constant (0xaa), Validity signature
3044 */
3045 static int nsp32_getprom_at24(nsp32_hw_data *data)
3046 {
3047 int ret, i;
3048 int auto_sync;
3049 nsp32_target *target;
3050 int entry;
3051
3052 /*
3053 * Reset time which is designated by EEPROM.
3054 *
3055 * TODO: Not used yet.
3056 */
3057 data->resettime = nsp32_prom_read(data, 0x12);
3058
3059 /*
3060 * HBA Synchronous Transfer Period
3061 *
3062 * Note: auto_sync = 0: auto, 1: manual. Ninja SCSI HBA spec says
3063 * that if auto_sync is 0 (auto), and connected SCSI devices are
3064 * same or lower than 3, then transfer speed is set as ULTRA-20M.
3065 * On the contrary if connected SCSI devices are same or higher
3066 * than 4, then transfer speed is set as FAST-10M.
3067 *
3068 * I break this rule. The number of connected SCSI devices are
3069 * only ignored. If auto_sync is 0 (auto), then transfer speed is
3070 * forced as ULTRA-20M.
3071 */
3072 ret = nsp32_prom_read(data, 0x07);
3073 switch (ret) {
3074 case 0:
3075 auto_sync = TRUE;
3076 break;
3077 case 1:
3078 auto_sync = FALSE;
3079 break;
3080 default:
3081 nsp32_msg(KERN_WARNING,
3082 "Unsupported Auto Sync mode. Fall back to manual mode.");
3083 auto_sync = TRUE;
3084 }
3085
3086 if (trans_mode == ULTRA20M_MODE) {
3087 auto_sync = TRUE;
3088 }
3089
3090 /*
3091 * each device Synchronous Transfer Period
3092 */
3093 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3094 target = &data->target[i];
3095 if (auto_sync == TRUE) {
3096 target->limit_entry = 0; /* set as ULTRA20M */
3097 } else {
3098 ret = nsp32_prom_read(data, i);
3099 entry = nsp32_search_period_entry(data, target, ret);
3100 if (entry < 0) {
3101 /* search failed... set maximum speed */
3102 entry = 0;
3103 }
3104 target->limit_entry = entry;
3105 }
3106 }
3107
3108 return TRUE;
3109 }
3110
3111
3112 /*
3113 * C16 110 (I-O Data: SC-NBD) data map:
3114 *
3115 * ROMADDR
3116 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
3117 * Value 0x0: 20MB/S, 0x1: 10MB/S, 0x2: 5MB/S, 0x3: ASYNC
3118 * 0x07 : 0 (HBA Synchronous Transfer Period: Auto Sync)
3119 * 0x08 - 0x0f : Not Used? (0x0)
3120 * 0x10 : Transfer Mode
3121 * Value 0: PIO, 1: Busmater
3122 * 0x11 : Bus Reset Delay Time (0x00-0x20)
3123 * 0x12 : Bus Termination
3124 * Value 0: Disable, 1: Enable
3125 * 0x13 - 0x19 : Disconnection
3126 * Value 0: Disable, 1: Enable
3127 * 0x1a - 0x7c : Not Used? (0)
3128 * 0x7d : Not Used? (0xf8)
3129 * 0x7e : Constant (0x55), Validity signature
3130 * 0x7f : Constant (0xaa), Validity signature
3131 */
3132 static int nsp32_getprom_c16(nsp32_hw_data *data)
3133 {
3134 int ret, i;
3135 nsp32_target *target;
3136 int entry, val;
3137
3138 /*
3139 * Reset time which is designated by EEPROM.
3140 *
3141 * TODO: Not used yet.
3142 */
3143 data->resettime = nsp32_prom_read(data, 0x11);
3144
3145 /*
3146 * each device Synchronous Transfer Period
3147 */
3148 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3149 target = &data->target[i];
3150 ret = nsp32_prom_read(data, i);
3151 switch (ret) {
3152 case 0: /* 20MB/s */
3153 val = 0x0c;
3154 break;
3155 case 1: /* 10MB/s */
3156 val = 0x19;
3157 break;
3158 case 2: /* 5MB/s */
3159 val = 0x32;
3160 break;
3161 case 3: /* ASYNC */
3162 val = 0x00;
3163 break;
3164 default: /* default 20MB/s */
3165 val = 0x0c;
3166 break;
3167 }
3168 entry = nsp32_search_period_entry(data, target, val);
3169 if (entry < 0 || trans_mode == ULTRA20M_MODE) {
3170 /* search failed... set maximum speed */
3171 entry = 0;
3172 }
3173 target->limit_entry = entry;
3174 }
3175
3176 return TRUE;
3177 }
3178
3179
3180 /*
3181 * Atmel AT24C01A (drived in 5V) serial EEPROM routines
3182 */
3183 static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3184 {
3185 int i, val;
3186
3187 /* start condition */
3188 nsp32_prom_start(data);
3189
3190 /* device address */
3191 nsp32_prom_write_bit(data, 1); /* 1 */
3192 nsp32_prom_write_bit(data, 0); /* 0 */
3193 nsp32_prom_write_bit(data, 1); /* 1 */
3194 nsp32_prom_write_bit(data, 0); /* 0 */
3195 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3196 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3197 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3198
3199 /* R/W: W for dummy write */
3200 nsp32_prom_write_bit(data, 0);
3201
3202 /* ack */
3203 nsp32_prom_write_bit(data, 0);
3204
3205 /* word address */
3206 for (i = 7; i >= 0; i--) {
3207 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3208 }
3209
3210 /* ack */
3211 nsp32_prom_write_bit(data, 0);
3212
3213 /* start condition */
3214 nsp32_prom_start(data);
3215
3216 /* device address */
3217 nsp32_prom_write_bit(data, 1); /* 1 */
3218 nsp32_prom_write_bit(data, 0); /* 0 */
3219 nsp32_prom_write_bit(data, 1); /* 1 */
3220 nsp32_prom_write_bit(data, 0); /* 0 */
3221 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3222 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3223 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3224
3225 /* R/W: R */
3226 nsp32_prom_write_bit(data, 1);
3227
3228 /* ack */
3229 nsp32_prom_write_bit(data, 0);
3230
3231 /* data... */
3232 val = 0;
3233 for (i = 7; i >= 0; i--) {
3234 val += (nsp32_prom_read_bit(data) << i);
3235 }
3236
3237 /* no ack */
3238 nsp32_prom_write_bit(data, 1);
3239
3240 /* stop condition */
3241 nsp32_prom_stop(data);
3242
3243 return val;
3244 }
3245
3246 static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3247 {
3248 int base = data->BaseAddress;
3249 int tmp;
3250
3251 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL);
3252
3253 if (val == 0) {
3254 tmp &= ~bit;
3255 } else {
3256 tmp |= bit;
3257 }
3258
3259 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp);
3260
3261 udelay(10);
3262 }
3263
3264 static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3265 {
3266 int base = data->BaseAddress;
3267 int tmp, ret;
3268
3269 if (bit != SDA) {
3270 nsp32_msg(KERN_ERR, "return value is not appropriate");
3271 return 0;
3272 }
3273
3274
3275 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit;
3276
3277 if (tmp == 0) {
3278 ret = 0;
3279 } else {
3280 ret = 1;
3281 }
3282
3283 udelay(10);
3284
3285 return ret;
3286 }
3287
3288 static void nsp32_prom_start (nsp32_hw_data *data)
3289 {
3290 /* start condition */
3291 nsp32_prom_set(data, SCL, 1);
3292 nsp32_prom_set(data, SDA, 1);
3293 nsp32_prom_set(data, ENA, 1); /* output mode */
3294 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting
3295 * SDA 1->0 is start condition */
3296 nsp32_prom_set(data, SCL, 0);
3297 }
3298
3299 static void nsp32_prom_stop (nsp32_hw_data *data)
3300 {
3301 /* stop condition */
3302 nsp32_prom_set(data, SCL, 1);
3303 nsp32_prom_set(data, SDA, 0);
3304 nsp32_prom_set(data, ENA, 1); /* output mode */
3305 nsp32_prom_set(data, SDA, 1);
3306 nsp32_prom_set(data, SCL, 0);
3307 }
3308
3309 static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3310 {
3311 /* write */
3312 nsp32_prom_set(data, SDA, val);
3313 nsp32_prom_set(data, SCL, 1 );
3314 nsp32_prom_set(data, SCL, 0 );
3315 }
3316
3317 static int nsp32_prom_read_bit(nsp32_hw_data *data)
3318 {
3319 int val;
3320
3321 /* read */
3322 nsp32_prom_set(data, ENA, 0); /* input mode */
3323 nsp32_prom_set(data, SCL, 1);
3324
3325 val = nsp32_prom_get(data, SDA);
3326
3327 nsp32_prom_set(data, SCL, 0);
3328 nsp32_prom_set(data, ENA, 1); /* output mode */
3329
3330 return val;
3331 }
3332
3333
3334 /**************************************************************************
3335 * Power Management
3336 */
3337 #ifdef CONFIG_PM
3338
3339 /* Device suspended */
3340 static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state)
3341 {
3342 struct Scsi_Host *host = pci_get_drvdata(pdev);
3343
3344 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state=%ld, slot=%s, host=0x%p", pdev, state, pci_name(pdev), host);
3345
3346 pci_save_state (pdev);
3347 pci_disable_device (pdev);
3348 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3349
3350 return 0;
3351 }
3352
3353 /* Device woken up */
3354 static int nsp32_resume(struct pci_dev *pdev)
3355 {
3356 struct Scsi_Host *host = pci_get_drvdata(pdev);
3357 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3358 unsigned short reg;
3359
3360 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p", pdev, pci_name(pdev), host);
3361
3362 pci_set_power_state(pdev, PCI_D0);
3363 pci_enable_wake (pdev, PCI_D0, 0);
3364 pci_restore_state (pdev);
3365
3366 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3367
3368 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3369
3370 if (reg == 0xffff) {
3371 nsp32_msg(KERN_INFO, "missing device. abort resume.");
3372 return 0;
3373 }
3374
3375 nsp32hw_init (data);
3376 nsp32_do_bus_reset(data);
3377
3378 nsp32_msg(KERN_INFO, "resume success");
3379
3380 return 0;
3381 }
3382
3383 #endif
3384
3385 /************************************************************************
3386 * PCI/Cardbus probe/remove routine
3387 */
3388 static int __devinit nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3389 {
3390 int ret;
3391 nsp32_hw_data *data = &nsp32_data_base;
3392
3393 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3394
3395 ret = pci_enable_device(pdev);
3396 if (ret) {
3397 nsp32_msg(KERN_ERR, "failed to enable pci device");
3398 return ret;
3399 }
3400
3401 data->Pci = pdev;
3402 data->pci_devid = id;
3403 data->IrqNumber = pdev->irq;
3404 data->BaseAddress = pci_resource_start(pdev, 0);
3405 data->NumAddress = pci_resource_len (pdev, 0);
3406 data->MmioAddress = ioremap_nocache(pci_resource_start(pdev, 1),
3407 pci_resource_len (pdev, 1));
3408 data->MmioLength = pci_resource_len (pdev, 1);
3409
3410 pci_set_master(pdev);
3411
3412 ret = nsp32_detect(pdev);
3413
3414 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s",
3415 pdev->irq,
3416 data->MmioAddress, data->MmioLength,
3417 pci_name(pdev),
3418 nsp32_model[id->driver_data]);
3419
3420 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret);
3421
3422 return ret;
3423 }
3424
3425 static void __devexit nsp32_remove(struct pci_dev *pdev)
3426 {
3427 struct Scsi_Host *host = pci_get_drvdata(pdev);
3428
3429 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3430
3431 scsi_remove_host(host);
3432
3433 nsp32_release(host);
3434
3435 scsi_host_put(host);
3436 }
3437
3438 static struct pci_driver nsp32_driver = {
3439 .name = "nsp32",
3440 .id_table = nsp32_pci_table,
3441 .probe = nsp32_probe,
3442 .remove = __devexit_p(nsp32_remove),
3443 #ifdef CONFIG_PM
3444 .suspend = nsp32_suspend,
3445 .resume = nsp32_resume,
3446 #endif
3447 };
3448
3449 /*********************************************************************
3450 * Moule entry point
3451 */
3452 static int __init init_nsp32(void) {
3453 nsp32_msg(KERN_INFO, "loading...");
3454 return pci_register_driver(&nsp32_driver);
3455 }
3456
3457 static void __exit exit_nsp32(void) {
3458 nsp32_msg(KERN_INFO, "unloading...");
3459 pci_unregister_driver(&nsp32_driver);
3460 }
3461
3462 module_init(init_nsp32);
3463 module_exit(exit_nsp32);
3464
3465 /* end */
kernel-based virtual machine