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ath9k: Move AR5416_VER_MASK to a common location
[linux-2.6/kvm.git] / drivers / net / wireless / ath9k / eeprom.c
blob49dee238c683177a68bcc5c29735a86a2396124b
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
20 u32 reg, u32 mask,
21 u32 shift, u32 val)
22 {
23 u32 regVal;
24
25 regVal = REG_READ(ah, reg) & ~mask;
26 regVal |= (val << shift) & mask;
27
28 REG_WRITE(ah, reg, regVal);
29
30 if (ah->config.analog_shiftreg)
31 udelay(100);
32
33 return;
34 }
35
36 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
37 {
38
39 if (fbin == AR5416_BCHAN_UNUSED)
40 return fbin;
41
42 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
43 }
44
45 static inline int16_t ath9k_hw_interpolate(u16 target,
46 u16 srcLeft, u16 srcRight,
47 int16_t targetLeft,
48 int16_t targetRight)
49 {
50 int16_t rv;
51
52 if (srcRight == srcLeft) {
53 rv = targetLeft;
54 } else {
55 rv = (int16_t) (((target - srcLeft) * targetRight +
56 (srcRight - target) * targetLeft) /
57 (srcRight - srcLeft));
58 }
59 return rv;
60 }
61
62 static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
63 u16 listSize, u16 *indexL,
64 u16 *indexR)
65 {
66 u16 i;
67
68 if (target <= pList[0]) {
69 *indexL = *indexR = 0;
70 return true;
71 }
72 if (target >= pList[listSize - 1]) {
73 *indexL = *indexR = (u16) (listSize - 1);
74 return true;
75 }
76
77 for (i = 0; i < listSize - 1; i++) {
78 if (pList[i] == target) {
79 *indexL = *indexR = i;
80 return true;
81 }
82 if (target < pList[i + 1]) {
83 *indexL = i;
84 *indexR = (u16) (i + 1);
85 return false;
86 }
87 }
88 return false;
89 }
90
91 static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
92 {
93 struct ath_softc *sc = ah->ah_sc;
94
95 return sc->bus_ops->eeprom_read(ah, off, data);
96 }
97
98 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
99 u8 *pVpdList, u16 numIntercepts,
100 u8 *pRetVpdList)
101 {
102 u16 i, k;
103 u8 currPwr = pwrMin;
104 u16 idxL = 0, idxR = 0;
105
106 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
107 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
108 numIntercepts, &(idxL),
109 &(idxR));
110 if (idxR < 1)
111 idxR = 1;
112 if (idxL == numIntercepts - 1)
113 idxL = (u16) (numIntercepts - 2);
114 if (pPwrList[idxL] == pPwrList[idxR])
115 k = pVpdList[idxL];
116 else
117 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
118 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
119 (pPwrList[idxR] - pPwrList[idxL]));
120 pRetVpdList[i] = (u8) k;
121 currPwr += 2;
122 }
123
124 return true;
125 }
126
127 static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
128 struct ath9k_channel *chan,
129 struct cal_target_power_leg *powInfo,
130 u16 numChannels,
131 struct cal_target_power_leg *pNewPower,
132 u16 numRates, bool isExtTarget)
133 {
134 struct chan_centers centers;
135 u16 clo, chi;
136 int i;
137 int matchIndex = -1, lowIndex = -1;
138 u16 freq;
139
140 ath9k_hw_get_channel_centers(ah, chan, &centers);
141 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
142
143 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
144 IS_CHAN_2GHZ(chan))) {
145 matchIndex = 0;
146 } else {
147 for (i = 0; (i < numChannels) &&
148 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
149 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
150 IS_CHAN_2GHZ(chan))) {
151 matchIndex = i;
152 break;
153 } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
154 IS_CHAN_2GHZ(chan))) &&
155 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
156 IS_CHAN_2GHZ(chan)))) {
157 lowIndex = i - 1;
158 break;
159 }
160 }
161 if ((matchIndex == -1) && (lowIndex == -1))
162 matchIndex = i - 1;
163 }
164
165 if (matchIndex != -1) {
166 *pNewPower = powInfo[matchIndex];
167 } else {
168 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
169 IS_CHAN_2GHZ(chan));
170 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
171 IS_CHAN_2GHZ(chan));
172
173 for (i = 0; i < numRates; i++) {
174 pNewPower->tPow2x[i] =
175 (u8)ath9k_hw_interpolate(freq, clo, chi,
176 powInfo[lowIndex].tPow2x[i],
177 powInfo[lowIndex + 1].tPow2x[i]);
178 }
179 }
180 }
181
182 static void ath9k_get_txgain_index(struct ath_hw *ah,
183 struct ath9k_channel *chan,
184 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
185 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
186 {
187 u8 pcdac, i = 0;
188 u16 idxL = 0, idxR = 0, numPiers;
189 bool match;
190 struct chan_centers centers;
191
192 ath9k_hw_get_channel_centers(ah, chan, &centers);
193
194 for (numPiers = 0; numPiers < availPiers; numPiers++)
195 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
196 break;
197
198 match = ath9k_hw_get_lower_upper_index(
199 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
200 calChans, numPiers, &idxL, &idxR);
201 if (match) {
202 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
203 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
204 } else {
205 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
206 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
207 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
208 }
209
210 while (pcdac > ah->originalGain[i] &&
211 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
212 i++;
213
214 *pcdacIdx = i;
215 return;
216 }
217
218 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
219 u32 initTxGain,
220 int txPower,
221 u8 *pPDADCValues)
222 {
223 u32 i;
224 u32 offset;
225
226 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
227 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
228 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
229 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
230
231 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
232 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
233
234 offset = txPower;
235 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
236 if (i < offset)
237 pPDADCValues[i] = 0x0;
238 else
239 pPDADCValues[i] = 0xFF;
240 }
241
242
243
244
245 static void ath9k_hw_get_target_powers(struct ath_hw *ah,
246 struct ath9k_channel *chan,
247 struct cal_target_power_ht *powInfo,
248 u16 numChannels,
249 struct cal_target_power_ht *pNewPower,
250 u16 numRates, bool isHt40Target)
251 {
252 struct chan_centers centers;
253 u16 clo, chi;
254 int i;
255 int matchIndex = -1, lowIndex = -1;
256 u16 freq;
257
258 ath9k_hw_get_channel_centers(ah, chan, &centers);
259 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
260
261 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
262 matchIndex = 0;
263 } else {
264 for (i = 0; (i < numChannels) &&
265 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
266 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
267 IS_CHAN_2GHZ(chan))) {
268 matchIndex = i;
269 break;
270 } else
271 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
272 IS_CHAN_2GHZ(chan))) &&
273 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
274 IS_CHAN_2GHZ(chan)))) {
275 lowIndex = i - 1;
276 break;
277 }
278 }
279 if ((matchIndex == -1) && (lowIndex == -1))
280 matchIndex = i - 1;
281 }
282
283 if (matchIndex != -1) {
284 *pNewPower = powInfo[matchIndex];
285 } else {
286 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
287 IS_CHAN_2GHZ(chan));
288 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
289 IS_CHAN_2GHZ(chan));
290
291 for (i = 0; i < numRates; i++) {
292 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
293 clo, chi,
294 powInfo[lowIndex].tPow2x[i],
295 powInfo[lowIndex + 1].tPow2x[i]);
296 }
297 }
298 }
299
300 static u16 ath9k_hw_get_max_edge_power(u16 freq,
301 struct cal_ctl_edges *pRdEdgesPower,
302 bool is2GHz, int num_band_edges)
303 {
304 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
305 int i;
306
307 for (i = 0; (i < num_band_edges) &&
308 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
309 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
310 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
311 break;
312 } else if ((i > 0) &&
313 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
314 is2GHz))) {
315 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
316 is2GHz) < freq &&
317 pRdEdgesPower[i - 1].flag) {
318 twiceMaxEdgePower =
319 pRdEdgesPower[i - 1].tPower;
320 }
321 break;
322 }
323 }
324
325 return twiceMaxEdgePower;
326 }
327
328 /****************************************/
329 /* EEPROM Operations for 4K sized cards */
330 /****************************************/
331
332 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
333 {
334 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
335 }
336
337 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
338 {
339 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
340 }
341
342 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
343 {
344 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
345 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
346 int addr, eep_start_loc = 0;
347
348 eep_start_loc = 64;
349
350 if (!ath9k_hw_use_flash(ah)) {
351 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
352 "Reading from EEPROM, not flash\n");
353 }
354
355 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
356 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
357 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
358 "Unable to read eeprom region \n");
359 return false;
360 }
361 eep_data++;
362 }
363
364 return true;
365 #undef SIZE_EEPROM_4K
366 }
367
368 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
369 {
370 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
371 struct ar5416_eeprom_4k *eep =
372 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
373 u16 *eepdata, temp, magic, magic2;
374 u32 sum = 0, el;
375 bool need_swap = false;
376 int i, addr;
377
378
379 if (!ath9k_hw_use_flash(ah)) {
380 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
381 &magic)) {
382 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
383 "Reading Magic # failed\n");
384 return false;
385 }
386
387 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
388 "Read Magic = 0x%04X\n", magic);
389
390 if (magic != AR5416_EEPROM_MAGIC) {
391 magic2 = swab16(magic);
392
393 if (magic2 == AR5416_EEPROM_MAGIC) {
394 need_swap = true;
395 eepdata = (u16 *) (&ah->eeprom);
396
397 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
398 temp = swab16(*eepdata);
399 *eepdata = temp;
400 eepdata++;
401 }
402 } else {
403 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
404 "Invalid EEPROM Magic. "
405 "endianness mismatch.\n");
406 return -EINVAL;
407 }
408 }
409 }
410
411 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
412 need_swap ? "True" : "False");
413
414 if (need_swap)
415 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
416 else
417 el = ah->eeprom.map4k.baseEepHeader.length;
418
419 if (el > sizeof(struct ar5416_eeprom_def))
420 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
421 else
422 el = el / sizeof(u16);
423
424 eepdata = (u16 *)(&ah->eeprom);
425
426 for (i = 0; i < el; i++)
427 sum ^= *eepdata++;
428
429 if (need_swap) {
430 u32 integer;
431 u16 word;
432
433 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
434 "EEPROM Endianness is not native.. Changing\n");
435
436 word = swab16(eep->baseEepHeader.length);
437 eep->baseEepHeader.length = word;
438
439 word = swab16(eep->baseEepHeader.checksum);
440 eep->baseEepHeader.checksum = word;
441
442 word = swab16(eep->baseEepHeader.version);
443 eep->baseEepHeader.version = word;
444
445 word = swab16(eep->baseEepHeader.regDmn[0]);
446 eep->baseEepHeader.regDmn[0] = word;
447
448 word = swab16(eep->baseEepHeader.regDmn[1]);
449 eep->baseEepHeader.regDmn[1] = word;
450
451 word = swab16(eep->baseEepHeader.rfSilent);
452 eep->baseEepHeader.rfSilent = word;
453
454 word = swab16(eep->baseEepHeader.blueToothOptions);
455 eep->baseEepHeader.blueToothOptions = word;
456
457 word = swab16(eep->baseEepHeader.deviceCap);
458 eep->baseEepHeader.deviceCap = word;
459
460 integer = swab32(eep->modalHeader.antCtrlCommon);
461 eep->modalHeader.antCtrlCommon = integer;
462
463 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
464 integer = swab32(eep->modalHeader.antCtrlChain[i]);
465 eep->modalHeader.antCtrlChain[i] = integer;
466 }
467
468 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
469 word = swab16(eep->modalHeader.spurChans[i].spurChan);
470 eep->modalHeader.spurChans[i].spurChan = word;
471 }
472 }
473
474 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
475 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
476 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
477 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
478 sum, ah->eep_ops->get_eeprom_ver(ah));
479 return -EINVAL;
480 }
481
482 return 0;
483 #undef EEPROM_4K_SIZE
484 }
485
486 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
487 enum eeprom_param param)
488 {
489 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
490 struct modal_eep_4k_header *pModal = &eep->modalHeader;
491 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
492
493 switch (param) {
494 case EEP_NFTHRESH_2:
495 return pModal->noiseFloorThreshCh[0];
496 case AR_EEPROM_MAC(0):
497 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
498 case AR_EEPROM_MAC(1):
499 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
500 case AR_EEPROM_MAC(2):
501 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
502 case EEP_REG_0:
503 return pBase->regDmn[0];
504 case EEP_REG_1:
505 return pBase->regDmn[1];
506 case EEP_OP_CAP:
507 return pBase->deviceCap;
508 case EEP_OP_MODE:
509 return pBase->opCapFlags;
510 case EEP_RF_SILENT:
511 return pBase->rfSilent;
512 case EEP_OB_2:
513 return pModal->ob_01;
514 case EEP_DB_2:
515 return pModal->db1_01;
516 case EEP_MINOR_REV:
517 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
518 case EEP_TX_MASK:
519 return pBase->txMask;
520 case EEP_RX_MASK:
521 return pBase->rxMask;
522 case EEP_FRAC_N_5G:
523 return 0;
524 default:
525 return 0;
526 }
527 }
528
529 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
530 struct ath9k_channel *chan,
531 struct cal_data_per_freq_4k *pRawDataSet,
532 u8 *bChans, u16 availPiers,
533 u16 tPdGainOverlap, int16_t *pMinCalPower,
534 u16 *pPdGainBoundaries, u8 *pPDADCValues,
535 u16 numXpdGains)
536 {
537 #define TMP_VAL_VPD_TABLE \
538 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
539 int i, j, k;
540 int16_t ss;
541 u16 idxL = 0, idxR = 0, numPiers;
542 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
543 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
544 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
545 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
546 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
547 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
548
549 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
550 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
551 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
552 int16_t vpdStep;
553 int16_t tmpVal;
554 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
555 bool match;
556 int16_t minDelta = 0;
557 struct chan_centers centers;
558 #define PD_GAIN_BOUNDARY_DEFAULT 58;
559
560 ath9k_hw_get_channel_centers(ah, chan, &centers);
561
562 for (numPiers = 0; numPiers < availPiers; numPiers++) {
563 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
564 break;
565 }
566
567 match = ath9k_hw_get_lower_upper_index(
568 (u8)FREQ2FBIN(centers.synth_center,
569 IS_CHAN_2GHZ(chan)), bChans, numPiers,
570 &idxL, &idxR);
571
572 if (match) {
573 for (i = 0; i < numXpdGains; i++) {
574 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
575 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
576 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
577 pRawDataSet[idxL].pwrPdg[i],
578 pRawDataSet[idxL].vpdPdg[i],
579 AR5416_EEP4K_PD_GAIN_ICEPTS,
580 vpdTableI[i]);
581 }
582 } else {
583 for (i = 0; i < numXpdGains; i++) {
584 pVpdL = pRawDataSet[idxL].vpdPdg[i];
585 pPwrL = pRawDataSet[idxL].pwrPdg[i];
586 pVpdR = pRawDataSet[idxR].vpdPdg[i];
587 pPwrR = pRawDataSet[idxR].pwrPdg[i];
588
589 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
590
591 maxPwrT4[i] =
592 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
593 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
594
595
596 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
597 pPwrL, pVpdL,
598 AR5416_EEP4K_PD_GAIN_ICEPTS,
599 vpdTableL[i]);
600 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
601 pPwrR, pVpdR,
602 AR5416_EEP4K_PD_GAIN_ICEPTS,
603 vpdTableR[i]);
604
605 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
606 vpdTableI[i][j] =
607 (u8)(ath9k_hw_interpolate((u16)
608 FREQ2FBIN(centers.
609 synth_center,
610 IS_CHAN_2GHZ
611 (chan)),
612 bChans[idxL], bChans[idxR],
613 vpdTableL[i][j], vpdTableR[i][j]));
614 }
615 }
616 }
617
618 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
619
620 k = 0;
621
622 for (i = 0; i < numXpdGains; i++) {
623 if (i == (numXpdGains - 1))
624 pPdGainBoundaries[i] =
625 (u16)(maxPwrT4[i] / 2);
626 else
627 pPdGainBoundaries[i] =
628 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
629
630 pPdGainBoundaries[i] =
631 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
632
633 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
634 minDelta = pPdGainBoundaries[0] - 23;
635 pPdGainBoundaries[0] = 23;
636 } else {
637 minDelta = 0;
638 }
639
640 if (i == 0) {
641 if (AR_SREV_9280_10_OR_LATER(ah))
642 ss = (int16_t)(0 - (minPwrT4[i] / 2));
643 else
644 ss = 0;
645 } else {
646 ss = (int16_t)((pPdGainBoundaries[i - 1] -
647 (minPwrT4[i] / 2)) -
648 tPdGainOverlap + 1 + minDelta);
649 }
650 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
651 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
652
653 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
654 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
655 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
656 ss++;
657 }
658
659 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
660 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
661 (minPwrT4[i] / 2));
662 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
663 tgtIndex : sizeCurrVpdTable;
664
665 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
666 pPDADCValues[k++] = vpdTableI[i][ss++];
667
668 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
669 vpdTableI[i][sizeCurrVpdTable - 2]);
670 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
671
672 if (tgtIndex >= maxIndex) {
673 while ((ss <= tgtIndex) &&
674 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
675 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
676 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
677 255 : tmpVal);
678 ss++;
679 }
680 }
681 }
682
683 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
684 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
685 i++;
686 }
687
688 while (k < AR5416_NUM_PDADC_VALUES) {
689 pPDADCValues[k] = pPDADCValues[k - 1];
690 k++;
691 }
692
693 return;
694 #undef TMP_VAL_VPD_TABLE
695 }
696
697 static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
698 struct ath9k_channel *chan,
699 int16_t *pTxPowerIndexOffset)
700 {
701 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
702 struct cal_data_per_freq_4k *pRawDataset;
703 u8 *pCalBChans = NULL;
704 u16 pdGainOverlap_t2;
705 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
706 u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
707 u16 numPiers, i, j;
708 int16_t tMinCalPower;
709 u16 numXpdGain, xpdMask;
710 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
711 u32 reg32, regOffset, regChainOffset;
712
713 xpdMask = pEepData->modalHeader.xpdGain;
714
715 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
716 AR5416_EEP_MINOR_VER_2) {
717 pdGainOverlap_t2 =
718 pEepData->modalHeader.pdGainOverlap;
719 } else {
720 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
721 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
722 }
723
724 pCalBChans = pEepData->calFreqPier2G;
725 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
726
727 numXpdGain = 0;
728
729 for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
730 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
731 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
732 break;
733 xpdGainValues[numXpdGain] =
734 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
735 numXpdGain++;
736 }
737 }
738
739 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
740 (numXpdGain - 1) & 0x3);
741 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
742 xpdGainValues[0]);
743 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
744 xpdGainValues[1]);
745 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
746
747 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
748 if (AR_SREV_5416_20_OR_LATER(ah) &&
749 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
750 (i != 0)) {
751 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
752 } else
753 regChainOffset = i * 0x1000;
754
755 if (pEepData->baseEepHeader.txMask & (1 << i)) {
756 pRawDataset = pEepData->calPierData2G[i];
757
758 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
759 pRawDataset, pCalBChans,
760 numPiers, pdGainOverlap_t2,
761 &tMinCalPower, gainBoundaries,
762 pdadcValues, numXpdGain);
763
764 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
765 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
766 SM(pdGainOverlap_t2,
767 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
768 | SM(gainBoundaries[0],
769 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
770 | SM(gainBoundaries[1],
771 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
772 | SM(gainBoundaries[2],
773 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
774 | SM(gainBoundaries[3],
775 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
776 }
777
778 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
779 for (j = 0; j < 32; j++) {
780 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
781 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
782 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
783 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
784 REG_WRITE(ah, regOffset, reg32);
785
786 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
787 "PDADC (%d,%4x): %4.4x %8.8x\n",
788 i, regChainOffset, regOffset,
789 reg32);
790 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
791 "PDADC: Chain %d | "
792 "PDADC %3d Value %3d | "
793 "PDADC %3d Value %3d | "
794 "PDADC %3d Value %3d | "
795 "PDADC %3d Value %3d |\n",
796 i, 4 * j, pdadcValues[4 * j],
797 4 * j + 1, pdadcValues[4 * j + 1],
798 4 * j + 2, pdadcValues[4 * j + 2],
799 4 * j + 3,
800 pdadcValues[4 * j + 3]);
801
802 regOffset += 4;
803 }
804 }
805 }
806
807 *pTxPowerIndexOffset = 0;
808
809 return true;
810 }
811
812 static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
813 struct ath9k_channel *chan,
814 int16_t *ratesArray,
815 u16 cfgCtl,
816 u16 AntennaReduction,
817 u16 twiceMaxRegulatoryPower,
818 u16 powerLimit)
819 {
820 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
821 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
822 static const u16 tpScaleReductionTable[5] =
823 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
824
825 int i;
826 int16_t twiceLargestAntenna;
827 struct cal_ctl_data_4k *rep;
828 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
829 0, { 0, 0, 0, 0}
830 };
831 struct cal_target_power_leg targetPowerOfdmExt = {
832 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
833 0, { 0, 0, 0, 0 }
834 };
835 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
836 0, {0, 0, 0, 0}
837 };
838 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
839 u16 ctlModesFor11g[] =
840 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
841 CTL_2GHT40
842 };
843 u16 numCtlModes, *pCtlMode, ctlMode, freq;
844 struct chan_centers centers;
845 int tx_chainmask;
846 u16 twiceMinEdgePower;
847
848 tx_chainmask = ah->txchainmask;
849
850 ath9k_hw_get_channel_centers(ah, chan, &centers);
851
852 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
853
854 twiceLargestAntenna = (int16_t)min(AntennaReduction -
855 twiceLargestAntenna, 0);
856
857 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
858
859 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
860 maxRegAllowedPower -=
861 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
862 }
863
864 scaledPower = min(powerLimit, maxRegAllowedPower);
865 scaledPower = max((u16)0, scaledPower);
866
867 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
868 pCtlMode = ctlModesFor11g;
869
870 ath9k_hw_get_legacy_target_powers(ah, chan,
871 pEepData->calTargetPowerCck,
872 AR5416_NUM_2G_CCK_TARGET_POWERS,
873 &targetPowerCck, 4, false);
874 ath9k_hw_get_legacy_target_powers(ah, chan,
875 pEepData->calTargetPower2G,
876 AR5416_NUM_2G_20_TARGET_POWERS,
877 &targetPowerOfdm, 4, false);
878 ath9k_hw_get_target_powers(ah, chan,
879 pEepData->calTargetPower2GHT20,
880 AR5416_NUM_2G_20_TARGET_POWERS,
881 &targetPowerHt20, 8, false);
882
883 if (IS_CHAN_HT40(chan)) {
884 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
885 ath9k_hw_get_target_powers(ah, chan,
886 pEepData->calTargetPower2GHT40,
887 AR5416_NUM_2G_40_TARGET_POWERS,
888 &targetPowerHt40, 8, true);
889 ath9k_hw_get_legacy_target_powers(ah, chan,
890 pEepData->calTargetPowerCck,
891 AR5416_NUM_2G_CCK_TARGET_POWERS,
892 &targetPowerCckExt, 4, true);
893 ath9k_hw_get_legacy_target_powers(ah, chan,
894 pEepData->calTargetPower2G,
895 AR5416_NUM_2G_20_TARGET_POWERS,
896 &targetPowerOfdmExt, 4, true);
897 }
898
899 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
900 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
901 (pCtlMode[ctlMode] == CTL_2GHT40);
902 if (isHt40CtlMode)
903 freq = centers.synth_center;
904 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
905 freq = centers.ext_center;
906 else
907 freq = centers.ctl_center;
908
909 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
910 ah->eep_ops->get_eeprom_rev(ah) <= 2)
911 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
912
913 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
914 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
915 "EXT_ADDITIVE %d\n",
916 ctlMode, numCtlModes, isHt40CtlMode,
917 (pCtlMode[ctlMode] & EXT_ADDITIVE));
918
919 for (i = 0; (i < AR5416_NUM_CTLS) &&
920 pEepData->ctlIndex[i]; i++) {
921 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
922 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
923 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
924 "chan %d\n",
925 i, cfgCtl, pCtlMode[ctlMode],
926 pEepData->ctlIndex[i], chan->channel);
927
928 if ((((cfgCtl & ~CTL_MODE_M) |
929 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
930 pEepData->ctlIndex[i]) ||
931 (((cfgCtl & ~CTL_MODE_M) |
932 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
933 ((pEepData->ctlIndex[i] & CTL_MODE_M) |
934 SD_NO_CTL))) {
935 rep = &(pEepData->ctlData[i]);
936
937 twiceMinEdgePower =
938 ath9k_hw_get_max_edge_power(freq,
939 rep->ctlEdges[ar5416_get_ntxchains
940 (tx_chainmask) - 1],
941 IS_CHAN_2GHZ(chan),
942 AR5416_EEP4K_NUM_BAND_EDGES);
943
944 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
945 " MATCH-EE_IDX %d: ch %d is2 %d "
946 "2xMinEdge %d chainmask %d chains %d\n",
947 i, freq, IS_CHAN_2GHZ(chan),
948 twiceMinEdgePower, tx_chainmask,
949 ar5416_get_ntxchains
950 (tx_chainmask));
951 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
952 twiceMaxEdgePower =
953 min(twiceMaxEdgePower,
954 twiceMinEdgePower);
955 } else {
956 twiceMaxEdgePower = twiceMinEdgePower;
957 break;
958 }
959 }
960 }
961
962 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
963
964 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
965 " SEL-Min ctlMode %d pCtlMode %d "
966 "2xMaxEdge %d sP %d minCtlPwr %d\n",
967 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
968 scaledPower, minCtlPower);
969
970 switch (pCtlMode[ctlMode]) {
971 case CTL_11B:
972 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
973 i++) {
974 targetPowerCck.tPow2x[i] =
975 min((u16)targetPowerCck.tPow2x[i],
976 minCtlPower);
977 }
978 break;
979 case CTL_11G:
980 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
981 i++) {
982 targetPowerOfdm.tPow2x[i] =
983 min((u16)targetPowerOfdm.tPow2x[i],
984 minCtlPower);
985 }
986 break;
987 case CTL_2GHT20:
988 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
989 i++) {
990 targetPowerHt20.tPow2x[i] =
991 min((u16)targetPowerHt20.tPow2x[i],
992 minCtlPower);
993 }
994 break;
995 case CTL_11B_EXT:
996 targetPowerCckExt.tPow2x[0] = min((u16)
997 targetPowerCckExt.tPow2x[0],
998 minCtlPower);
999 break;
1000 case CTL_11G_EXT:
1001 targetPowerOfdmExt.tPow2x[0] = min((u16)
1002 targetPowerOfdmExt.tPow2x[0],
1003 minCtlPower);
1004 break;
1005 case CTL_2GHT40:
1006 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
1007 i++) {
1008 targetPowerHt40.tPow2x[i] =
1009 min((u16)targetPowerHt40.tPow2x[i],
1010 minCtlPower);
1011 }
1012 break;
1013 default:
1014 break;
1015 }
1016 }
1017
1018 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1019 ratesArray[rate18mb] = ratesArray[rate24mb] =
1020 targetPowerOfdm.tPow2x[0];
1021 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1022 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1023 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1024 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1025
1026 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1027 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1028
1029 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1030 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1031 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1032 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1033
1034 if (IS_CHAN_HT40(chan)) {
1035 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1036 ratesArray[rateHt40_0 + i] =
1037 targetPowerHt40.tPow2x[i];
1038 }
1039 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1040 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1041 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1042 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1043 }
1044 return true;
1045 }
1046
1047 static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1048 struct ath9k_channel *chan,
1049 u16 cfgCtl,
1050 u8 twiceAntennaReduction,
1051 u8 twiceMaxRegulatoryPower,
1052 u8 powerLimit)
1053 {
1054 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1055 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1056 int16_t ratesArray[Ar5416RateSize];
1057 int16_t txPowerIndexOffset = 0;
1058 u8 ht40PowerIncForPdadc = 2;
1059 int i;
1060
1061 memset(ratesArray, 0, sizeof(ratesArray));
1062
1063 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1064 AR5416_EEP_MINOR_VER_2) {
1065 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1066 }
1067
1068 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1069 &ratesArray[0], cfgCtl,
1070 twiceAntennaReduction,
1071 twiceMaxRegulatoryPower,
1072 powerLimit)) {
1073 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1074 "ath9k_hw_set_txpower: unable to set "
1075 "tx power per rate table\n");
1076 return -EIO;
1077 }
1078
1079 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1080 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1081 "ath9k_hw_set_txpower: unable to set power table\n");
1082 return -EIO;
1083 }
1084
1085 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1086 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1087 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1088 ratesArray[i] = AR5416_MAX_RATE_POWER;
1089 }
1090
1091 if (AR_SREV_9280_10_OR_LATER(ah)) {
1092 for (i = 0; i < Ar5416RateSize; i++)
1093 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1094 }
1095
1096 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1097 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1098 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1099 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1100 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1101 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1102 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1103 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1104 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1105 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1106
1107 if (IS_CHAN_2GHZ(chan)) {
1108 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1109 ATH9K_POW_SM(ratesArray[rate2s], 24)
1110 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1111 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1112 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1113 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1114 ATH9K_POW_SM(ratesArray[rate11s], 24)
1115 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1116 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1117 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1118 }
1119
1120 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1121 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1122 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1123 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1124 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1125 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1126 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1127 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1128 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1129 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1130
1131 if (IS_CHAN_HT40(chan)) {
1132 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1133 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1134 ht40PowerIncForPdadc, 24)
1135 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1136 ht40PowerIncForPdadc, 16)
1137 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1138 ht40PowerIncForPdadc, 8)
1139 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1140 ht40PowerIncForPdadc, 0));
1141 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1142 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1143 ht40PowerIncForPdadc, 24)
1144 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1145 ht40PowerIncForPdadc, 16)
1146 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1147 ht40PowerIncForPdadc, 8)
1148 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1149 ht40PowerIncForPdadc, 0));
1150
1151 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1152 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1153 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1154 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1155 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1156 }
1157
1158 i = rate6mb;
1159
1160 if (IS_CHAN_HT40(chan))
1161 i = rateHt40_0;
1162 else if (IS_CHAN_HT20(chan))
1163 i = rateHt20_0;
1164
1165 if (AR_SREV_9280_10_OR_LATER(ah))
1166 ah->regulatory.max_power_level =
1167 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1168 else
1169 ah->regulatory.max_power_level = ratesArray[i];
1170
1171 return 0;
1172 }
1173
1174 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1175 struct ath9k_channel *chan)
1176 {
1177 struct modal_eep_4k_header *pModal;
1178 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1179 u8 biaslevel;
1180
1181 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1182 return;
1183
1184 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1185 return;
1186
1187 pModal = &eep->modalHeader;
1188
1189 if (pModal->xpaBiasLvl != 0xff) {
1190 biaslevel = pModal->xpaBiasLvl;
1191 INI_RA(&ah->iniAddac, 7, 1) =
1192 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
1193 }
1194 }
1195
1196 static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1197 struct ath9k_channel *chan)
1198 {
1199 struct modal_eep_4k_header *pModal;
1200 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1201 int regChainOffset;
1202 u8 txRxAttenLocal;
1203 u8 ob[5], db1[5], db2[5];
1204 u8 ant_div_control1, ant_div_control2;
1205 u32 regVal;
1206
1207
1208 pModal = &eep->modalHeader;
1209
1210 txRxAttenLocal = 23;
1211
1212 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1213 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1214
1215 regChainOffset = 0;
1216 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1217 pModal->antCtrlChain[0]);
1218
1219 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1220 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1221 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1222 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1223 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1224 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1225
1226 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1227 AR5416_EEP_MINOR_VER_3) {
1228 txRxAttenLocal = pModal->txRxAttenCh[0];
1229 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1230 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1231 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1232 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1233 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1234 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1235 pModal->xatten2Margin[0]);
1236 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1237 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1238 }
1239
1240 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1241 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1242 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1243 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1244
1245 if (AR_SREV_9285_11(ah))
1246 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1247
1248 /* Initialize Ant Diversity settings from EEPROM */
1249 if (pModal->version == 3) {
1250 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
1251 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
1252 regVal = REG_READ(ah, 0x99ac);
1253 regVal &= (~(0x7f000000));
1254 regVal |= ((ant_div_control1 & 0x1) << 24);
1255 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
1256 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
1257 regVal |= ((ant_div_control2 & 0x3) << 25);
1258 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
1259 REG_WRITE(ah, 0x99ac, regVal);
1260 regVal = REG_READ(ah, 0x99ac);
1261 regVal = REG_READ(ah, 0xa208);
1262 regVal &= (~(0x1 << 13));
1263 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
1264 REG_WRITE(ah, 0xa208, regVal);
1265 regVal = REG_READ(ah, 0xa208);
1266 }
1267
1268 if (pModal->version >= 2) {
1269 ob[0] = (pModal->ob_01 & 0xf);
1270 ob[1] = (pModal->ob_01 >> 4) & 0xf;
1271 ob[2] = (pModal->ob_234 & 0xf);
1272 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
1273 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
1274
1275 db1[0] = (pModal->db1_01 & 0xf);
1276 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
1277 db1[2] = (pModal->db1_234 & 0xf);
1278 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
1279 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
1280
1281 db2[0] = (pModal->db2_01 & 0xf);
1282 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
1283 db2[2] = (pModal->db2_234 & 0xf);
1284 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
1285 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
1286
1287 } else if (pModal->version == 1) {
1288 ob[0] = (pModal->ob_01 & 0xf);
1289 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
1290 db1[0] = (pModal->db1_01 & 0xf);
1291 db1[1] = db1[2] = db1[3] =
1292 db1[4] = ((pModal->db1_01 >> 4) & 0xf);
1293 db2[0] = (pModal->db2_01 & 0xf);
1294 db2[1] = db2[2] = db2[3] =
1295 db2[4] = ((pModal->db2_01 >> 4) & 0xf);
1296 } else {
1297 int i;
1298 for (i = 0; i < 5; i++) {
1299 ob[i] = pModal->ob_01;
1300 db1[i] = pModal->db1_01;
1301 db2[i] = pModal->db1_01;
1302 }
1303 }
1304
1305 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1306 AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]);
1307 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1308 AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]);
1309 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1310 AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]);
1311 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1312 AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]);
1313 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1314 AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]);
1315
1316 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1317 AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]);
1318 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1319 AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]);
1320 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1321 AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]);
1322 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1323 AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]);
1324 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1325 AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1326
1327 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1328 AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]);
1329 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1330 AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]);
1331 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1332 AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]);
1333 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1334 AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]);
1335 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1336 AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]);
1337
1338
1339 if (AR_SREV_9285_11(ah))
1340 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1341
1342 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1343 pModal->switchSettling);
1344 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1345 pModal->adcDesiredSize);
1346
1347 REG_WRITE(ah, AR_PHY_RF_CTL4,
1348 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1349 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1350 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1351 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1352
1353 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1354 pModal->txEndToRxOn);
1355 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1356 pModal->thresh62);
1357 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1358 pModal->thresh62);
1359
1360 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1361 AR5416_EEP_MINOR_VER_2) {
1362 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1363 pModal->txFrameToDataStart);
1364 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1365 pModal->txFrameToPaOn);
1366 }
1367
1368 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1369 AR5416_EEP_MINOR_VER_3) {
1370 if (IS_CHAN_HT40(chan))
1371 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1372 AR_PHY_SETTLING_SWITCH,
1373 pModal->swSettleHt40);
1374 }
1375
1376 return true;
1377 }
1378
1379 static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1380 struct ath9k_channel *chan)
1381 {
1382 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1383 struct modal_eep_4k_header *pModal = &eep->modalHeader;
1384
1385 return pModal->antCtrlCommon & 0xFFFF;
1386 }
1387
1388 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1389 enum ieee80211_band freq_band)
1390 {
1391 return 1;
1392 }
1393
1394 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1395 {
1396 #define EEP_MAP4K_SPURCHAN \
1397 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1398
1399 u16 spur_val = AR_NO_SPUR;
1400
1401 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1402 "Getting spur idx %d is2Ghz. %d val %x\n",
1403 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1404
1405 switch (ah->config.spurmode) {
1406 case SPUR_DISABLE:
1407 break;
1408 case SPUR_ENABLE_IOCTL:
1409 spur_val = ah->config.spurchans[i][is2GHz];
1410 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1411 "Getting spur val from new loc. %d\n", spur_val);
1412 break;
1413 case SPUR_ENABLE_EEPROM:
1414 spur_val = EEP_MAP4K_SPURCHAN;
1415 break;
1416 }
1417
1418 return spur_val;
1419
1420 #undef EEP_MAP4K_SPURCHAN
1421 }
1422
1423 static struct eeprom_ops eep_4k_ops = {
1424 .check_eeprom = ath9k_hw_4k_check_eeprom,
1425 .get_eeprom = ath9k_hw_4k_get_eeprom,
1426 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
1427 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1428 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
1429 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
1430 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1431 .set_board_values = ath9k_hw_4k_set_board_values,
1432 .set_addac = ath9k_hw_4k_set_addac,
1433 .set_txpower = ath9k_hw_4k_set_txpower,
1434 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1435 };
1436
1437 /************************************************/
1438 /* EEPROM Operations for non-4K (Default) cards */
1439 /************************************************/
1440
1441 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
1442 {
1443 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
1444 }
1445
1446 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1447 {
1448 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
1449 }
1450
1451 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1452 {
1453 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1454 u16 *eep_data = (u16 *)&ah->eeprom.def;
1455 int addr, ar5416_eep_start_loc = 0x100;
1456
1457 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
1458 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
1459 eep_data)) {
1460 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1461 "Unable to read eeprom region\n");
1462 return false;
1463 }
1464 eep_data++;
1465 }
1466 return true;
1467 #undef SIZE_EEPROM_DEF
1468 }
1469
1470 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1471 {
1472 struct ar5416_eeprom_def *eep =
1473 (struct ar5416_eeprom_def *) &ah->eeprom.def;
1474 u16 *eepdata, temp, magic, magic2;
1475 u32 sum = 0, el;
1476 bool need_swap = false;
1477 int i, addr, size;
1478
1479 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
1480 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
1481 return false;
1482 }
1483
1484 if (!ath9k_hw_use_flash(ah)) {
1485 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1486 "Read Magic = 0x%04X\n", magic);
1487
1488 if (magic != AR5416_EEPROM_MAGIC) {
1489 magic2 = swab16(magic);
1490
1491 if (magic2 == AR5416_EEPROM_MAGIC) {
1492 size = sizeof(struct ar5416_eeprom_def);
1493 need_swap = true;
1494 eepdata = (u16 *) (&ah->eeprom);
1495
1496 for (addr = 0; addr < size / sizeof(u16); addr++) {
1497 temp = swab16(*eepdata);
1498 *eepdata = temp;
1499 eepdata++;
1500 }
1501 } else {
1502 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1503 "Invalid EEPROM Magic. "
1504 "Endianness mismatch.\n");
1505 return -EINVAL;
1506 }
1507 }
1508 }
1509
1510 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
1511 need_swap ? "True" : "False");
1512
1513 if (need_swap)
1514 el = swab16(ah->eeprom.def.baseEepHeader.length);
1515 else
1516 el = ah->eeprom.def.baseEepHeader.length;
1517
1518 if (el > sizeof(struct ar5416_eeprom_def))
1519 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
1520 else
1521 el = el / sizeof(u16);
1522
1523 eepdata = (u16 *)(&ah->eeprom);
1524
1525 for (i = 0; i < el; i++)
1526 sum ^= *eepdata++;
1527
1528 if (need_swap) {
1529 u32 integer, j;
1530 u16 word;
1531
1532 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1533 "EEPROM Endianness is not native.. Changing.\n");
1534
1535 word = swab16(eep->baseEepHeader.length);
1536 eep->baseEepHeader.length = word;
1537
1538 word = swab16(eep->baseEepHeader.checksum);
1539 eep->baseEepHeader.checksum = word;
1540
1541 word = swab16(eep->baseEepHeader.version);
1542 eep->baseEepHeader.version = word;
1543
1544 word = swab16(eep->baseEepHeader.regDmn[0]);
1545 eep->baseEepHeader.regDmn[0] = word;
1546
1547 word = swab16(eep->baseEepHeader.regDmn[1]);
1548 eep->baseEepHeader.regDmn[1] = word;
1549
1550 word = swab16(eep->baseEepHeader.rfSilent);
1551 eep->baseEepHeader.rfSilent = word;
1552
1553 word = swab16(eep->baseEepHeader.blueToothOptions);
1554 eep->baseEepHeader.blueToothOptions = word;
1555
1556 word = swab16(eep->baseEepHeader.deviceCap);
1557 eep->baseEepHeader.deviceCap = word;
1558
1559 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
1560 struct modal_eep_header *pModal =
1561 &eep->modalHeader[j];
1562 integer = swab32(pModal->antCtrlCommon);
1563 pModal->antCtrlCommon = integer;
1564
1565 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1566 integer = swab32(pModal->antCtrlChain[i]);
1567 pModal->antCtrlChain[i] = integer;
1568 }
1569
1570 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
1571 word = swab16(pModal->spurChans[i].spurChan);
1572 pModal->spurChans[i].spurChan = word;
1573 }
1574 }
1575 }
1576
1577 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
1578 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
1579 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1580 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1581 sum, ah->eep_ops->get_eeprom_ver(ah));
1582 return -EINVAL;
1583 }
1584
1585 return 0;
1586 }
1587
1588 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1589 enum eeprom_param param)
1590 {
1591 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1592 struct modal_eep_header *pModal = eep->modalHeader;
1593 struct base_eep_header *pBase = &eep->baseEepHeader;
1594
1595 switch (param) {
1596 case EEP_NFTHRESH_5:
1597 return pModal[0].noiseFloorThreshCh[0];
1598 case EEP_NFTHRESH_2:
1599 return pModal[1].noiseFloorThreshCh[0];
1600 case AR_EEPROM_MAC(0):
1601 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1602 case AR_EEPROM_MAC(1):
1603 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1604 case AR_EEPROM_MAC(2):
1605 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1606 case EEP_REG_0:
1607 return pBase->regDmn[0];
1608 case EEP_REG_1:
1609 return pBase->regDmn[1];
1610 case EEP_OP_CAP:
1611 return pBase->deviceCap;
1612 case EEP_OP_MODE:
1613 return pBase->opCapFlags;
1614 case EEP_RF_SILENT:
1615 return pBase->rfSilent;
1616 case EEP_OB_5:
1617 return pModal[0].ob;
1618 case EEP_DB_5:
1619 return pModal[0].db;
1620 case EEP_OB_2:
1621 return pModal[1].ob;
1622 case EEP_DB_2:
1623 return pModal[1].db;
1624 case EEP_MINOR_REV:
1625 return AR5416_VER_MASK;
1626 case EEP_TX_MASK:
1627 return pBase->txMask;
1628 case EEP_RX_MASK:
1629 return pBase->rxMask;
1630 case EEP_RXGAIN_TYPE:
1631 return pBase->rxGainType;
1632 case EEP_TXGAIN_TYPE:
1633 return pBase->txGainType;
1634 case EEP_OL_PWRCTRL:
1635 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1636 return pBase->openLoopPwrCntl ? true : false;
1637 else
1638 return false;
1639 case EEP_RC_CHAIN_MASK:
1640 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1641 return pBase->rcChainMask;
1642 else
1643 return 0;
1644 case EEP_DAC_HPWR_5G:
1645 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
1646 return pBase->dacHiPwrMode_5G;
1647 else
1648 return 0;
1649 case EEP_FRAC_N_5G:
1650 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
1651 return pBase->frac_n_5g;
1652 else
1653 return 0;
1654 default:
1655 return 0;
1656 }
1657 }
1658
1659 /* XXX: Clean me up, make me more legible */
1660 static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1661 struct ath9k_channel *chan)
1662 {
1663 struct modal_eep_header *pModal;
1664 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1665 int i, regChainOffset;
1666 u8 txRxAttenLocal;
1667
1668 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1669
1670 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1671
1672 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1673 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1674
1675 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1676 if (AR_SREV_9280(ah)) {
1677 if (i >= 2)
1678 break;
1679 }
1680
1681 if (AR_SREV_5416_20_OR_LATER(ah) &&
1682 (ah->rxchainmask == 5 || ah->txchainmask == 5)
1683 && (i != 0))
1684 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1685 else
1686 regChainOffset = i * 0x1000;
1687
1688 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1689 pModal->antCtrlChain[i]);
1690
1691 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1692 (REG_READ(ah,
1693 AR_PHY_TIMING_CTRL4(0) +
1694 regChainOffset) &
1695 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1696 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1697 SM(pModal->iqCalICh[i],
1698 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1699 SM(pModal->iqCalQCh[i],
1700 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1701
1702 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
1703 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1704 txRxAttenLocal = pModal->txRxAttenCh[i];
1705 if (AR_SREV_9280_10_OR_LATER(ah)) {
1706 REG_RMW_FIELD(ah,
1707 AR_PHY_GAIN_2GHZ +
1708 regChainOffset,
1709 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1710 pModal->
1711 bswMargin[i]);
1712 REG_RMW_FIELD(ah,
1713 AR_PHY_GAIN_2GHZ +
1714 regChainOffset,
1715 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1716 pModal->
1717 bswAtten[i]);
1718 REG_RMW_FIELD(ah,
1719 AR_PHY_GAIN_2GHZ +
1720 regChainOffset,
1721 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1722 pModal->
1723 xatten2Margin[i]);
1724 REG_RMW_FIELD(ah,
1725 AR_PHY_GAIN_2GHZ +
1726 regChainOffset,
1727 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1728 pModal->
1729 xatten2Db[i]);
1730 } else {
1731 REG_WRITE(ah,
1732 AR_PHY_GAIN_2GHZ +
1733 regChainOffset,
1734 (REG_READ(ah,
1735 AR_PHY_GAIN_2GHZ +
1736 regChainOffset) &
1737 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1738 | SM(pModal->
1739 bswMargin[i],
1740 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1741 REG_WRITE(ah,
1742 AR_PHY_GAIN_2GHZ +
1743 regChainOffset,
1744 (REG_READ(ah,
1745 AR_PHY_GAIN_2GHZ +
1746 regChainOffset) &
1747 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1748 | SM(pModal->bswAtten[i],
1749 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1750 }
1751 }
1752 if (AR_SREV_9280_10_OR_LATER(ah)) {
1753 REG_RMW_FIELD(ah,
1754 AR_PHY_RXGAIN +
1755 regChainOffset,
1756 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1757 txRxAttenLocal);
1758 REG_RMW_FIELD(ah,
1759 AR_PHY_RXGAIN +
1760 regChainOffset,
1761 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1762 pModal->rxTxMarginCh[i]);
1763 } else {
1764 REG_WRITE(ah,
1765 AR_PHY_RXGAIN + regChainOffset,
1766 (REG_READ(ah,
1767 AR_PHY_RXGAIN +
1768 regChainOffset) &
1769 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1770 SM(txRxAttenLocal,
1771 AR_PHY_RXGAIN_TXRX_ATTEN));
1772 REG_WRITE(ah,
1773 AR_PHY_GAIN_2GHZ +
1774 regChainOffset,
1775 (REG_READ(ah,
1776 AR_PHY_GAIN_2GHZ +
1777 regChainOffset) &
1778 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1779 SM(pModal->rxTxMarginCh[i],
1780 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1781 }
1782 }
1783 }
1784
1785 if (AR_SREV_9280_10_OR_LATER(ah)) {
1786 if (IS_CHAN_2GHZ(chan)) {
1787 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1788 AR_AN_RF2G1_CH0_OB,
1789 AR_AN_RF2G1_CH0_OB_S,
1790 pModal->ob);
1791 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1792 AR_AN_RF2G1_CH0_DB,
1793 AR_AN_RF2G1_CH0_DB_S,
1794 pModal->db);
1795 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1796 AR_AN_RF2G1_CH1_OB,
1797 AR_AN_RF2G1_CH1_OB_S,
1798 pModal->ob_ch1);
1799 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1800 AR_AN_RF2G1_CH1_DB,
1801 AR_AN_RF2G1_CH1_DB_S,
1802 pModal->db_ch1);
1803 } else {
1804 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1805 AR_AN_RF5G1_CH0_OB5,
1806 AR_AN_RF5G1_CH0_OB5_S,
1807 pModal->ob);
1808 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1809 AR_AN_RF5G1_CH0_DB5,
1810 AR_AN_RF5G1_CH0_DB5_S,
1811 pModal->db);
1812 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1813 AR_AN_RF5G1_CH1_OB5,
1814 AR_AN_RF5G1_CH1_OB5_S,
1815 pModal->ob_ch1);
1816 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1817 AR_AN_RF5G1_CH1_DB5,
1818 AR_AN_RF5G1_CH1_DB5_S,
1819 pModal->db_ch1);
1820 }
1821 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1822 AR_AN_TOP2_XPABIAS_LVL,
1823 AR_AN_TOP2_XPABIAS_LVL_S,
1824 pModal->xpaBiasLvl);
1825 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1826 AR_AN_TOP2_LOCALBIAS,
1827 AR_AN_TOP2_LOCALBIAS_S,
1828 pModal->local_bias);
1829 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
1830 pModal->force_xpaon);
1831 }
1832
1833 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1834 pModal->switchSettling);
1835 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1836 pModal->adcDesiredSize);
1837
1838 if (!AR_SREV_9280_10_OR_LATER(ah))
1839 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1840 AR_PHY_DESIRED_SZ_PGA,
1841 pModal->pgaDesiredSize);
1842
1843 REG_WRITE(ah, AR_PHY_RF_CTL4,
1844 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1845 | SM(pModal->txEndToXpaOff,
1846 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1847 | SM(pModal->txFrameToXpaOn,
1848 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1849 | SM(pModal->txFrameToXpaOn,
1850 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1851
1852 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1853 pModal->txEndToRxOn);
1854
1855 if (AR_SREV_9280_10_OR_LATER(ah)) {
1856 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1857 pModal->thresh62);
1858 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1859 AR_PHY_EXT_CCA0_THRESH62,
1860 pModal->thresh62);
1861 } else {
1862 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1863 pModal->thresh62);
1864 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1865 AR_PHY_EXT_CCA_THRESH62,
1866 pModal->thresh62);
1867 }
1868
1869 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1870 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1871 AR_PHY_TX_END_DATA_START,
1872 pModal->txFrameToDataStart);
1873 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1874 pModal->txFrameToPaOn);
1875 }
1876
1877 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1878 if (IS_CHAN_HT40(chan))
1879 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1880 AR_PHY_SETTLING_SWITCH,
1881 pModal->swSettleHt40);
1882 }
1883
1884 if (AR_SREV_9280_20_OR_LATER(ah) &&
1885 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1886 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
1887 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
1888 pModal->miscBits);
1889
1890
1891 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
1892 if (IS_CHAN_2GHZ(chan))
1893 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1894 eep->baseEepHeader.dacLpMode);
1895 else if (eep->baseEepHeader.dacHiPwrMode_5G)
1896 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
1897 else
1898 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1899 eep->baseEepHeader.dacLpMode);
1900
1901 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
1902 pModal->miscBits >> 2);
1903
1904 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
1905 AR_PHY_TX_DESIRED_SCALE_CCK,
1906 eep->baseEepHeader.desiredScaleCCK);
1907 }
1908
1909 return true;
1910 }
1911
1912 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
1913 struct ath9k_channel *chan)
1914 {
1915 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1916 struct modal_eep_header *pModal;
1917 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1918 u8 biaslevel;
1919
1920 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1921 return;
1922
1923 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1924 return;
1925
1926 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1927
1928 if (pModal->xpaBiasLvl != 0xff) {
1929 biaslevel = pModal->xpaBiasLvl;
1930 } else {
1931 u16 resetFreqBin, freqBin, freqCount = 0;
1932 struct chan_centers centers;
1933
1934 ath9k_hw_get_channel_centers(ah, chan, &centers);
1935
1936 resetFreqBin = FREQ2FBIN(centers.synth_center,
1937 IS_CHAN_2GHZ(chan));
1938 freqBin = XPA_LVL_FREQ(0) & 0xff;
1939 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
1940
1941 freqCount++;
1942
1943 while (freqCount < 3) {
1944 if (XPA_LVL_FREQ(freqCount) == 0x0)
1945 break;
1946
1947 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
1948 if (resetFreqBin >= freqBin)
1949 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
1950 else
1951 break;
1952 freqCount++;
1953 }
1954 }
1955
1956 if (IS_CHAN_2GHZ(chan)) {
1957 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
1958 7, 1) & (~0x18)) | biaslevel << 3;
1959 } else {
1960 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
1961 6, 1) & (~0xc0)) | biaslevel << 6;
1962 }
1963 #undef XPA_LVL_FREQ
1964 }
1965
1966 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
1967 struct ath9k_channel *chan,
1968 struct cal_data_per_freq *pRawDataSet,
1969 u8 *bChans, u16 availPiers,
1970 u16 tPdGainOverlap, int16_t *pMinCalPower,
1971 u16 *pPdGainBoundaries, u8 *pPDADCValues,
1972 u16 numXpdGains)
1973 {
1974 int i, j, k;
1975 int16_t ss;
1976 u16 idxL = 0, idxR = 0, numPiers;
1977 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
1978 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1979 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
1980 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1981 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
1982 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1983
1984 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
1985 u8 minPwrT4[AR5416_NUM_PD_GAINS];
1986 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
1987 int16_t vpdStep;
1988 int16_t tmpVal;
1989 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
1990 bool match;
1991 int16_t minDelta = 0;
1992 struct chan_centers centers;
1993
1994 ath9k_hw_get_channel_centers(ah, chan, &centers);
1995
1996 for (numPiers = 0; numPiers < availPiers; numPiers++) {
1997 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
1998 break;
1999 }
2000
2001 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
2002 IS_CHAN_2GHZ(chan)),
2003 bChans, numPiers, &idxL, &idxR);
2004
2005 if (match) {
2006 for (i = 0; i < numXpdGains; i++) {
2007 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2008 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2009 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2010 pRawDataSet[idxL].pwrPdg[i],
2011 pRawDataSet[idxL].vpdPdg[i],
2012 AR5416_PD_GAIN_ICEPTS,
2013 vpdTableI[i]);
2014 }
2015 } else {
2016 for (i = 0; i < numXpdGains; i++) {
2017 pVpdL = pRawDataSet[idxL].vpdPdg[i];
2018 pPwrL = pRawDataSet[idxL].pwrPdg[i];
2019 pVpdR = pRawDataSet[idxR].vpdPdg[i];
2020 pPwrR = pRawDataSet[idxR].pwrPdg[i];
2021
2022 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
2023
2024 maxPwrT4[i] =
2025 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
2026 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
2027
2028
2029 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2030 pPwrL, pVpdL,
2031 AR5416_PD_GAIN_ICEPTS,
2032 vpdTableL[i]);
2033 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2034 pPwrR, pVpdR,
2035 AR5416_PD_GAIN_ICEPTS,
2036 vpdTableR[i]);
2037
2038 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
2039 vpdTableI[i][j] =
2040 (u8)(ath9k_hw_interpolate((u16)
2041 FREQ2FBIN(centers.
2042 synth_center,
2043 IS_CHAN_2GHZ
2044 (chan)),
2045 bChans[idxL], bChans[idxR],
2046 vpdTableL[i][j], vpdTableR[i][j]));
2047 }
2048 }
2049 }
2050
2051 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
2052
2053 k = 0;
2054
2055 for (i = 0; i < numXpdGains; i++) {
2056 if (i == (numXpdGains - 1))
2057 pPdGainBoundaries[i] =
2058 (u16)(maxPwrT4[i] / 2);
2059 else
2060 pPdGainBoundaries[i] =
2061 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
2062
2063 pPdGainBoundaries[i] =
2064 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2065
2066 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
2067 minDelta = pPdGainBoundaries[0] - 23;
2068 pPdGainBoundaries[0] = 23;
2069 } else {
2070 minDelta = 0;
2071 }
2072
2073 if (i == 0) {
2074 if (AR_SREV_9280_10_OR_LATER(ah))
2075 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2076 else
2077 ss = 0;
2078 } else {
2079 ss = (int16_t)((pPdGainBoundaries[i - 1] -
2080 (minPwrT4[i] / 2)) -
2081 tPdGainOverlap + 1 + minDelta);
2082 }
2083 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2084 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2085
2086 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2087 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2088 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
2089 ss++;
2090 }
2091
2092 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
2093 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
2094 (minPwrT4[i] / 2));
2095 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
2096 tgtIndex : sizeCurrVpdTable;
2097
2098 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2099 pPDADCValues[k++] = vpdTableI[i][ss++];
2100 }
2101
2102 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
2103 vpdTableI[i][sizeCurrVpdTable - 2]);
2104 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2105
2106 if (tgtIndex > maxIndex) {
2107 while ((ss <= tgtIndex) &&
2108 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2109 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2110 (ss - maxIndex + 1) * vpdStep));
2111 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
2112 255 : tmpVal);
2113 ss++;
2114 }
2115 }
2116 }
2117
2118 while (i < AR5416_PD_GAINS_IN_MASK) {
2119 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
2120 i++;
2121 }
2122
2123 while (k < AR5416_NUM_PDADC_VALUES) {
2124 pPDADCValues[k] = pPDADCValues[k - 1];
2125 k++;
2126 }
2127
2128 return;
2129 }
2130
2131 static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2132 struct ath9k_channel *chan,
2133 int16_t *pTxPowerIndexOffset)
2134 {
2135 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2136 #define SM_PDGAIN_B(x, y) \
2137 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2138
2139 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2140 struct cal_data_per_freq *pRawDataset;
2141 u8 *pCalBChans = NULL;
2142 u16 pdGainOverlap_t2;
2143 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
2144 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
2145 u16 numPiers, i, j;
2146 int16_t tMinCalPower;
2147 u16 numXpdGain, xpdMask;
2148 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
2149 u32 reg32, regOffset, regChainOffset;
2150 int16_t modalIdx;
2151
2152 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
2153 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
2154
2155 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2156 AR5416_EEP_MINOR_VER_2) {
2157 pdGainOverlap_t2 =
2158 pEepData->modalHeader[modalIdx].pdGainOverlap;
2159 } else {
2160 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
2161 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
2162 }
2163
2164 if (IS_CHAN_2GHZ(chan)) {
2165 pCalBChans = pEepData->calFreqPier2G;
2166 numPiers = AR5416_NUM_2G_CAL_PIERS;
2167 } else {
2168 pCalBChans = pEepData->calFreqPier5G;
2169 numPiers = AR5416_NUM_5G_CAL_PIERS;
2170 }
2171
2172 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
2173 pRawDataset = pEepData->calPierData2G[0];
2174 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
2175 pRawDataset)->vpdPdg[0][0];
2176 }
2177
2178 numXpdGain = 0;
2179
2180 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
2181 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
2182 if (numXpdGain >= AR5416_NUM_PD_GAINS)
2183 break;
2184 xpdGainValues[numXpdGain] =
2185 (u16)(AR5416_PD_GAINS_IN_MASK - i);
2186 numXpdGain++;
2187 }
2188 }
2189
2190 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
2191 (numXpdGain - 1) & 0x3);
2192 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
2193 xpdGainValues[0]);
2194 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
2195 xpdGainValues[1]);
2196 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
2197 xpdGainValues[2]);
2198
2199 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2200 if (AR_SREV_5416_20_OR_LATER(ah) &&
2201 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2202 (i != 0)) {
2203 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2204 } else
2205 regChainOffset = i * 0x1000;
2206
2207 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2208 if (IS_CHAN_2GHZ(chan))
2209 pRawDataset = pEepData->calPierData2G[i];
2210 else
2211 pRawDataset = pEepData->calPierData5G[i];
2212
2213
2214 if (OLC_FOR_AR9280_20_LATER) {
2215 u8 pcdacIdx;
2216 u8 txPower;
2217
2218 ath9k_get_txgain_index(ah, chan,
2219 (struct calDataPerFreqOpLoop *)pRawDataset,
2220 pCalBChans, numPiers, &txPower, &pcdacIdx);
2221 ath9k_olc_get_pdadcs(ah, pcdacIdx,
2222 txPower/2, pdadcValues);
2223 } else {
2224 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
2225 chan, pRawDataset,
2226 pCalBChans, numPiers,
2227 pdGainOverlap_t2,
2228 &tMinCalPower,
2229 gainBoundaries,
2230 pdadcValues,
2231 numXpdGain);
2232 }
2233
2234 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
2235 if (OLC_FOR_AR9280_20_LATER) {
2236 REG_WRITE(ah,
2237 AR_PHY_TPCRG5 + regChainOffset,
2238 SM(0x6,
2239 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2240 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2241 SM_PD_GAIN(3) | SM_PD_GAIN(4));
2242 } else {
2243 REG_WRITE(ah,
2244 AR_PHY_TPCRG5 + regChainOffset,
2245 SM(pdGainOverlap_t2,
2246 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
2247 SM_PDGAIN_B(0, 1) |
2248 SM_PDGAIN_B(1, 2) |
2249 SM_PDGAIN_B(2, 3) |
2250 SM_PDGAIN_B(3, 4));
2251 }
2252 }
2253
2254 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2255 for (j = 0; j < 32; j++) {
2256 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
2257 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
2258 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
2259 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
2260 REG_WRITE(ah, regOffset, reg32);
2261
2262 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2263 "PDADC (%d,%4x): %4.4x %8.8x\n",
2264 i, regChainOffset, regOffset,
2265 reg32);
2266 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2267 "PDADC: Chain %d | PDADC %3d "
2268 "Value %3d | PDADC %3d Value %3d | "
2269 "PDADC %3d Value %3d | PDADC %3d "
2270 "Value %3d |\n",
2271 i, 4 * j, pdadcValues[4 * j],
2272 4 * j + 1, pdadcValues[4 * j + 1],
2273 4 * j + 2, pdadcValues[4 * j + 2],
2274 4 * j + 3,
2275 pdadcValues[4 * j + 3]);
2276
2277 regOffset += 4;
2278 }
2279 }
2280 }
2281
2282 *pTxPowerIndexOffset = 0;
2283
2284 return true;
2285 #undef SM_PD_GAIN
2286 #undef SM_PDGAIN_B
2287 }
2288
2289 static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2290 struct ath9k_channel *chan,
2291 int16_t *ratesArray,
2292 u16 cfgCtl,
2293 u16 AntennaReduction,
2294 u16 twiceMaxRegulatoryPower,
2295 u16 powerLimit)
2296 {
2297 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
2298 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
2299
2300 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2301 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2302 static const u16 tpScaleReductionTable[5] =
2303 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
2304
2305 int i;
2306 int16_t twiceLargestAntenna;
2307 struct cal_ctl_data *rep;
2308 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
2309 0, { 0, 0, 0, 0}
2310 };
2311 struct cal_target_power_leg targetPowerOfdmExt = {
2312 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
2313 0, { 0, 0, 0, 0 }
2314 };
2315 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
2316 0, {0, 0, 0, 0}
2317 };
2318 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
2319 u16 ctlModesFor11a[] =
2320 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
2321 u16 ctlModesFor11g[] =
2322 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
2323 CTL_2GHT40
2324 };
2325 u16 numCtlModes, *pCtlMode, ctlMode, freq;
2326 struct chan_centers centers;
2327 int tx_chainmask;
2328 u16 twiceMinEdgePower;
2329
2330 tx_chainmask = ah->txchainmask;
2331
2332 ath9k_hw_get_channel_centers(ah, chan, &centers);
2333
2334 twiceLargestAntenna = max(
2335 pEepData->modalHeader
2336 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
2337 pEepData->modalHeader
2338 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
2339
2340 twiceLargestAntenna = max((u8)twiceLargestAntenna,
2341 pEepData->modalHeader
2342 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
2343
2344 twiceLargestAntenna = (int16_t)min(AntennaReduction -
2345 twiceLargestAntenna, 0);
2346
2347 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
2348
2349 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
2350 maxRegAllowedPower -=
2351 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
2352 }
2353
2354 scaledPower = min(powerLimit, maxRegAllowedPower);
2355
2356 switch (ar5416_get_ntxchains(tx_chainmask)) {
2357 case 1:
2358 break;
2359 case 2:
2360 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
2361 break;
2362 case 3:
2363 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
2364 break;
2365 }
2366
2367 scaledPower = max((u16)0, scaledPower);
2368
2369 if (IS_CHAN_2GHZ(chan)) {
2370 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
2371 SUB_NUM_CTL_MODES_AT_2G_40;
2372 pCtlMode = ctlModesFor11g;
2373
2374 ath9k_hw_get_legacy_target_powers(ah, chan,
2375 pEepData->calTargetPowerCck,
2376 AR5416_NUM_2G_CCK_TARGET_POWERS,
2377 &targetPowerCck, 4, false);
2378 ath9k_hw_get_legacy_target_powers(ah, chan,
2379 pEepData->calTargetPower2G,
2380 AR5416_NUM_2G_20_TARGET_POWERS,
2381 &targetPowerOfdm, 4, false);
2382 ath9k_hw_get_target_powers(ah, chan,
2383 pEepData->calTargetPower2GHT20,
2384 AR5416_NUM_2G_20_TARGET_POWERS,
2385 &targetPowerHt20, 8, false);
2386
2387 if (IS_CHAN_HT40(chan)) {
2388 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
2389 ath9k_hw_get_target_powers(ah, chan,
2390 pEepData->calTargetPower2GHT40,
2391 AR5416_NUM_2G_40_TARGET_POWERS,
2392 &targetPowerHt40, 8, true);
2393 ath9k_hw_get_legacy_target_powers(ah, chan,
2394 pEepData->calTargetPowerCck,
2395 AR5416_NUM_2G_CCK_TARGET_POWERS,
2396 &targetPowerCckExt, 4, true);
2397 ath9k_hw_get_legacy_target_powers(ah, chan,
2398 pEepData->calTargetPower2G,
2399 AR5416_NUM_2G_20_TARGET_POWERS,
2400 &targetPowerOfdmExt, 4, true);
2401 }
2402 } else {
2403 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
2404 SUB_NUM_CTL_MODES_AT_5G_40;
2405 pCtlMode = ctlModesFor11a;
2406
2407 ath9k_hw_get_legacy_target_powers(ah, chan,
2408 pEepData->calTargetPower5G,
2409 AR5416_NUM_5G_20_TARGET_POWERS,
2410 &targetPowerOfdm, 4, false);
2411 ath9k_hw_get_target_powers(ah, chan,
2412 pEepData->calTargetPower5GHT20,
2413 AR5416_NUM_5G_20_TARGET_POWERS,
2414 &targetPowerHt20, 8, false);
2415
2416 if (IS_CHAN_HT40(chan)) {
2417 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
2418 ath9k_hw_get_target_powers(ah, chan,
2419 pEepData->calTargetPower5GHT40,
2420 AR5416_NUM_5G_40_TARGET_POWERS,
2421 &targetPowerHt40, 8, true);
2422 ath9k_hw_get_legacy_target_powers(ah, chan,
2423 pEepData->calTargetPower5G,
2424 AR5416_NUM_5G_20_TARGET_POWERS,
2425 &targetPowerOfdmExt, 4, true);
2426 }
2427 }
2428
2429 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
2430 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
2431 (pCtlMode[ctlMode] == CTL_2GHT40);
2432 if (isHt40CtlMode)
2433 freq = centers.synth_center;
2434 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
2435 freq = centers.ext_center;
2436 else
2437 freq = centers.ctl_center;
2438
2439 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
2440 ah->eep_ops->get_eeprom_rev(ah) <= 2)
2441 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2442
2443 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2444 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2445 "EXT_ADDITIVE %d\n",
2446 ctlMode, numCtlModes, isHt40CtlMode,
2447 (pCtlMode[ctlMode] & EXT_ADDITIVE));
2448
2449 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2450 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2451 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2452 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2453 "chan %d\n",
2454 i, cfgCtl, pCtlMode[ctlMode],
2455 pEepData->ctlIndex[i], chan->channel);
2456
2457 if ((((cfgCtl & ~CTL_MODE_M) |
2458 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2459 pEepData->ctlIndex[i]) ||
2460 (((cfgCtl & ~CTL_MODE_M) |
2461 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2462 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
2463 rep = &(pEepData->ctlData[i]);
2464
2465 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
2466 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2467 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2468
2469 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2470 " MATCH-EE_IDX %d: ch %d is2 %d "
2471 "2xMinEdge %d chainmask %d chains %d\n",
2472 i, freq, IS_CHAN_2GHZ(chan),
2473 twiceMinEdgePower, tx_chainmask,
2474 ar5416_get_ntxchains
2475 (tx_chainmask));
2476 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
2477 twiceMaxEdgePower = min(twiceMaxEdgePower,
2478 twiceMinEdgePower);
2479 } else {
2480 twiceMaxEdgePower = twiceMinEdgePower;
2481 break;
2482 }
2483 }
2484 }
2485
2486 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2487
2488 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2489 " SEL-Min ctlMode %d pCtlMode %d "
2490 "2xMaxEdge %d sP %d minCtlPwr %d\n",
2491 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
2492 scaledPower, minCtlPower);
2493
2494 switch (pCtlMode[ctlMode]) {
2495 case CTL_11B:
2496 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
2497 targetPowerCck.tPow2x[i] =
2498 min((u16)targetPowerCck.tPow2x[i],
2499 minCtlPower);
2500 }
2501 break;
2502 case CTL_11A:
2503 case CTL_11G:
2504 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
2505 targetPowerOfdm.tPow2x[i] =
2506 min((u16)targetPowerOfdm.tPow2x[i],
2507 minCtlPower);
2508 }
2509 break;
2510 case CTL_5GHT20:
2511 case CTL_2GHT20:
2512 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
2513 targetPowerHt20.tPow2x[i] =
2514 min((u16)targetPowerHt20.tPow2x[i],
2515 minCtlPower);
2516 }
2517 break;
2518 case CTL_11B_EXT:
2519 targetPowerCckExt.tPow2x[0] = min((u16)
2520 targetPowerCckExt.tPow2x[0],
2521 minCtlPower);
2522 break;
2523 case CTL_11A_EXT:
2524 case CTL_11G_EXT:
2525 targetPowerOfdmExt.tPow2x[0] = min((u16)
2526 targetPowerOfdmExt.tPow2x[0],
2527 minCtlPower);
2528 break;
2529 case CTL_5GHT40:
2530 case CTL_2GHT40:
2531 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2532 targetPowerHt40.tPow2x[i] =
2533 min((u16)targetPowerHt40.tPow2x[i],
2534 minCtlPower);
2535 }
2536 break;
2537 default:
2538 break;
2539 }
2540 }
2541
2542 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
2543 ratesArray[rate18mb] = ratesArray[rate24mb] =
2544 targetPowerOfdm.tPow2x[0];
2545 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
2546 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
2547 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
2548 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
2549
2550 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
2551 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
2552
2553 if (IS_CHAN_2GHZ(chan)) {
2554 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
2555 ratesArray[rate2s] = ratesArray[rate2l] =
2556 targetPowerCck.tPow2x[1];
2557 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
2558 targetPowerCck.tPow2x[2];
2559 ;
2560 ratesArray[rate11s] = ratesArray[rate11l] =
2561 targetPowerCck.tPow2x[3];
2562 ;
2563 }
2564 if (IS_CHAN_HT40(chan)) {
2565 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2566 ratesArray[rateHt40_0 + i] =
2567 targetPowerHt40.tPow2x[i];
2568 }
2569 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2570 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2571 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2572 if (IS_CHAN_2GHZ(chan)) {
2573 ratesArray[rateExtCck] =
2574 targetPowerCckExt.tPow2x[0];
2575 }
2576 }
2577 return true;
2578 }
2579
2580 static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2581 struct ath9k_channel *chan,
2582 u16 cfgCtl,
2583 u8 twiceAntennaReduction,
2584 u8 twiceMaxRegulatoryPower,
2585 u8 powerLimit)
2586 {
2587 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2588 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2589 struct modal_eep_header *pModal =
2590 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
2591 int16_t ratesArray[Ar5416RateSize];
2592 int16_t txPowerIndexOffset = 0;
2593 u8 ht40PowerIncForPdadc = 2;
2594 int i, cck_ofdm_delta = 0;
2595
2596 memset(ratesArray, 0, sizeof(ratesArray));
2597
2598 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2599 AR5416_EEP_MINOR_VER_2) {
2600 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2601 }
2602
2603 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
2604 &ratesArray[0], cfgCtl,
2605 twiceAntennaReduction,
2606 twiceMaxRegulatoryPower,
2607 powerLimit)) {
2608 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2609 "ath9k_hw_set_txpower: unable to set "
2610 "tx power per rate table\n");
2611 return -EIO;
2612 }
2613
2614 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
2615 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2616 "ath9k_hw_set_txpower: unable to set power table\n");
2617 return -EIO;
2618 }
2619
2620 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2621 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2622 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2623 ratesArray[i] = AR5416_MAX_RATE_POWER;
2624 }
2625
2626 if (AR_SREV_9280_10_OR_LATER(ah)) {
2627 for (i = 0; i < Ar5416RateSize; i++)
2628 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
2629 }
2630
2631 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
2632 ATH9K_POW_SM(ratesArray[rate18mb], 24)
2633 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
2634 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
2635 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
2636 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
2637 ATH9K_POW_SM(ratesArray[rate54mb], 24)
2638 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
2639 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
2640 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
2641
2642 if (IS_CHAN_2GHZ(chan)) {
2643 if (OLC_FOR_AR9280_20_LATER) {
2644 cck_ofdm_delta = 2;
2645 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2646 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
2647 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
2648 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2649 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
2650 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2651 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
2652 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
2653 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
2654 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
2655 } else {
2656 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2657 ATH9K_POW_SM(ratesArray[rate2s], 24)
2658 | ATH9K_POW_SM(ratesArray[rate2l], 16)
2659 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2660 | ATH9K_POW_SM(ratesArray[rate1l], 0));
2661 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2662 ATH9K_POW_SM(ratesArray[rate11s], 24)
2663 | ATH9K_POW_SM(ratesArray[rate11l], 16)
2664 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
2665 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
2666 }
2667 }
2668
2669 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
2670 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
2671 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
2672 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
2673 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
2674 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
2675 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
2676 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
2677 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
2678 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
2679
2680 if (IS_CHAN_HT40(chan)) {
2681 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
2682 ATH9K_POW_SM(ratesArray[rateHt40_3] +
2683 ht40PowerIncForPdadc, 24)
2684 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
2685 ht40PowerIncForPdadc, 16)
2686 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
2687 ht40PowerIncForPdadc, 8)
2688 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
2689 ht40PowerIncForPdadc, 0));
2690 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
2691 ATH9K_POW_SM(ratesArray[rateHt40_7] +
2692 ht40PowerIncForPdadc, 24)
2693 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
2694 ht40PowerIncForPdadc, 16)
2695 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
2696 ht40PowerIncForPdadc, 8)
2697 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
2698 ht40PowerIncForPdadc, 0));
2699 if (OLC_FOR_AR9280_20_LATER) {
2700 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2701 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2702 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
2703 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2704 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
2705 } else {
2706 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2707 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2708 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
2709 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2710 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
2711 }
2712 }
2713
2714 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2715 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
2716 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
2717
2718 i = rate6mb;
2719
2720 if (IS_CHAN_HT40(chan))
2721 i = rateHt40_0;
2722 else if (IS_CHAN_HT20(chan))
2723 i = rateHt20_0;
2724
2725 if (AR_SREV_9280_10_OR_LATER(ah))
2726 ah->regulatory.max_power_level =
2727 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
2728 else
2729 ah->regulatory.max_power_level = ratesArray[i];
2730
2731 switch(ar5416_get_ntxchains(ah->txchainmask)) {
2732 case 1:
2733 break;
2734 case 2:
2735 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
2736 break;
2737 case 3:
2738 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
2739 break;
2740 default:
2741 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2742 "Invalid chainmask configuration\n");
2743 break;
2744 }
2745
2746 return 0;
2747 }
2748
2749 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2750 enum ieee80211_band freq_band)
2751 {
2752 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2753 struct modal_eep_header *pModal =
2754 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2755 struct base_eep_header *pBase = &eep->baseEepHeader;
2756 u8 num_ant_config;
2757
2758 num_ant_config = 1;
2759
2760 if (pBase->version >= 0x0E0D)
2761 if (pModal->useAnt1)
2762 num_ant_config += 1;
2763
2764 return num_ant_config;
2765 }
2766
2767 static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
2768 struct ath9k_channel *chan)
2769 {
2770 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2771 struct modal_eep_header *pModal =
2772 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2773
2774 return pModal->antCtrlCommon & 0xFFFF;
2775 }
2776
2777 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
2778 {
2779 #define EEP_DEF_SPURCHAN \
2780 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2781
2782 u16 spur_val = AR_NO_SPUR;
2783
2784 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2785 "Getting spur idx %d is2Ghz. %d val %x\n",
2786 i, is2GHz, ah->config.spurchans[i][is2GHz]);
2787
2788 switch (ah->config.spurmode) {
2789 case SPUR_DISABLE:
2790 break;
2791 case SPUR_ENABLE_IOCTL:
2792 spur_val = ah->config.spurchans[i][is2GHz];
2793 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2794 "Getting spur val from new loc. %d\n", spur_val);
2795 break;
2796 case SPUR_ENABLE_EEPROM:
2797 spur_val = EEP_DEF_SPURCHAN;
2798 break;
2799 }
2800
2801 return spur_val;
2802
2803 #undef EEP_DEF_SPURCHAN
2804 }
2805
2806 static struct eeprom_ops eep_def_ops = {
2807 .check_eeprom = ath9k_hw_def_check_eeprom,
2808 .get_eeprom = ath9k_hw_def_get_eeprom,
2809 .fill_eeprom = ath9k_hw_def_fill_eeprom,
2810 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
2811 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
2812 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
2813 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
2814 .set_board_values = ath9k_hw_def_set_board_values,
2815 .set_addac = ath9k_hw_def_set_addac,
2816 .set_txpower = ath9k_hw_def_set_txpower,
2817 .get_spur_channel = ath9k_hw_def_get_spur_channel
2818 };
2819
2820 int ath9k_hw_eeprom_attach(struct ath_hw *ah)
2821 {
2822 int status;
2823
2824 if (AR_SREV_9285(ah)) {
2825 ah->eep_map = EEP_MAP_4KBITS;
2826 ah->eep_ops = &eep_4k_ops;
2827 } else {
2828 ah->eep_map = EEP_MAP_DEFAULT;
2829 ah->eep_ops = &eep_def_ops;
2830 }
2831
2832 if (!ah->eep_ops->fill_eeprom(ah))
2833 return -EIO;
2834
2835 status = ah->eep_ops->check_eeprom(ah);
2836
2837 return status;
2838 }
kernel-based virtual machine