1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
41 * mac80211 queues, ACs, hardware queues, FIFOs.
43 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
45 * Mac80211 uses the following numbers, which we get as from it
46 * by way of skb_get_queue_mapping(skb):
54 * Regular (not A-MPDU) frames are put into hardware queues corresponding
55 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
56 * own queue per aggregation session (RA/TID combination), such queues are
57 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
58 * order to map frames to the right queue, we also need an AC->hw queue
59 * mapping. This is implemented here.
61 * Due to the way hw queues are set up (by the hw specific modules like
62 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
66 static const u8 tid_to_ac
[] = {
67 /* this matches the mac80211 numbers */
68 2, 3, 3, 2, 1, 1, 0, 0
71 static const u8 ac_to_fifo
[] = {
78 static inline int get_fifo_from_ac(u8 ac
)
80 return ac_to_fifo
[ac
];
83 static inline int get_queue_from_ac(u16 ac
)
88 static inline int get_fifo_from_tid(u16 tid
)
90 if (likely(tid
< ARRAY_SIZE(tid_to_ac
)))
91 return get_fifo_from_ac(tid_to_ac
[tid
]);
93 /* no support for TIDs 8-15 yet */
97 static inline int iwl_alloc_dma_ptr(struct iwl_priv
*priv
,
98 struct iwl_dma_ptr
*ptr
, size_t size
)
100 ptr
->addr
= dma_alloc_coherent(&priv
->pci_dev
->dev
, size
, &ptr
->dma
,
108 static inline void iwl_free_dma_ptr(struct iwl_priv
*priv
,
109 struct iwl_dma_ptr
*ptr
)
111 if (unlikely(!ptr
->addr
))
114 dma_free_coherent(&priv
->pci_dev
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
115 memset(ptr
, 0, sizeof(*ptr
));
119 * iwl_txq_update_write_ptr - Send new write index to hardware
121 void iwl_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
124 int txq_id
= txq
->q
.id
;
126 if (txq
->need_update
== 0)
129 /* if we're trying to save power */
130 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
131 /* wake up nic if it's powered down ...
132 * uCode will wake up, and interrupt us again, so next
133 * time we'll skip this part. */
134 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
136 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
137 IWL_DEBUG_INFO(priv
, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
139 iwl_set_bit(priv
, CSR_GP_CNTRL
,
140 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
144 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
145 txq
->q
.write_ptr
| (txq_id
<< 8));
147 /* else not in power-save mode, uCode will never sleep when we're
148 * trying to tx (during RFKILL, we're not trying to tx). */
150 iwl_write32(priv
, HBUS_TARG_WRPTR
,
151 txq
->q
.write_ptr
| (txq_id
<< 8));
153 txq
->need_update
= 0;
155 EXPORT_SYMBOL(iwl_txq_update_write_ptr
);
158 void iwl_free_tfds_in_queue(struct iwl_priv
*priv
,
159 int sta_id
, int tid
, int freed
)
161 if (priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
>= freed
)
162 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
164 IWL_DEBUG_TX(priv
, "free more than tfds_in_queue (%u:%d)\n",
165 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
,
167 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
= 0;
170 EXPORT_SYMBOL(iwl_free_tfds_in_queue
);
173 * iwl_tx_queue_free - Deallocate DMA queue.
174 * @txq: Transmit queue to deallocate.
176 * Empty queue by removing and destroying all BD's.
178 * 0-fill, but do not free "txq" descriptor structure.
180 void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
182 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
183 struct iwl_queue
*q
= &txq
->q
;
184 struct device
*dev
= &priv
->pci_dev
->dev
;
190 /* first, empty all BD's */
191 for (; q
->write_ptr
!= q
->read_ptr
;
192 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
))
193 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
195 /* De-alloc array of command/tx buffers */
196 for (i
= 0; i
< TFD_TX_CMD_SLOTS
; i
++)
199 /* De-alloc circular buffer of TFDs */
201 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
*
202 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
204 /* De-alloc array of per-TFD driver data */
208 /* deallocate arrays */
214 /* 0-fill queue descriptor structure */
215 memset(txq
, 0, sizeof(*txq
));
217 EXPORT_SYMBOL(iwl_tx_queue_free
);
220 * iwl_cmd_queue_free - Deallocate DMA queue.
221 * @txq: Transmit queue to deallocate.
223 * Empty queue by removing and destroying all BD's.
225 * 0-fill, but do not free "txq" descriptor structure.
227 void iwl_cmd_queue_free(struct iwl_priv
*priv
)
229 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
230 struct iwl_queue
*q
= &txq
->q
;
231 struct device
*dev
= &priv
->pci_dev
->dev
;
237 /* De-alloc array of command/tx buffers */
238 for (i
= 0; i
<= TFD_CMD_SLOTS
; i
++)
241 /* De-alloc circular buffer of TFDs */
243 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
* txq
->q
.n_bd
,
244 txq
->tfds
, txq
->q
.dma_addr
);
246 /* deallocate arrays */
252 /* 0-fill queue descriptor structure */
253 memset(txq
, 0, sizeof(*txq
));
255 EXPORT_SYMBOL(iwl_cmd_queue_free
);
257 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
260 * Theory of operation
262 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
263 * of buffer descriptors, each of which points to one or more data buffers for
264 * the device to read from or fill. Driver and device exchange status of each
265 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
266 * entries in each circular buffer, to protect against confusing empty and full
269 * The device reads or writes the data in the queues via the device's several
270 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
272 * For Tx queue, there are low mark and high mark limits. If, after queuing
273 * the packet for Tx, free space become < low mark, Tx queue stopped. When
274 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
277 * See more detailed info in iwl-4965-hw.h.
278 ***************************************************/
280 int iwl_queue_space(const struct iwl_queue
*q
)
282 int s
= q
->read_ptr
- q
->write_ptr
;
284 if (q
->read_ptr
> q
->write_ptr
)
289 /* keep some reserve to not confuse empty and full situations */
295 EXPORT_SYMBOL(iwl_queue_space
);
299 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
301 static int iwl_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
302 int count
, int slots_num
, u32 id
)
305 q
->n_window
= slots_num
;
308 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
309 * and iwl_queue_dec_wrap are broken. */
310 BUG_ON(!is_power_of_2(count
));
312 /* slots_num must be power-of-two size, otherwise
313 * get_cmd_index is broken. */
314 BUG_ON(!is_power_of_2(slots_num
));
316 q
->low_mark
= q
->n_window
/ 4;
320 q
->high_mark
= q
->n_window
/ 8;
321 if (q
->high_mark
< 2)
324 q
->write_ptr
= q
->read_ptr
= 0;
330 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
332 static int iwl_tx_queue_alloc(struct iwl_priv
*priv
,
333 struct iwl_tx_queue
*txq
, u32 id
)
335 struct device
*dev
= &priv
->pci_dev
->dev
;
336 size_t tfd_sz
= priv
->hw_params
.tfd_size
* TFD_QUEUE_SIZE_MAX
;
338 /* Driver private data, only for Tx (not command) queues,
339 * not shared with device. */
340 if (id
!= IWL_CMD_QUEUE_NUM
) {
341 txq
->txb
= kmalloc(sizeof(txq
->txb
[0]) *
342 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
344 IWL_ERR(priv
, "kmalloc for auxiliary BD "
345 "structures failed\n");
352 /* Circular buffer of transmit frame descriptors (TFDs),
353 * shared with device */
354 txq
->tfds
= dma_alloc_coherent(dev
, tfd_sz
, &txq
->q
.dma_addr
,
357 IWL_ERR(priv
, "pci_alloc_consistent(%zd) failed\n", tfd_sz
);
372 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
374 int iwl_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
375 int slots_num
, u32 txq_id
)
379 int actual_slots
= slots_num
;
382 * Alloc buffer array for commands (Tx or other types of commands).
383 * For the command queue (#4), allocate command space + one big
384 * command for scan, since scan command is very huge; the system will
385 * not have two scans at the same time, so only one is needed.
386 * For normal Tx queues (all other queues), no super-size command
389 if (txq_id
== IWL_CMD_QUEUE_NUM
)
392 txq
->meta
= kzalloc(sizeof(struct iwl_cmd_meta
) * actual_slots
,
394 txq
->cmd
= kzalloc(sizeof(struct iwl_device_cmd
*) * actual_slots
,
397 if (!txq
->meta
|| !txq
->cmd
)
398 goto out_free_arrays
;
400 len
= sizeof(struct iwl_device_cmd
);
401 for (i
= 0; i
< actual_slots
; i
++) {
402 /* only happens for cmd queue */
404 len
= IWL_MAX_CMD_SIZE
;
406 txq
->cmd
[i
] = kmalloc(len
, GFP_KERNEL
);
411 /* Alloc driver data array and TFD circular buffer */
412 ret
= iwl_tx_queue_alloc(priv
, txq
, txq_id
);
416 txq
->need_update
= 0;
419 * Aggregation TX queues will get their ID when aggregation begins;
420 * they overwrite the setting done here. The command FIFO doesn't
421 * need an swq_id so don't set one to catch errors, all others can
422 * be set up to the identity mapping.
424 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
425 txq
->swq_id
= txq_id
;
427 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
428 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
429 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
431 /* Initialize queue's high/low-water marks, and head/tail indexes */
432 iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
434 /* Tell device where to find queue */
435 priv
->cfg
->ops
->lib
->txq_init(priv
, txq
);
439 for (i
= 0; i
< actual_slots
; i
++)
447 EXPORT_SYMBOL(iwl_tx_queue_init
);
450 * iwl_hw_txq_ctx_free - Free TXQ Context
452 * Destroy all TX DMA queues and structures
454 void iwl_hw_txq_ctx_free(struct iwl_priv
*priv
)
460 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
;
462 if (txq_id
== IWL_CMD_QUEUE_NUM
)
463 iwl_cmd_queue_free(priv
);
465 iwl_tx_queue_free(priv
, txq_id
);
467 iwl_free_dma_ptr(priv
, &priv
->kw
);
469 iwl_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
471 /* free tx queue structure */
472 iwl_free_txq_mem(priv
);
474 EXPORT_SYMBOL(iwl_hw_txq_ctx_free
);
477 * iwl_txq_ctx_reset - Reset TX queue context
478 * Destroys all DMA structures and initialize them again
483 int iwl_txq_ctx_reset(struct iwl_priv
*priv
)
486 int txq_id
, slots_num
;
489 /* Free all tx/cmd queues and keep-warm buffer */
490 iwl_hw_txq_ctx_free(priv
);
492 ret
= iwl_alloc_dma_ptr(priv
, &priv
->scd_bc_tbls
,
493 priv
->hw_params
.scd_bc_tbls_size
);
495 IWL_ERR(priv
, "Scheduler BC Table allocation failed\n");
498 /* Alloc keep-warm buffer */
499 ret
= iwl_alloc_dma_ptr(priv
, &priv
->kw
, IWL_KW_SIZE
);
501 IWL_ERR(priv
, "Keep Warm allocation failed\n");
505 /* allocate tx queue structure */
506 ret
= iwl_alloc_txq_mem(priv
);
510 spin_lock_irqsave(&priv
->lock
, flags
);
512 /* Turn off all Tx DMA fifos */
513 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
515 /* Tell NIC where to find the "keep warm" buffer */
516 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
518 spin_unlock_irqrestore(&priv
->lock
, flags
);
520 /* Alloc and init all Tx queues, including the command queue (#4) */
521 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
522 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
523 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
524 ret
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
527 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
535 iwl_hw_txq_ctx_free(priv
);
536 iwl_free_dma_ptr(priv
, &priv
->kw
);
538 iwl_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
544 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
546 void iwl_txq_ctx_stop(struct iwl_priv
*priv
)
551 /* Turn off all Tx DMA fifos */
552 spin_lock_irqsave(&priv
->lock
, flags
);
554 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
556 /* Stop each Tx DMA channel, and wait for it to be idle */
557 for (ch
= 0; ch
< priv
->hw_params
.dma_chnl_num
; ch
++) {
558 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
559 iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
560 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
563 spin_unlock_irqrestore(&priv
->lock
, flags
);
565 /* Deallocate memory for all Tx queues */
566 iwl_hw_txq_ctx_free(priv
);
568 EXPORT_SYMBOL(iwl_txq_ctx_stop
);
571 * handle build REPLY_TX command notification.
573 static void iwl_tx_cmd_build_basic(struct iwl_priv
*priv
,
574 struct iwl_tx_cmd
*tx_cmd
,
575 struct ieee80211_tx_info
*info
,
576 struct ieee80211_hdr
*hdr
,
579 __le16 fc
= hdr
->frame_control
;
580 __le32 tx_flags
= tx_cmd
->tx_flags
;
582 tx_cmd
->stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
583 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
)) {
584 tx_flags
|= TX_CMD_FLG_ACK_MSK
;
585 if (ieee80211_is_mgmt(fc
))
586 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
587 if (ieee80211_is_probe_resp(fc
) &&
588 !(le16_to_cpu(hdr
->seq_ctrl
) & 0xf))
589 tx_flags
|= TX_CMD_FLG_TSF_MSK
;
591 tx_flags
&= (~TX_CMD_FLG_ACK_MSK
);
592 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
595 if (ieee80211_is_back_req(fc
))
596 tx_flags
|= TX_CMD_FLG_ACK_MSK
| TX_CMD_FLG_IMM_BA_RSP_MASK
;
599 tx_cmd
->sta_id
= std_id
;
600 if (ieee80211_has_morefrags(fc
))
601 tx_flags
|= TX_CMD_FLG_MORE_FRAG_MSK
;
603 if (ieee80211_is_data_qos(fc
)) {
604 u8
*qc
= ieee80211_get_qos_ctl(hdr
);
605 tx_cmd
->tid_tspec
= qc
[0] & 0xf;
606 tx_flags
&= ~TX_CMD_FLG_SEQ_CTL_MSK
;
608 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
611 priv
->cfg
->ops
->utils
->rts_tx_cmd_flag(info
, &tx_flags
);
613 if ((tx_flags
& TX_CMD_FLG_RTS_MSK
) || (tx_flags
& TX_CMD_FLG_CTS_MSK
))
614 tx_flags
|= TX_CMD_FLG_FULL_TXOP_PROT_MSK
;
616 tx_flags
&= ~(TX_CMD_FLG_ANT_SEL_MSK
);
617 if (ieee80211_is_mgmt(fc
)) {
618 if (ieee80211_is_assoc_req(fc
) || ieee80211_is_reassoc_req(fc
))
619 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(3);
621 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(2);
623 tx_cmd
->timeout
.pm_frame_timeout
= 0;
626 tx_cmd
->driver_txop
= 0;
627 tx_cmd
->tx_flags
= tx_flags
;
628 tx_cmd
->next_frame_len
= 0;
631 #define RTS_DFAULT_RETRY_LIMIT 60
633 static void iwl_tx_cmd_build_rate(struct iwl_priv
*priv
,
634 struct iwl_tx_cmd
*tx_cmd
,
635 struct ieee80211_tx_info
*info
,
644 /* Set retry limit on DATA packets and Probe Responses*/
645 if (ieee80211_is_probe_resp(fc
))
646 data_retry_limit
= 3;
648 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
649 tx_cmd
->data_retry_limit
= data_retry_limit
;
651 /* Set retry limit on RTS packets */
652 rts_retry_limit
= RTS_DFAULT_RETRY_LIMIT
;
653 if (data_retry_limit
< rts_retry_limit
)
654 rts_retry_limit
= data_retry_limit
;
655 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
657 /* DATA packets will use the uCode station table for rate/antenna
659 if (ieee80211_is_data(fc
)) {
660 tx_cmd
->initial_rate_index
= 0;
661 tx_cmd
->tx_flags
|= TX_CMD_FLG_STA_RATE_MSK
;
666 * If the current TX rate stored in mac80211 has the MCS bit set, it's
667 * not really a TX rate. Thus, we use the lowest supported rate for
668 * this band. Also use the lowest supported rate if the stored rate
671 rate_idx
= info
->control
.rates
[0].idx
;
672 if (info
->control
.rates
[0].flags
& IEEE80211_TX_RC_MCS
||
673 (rate_idx
< 0) || (rate_idx
> IWL_RATE_COUNT_LEGACY
))
674 rate_idx
= rate_lowest_index(&priv
->bands
[info
->band
],
676 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
677 if (info
->band
== IEEE80211_BAND_5GHZ
)
678 rate_idx
+= IWL_FIRST_OFDM_RATE
;
679 /* Get PLCP rate for tx_cmd->rate_n_flags */
680 rate_plcp
= iwl_rates
[rate_idx
].plcp
;
681 /* Zero out flags for this packet */
684 /* Set CCK flag as needed */
685 if ((rate_idx
>= IWL_FIRST_CCK_RATE
) && (rate_idx
<= IWL_LAST_CCK_RATE
))
686 rate_flags
|= RATE_MCS_CCK_MSK
;
688 /* Set up RTS and CTS flags for certain packets */
689 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
690 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
691 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
692 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
693 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
694 if (tx_cmd
->tx_flags
& TX_CMD_FLG_RTS_MSK
) {
695 tx_cmd
->tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
696 tx_cmd
->tx_flags
|= TX_CMD_FLG_CTS_MSK
;
703 /* Set up antennas */
704 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
);
705 rate_flags
|= iwl_ant_idx_to_flags(priv
->mgmt_tx_ant
);
707 /* Set the rate in the TX cmd */
708 tx_cmd
->rate_n_flags
= iwl_hw_set_rate_n_flags(rate_plcp
, rate_flags
);
711 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv
*priv
,
712 struct ieee80211_tx_info
*info
,
713 struct iwl_tx_cmd
*tx_cmd
,
714 struct sk_buff
*skb_frag
,
717 struct ieee80211_key_conf
*keyconf
= info
->control
.hw_key
;
719 switch (keyconf
->alg
) {
721 tx_cmd
->sec_ctl
= TX_CMD_SEC_CCM
;
722 memcpy(tx_cmd
->key
, keyconf
->key
, keyconf
->keylen
);
723 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
724 tx_cmd
->tx_flags
|= TX_CMD_FLG_AGG_CCMP_MSK
;
725 IWL_DEBUG_TX(priv
, "tx_cmd with AES hwcrypto\n");
729 tx_cmd
->sec_ctl
= TX_CMD_SEC_TKIP
;
730 ieee80211_get_tkip_key(keyconf
, skb_frag
,
731 IEEE80211_TKIP_P2_KEY
, tx_cmd
->key
);
732 IWL_DEBUG_TX(priv
, "tx_cmd with tkip hwcrypto\n");
736 tx_cmd
->sec_ctl
|= (TX_CMD_SEC_WEP
|
737 (keyconf
->keyidx
& TX_CMD_SEC_MSK
) << TX_CMD_SEC_SHIFT
);
739 if (keyconf
->keylen
== WEP_KEY_LEN_128
)
740 tx_cmd
->sec_ctl
|= TX_CMD_SEC_KEY128
;
742 memcpy(&tx_cmd
->key
[3], keyconf
->key
, keyconf
->keylen
);
744 IWL_DEBUG_TX(priv
, "Configuring packet for WEP encryption "
745 "with key %d\n", keyconf
->keyidx
);
749 IWL_ERR(priv
, "Unknown encode alg %d\n", keyconf
->alg
);
755 * start REPLY_TX command process
757 int iwl_tx_skb(struct iwl_priv
*priv
, struct sk_buff
*skb
)
759 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
760 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
761 struct ieee80211_sta
*sta
= info
->control
.sta
;
762 struct iwl_station_priv
*sta_priv
= NULL
;
763 struct iwl_tx_queue
*txq
;
765 struct iwl_device_cmd
*out_cmd
;
766 struct iwl_cmd_meta
*out_meta
;
767 struct iwl_tx_cmd
*tx_cmd
;
769 dma_addr_t phys_addr
;
770 dma_addr_t txcmd_phys
;
771 dma_addr_t scratch_phys
;
772 u16 len
, len_org
, firstlen
, secondlen
;
777 u8 wait_write_ptr
= 0;
782 spin_lock_irqsave(&priv
->lock
, flags
);
783 if (iwl_is_rfkill(priv
)) {
784 IWL_DEBUG_DROP(priv
, "Dropping - RF KILL\n");
788 fc
= hdr
->frame_control
;
790 #ifdef CONFIG_IWLWIFI_DEBUG
791 if (ieee80211_is_auth(fc
))
792 IWL_DEBUG_TX(priv
, "Sending AUTH frame\n");
793 else if (ieee80211_is_assoc_req(fc
))
794 IWL_DEBUG_TX(priv
, "Sending ASSOC frame\n");
795 else if (ieee80211_is_reassoc_req(fc
))
796 IWL_DEBUG_TX(priv
, "Sending REASSOC frame\n");
799 hdr_len
= ieee80211_hdrlen(fc
);
801 /* Find (or create) index into station table for destination station */
802 if (info
->flags
& IEEE80211_TX_CTL_INJECTED
)
803 sta_id
= priv
->hw_params
.bcast_sta_id
;
805 sta_id
= iwl_get_sta_id(priv
, hdr
);
806 if (sta_id
== IWL_INVALID_STATION
) {
807 IWL_DEBUG_DROP(priv
, "Dropping - INVALID STATION: %pM\n",
812 IWL_DEBUG_TX(priv
, "station Id %d\n", sta_id
);
815 sta_priv
= (void *)sta
->drv_priv
;
817 if (sta_priv
&& sta_id
!= priv
->hw_params
.bcast_sta_id
&&
819 WARN_ON(!(info
->flags
& IEEE80211_TX_CTL_PSPOLL_RESPONSE
));
821 * This sends an asynchronous command to the device,
822 * but we can rely on it being processed before the
823 * next frame is processed -- and the next frame to
824 * this station is the one that will consume this
826 * For now set the counter to just 1 since we do not
829 iwl_sta_modify_sleep_tx_count(priv
, sta_id
, 1);
832 txq_id
= get_queue_from_ac(skb_get_queue_mapping(skb
));
833 if (ieee80211_is_data_qos(fc
)) {
834 qc
= ieee80211_get_qos_ctl(hdr
);
835 tid
= qc
[0] & IEEE80211_QOS_CTL_TID_MASK
;
836 if (unlikely(tid
>= MAX_TID_COUNT
))
838 seq_number
= priv
->stations
[sta_id
].tid
[tid
].seq_number
;
839 seq_number
&= IEEE80211_SCTL_SEQ
;
840 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
841 cpu_to_le16(IEEE80211_SCTL_FRAG
);
842 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
844 /* aggregation is on for this <sta,tid> */
845 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
&&
846 priv
->stations
[sta_id
].tid
[tid
].agg
.state
== IWL_AGG_ON
) {
847 txq_id
= priv
->stations
[sta_id
].tid
[tid
].agg
.txq_id
;
851 txq
= &priv
->txq
[txq_id
];
852 swq_id
= txq
->swq_id
;
855 if (unlikely(iwl_queue_space(q
) < q
->high_mark
))
858 if (ieee80211_is_data_qos(fc
))
859 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
++;
861 /* Set up driver data for this TFD */
862 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
863 txq
->txb
[q
->write_ptr
].skb
[0] = skb
;
865 /* Set up first empty entry in queue's array of Tx/cmd buffers */
866 out_cmd
= txq
->cmd
[q
->write_ptr
];
867 out_meta
= &txq
->meta
[q
->write_ptr
];
868 tx_cmd
= &out_cmd
->cmd
.tx
;
869 memset(&out_cmd
->hdr
, 0, sizeof(out_cmd
->hdr
));
870 memset(tx_cmd
, 0, sizeof(struct iwl_tx_cmd
));
873 * Set up the Tx-command (not MAC!) header.
874 * Store the chosen Tx queue and TFD index within the sequence field;
875 * after Tx, uCode's Tx response will return this value so driver can
876 * locate the frame within the tx queue and do post-tx processing.
878 out_cmd
->hdr
.cmd
= REPLY_TX
;
879 out_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
880 INDEX_TO_SEQ(q
->write_ptr
)));
882 /* Copy MAC header from skb into command buffer */
883 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
886 /* Total # bytes to be transmitted */
888 tx_cmd
->len
= cpu_to_le16(len
);
890 if (info
->control
.hw_key
)
891 iwl_tx_cmd_build_hwcrypto(priv
, info
, tx_cmd
, skb
, sta_id
);
893 /* TODO need this for burst mode later on */
894 iwl_tx_cmd_build_basic(priv
, tx_cmd
, info
, hdr
, sta_id
);
895 iwl_dbg_log_tx_data_frame(priv
, len
, hdr
);
897 iwl_tx_cmd_build_rate(priv
, tx_cmd
, info
, fc
);
899 iwl_update_stats(priv
, true, fc
, len
);
901 * Use the first empty entry in this queue's command buffer array
902 * to contain the Tx command and MAC header concatenated together
903 * (payload data will be in another buffer).
904 * Size of this varies, due to varying MAC header length.
905 * If end is not dword aligned, we'll have 2 extra bytes at the end
906 * of the MAC header (device reads on dword boundaries).
907 * We'll tell device about this padding later.
909 len
= sizeof(struct iwl_tx_cmd
) +
910 sizeof(struct iwl_cmd_header
) + hdr_len
;
913 firstlen
= len
= (len
+ 3) & ~3;
920 /* Tell NIC about any 2-byte padding after MAC header */
922 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
924 /* Physical address of this Tx command's header (not MAC header!),
925 * within command buffer array. */
926 txcmd_phys
= pci_map_single(priv
->pci_dev
,
928 PCI_DMA_BIDIRECTIONAL
);
929 pci_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
930 pci_unmap_len_set(out_meta
, len
, len
);
931 /* Add buffer containing Tx command and MAC(!) header to TFD's
933 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
934 txcmd_phys
, len
, 1, 0);
936 if (!ieee80211_has_morefrags(hdr
->frame_control
)) {
937 txq
->need_update
= 1;
939 priv
->stations
[sta_id
].tid
[tid
].seq_number
= seq_number
;
942 txq
->need_update
= 0;
945 /* Set up TFD's 2nd entry to point directly to remainder of skb,
946 * if any (802.11 null frames have no payload). */
947 secondlen
= len
= skb
->len
- hdr_len
;
949 phys_addr
= pci_map_single(priv
->pci_dev
, skb
->data
+ hdr_len
,
950 len
, PCI_DMA_TODEVICE
);
951 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
956 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
957 offsetof(struct iwl_tx_cmd
, scratch
);
959 len
= sizeof(struct iwl_tx_cmd
) +
960 sizeof(struct iwl_cmd_header
) + hdr_len
;
961 /* take back ownership of DMA buffer to enable update */
962 pci_dma_sync_single_for_cpu(priv
->pci_dev
, txcmd_phys
,
963 len
, PCI_DMA_BIDIRECTIONAL
);
964 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
965 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
967 IWL_DEBUG_TX(priv
, "sequence nr = 0X%x \n",
968 le16_to_cpu(out_cmd
->hdr
.sequence
));
969 IWL_DEBUG_TX(priv
, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd
->tx_flags
));
970 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
971 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
973 /* Set up entry for this TFD in Tx byte-count array */
974 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
975 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
,
976 le16_to_cpu(tx_cmd
->len
));
978 pci_dma_sync_single_for_device(priv
->pci_dev
, txcmd_phys
,
979 len
, PCI_DMA_BIDIRECTIONAL
);
981 trace_iwlwifi_dev_tx(priv
,
982 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
983 sizeof(struct iwl_tfd
),
984 &out_cmd
->hdr
, firstlen
,
985 skb
->data
+ hdr_len
, secondlen
);
987 /* Tell device the write index *just past* this latest filled TFD */
988 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
989 iwl_txq_update_write_ptr(priv
, txq
);
990 spin_unlock_irqrestore(&priv
->lock
, flags
);
993 * At this point the frame is "transmitted" successfully
994 * and we will get a TX status notification eventually,
995 * regardless of the value of ret. "ret" only indicates
996 * whether or not we should update the write pointer.
999 /* avoid atomic ops if it isn't an associated client */
1000 if (sta_priv
&& sta_priv
->client
)
1001 atomic_inc(&sta_priv
->pending_frames
);
1003 if ((iwl_queue_space(q
) < q
->high_mark
) && priv
->mac80211_registered
) {
1004 if (wait_write_ptr
) {
1005 spin_lock_irqsave(&priv
->lock
, flags
);
1006 txq
->need_update
= 1;
1007 iwl_txq_update_write_ptr(priv
, txq
);
1008 spin_unlock_irqrestore(&priv
->lock
, flags
);
1010 iwl_stop_queue(priv
, txq
->swq_id
);
1017 spin_unlock_irqrestore(&priv
->lock
, flags
);
1020 EXPORT_SYMBOL(iwl_tx_skb
);
1022 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1025 * iwl_enqueue_hcmd - enqueue a uCode command
1026 * @priv: device private data point
1027 * @cmd: a point to the ucode command structure
1029 * The function returns < 0 values to indicate the operation is
1030 * failed. On success, it turns the index (> 0) of command in the
1033 int iwl_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
1035 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
1036 struct iwl_queue
*q
= &txq
->q
;
1037 struct iwl_device_cmd
*out_cmd
;
1038 struct iwl_cmd_meta
*out_meta
;
1039 dma_addr_t phys_addr
;
1040 unsigned long flags
;
1045 cmd
->len
= priv
->cfg
->ops
->utils
->get_hcmd_size(cmd
->id
, cmd
->len
);
1046 fix_size
= (u16
)(cmd
->len
+ sizeof(out_cmd
->hdr
));
1048 /* If any of the command structures end up being larger than
1049 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1050 * we will need to increase the size of the TFD entries
1051 * Also, check to see if command buffer should not exceed the size
1052 * of device_cmd and max_cmd_size. */
1053 BUG_ON((fix_size
> TFD_MAX_PAYLOAD_SIZE
) &&
1054 !(cmd
->flags
& CMD_SIZE_HUGE
));
1055 BUG_ON(fix_size
> IWL_MAX_CMD_SIZE
);
1057 if (iwl_is_rfkill(priv
) || iwl_is_ctkill(priv
)) {
1058 IWL_WARN(priv
, "Not sending command - %s KILL\n",
1059 iwl_is_rfkill(priv
) ? "RF" : "CT");
1063 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1064 IWL_ERR(priv
, "No space in command queue\n");
1065 if (iwl_within_ct_kill_margin(priv
))
1066 iwl_tt_enter_ct_kill(priv
);
1068 IWL_ERR(priv
, "Restarting adapter due to queue full\n");
1069 queue_work(priv
->workqueue
, &priv
->restart
);
1074 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
1076 idx
= get_cmd_index(q
, q
->write_ptr
, cmd
->flags
& CMD_SIZE_HUGE
);
1077 out_cmd
= txq
->cmd
[idx
];
1078 out_meta
= &txq
->meta
[idx
];
1080 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1081 out_meta
->flags
= cmd
->flags
;
1082 if (cmd
->flags
& CMD_WANT_SKB
)
1083 out_meta
->source
= cmd
;
1084 if (cmd
->flags
& CMD_ASYNC
)
1085 out_meta
->callback
= cmd
->callback
;
1087 out_cmd
->hdr
.cmd
= cmd
->id
;
1088 memcpy(&out_cmd
->cmd
.payload
, cmd
->data
, cmd
->len
);
1090 /* At this point, the out_cmd now has all of the incoming cmd
1093 out_cmd
->hdr
.flags
= 0;
1094 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM
) |
1095 INDEX_TO_SEQ(q
->write_ptr
));
1096 if (cmd
->flags
& CMD_SIZE_HUGE
)
1097 out_cmd
->hdr
.sequence
|= SEQ_HUGE_FRAME
;
1098 len
= sizeof(struct iwl_device_cmd
);
1099 if (idx
== TFD_CMD_SLOTS
)
1100 len
= IWL_MAX_CMD_SIZE
;
1102 #ifdef CONFIG_IWLWIFI_DEBUG
1103 switch (out_cmd
->hdr
.cmd
) {
1104 case REPLY_TX_LINK_QUALITY_CMD
:
1105 case SENSITIVITY_CMD
:
1106 IWL_DEBUG_HC_DUMP(priv
, "Sending command %s (#%x), seq: 0x%04X, "
1107 "%d bytes at %d[%d]:%d\n",
1108 get_cmd_string(out_cmd
->hdr
.cmd
),
1110 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
1111 q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
1114 IWL_DEBUG_HC(priv
, "Sending command %s (#%x), seq: 0x%04X, "
1115 "%d bytes at %d[%d]:%d\n",
1116 get_cmd_string(out_cmd
->hdr
.cmd
),
1118 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
1119 q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
1122 txq
->need_update
= 1;
1124 if (priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl
)
1125 /* Set up entry in queue's byte count circular buffer */
1126 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, 0);
1128 phys_addr
= pci_map_single(priv
->pci_dev
, &out_cmd
->hdr
,
1129 fix_size
, PCI_DMA_BIDIRECTIONAL
);
1130 pci_unmap_addr_set(out_meta
, mapping
, phys_addr
);
1131 pci_unmap_len_set(out_meta
, len
, fix_size
);
1133 trace_iwlwifi_dev_hcmd(priv
, &out_cmd
->hdr
, fix_size
, cmd
->flags
);
1135 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
1136 phys_addr
, fix_size
, 1,
1139 /* Increment and update queue's write index */
1140 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1141 iwl_txq_update_write_ptr(priv
, txq
);
1143 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
1147 static void iwl_tx_status(struct iwl_priv
*priv
, struct sk_buff
*skb
)
1149 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1150 struct ieee80211_sta
*sta
;
1151 struct iwl_station_priv
*sta_priv
;
1153 sta
= ieee80211_find_sta(priv
->vif
, hdr
->addr1
);
1155 sta_priv
= (void *)sta
->drv_priv
;
1156 /* avoid atomic ops if this isn't a client */
1157 if (sta_priv
->client
&&
1158 atomic_dec_return(&sta_priv
->pending_frames
) == 0)
1159 ieee80211_sta_block_awake(priv
->hw
, sta
, false);
1162 ieee80211_tx_status_irqsafe(priv
->hw
, skb
);
1165 int iwl_tx_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1167 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1168 struct iwl_queue
*q
= &txq
->q
;
1169 struct iwl_tx_info
*tx_info
;
1171 struct ieee80211_hdr
*hdr
;
1173 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1174 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1175 "is out of range [0-%d] %d %d.\n", txq_id
,
1176 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1180 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
);
1181 q
->read_ptr
!= index
;
1182 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1184 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
1185 iwl_tx_status(priv
, tx_info
->skb
[0]);
1187 hdr
= (struct ieee80211_hdr
*)tx_info
->skb
[0]->data
;
1188 if (hdr
&& ieee80211_is_data_qos(hdr
->frame_control
))
1190 tx_info
->skb
[0] = NULL
;
1192 if (priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl
)
1193 priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl(priv
, txq
);
1195 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
1199 EXPORT_SYMBOL(iwl_tx_queue_reclaim
);
1203 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1205 * When FW advances 'R' index, all entries between old and new 'R' index
1206 * need to be reclaimed. As result, some free space forms. If there is
1207 * enough free space (> low mark), wake the stack that feeds us.
1209 static void iwl_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
,
1210 int idx
, int cmd_idx
)
1212 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1213 struct iwl_queue
*q
= &txq
->q
;
1216 if ((idx
>= q
->n_bd
) || (iwl_queue_used(q
, idx
) == 0)) {
1217 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1218 "is out of range [0-%d] %d %d.\n", txq_id
,
1219 idx
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1223 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
1224 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1227 IWL_ERR(priv
, "HCMD skipped: index (%d) %d %d\n", idx
,
1228 q
->write_ptr
, q
->read_ptr
);
1229 queue_work(priv
->workqueue
, &priv
->restart
);
1236 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1237 * @rxb: Rx buffer to reclaim
1239 * If an Rx buffer has an async callback associated with it the callback
1240 * will be executed. The attached skb (if present) will only be freed
1241 * if the callback returns 1
1243 void iwl_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
1245 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1246 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1247 int txq_id
= SEQ_TO_QUEUE(sequence
);
1248 int index
= SEQ_TO_INDEX(sequence
);
1250 bool huge
= !!(pkt
->hdr
.sequence
& SEQ_HUGE_FRAME
);
1251 struct iwl_device_cmd
*cmd
;
1252 struct iwl_cmd_meta
*meta
;
1254 /* If a Tx command is being handled and it isn't in the actual
1255 * command queue then there a command routing bug has been introduced
1256 * in the queue management code. */
1257 if (WARN(txq_id
!= IWL_CMD_QUEUE_NUM
,
1258 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1260 priv
->txq
[IWL_CMD_QUEUE_NUM
].q
.read_ptr
,
1261 priv
->txq
[IWL_CMD_QUEUE_NUM
].q
.write_ptr
)) {
1262 iwl_print_hex_error(priv
, pkt
, 32);
1266 cmd_index
= get_cmd_index(&priv
->txq
[IWL_CMD_QUEUE_NUM
].q
, index
, huge
);
1267 cmd
= priv
->txq
[IWL_CMD_QUEUE_NUM
].cmd
[cmd_index
];
1268 meta
= &priv
->txq
[IWL_CMD_QUEUE_NUM
].meta
[cmd_index
];
1270 pci_unmap_single(priv
->pci_dev
,
1271 pci_unmap_addr(meta
, mapping
),
1272 pci_unmap_len(meta
, len
),
1273 PCI_DMA_BIDIRECTIONAL
);
1275 /* Input error checking is done when commands are added to queue. */
1276 if (meta
->flags
& CMD_WANT_SKB
) {
1277 meta
->source
->reply_page
= (unsigned long)rxb_addr(rxb
);
1279 } else if (meta
->callback
)
1280 meta
->callback(priv
, cmd
, pkt
);
1282 iwl_hcmd_queue_reclaim(priv
, txq_id
, index
, cmd_index
);
1284 if (!(meta
->flags
& CMD_ASYNC
)) {
1285 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
1286 IWL_DEBUG_INFO(priv
, "Clearing HCMD_ACTIVE for command %s \n",
1287 get_cmd_string(cmd
->hdr
.cmd
));
1288 wake_up_interruptible(&priv
->wait_command_queue
);
1291 EXPORT_SYMBOL(iwl_tx_cmd_complete
);
1294 * Find first available (lowest unused) Tx Queue, mark it "active".
1295 * Called only when finding queue for aggregation.
1296 * Should never return anything < 7, because they should already
1297 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
1299 static int iwl_txq_ctx_activate_free(struct iwl_priv
*priv
)
1303 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
1304 if (!test_and_set_bit(txq_id
, &priv
->txq_ctx_active_msk
))
1309 int iwl_tx_agg_start(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
, u16
*ssn
)
1315 unsigned long flags
;
1316 struct iwl_tid_data
*tid_data
;
1318 tx_fifo
= get_fifo_from_tid(tid
);
1319 if (unlikely(tx_fifo
< 0))
1322 IWL_WARN(priv
, "%s on ra = %pM tid = %d\n",
1325 sta_id
= iwl_find_station(priv
, ra
);
1326 if (sta_id
== IWL_INVALID_STATION
) {
1327 IWL_ERR(priv
, "Start AGG on invalid station\n");
1330 if (unlikely(tid
>= MAX_TID_COUNT
))
1333 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_OFF
) {
1334 IWL_ERR(priv
, "Start AGG when state is not IWL_AGG_OFF !\n");
1338 txq_id
= iwl_txq_ctx_activate_free(priv
);
1340 IWL_ERR(priv
, "No free aggregation queue available\n");
1344 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1345 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1346 *ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1347 tid_data
->agg
.txq_id
= txq_id
;
1348 priv
->txq
[txq_id
].swq_id
= iwl_virtual_agg_queue_num(tx_fifo
, txq_id
);
1349 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1351 ret
= priv
->cfg
->ops
->lib
->txq_agg_enable(priv
, txq_id
, tx_fifo
,
1356 if (tid_data
->tfds_in_queue
== 0) {
1357 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1358 tid_data
->agg
.state
= IWL_AGG_ON
;
1359 ieee80211_start_tx_ba_cb_irqsafe(priv
->vif
, ra
, tid
);
1361 IWL_DEBUG_HT(priv
, "HW queue is NOT empty: %d packets in HW queue\n",
1362 tid_data
->tfds_in_queue
);
1363 tid_data
->agg
.state
= IWL_EMPTYING_HW_QUEUE_ADDBA
;
1367 EXPORT_SYMBOL(iwl_tx_agg_start
);
1369 int iwl_tx_agg_stop(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
)
1371 int tx_fifo_id
, txq_id
, sta_id
, ssn
= -1;
1372 struct iwl_tid_data
*tid_data
;
1373 int write_ptr
, read_ptr
;
1374 unsigned long flags
;
1377 IWL_ERR(priv
, "ra = NULL\n");
1381 tx_fifo_id
= get_fifo_from_tid(tid
);
1382 if (unlikely(tx_fifo_id
< 0))
1385 sta_id
= iwl_find_station(priv
, ra
);
1387 if (sta_id
== IWL_INVALID_STATION
) {
1388 IWL_ERR(priv
, "Invalid station for AGG tid %d\n", tid
);
1392 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
==
1393 IWL_EMPTYING_HW_QUEUE_ADDBA
) {
1394 IWL_DEBUG_HT(priv
, "AGG stop before setup done\n");
1395 ieee80211_stop_tx_ba_cb_irqsafe(priv
->vif
, ra
, tid
);
1396 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1400 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_ON
)
1401 IWL_WARN(priv
, "Stopping AGG while state not ON or starting\n");
1403 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1404 ssn
= (tid_data
->seq_number
& IEEE80211_SCTL_SEQ
) >> 4;
1405 txq_id
= tid_data
->agg
.txq_id
;
1406 write_ptr
= priv
->txq
[txq_id
].q
.write_ptr
;
1407 read_ptr
= priv
->txq
[txq_id
].q
.read_ptr
;
1409 /* The queue is not empty */
1410 if (write_ptr
!= read_ptr
) {
1411 IWL_DEBUG_HT(priv
, "Stopping a non empty AGG HW QUEUE\n");
1412 priv
->stations
[sta_id
].tid
[tid
].agg
.state
=
1413 IWL_EMPTYING_HW_QUEUE_DELBA
;
1417 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1418 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1420 spin_lock_irqsave(&priv
->lock
, flags
);
1422 * the only reason this call can fail is queue number out of range,
1423 * which can happen if uCode is reloaded and all the station
1424 * information are lost. if it is outside the range, there is no need
1425 * to deactivate the uCode queue, just return "success" to allow
1426 * mac80211 to clean up it own data.
1428 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
, ssn
,
1430 spin_unlock_irqrestore(&priv
->lock
, flags
);
1432 ieee80211_stop_tx_ba_cb_irqsafe(priv
->vif
, ra
, tid
);
1436 EXPORT_SYMBOL(iwl_tx_agg_stop
);
1438 int iwl_txq_check_empty(struct iwl_priv
*priv
, int sta_id
, u8 tid
, int txq_id
)
1440 struct iwl_queue
*q
= &priv
->txq
[txq_id
].q
;
1441 u8
*addr
= priv
->stations
[sta_id
].sta
.sta
.addr
;
1442 struct iwl_tid_data
*tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1444 switch (priv
->stations
[sta_id
].tid
[tid
].agg
.state
) {
1445 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1446 /* We are reclaiming the last packet of the */
1447 /* aggregated HW queue */
1448 if ((txq_id
== tid_data
->agg
.txq_id
) &&
1449 (q
->read_ptr
== q
->write_ptr
)) {
1450 u16 ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1451 int tx_fifo
= get_fifo_from_tid(tid
);
1452 IWL_DEBUG_HT(priv
, "HW queue empty: continue DELBA flow\n");
1453 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
,
1455 tid_data
->agg
.state
= IWL_AGG_OFF
;
1456 ieee80211_stop_tx_ba_cb_irqsafe(priv
->vif
, addr
, tid
);
1459 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1460 /* We are reclaiming the last packet of the queue */
1461 if (tid_data
->tfds_in_queue
== 0) {
1462 IWL_DEBUG_HT(priv
, "HW queue empty: continue ADDBA flow\n");
1463 tid_data
->agg
.state
= IWL_AGG_ON
;
1464 ieee80211_start_tx_ba_cb_irqsafe(priv
->vif
, addr
, tid
);
1470 EXPORT_SYMBOL(iwl_txq_check_empty
);
1473 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1475 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1476 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1478 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv
*priv
,
1479 struct iwl_ht_agg
*agg
,
1480 struct iwl_compressed_ba_resp
*ba_resp
)
1484 u16 seq_ctl
= le16_to_cpu(ba_resp
->seq_ctl
);
1485 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1488 struct ieee80211_tx_info
*info
;
1490 if (unlikely(!agg
->wait_for_ba
)) {
1491 IWL_ERR(priv
, "Received BA when not expected\n");
1495 /* Mark that the expected block-ack response arrived */
1496 agg
->wait_for_ba
= 0;
1497 IWL_DEBUG_TX_REPLY(priv
, "BA %d %d\n", agg
->start_idx
, ba_resp
->seq_ctl
);
1499 /* Calculate shift to align block-ack bits with our Tx window bits */
1500 sh
= agg
->start_idx
- SEQ_TO_INDEX(seq_ctl
>> 4);
1501 if (sh
< 0) /* tbw something is wrong with indices */
1504 /* don't use 64-bit values for now */
1505 bitmap
= le64_to_cpu(ba_resp
->bitmap
) >> sh
;
1507 if (agg
->frame_count
> (64 - sh
)) {
1508 IWL_DEBUG_TX_REPLY(priv
, "more frames than bitmap size");
1512 /* check for success or failure according to the
1513 * transmitted bitmap and block-ack bitmap */
1514 bitmap
&= agg
->bitmap
;
1516 /* For each frame attempted in aggregation,
1517 * update driver's record of tx frame's status. */
1518 for (i
= 0; i
< agg
->frame_count
; i
++) {
1519 ack
= bitmap
& (1ULL << i
);
1521 IWL_DEBUG_TX_REPLY(priv
, "%s ON i=%d idx=%d raw=%d\n",
1522 ack
? "ACK" : "NACK", i
, (agg
->start_idx
+ i
) & 0xff,
1523 agg
->start_idx
+ i
);
1526 info
= IEEE80211_SKB_CB(priv
->txq
[scd_flow
].txb
[agg
->start_idx
].skb
[0]);
1527 memset(&info
->status
, 0, sizeof(info
->status
));
1528 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1529 info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
1530 info
->status
.ampdu_ack_map
= successes
;
1531 info
->status
.ampdu_ack_len
= agg
->frame_count
;
1532 iwl_hwrate_to_tx_control(priv
, agg
->rate_n_flags
, info
);
1534 IWL_DEBUG_TX_REPLY(priv
, "Bitmap %llx\n", (unsigned long long)bitmap
);
1540 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1542 * Handles block-acknowledge notification from device, which reports success
1543 * of frames sent via aggregation.
1545 void iwl_rx_reply_compressed_ba(struct iwl_priv
*priv
,
1546 struct iwl_rx_mem_buffer
*rxb
)
1548 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1549 struct iwl_compressed_ba_resp
*ba_resp
= &pkt
->u
.compressed_ba
;
1550 struct iwl_tx_queue
*txq
= NULL
;
1551 struct iwl_ht_agg
*agg
;
1556 /* "flow" corresponds to Tx queue */
1557 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1559 /* "ssn" is start of block-ack Tx window, corresponds to index
1560 * (in Tx queue's circular buffer) of first TFD/frame in window */
1561 u16 ba_resp_scd_ssn
= le16_to_cpu(ba_resp
->scd_ssn
);
1563 if (scd_flow
>= priv
->hw_params
.max_txq_num
) {
1565 "BUG_ON scd_flow is bigger than number of queues\n");
1569 txq
= &priv
->txq
[scd_flow
];
1570 sta_id
= ba_resp
->sta_id
;
1572 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1574 /* Find index just before block-ack window */
1575 index
= iwl_queue_dec_wrap(ba_resp_scd_ssn
& 0xff, txq
->q
.n_bd
);
1577 /* TODO: Need to get this copy more safely - now good for debug */
1579 IWL_DEBUG_TX_REPLY(priv
, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1582 (u8
*) &ba_resp
->sta_addr_lo32
,
1584 IWL_DEBUG_TX_REPLY(priv
, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1585 "%d, scd_ssn = %d\n",
1588 (unsigned long long)le64_to_cpu(ba_resp
->bitmap
),
1591 IWL_DEBUG_TX_REPLY(priv
, "DAT start_idx = %d, bitmap = 0x%llx \n",
1593 (unsigned long long)agg
->bitmap
);
1595 /* Update driver's record of ACK vs. not for each frame in window */
1596 iwl_tx_status_reply_compressed_ba(priv
, agg
, ba_resp
);
1598 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1599 * block-ack window (we assume that they've been successfully
1600 * transmitted ... if not, it's too late anyway). */
1601 if (txq
->q
.read_ptr
!= (ba_resp_scd_ssn
& 0xff)) {
1602 /* calculate mac80211 ampdu sw queue to wake */
1603 int freed
= iwl_tx_queue_reclaim(priv
, scd_flow
, index
);
1604 iwl_free_tfds_in_queue(priv
, sta_id
, tid
, freed
);
1606 if ((iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1607 priv
->mac80211_registered
&&
1608 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
))
1609 iwl_wake_queue(priv
, txq
->swq_id
);
1611 iwl_txq_check_empty(priv
, sta_id
, tid
, scd_flow
);
1614 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba
);
1616 #ifdef CONFIG_IWLWIFI_DEBUG
1617 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1619 const char *iwl_get_tx_fail_reason(u32 status
)
1621 switch (status
& TX_STATUS_MSK
) {
1622 case TX_STATUS_SUCCESS
:
1624 TX_STATUS_ENTRY(SHORT_LIMIT
);
1625 TX_STATUS_ENTRY(LONG_LIMIT
);
1626 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
1627 TX_STATUS_ENTRY(MGMNT_ABORT
);
1628 TX_STATUS_ENTRY(NEXT_FRAG
);
1629 TX_STATUS_ENTRY(LIFE_EXPIRE
);
1630 TX_STATUS_ENTRY(DEST_PS
);
1631 TX_STATUS_ENTRY(ABORTED
);
1632 TX_STATUS_ENTRY(BT_RETRY
);
1633 TX_STATUS_ENTRY(STA_INVALID
);
1634 TX_STATUS_ENTRY(FRAG_DROPPED
);
1635 TX_STATUS_ENTRY(TID_DISABLE
);
1636 TX_STATUS_ENTRY(FRAME_FLUSHED
);
1637 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
1638 TX_STATUS_ENTRY(TX_LOCKED
);
1639 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
1644 EXPORT_SYMBOL(iwl_get_tx_fail_reason
);
1645 #endif /* CONFIG_IWLWIFI_DEBUG */