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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6/kvm.git] / drivers / net / wireless / ath / ath9k / xmit.c
bloba3b6cf20f8a125b1f23f8b31927a619d6696cadd
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_txq *txq,
63 struct list_head *bf_q,
64 int txok, int sendbar);
65 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
66 struct list_head *head);
67 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
68 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
69 int txok);
70 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
71 int nbad, int txok, bool update_rc);
72
73 enum {
74 MCS_DEFAULT,
75 MCS_HT40,
76 MCS_HT40_SGI,
77 };
78
79 static int ath_max_4ms_framelen[3][16] = {
80 [MCS_DEFAULT] = {
81 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180,
82 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320,
83 },
84 [MCS_HT40] = {
85 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840,
86 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600,
87 },
88 [MCS_HT40_SGI] = {
89 /* TODO: Only MCS 7 and 15 updated, recalculate the rest */
90 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200,
91 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400,
92 }
93 };
94
95
96 /*********************/
97 /* Aggregation logic */
98 /*********************/
99
100 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
101 {
102 struct ath_atx_ac *ac = tid->ac;
103
104 if (tid->paused)
105 return;
106
107 if (tid->sched)
108 return;
109
110 tid->sched = true;
111 list_add_tail(&tid->list, &ac->tid_q);
112
113 if (ac->sched)
114 return;
115
116 ac->sched = true;
117 list_add_tail(&ac->list, &txq->axq_acq);
118 }
119
120 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
121 {
122 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
123
124 spin_lock_bh(&txq->axq_lock);
125 tid->paused++;
126 spin_unlock_bh(&txq->axq_lock);
127 }
128
129 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
130 {
131 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
132
133 BUG_ON(tid->paused <= 0);
134 spin_lock_bh(&txq->axq_lock);
135
136 tid->paused--;
137
138 if (tid->paused > 0)
139 goto unlock;
140
141 if (list_empty(&tid->buf_q))
142 goto unlock;
143
144 ath_tx_queue_tid(txq, tid);
145 ath_txq_schedule(sc, txq);
146 unlock:
147 spin_unlock_bh(&txq->axq_lock);
148 }
149
150 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 {
152 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
153 struct ath_buf *bf;
154 struct list_head bf_head;
155 INIT_LIST_HEAD(&bf_head);
156
157 BUG_ON(tid->paused <= 0);
158 spin_lock_bh(&txq->axq_lock);
159
160 tid->paused--;
161
162 if (tid->paused > 0) {
163 spin_unlock_bh(&txq->axq_lock);
164 return;
165 }
166
167 while (!list_empty(&tid->buf_q)) {
168 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
169 BUG_ON(bf_isretried(bf));
170 list_move_tail(&bf->list, &bf_head);
171 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
172 }
173
174 spin_unlock_bh(&txq->axq_lock);
175 }
176
177 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
178 int seqno)
179 {
180 int index, cindex;
181
182 index = ATH_BA_INDEX(tid->seq_start, seqno);
183 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
184
185 tid->tx_buf[cindex] = NULL;
186
187 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
188 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
189 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
190 }
191 }
192
193 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
194 struct ath_buf *bf)
195 {
196 int index, cindex;
197
198 if (bf_isretried(bf))
199 return;
200
201 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203
204 BUG_ON(tid->tx_buf[cindex] != NULL);
205 tid->tx_buf[cindex] = bf;
206
207 if (index >= ((tid->baw_tail - tid->baw_head) &
208 (ATH_TID_MAX_BUFS - 1))) {
209 tid->baw_tail = cindex;
210 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
211 }
212 }
213
214 /*
215 * TODO: For frame(s) that are in the retry state, we will reuse the
216 * sequence number(s) without setting the retry bit. The
217 * alternative is to give up on these and BAR the receiver's window
218 * forward.
219 */
220 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
221 struct ath_atx_tid *tid)
222
223 {
224 struct ath_buf *bf;
225 struct list_head bf_head;
226 INIT_LIST_HEAD(&bf_head);
227
228 for (;;) {
229 if (list_empty(&tid->buf_q))
230 break;
231
232 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
233 list_move_tail(&bf->list, &bf_head);
234
235 if (bf_isretried(bf))
236 ath_tx_update_baw(sc, tid, bf->bf_seqno);
237
238 spin_unlock(&txq->axq_lock);
239 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
240 spin_lock(&txq->axq_lock);
241 }
242
243 tid->seq_next = tid->seq_start;
244 tid->baw_tail = tid->baw_head;
245 }
246
247 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
248 struct ath_buf *bf)
249 {
250 struct sk_buff *skb;
251 struct ieee80211_hdr *hdr;
252
253 bf->bf_state.bf_type |= BUF_RETRY;
254 bf->bf_retries++;
255 TX_STAT_INC(txq->axq_qnum, a_retries);
256
257 skb = bf->bf_mpdu;
258 hdr = (struct ieee80211_hdr *)skb->data;
259 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
260 }
261
262 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
263 {
264 struct ath_buf *tbf;
265
266 spin_lock_bh(&sc->tx.txbuflock);
267 if (WARN_ON(list_empty(&sc->tx.txbuf))) {
268 spin_unlock_bh(&sc->tx.txbuflock);
269 return NULL;
270 }
271 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
272 list_del(&tbf->list);
273 spin_unlock_bh(&sc->tx.txbuflock);
274
275 ATH_TXBUF_RESET(tbf);
276
277 tbf->aphy = bf->aphy;
278 tbf->bf_mpdu = bf->bf_mpdu;
279 tbf->bf_buf_addr = bf->bf_buf_addr;
280 *(tbf->bf_desc) = *(bf->bf_desc);
281 tbf->bf_state = bf->bf_state;
282 tbf->bf_dmacontext = bf->bf_dmacontext;
283
284 return tbf;
285 }
286
287 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
288 struct ath_buf *bf, struct list_head *bf_q,
289 int txok)
290 {
291 struct ath_node *an = NULL;
292 struct sk_buff *skb;
293 struct ieee80211_sta *sta;
294 struct ieee80211_hw *hw;
295 struct ieee80211_hdr *hdr;
296 struct ieee80211_tx_info *tx_info;
297 struct ath_atx_tid *tid = NULL;
298 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
299 struct ath_desc *ds = bf_last->bf_desc;
300 struct list_head bf_head, bf_pending;
301 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
302 u32 ba[WME_BA_BMP_SIZE >> 5];
303 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
304 bool rc_update = true;
305
306 skb = bf->bf_mpdu;
307 hdr = (struct ieee80211_hdr *)skb->data;
308
309 tx_info = IEEE80211_SKB_CB(skb);
310 hw = bf->aphy->hw;
311
312 rcu_read_lock();
313
314 /* XXX: use ieee80211_find_sta! */
315 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
316 if (!sta) {
317 rcu_read_unlock();
318 return;
319 }
320
321 an = (struct ath_node *)sta->drv_priv;
322 tid = ATH_AN_2_TID(an, bf->bf_tidno);
323
324 isaggr = bf_isaggr(bf);
325 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
326
327 if (isaggr && txok) {
328 if (ATH_DS_TX_BA(ds)) {
329 seq_st = ATH_DS_BA_SEQ(ds);
330 memcpy(ba, ATH_DS_BA_BITMAP(ds),
331 WME_BA_BMP_SIZE >> 3);
332 } else {
333 /*
334 * AR5416 can become deaf/mute when BA
335 * issue happens. Chip needs to be reset.
336 * But AP code may have sychronization issues
337 * when perform internal reset in this routine.
338 * Only enable reset in STA mode for now.
339 */
340 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
341 needreset = 1;
342 }
343 }
344
345 INIT_LIST_HEAD(&bf_pending);
346 INIT_LIST_HEAD(&bf_head);
347
348 nbad = ath_tx_num_badfrms(sc, bf, txok);
349 while (bf) {
350 txfail = txpending = 0;
351 bf_next = bf->bf_next;
352
353 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
354 /* transmit completion, subframe is
355 * acked by block ack */
356 acked_cnt++;
357 } else if (!isaggr && txok) {
358 /* transmit completion */
359 acked_cnt++;
360 } else {
361 if (!(tid->state & AGGR_CLEANUP) &&
362 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
363 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
364 ath_tx_set_retry(sc, txq, bf);
365 txpending = 1;
366 } else {
367 bf->bf_state.bf_type |= BUF_XRETRY;
368 txfail = 1;
369 sendbar = 1;
370 txfail_cnt++;
371 }
372 } else {
373 /*
374 * cleanup in progress, just fail
375 * the un-acked sub-frames
376 */
377 txfail = 1;
378 }
379 }
380
381 if (bf_next == NULL) {
382 /*
383 * Make sure the last desc is reclaimed if it
384 * not a holding desc.
385 */
386 if (!bf_last->bf_stale)
387 list_move_tail(&bf->list, &bf_head);
388 else
389 INIT_LIST_HEAD(&bf_head);
390 } else {
391 BUG_ON(list_empty(bf_q));
392 list_move_tail(&bf->list, &bf_head);
393 }
394
395 if (!txpending) {
396 /*
397 * complete the acked-ones/xretried ones; update
398 * block-ack window
399 */
400 spin_lock_bh(&txq->axq_lock);
401 ath_tx_update_baw(sc, tid, bf->bf_seqno);
402 spin_unlock_bh(&txq->axq_lock);
403
404 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
405 ath_tx_rc_status(bf, ds, nbad, txok, true);
406 rc_update = false;
407 } else {
408 ath_tx_rc_status(bf, ds, nbad, txok, false);
409 }
410
411 ath_tx_complete_buf(sc, bf, txq, &bf_head, !txfail, sendbar);
412 } else {
413 /* retry the un-acked ones */
414 if (bf->bf_next == NULL && bf_last->bf_stale) {
415 struct ath_buf *tbf;
416
417 tbf = ath_clone_txbuf(sc, bf_last);
418 /*
419 * Update tx baw and complete the frame with
420 * failed status if we run out of tx buf
421 */
422 if (!tbf) {
423 spin_lock_bh(&txq->axq_lock);
424 ath_tx_update_baw(sc, tid,
425 bf->bf_seqno);
426 spin_unlock_bh(&txq->axq_lock);
427
428 bf->bf_state.bf_type |= BUF_XRETRY;
429 ath_tx_rc_status(bf, ds, nbad,
430 0, false);
431 ath_tx_complete_buf(sc, bf, txq,
432 &bf_head, 0, 0);
433 break;
434 }
435
436 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
437 list_add_tail(&tbf->list, &bf_head);
438 } else {
439 /*
440 * Clear descriptor status words for
441 * software retry
442 */
443 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
444 }
445
446 /*
447 * Put this buffer to the temporary pending
448 * queue to retain ordering
449 */
450 list_splice_tail_init(&bf_head, &bf_pending);
451 }
452
453 bf = bf_next;
454 }
455
456 if (tid->state & AGGR_CLEANUP) {
457 if (tid->baw_head == tid->baw_tail) {
458 tid->state &= ~AGGR_ADDBA_COMPLETE;
459 tid->state &= ~AGGR_CLEANUP;
460
461 /* send buffered frames as singles */
462 ath_tx_flush_tid(sc, tid);
463 }
464 rcu_read_unlock();
465 return;
466 }
467
468 /* prepend un-acked frames to the beginning of the pending frame queue */
469 if (!list_empty(&bf_pending)) {
470 spin_lock_bh(&txq->axq_lock);
471 list_splice(&bf_pending, &tid->buf_q);
472 ath_tx_queue_tid(txq, tid);
473 spin_unlock_bh(&txq->axq_lock);
474 }
475
476 rcu_read_unlock();
477
478 if (needreset)
479 ath_reset(sc, false);
480 }
481
482 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
483 struct ath_atx_tid *tid)
484 {
485 struct sk_buff *skb;
486 struct ieee80211_tx_info *tx_info;
487 struct ieee80211_tx_rate *rates;
488 u32 max_4ms_framelen, frmlen;
489 u16 aggr_limit, legacy = 0;
490 int i;
491
492 skb = bf->bf_mpdu;
493 tx_info = IEEE80211_SKB_CB(skb);
494 rates = tx_info->control.rates;
495
496 /*
497 * Find the lowest frame length among the rate series that will have a
498 * 4ms transmit duration.
499 * TODO - TXOP limit needs to be considered.
500 */
501 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
502
503 for (i = 0; i < 4; i++) {
504 if (rates[i].count) {
505 int modeidx;
506 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
507 legacy = 1;
508 break;
509 }
510
511 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
512 modeidx = MCS_HT40_SGI;
513 else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
514 modeidx = MCS_HT40;
515 else
516 modeidx = MCS_DEFAULT;
517
518 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
519 max_4ms_framelen = min(max_4ms_framelen, frmlen);
520 }
521 }
522
523 /*
524 * limit aggregate size by the minimum rate if rate selected is
525 * not a probe rate, if rate selected is a probe rate then
526 * avoid aggregation of this packet.
527 */
528 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
529 return 0;
530
531 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
532 aggr_limit = min((max_4ms_framelen * 3) / 8,
533 (u32)ATH_AMPDU_LIMIT_MAX);
534 else
535 aggr_limit = min(max_4ms_framelen,
536 (u32)ATH_AMPDU_LIMIT_MAX);
537
538 /*
539 * h/w can accept aggregates upto 16 bit lengths (65535).
540 * The IE, however can hold upto 65536, which shows up here
541 * as zero. Ignore 65536 since we are constrained by hw.
542 */
543 if (tid->an->maxampdu)
544 aggr_limit = min(aggr_limit, tid->an->maxampdu);
545
546 return aggr_limit;
547 }
548
549 /*
550 * Returns the number of delimiters to be added to
551 * meet the minimum required mpdudensity.
552 */
553 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
554 struct ath_buf *bf, u16 frmlen)
555 {
556 struct sk_buff *skb = bf->bf_mpdu;
557 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
558 u32 nsymbits, nsymbols;
559 u16 minlen;
560 u8 flags, rix;
561 int width, half_gi, ndelim, mindelim;
562
563 /* Select standard number of delimiters based on frame length alone */
564 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
565
566 /*
567 * If encryption enabled, hardware requires some more padding between
568 * subframes.
569 * TODO - this could be improved to be dependent on the rate.
570 * The hardware can keep up at lower rates, but not higher rates
571 */
572 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
573 ndelim += ATH_AGGR_ENCRYPTDELIM;
574
575 /*
576 * Convert desired mpdu density from microeconds to bytes based
577 * on highest rate in rate series (i.e. first rate) to determine
578 * required minimum length for subframe. Take into account
579 * whether high rate is 20 or 40Mhz and half or full GI.
580 *
581 * If there is no mpdu density restriction, no further calculation
582 * is needed.
583 */
584
585 if (tid->an->mpdudensity == 0)
586 return ndelim;
587
588 rix = tx_info->control.rates[0].idx;
589 flags = tx_info->control.rates[0].flags;
590 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
591 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
592
593 if (half_gi)
594 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
595 else
596 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
597
598 if (nsymbols == 0)
599 nsymbols = 1;
600
601 nsymbits = bits_per_symbol[rix][width];
602 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
603
604 if (frmlen < minlen) {
605 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
606 ndelim = max(mindelim, ndelim);
607 }
608
609 return ndelim;
610 }
611
612 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
613 struct ath_txq *txq,
614 struct ath_atx_tid *tid,
615 struct list_head *bf_q)
616 {
617 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
618 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
619 int rl = 0, nframes = 0, ndelim, prev_al = 0;
620 u16 aggr_limit = 0, al = 0, bpad = 0,
621 al_delta, h_baw = tid->baw_size / 2;
622 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
623
624 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
625
626 do {
627 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
628
629 /* do not step over block-ack window */
630 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
631 status = ATH_AGGR_BAW_CLOSED;
632 break;
633 }
634
635 if (!rl) {
636 aggr_limit = ath_lookup_rate(sc, bf, tid);
637 rl = 1;
638 }
639
640 /* do not exceed aggregation limit */
641 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
642
643 if (nframes &&
644 (aggr_limit < (al + bpad + al_delta + prev_al))) {
645 status = ATH_AGGR_LIMITED;
646 break;
647 }
648
649 /* do not exceed subframe limit */
650 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
651 status = ATH_AGGR_LIMITED;
652 break;
653 }
654 nframes++;
655
656 /* add padding for previous frame to aggregation length */
657 al += bpad + al_delta;
658
659 /*
660 * Get the delimiters needed to meet the MPDU
661 * density for this node.
662 */
663 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
664 bpad = PADBYTES(al_delta) + (ndelim << 2);
665
666 bf->bf_next = NULL;
667 bf->bf_desc->ds_link = 0;
668
669 /* link buffers of this frame to the aggregate */
670 ath_tx_addto_baw(sc, tid, bf);
671 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
672 list_move_tail(&bf->list, bf_q);
673 if (bf_prev) {
674 bf_prev->bf_next = bf;
675 bf_prev->bf_desc->ds_link = bf->bf_daddr;
676 }
677 bf_prev = bf;
678
679 } while (!list_empty(&tid->buf_q));
680
681 bf_first->bf_al = al;
682 bf_first->bf_nframes = nframes;
683
684 return status;
685 #undef PADBYTES
686 }
687
688 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
689 struct ath_atx_tid *tid)
690 {
691 struct ath_buf *bf;
692 enum ATH_AGGR_STATUS status;
693 struct list_head bf_q;
694
695 do {
696 if (list_empty(&tid->buf_q))
697 return;
698
699 INIT_LIST_HEAD(&bf_q);
700
701 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
702
703 /*
704 * no frames picked up to be aggregated;
705 * block-ack window is not open.
706 */
707 if (list_empty(&bf_q))
708 break;
709
710 bf = list_first_entry(&bf_q, struct ath_buf, list);
711 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
712
713 /* if only one frame, send as non-aggregate */
714 if (bf->bf_nframes == 1) {
715 bf->bf_state.bf_type &= ~BUF_AGGR;
716 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
717 ath_buf_set_rate(sc, bf);
718 ath_tx_txqaddbuf(sc, txq, &bf_q);
719 continue;
720 }
721
722 /* setup first desc of aggregate */
723 bf->bf_state.bf_type |= BUF_AGGR;
724 ath_buf_set_rate(sc, bf);
725 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
726
727 /* anchor last desc of aggregate */
728 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
729
730 ath_tx_txqaddbuf(sc, txq, &bf_q);
731 TX_STAT_INC(txq->axq_qnum, a_aggr);
732
733 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
734 status != ATH_AGGR_BAW_CLOSED);
735 }
736
737 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
738 u16 tid, u16 *ssn)
739 {
740 struct ath_atx_tid *txtid;
741 struct ath_node *an;
742
743 an = (struct ath_node *)sta->drv_priv;
744 txtid = ATH_AN_2_TID(an, tid);
745 txtid->state |= AGGR_ADDBA_PROGRESS;
746 ath_tx_pause_tid(sc, txtid);
747 *ssn = txtid->seq_start;
748 }
749
750 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
751 {
752 struct ath_node *an = (struct ath_node *)sta->drv_priv;
753 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
754 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
755 struct ath_buf *bf;
756 struct list_head bf_head;
757 INIT_LIST_HEAD(&bf_head);
758
759 if (txtid->state & AGGR_CLEANUP)
760 return;
761
762 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
763 txtid->state &= ~AGGR_ADDBA_PROGRESS;
764 return;
765 }
766
767 ath_tx_pause_tid(sc, txtid);
768
769 /* drop all software retried frames and mark this TID */
770 spin_lock_bh(&txq->axq_lock);
771 while (!list_empty(&txtid->buf_q)) {
772 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
773 if (!bf_isretried(bf)) {
774 /*
775 * NB: it's based on the assumption that
776 * software retried frame will always stay
777 * at the head of software queue.
778 */
779 break;
780 }
781 list_move_tail(&bf->list, &bf_head);
782 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
783 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
784 }
785 spin_unlock_bh(&txq->axq_lock);
786
787 if (txtid->baw_head != txtid->baw_tail) {
788 txtid->state |= AGGR_CLEANUP;
789 } else {
790 txtid->state &= ~AGGR_ADDBA_COMPLETE;
791 ath_tx_flush_tid(sc, txtid);
792 }
793 }
794
795 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
796 {
797 struct ath_atx_tid *txtid;
798 struct ath_node *an;
799
800 an = (struct ath_node *)sta->drv_priv;
801
802 if (sc->sc_flags & SC_OP_TXAGGR) {
803 txtid = ATH_AN_2_TID(an, tid);
804 txtid->baw_size =
805 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
806 txtid->state |= AGGR_ADDBA_COMPLETE;
807 txtid->state &= ~AGGR_ADDBA_PROGRESS;
808 ath_tx_resume_tid(sc, txtid);
809 }
810 }
811
812 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
813 {
814 struct ath_atx_tid *txtid;
815
816 if (!(sc->sc_flags & SC_OP_TXAGGR))
817 return false;
818
819 txtid = ATH_AN_2_TID(an, tidno);
820
821 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
822 return true;
823 return false;
824 }
825
826 /********************/
827 /* Queue Management */
828 /********************/
829
830 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
831 struct ath_txq *txq)
832 {
833 struct ath_atx_ac *ac, *ac_tmp;
834 struct ath_atx_tid *tid, *tid_tmp;
835
836 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
837 list_del(&ac->list);
838 ac->sched = false;
839 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
840 list_del(&tid->list);
841 tid->sched = false;
842 ath_tid_drain(sc, txq, tid);
843 }
844 }
845 }
846
847 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
848 {
849 struct ath_hw *ah = sc->sc_ah;
850 struct ath_common *common = ath9k_hw_common(ah);
851 struct ath9k_tx_queue_info qi;
852 int qnum;
853
854 memset(&qi, 0, sizeof(qi));
855 qi.tqi_subtype = subtype;
856 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
857 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
858 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
859 qi.tqi_physCompBuf = 0;
860
861 /*
862 * Enable interrupts only for EOL and DESC conditions.
863 * We mark tx descriptors to receive a DESC interrupt
864 * when a tx queue gets deep; otherwise waiting for the
865 * EOL to reap descriptors. Note that this is done to
866 * reduce interrupt load and this only defers reaping
867 * descriptors, never transmitting frames. Aside from
868 * reducing interrupts this also permits more concurrency.
869 * The only potential downside is if the tx queue backs
870 * up in which case the top half of the kernel may backup
871 * due to a lack of tx descriptors.
872 *
873 * The UAPSD queue is an exception, since we take a desc-
874 * based intr on the EOSP frames.
875 */
876 if (qtype == ATH9K_TX_QUEUE_UAPSD)
877 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
878 else
879 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
880 TXQ_FLAG_TXDESCINT_ENABLE;
881 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
882 if (qnum == -1) {
883 /*
884 * NB: don't print a message, this happens
885 * normally on parts with too few tx queues
886 */
887 return NULL;
888 }
889 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
890 ath_print(common, ATH_DBG_FATAL,
891 "qnum %u out of range, max %u!\n",
892 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
893 ath9k_hw_releasetxqueue(ah, qnum);
894 return NULL;
895 }
896 if (!ATH_TXQ_SETUP(sc, qnum)) {
897 struct ath_txq *txq = &sc->tx.txq[qnum];
898
899 txq->axq_qnum = qnum;
900 txq->axq_link = NULL;
901 INIT_LIST_HEAD(&txq->axq_q);
902 INIT_LIST_HEAD(&txq->axq_acq);
903 spin_lock_init(&txq->axq_lock);
904 txq->axq_depth = 0;
905 txq->axq_tx_inprogress = false;
906 sc->tx.txqsetup |= 1<<qnum;
907 }
908 return &sc->tx.txq[qnum];
909 }
910
911 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
912 {
913 int qnum;
914
915 switch (qtype) {
916 case ATH9K_TX_QUEUE_DATA:
917 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
918 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
919 "HAL AC %u out of range, max %zu!\n",
920 haltype, ARRAY_SIZE(sc->tx.hwq_map));
921 return -1;
922 }
923 qnum = sc->tx.hwq_map[haltype];
924 break;
925 case ATH9K_TX_QUEUE_BEACON:
926 qnum = sc->beacon.beaconq;
927 break;
928 case ATH9K_TX_QUEUE_CAB:
929 qnum = sc->beacon.cabq->axq_qnum;
930 break;
931 default:
932 qnum = -1;
933 }
934 return qnum;
935 }
936
937 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
938 {
939 struct ath_txq *txq = NULL;
940 u16 skb_queue = skb_get_queue_mapping(skb);
941 int qnum;
942
943 qnum = ath_get_hal_qnum(skb_queue, sc);
944 txq = &sc->tx.txq[qnum];
945
946 spin_lock_bh(&txq->axq_lock);
947
948 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
949 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
950 "TX queue: %d is full, depth: %d\n",
951 qnum, txq->axq_depth);
952 ath_mac80211_stop_queue(sc, skb_queue);
953 txq->stopped = 1;
954 spin_unlock_bh(&txq->axq_lock);
955 return NULL;
956 }
957
958 spin_unlock_bh(&txq->axq_lock);
959
960 return txq;
961 }
962
963 int ath_txq_update(struct ath_softc *sc, int qnum,
964 struct ath9k_tx_queue_info *qinfo)
965 {
966 struct ath_hw *ah = sc->sc_ah;
967 int error = 0;
968 struct ath9k_tx_queue_info qi;
969
970 if (qnum == sc->beacon.beaconq) {
971 /*
972 * XXX: for beacon queue, we just save the parameter.
973 * It will be picked up by ath_beaconq_config when
974 * it's necessary.
975 */
976 sc->beacon.beacon_qi = *qinfo;
977 return 0;
978 }
979
980 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
981
982 ath9k_hw_get_txq_props(ah, qnum, &qi);
983 qi.tqi_aifs = qinfo->tqi_aifs;
984 qi.tqi_cwmin = qinfo->tqi_cwmin;
985 qi.tqi_cwmax = qinfo->tqi_cwmax;
986 qi.tqi_burstTime = qinfo->tqi_burstTime;
987 qi.tqi_readyTime = qinfo->tqi_readyTime;
988
989 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
990 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
991 "Unable to update hardware queue %u!\n", qnum);
992 error = -EIO;
993 } else {
994 ath9k_hw_resettxqueue(ah, qnum);
995 }
996
997 return error;
998 }
999
1000 int ath_cabq_update(struct ath_softc *sc)
1001 {
1002 struct ath9k_tx_queue_info qi;
1003 int qnum = sc->beacon.cabq->axq_qnum;
1004
1005 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1006 /*
1007 * Ensure the readytime % is within the bounds.
1008 */
1009 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1010 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1011 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1012 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1013
1014 qi.tqi_readyTime = (sc->beacon_interval *
1015 sc->config.cabqReadytime) / 100;
1016 ath_txq_update(sc, qnum, &qi);
1017
1018 return 0;
1019 }
1020
1021 /*
1022 * Drain a given TX queue (could be Beacon or Data)
1023 *
1024 * This assumes output has been stopped and
1025 * we do not need to block ath_tx_tasklet.
1026 */
1027 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1028 {
1029 struct ath_buf *bf, *lastbf;
1030 struct list_head bf_head;
1031
1032 INIT_LIST_HEAD(&bf_head);
1033
1034 for (;;) {
1035 spin_lock_bh(&txq->axq_lock);
1036
1037 if (list_empty(&txq->axq_q)) {
1038 txq->axq_link = NULL;
1039 spin_unlock_bh(&txq->axq_lock);
1040 break;
1041 }
1042
1043 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1044
1045 if (bf->bf_stale) {
1046 list_del(&bf->list);
1047 spin_unlock_bh(&txq->axq_lock);
1048
1049 spin_lock_bh(&sc->tx.txbuflock);
1050 list_add_tail(&bf->list, &sc->tx.txbuf);
1051 spin_unlock_bh(&sc->tx.txbuflock);
1052 continue;
1053 }
1054
1055 lastbf = bf->bf_lastbf;
1056 if (!retry_tx)
1057 lastbf->bf_desc->ds_txstat.ts_flags =
1058 ATH9K_TX_SW_ABORTED;
1059
1060 /* remove ath_buf's of the same mpdu from txq */
1061 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1062 txq->axq_depth--;
1063
1064 spin_unlock_bh(&txq->axq_lock);
1065
1066 if (bf_isampdu(bf))
1067 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1068 else
1069 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
1070 }
1071
1072 spin_lock_bh(&txq->axq_lock);
1073 txq->axq_tx_inprogress = false;
1074 spin_unlock_bh(&txq->axq_lock);
1075
1076 /* flush any pending frames if aggregation is enabled */
1077 if (sc->sc_flags & SC_OP_TXAGGR) {
1078 if (!retry_tx) {
1079 spin_lock_bh(&txq->axq_lock);
1080 ath_txq_drain_pending_buffers(sc, txq);
1081 spin_unlock_bh(&txq->axq_lock);
1082 }
1083 }
1084 }
1085
1086 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1087 {
1088 struct ath_hw *ah = sc->sc_ah;
1089 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1090 struct ath_txq *txq;
1091 int i, npend = 0;
1092
1093 if (sc->sc_flags & SC_OP_INVALID)
1094 return;
1095
1096 /* Stop beacon queue */
1097 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1098
1099 /* Stop data queues */
1100 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1101 if (ATH_TXQ_SETUP(sc, i)) {
1102 txq = &sc->tx.txq[i];
1103 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1104 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1105 }
1106 }
1107
1108 if (npend) {
1109 int r;
1110
1111 ath_print(common, ATH_DBG_FATAL,
1112 "Unable to stop TxDMA. Reset HAL!\n");
1113
1114 spin_lock_bh(&sc->sc_resetlock);
1115 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1116 if (r)
1117 ath_print(common, ATH_DBG_FATAL,
1118 "Unable to reset hardware; reset status %d\n",
1119 r);
1120 spin_unlock_bh(&sc->sc_resetlock);
1121 }
1122
1123 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1124 if (ATH_TXQ_SETUP(sc, i))
1125 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1126 }
1127 }
1128
1129 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1130 {
1131 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1132 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1133 }
1134
1135 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1136 {
1137 struct ath_atx_ac *ac;
1138 struct ath_atx_tid *tid;
1139
1140 if (list_empty(&txq->axq_acq))
1141 return;
1142
1143 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1144 list_del(&ac->list);
1145 ac->sched = false;
1146
1147 do {
1148 if (list_empty(&ac->tid_q))
1149 return;
1150
1151 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1152 list_del(&tid->list);
1153 tid->sched = false;
1154
1155 if (tid->paused)
1156 continue;
1157
1158 ath_tx_sched_aggr(sc, txq, tid);
1159
1160 /*
1161 * add tid to round-robin queue if more frames
1162 * are pending for the tid
1163 */
1164 if (!list_empty(&tid->buf_q))
1165 ath_tx_queue_tid(txq, tid);
1166
1167 break;
1168 } while (!list_empty(&ac->tid_q));
1169
1170 if (!list_empty(&ac->tid_q)) {
1171 if (!ac->sched) {
1172 ac->sched = true;
1173 list_add_tail(&ac->list, &txq->axq_acq);
1174 }
1175 }
1176 }
1177
1178 int ath_tx_setup(struct ath_softc *sc, int haltype)
1179 {
1180 struct ath_txq *txq;
1181
1182 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1183 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1184 "HAL AC %u out of range, max %zu!\n",
1185 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1186 return 0;
1187 }
1188 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1189 if (txq != NULL) {
1190 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1191 return 1;
1192 } else
1193 return 0;
1194 }
1195
1196 /***********/
1197 /* TX, DMA */
1198 /***********/
1199
1200 /*
1201 * Insert a chain of ath_buf (descriptors) on a txq and
1202 * assume the descriptors are already chained together by caller.
1203 */
1204 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1205 struct list_head *head)
1206 {
1207 struct ath_hw *ah = sc->sc_ah;
1208 struct ath_common *common = ath9k_hw_common(ah);
1209 struct ath_buf *bf;
1210
1211 /*
1212 * Insert the frame on the outbound list and
1213 * pass it on to the hardware.
1214 */
1215
1216 if (list_empty(head))
1217 return;
1218
1219 bf = list_first_entry(head, struct ath_buf, list);
1220
1221 list_splice_tail_init(head, &txq->axq_q);
1222 txq->axq_depth++;
1223
1224 ath_print(common, ATH_DBG_QUEUE,
1225 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1226
1227 if (txq->axq_link == NULL) {
1228 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1229 ath_print(common, ATH_DBG_XMIT,
1230 "TXDP[%u] = %llx (%p)\n",
1231 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1232 } else {
1233 *txq->axq_link = bf->bf_daddr;
1234 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1235 txq->axq_qnum, txq->axq_link,
1236 ito64(bf->bf_daddr), bf->bf_desc);
1237 }
1238 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1239 ath9k_hw_txstart(ah, txq->axq_qnum);
1240 }
1241
1242 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1243 {
1244 struct ath_buf *bf = NULL;
1245
1246 spin_lock_bh(&sc->tx.txbuflock);
1247
1248 if (unlikely(list_empty(&sc->tx.txbuf))) {
1249 spin_unlock_bh(&sc->tx.txbuflock);
1250 return NULL;
1251 }
1252
1253 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1254 list_del(&bf->list);
1255
1256 spin_unlock_bh(&sc->tx.txbuflock);
1257
1258 return bf;
1259 }
1260
1261 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1262 struct list_head *bf_head,
1263 struct ath_tx_control *txctl)
1264 {
1265 struct ath_buf *bf;
1266
1267 bf = list_first_entry(bf_head, struct ath_buf, list);
1268 bf->bf_state.bf_type |= BUF_AMPDU;
1269 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1270
1271 /*
1272 * Do not queue to h/w when any of the following conditions is true:
1273 * - there are pending frames in software queue
1274 * - the TID is currently paused for ADDBA/BAR request
1275 * - seqno is not within block-ack window
1276 * - h/w queue depth exceeds low water mark
1277 */
1278 if (!list_empty(&tid->buf_q) || tid->paused ||
1279 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1280 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1281 /*
1282 * Add this frame to software queue for scheduling later
1283 * for aggregation.
1284 */
1285 list_move_tail(&bf->list, &tid->buf_q);
1286 ath_tx_queue_tid(txctl->txq, tid);
1287 return;
1288 }
1289
1290 /* Add sub-frame to BAW */
1291 ath_tx_addto_baw(sc, tid, bf);
1292
1293 /* Queue to h/w without aggregation */
1294 bf->bf_nframes = 1;
1295 bf->bf_lastbf = bf;
1296 ath_buf_set_rate(sc, bf);
1297 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1298 }
1299
1300 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1301 struct ath_atx_tid *tid,
1302 struct list_head *bf_head)
1303 {
1304 struct ath_buf *bf;
1305
1306 bf = list_first_entry(bf_head, struct ath_buf, list);
1307 bf->bf_state.bf_type &= ~BUF_AMPDU;
1308
1309 /* update starting sequence number for subsequent ADDBA request */
1310 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1311
1312 bf->bf_nframes = 1;
1313 bf->bf_lastbf = bf;
1314 ath_buf_set_rate(sc, bf);
1315 ath_tx_txqaddbuf(sc, txq, bf_head);
1316 TX_STAT_INC(txq->axq_qnum, queued);
1317 }
1318
1319 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1320 struct list_head *bf_head)
1321 {
1322 struct ath_buf *bf;
1323
1324 bf = list_first_entry(bf_head, struct ath_buf, list);
1325
1326 bf->bf_lastbf = bf;
1327 bf->bf_nframes = 1;
1328 ath_buf_set_rate(sc, bf);
1329 ath_tx_txqaddbuf(sc, txq, bf_head);
1330 TX_STAT_INC(txq->axq_qnum, queued);
1331 }
1332
1333 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1334 {
1335 struct ieee80211_hdr *hdr;
1336 enum ath9k_pkt_type htype;
1337 __le16 fc;
1338
1339 hdr = (struct ieee80211_hdr *)skb->data;
1340 fc = hdr->frame_control;
1341
1342 if (ieee80211_is_beacon(fc))
1343 htype = ATH9K_PKT_TYPE_BEACON;
1344 else if (ieee80211_is_probe_resp(fc))
1345 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1346 else if (ieee80211_is_atim(fc))
1347 htype = ATH9K_PKT_TYPE_ATIM;
1348 else if (ieee80211_is_pspoll(fc))
1349 htype = ATH9K_PKT_TYPE_PSPOLL;
1350 else
1351 htype = ATH9K_PKT_TYPE_NORMAL;
1352
1353 return htype;
1354 }
1355
1356 static int get_hw_crypto_keytype(struct sk_buff *skb)
1357 {
1358 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1359
1360 if (tx_info->control.hw_key) {
1361 if (tx_info->control.hw_key->alg == ALG_WEP)
1362 return ATH9K_KEY_TYPE_WEP;
1363 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1364 return ATH9K_KEY_TYPE_TKIP;
1365 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1366 return ATH9K_KEY_TYPE_AES;
1367 }
1368
1369 return ATH9K_KEY_TYPE_CLEAR;
1370 }
1371
1372 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1373 struct ath_buf *bf)
1374 {
1375 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1376 struct ieee80211_hdr *hdr;
1377 struct ath_node *an;
1378 struct ath_atx_tid *tid;
1379 __le16 fc;
1380 u8 *qc;
1381
1382 if (!tx_info->control.sta)
1383 return;
1384
1385 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1386 hdr = (struct ieee80211_hdr *)skb->data;
1387 fc = hdr->frame_control;
1388
1389 if (ieee80211_is_data_qos(fc)) {
1390 qc = ieee80211_get_qos_ctl(hdr);
1391 bf->bf_tidno = qc[0] & 0xf;
1392 }
1393
1394 /*
1395 * For HT capable stations, we save tidno for later use.
1396 * We also override seqno set by upper layer with the one
1397 * in tx aggregation state.
1398 */
1399 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1400 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1401 bf->bf_seqno = tid->seq_next;
1402 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1403 }
1404
1405 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1406 struct ath_txq *txq)
1407 {
1408 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1409 int flags = 0;
1410
1411 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1412 flags |= ATH9K_TXDESC_INTREQ;
1413
1414 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1415 flags |= ATH9K_TXDESC_NOACK;
1416
1417 return flags;
1418 }
1419
1420 /*
1421 * rix - rate index
1422 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1423 * width - 0 for 20 MHz, 1 for 40 MHz
1424 * half_gi - to use 4us v/s 3.6 us for symbol time
1425 */
1426 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1427 int width, int half_gi, bool shortPreamble)
1428 {
1429 u32 nbits, nsymbits, duration, nsymbols;
1430 int streams, pktlen;
1431
1432 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1433
1434 /* find number of symbols: PLCP + data */
1435 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1436 nsymbits = bits_per_symbol[rix][width];
1437 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1438
1439 if (!half_gi)
1440 duration = SYMBOL_TIME(nsymbols);
1441 else
1442 duration = SYMBOL_TIME_HALFGI(nsymbols);
1443
1444 /* addup duration for legacy/ht training and signal fields */
1445 streams = HT_RC_2_STREAMS(rix);
1446 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1447
1448 return duration;
1449 }
1450
1451 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1452 {
1453 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1454 struct ath9k_11n_rate_series series[4];
1455 struct sk_buff *skb;
1456 struct ieee80211_tx_info *tx_info;
1457 struct ieee80211_tx_rate *rates;
1458 const struct ieee80211_rate *rate;
1459 struct ieee80211_hdr *hdr;
1460 int i, flags = 0;
1461 u8 rix = 0, ctsrate = 0;
1462 bool is_pspoll;
1463
1464 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1465
1466 skb = bf->bf_mpdu;
1467 tx_info = IEEE80211_SKB_CB(skb);
1468 rates = tx_info->control.rates;
1469 hdr = (struct ieee80211_hdr *)skb->data;
1470 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1471
1472 /*
1473 * We check if Short Preamble is needed for the CTS rate by
1474 * checking the BSS's global flag.
1475 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1476 */
1477 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1478 ctsrate = rate->hw_value;
1479 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1480 ctsrate |= rate->hw_value_short;
1481
1482 for (i = 0; i < 4; i++) {
1483 bool is_40, is_sgi, is_sp;
1484 int phy;
1485
1486 if (!rates[i].count || (rates[i].idx < 0))
1487 continue;
1488
1489 rix = rates[i].idx;
1490 series[i].Tries = rates[i].count;
1491 series[i].ChSel = common->tx_chainmask;
1492
1493 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1494 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1495 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1496 flags |= ATH9K_TXDESC_RTSENA;
1497 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1498 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1499 flags |= ATH9K_TXDESC_CTSENA;
1500 }
1501
1502 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1503 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1504 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1505 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1506
1507 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1508 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1509 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1510
1511 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1512 /* MCS rates */
1513 series[i].Rate = rix | 0x80;
1514 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1515 is_40, is_sgi, is_sp);
1516 continue;
1517 }
1518
1519 /* legcay rates */
1520 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1521 !(rate->flags & IEEE80211_RATE_ERP_G))
1522 phy = WLAN_RC_PHY_CCK;
1523 else
1524 phy = WLAN_RC_PHY_OFDM;
1525
1526 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1527 series[i].Rate = rate->hw_value;
1528 if (rate->hw_value_short) {
1529 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1530 series[i].Rate |= rate->hw_value_short;
1531 } else {
1532 is_sp = false;
1533 }
1534
1535 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1536 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1537 }
1538
1539 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1540 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1541 flags &= ~ATH9K_TXDESC_RTSENA;
1542
1543 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1544 if (flags & ATH9K_TXDESC_RTSENA)
1545 flags &= ~ATH9K_TXDESC_CTSENA;
1546
1547 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1548 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1549 bf->bf_lastbf->bf_desc,
1550 !is_pspoll, ctsrate,
1551 0, series, 4, flags);
1552
1553 if (sc->config.ath_aggr_prot && flags)
1554 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1555 }
1556
1557 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1558 struct sk_buff *skb,
1559 struct ath_tx_control *txctl)
1560 {
1561 struct ath_wiphy *aphy = hw->priv;
1562 struct ath_softc *sc = aphy->sc;
1563 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1564 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1565 int hdrlen;
1566 __le16 fc;
1567 int padpos, padsize;
1568
1569 tx_info->pad[0] = 0;
1570 switch (txctl->frame_type) {
1571 case ATH9K_NOT_INTERNAL:
1572 break;
1573 case ATH9K_INT_PAUSE:
1574 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1575 /* fall through */
1576 case ATH9K_INT_UNPAUSE:
1577 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1578 break;
1579 }
1580 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1581 fc = hdr->frame_control;
1582
1583 ATH_TXBUF_RESET(bf);
1584
1585 bf->aphy = aphy;
1586 bf->bf_frmlen = skb->len + FCS_LEN;
1587 /* Remove the padding size from bf_frmlen, if any */
1588 padpos = ath9k_cmn_padpos(hdr->frame_control);
1589 padsize = padpos & 3;
1590 if (padsize && skb->len>padpos+padsize) {
1591 bf->bf_frmlen -= padsize;
1592 }
1593
1594 if (conf_is_ht(&hw->conf))
1595 bf->bf_state.bf_type |= BUF_HT;
1596
1597 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1598
1599 bf->bf_keytype = get_hw_crypto_keytype(skb);
1600 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1601 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1602 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1603 } else {
1604 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1605 }
1606
1607 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1608 (sc->sc_flags & SC_OP_TXAGGR))
1609 assign_aggr_tid_seqno(skb, bf);
1610
1611 bf->bf_mpdu = skb;
1612
1613 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1614 skb->len, DMA_TO_DEVICE);
1615 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1616 bf->bf_mpdu = NULL;
1617 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1618 "dma_mapping_error() on TX\n");
1619 return -ENOMEM;
1620 }
1621
1622 bf->bf_buf_addr = bf->bf_dmacontext;
1623
1624 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1625 if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
1626 bf->bf_isnullfunc = true;
1627 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1628 } else
1629 bf->bf_isnullfunc = false;
1630
1631 return 0;
1632 }
1633
1634 /* FIXME: tx power */
1635 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1636 struct ath_tx_control *txctl)
1637 {
1638 struct sk_buff *skb = bf->bf_mpdu;
1639 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1640 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1641 struct ath_node *an = NULL;
1642 struct list_head bf_head;
1643 struct ath_desc *ds;
1644 struct ath_atx_tid *tid;
1645 struct ath_hw *ah = sc->sc_ah;
1646 int frm_type;
1647 __le16 fc;
1648
1649 frm_type = get_hw_packet_type(skb);
1650 fc = hdr->frame_control;
1651
1652 INIT_LIST_HEAD(&bf_head);
1653 list_add_tail(&bf->list, &bf_head);
1654
1655 ds = bf->bf_desc;
1656 ds->ds_link = 0;
1657 ds->ds_data = bf->bf_buf_addr;
1658
1659 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1660 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1661
1662 ath9k_hw_filltxdesc(ah, ds,
1663 skb->len, /* segment length */
1664 true, /* first segment */
1665 true, /* last segment */
1666 ds); /* first descriptor */
1667
1668 spin_lock_bh(&txctl->txq->axq_lock);
1669
1670 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1671 tx_info->control.sta) {
1672 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1673 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1674
1675 if (!ieee80211_is_data_qos(fc)) {
1676 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1677 goto tx_done;
1678 }
1679
1680 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1681 /*
1682 * Try aggregation if it's a unicast data frame
1683 * and the destination is HT capable.
1684 */
1685 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1686 } else {
1687 /*
1688 * Send this frame as regular when ADDBA
1689 * exchange is neither complete nor pending.
1690 */
1691 ath_tx_send_ht_normal(sc, txctl->txq,
1692 tid, &bf_head);
1693 }
1694 } else {
1695 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1696 }
1697
1698 tx_done:
1699 spin_unlock_bh(&txctl->txq->axq_lock);
1700 }
1701
1702 /* Upon failure caller should free skb */
1703 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1704 struct ath_tx_control *txctl)
1705 {
1706 struct ath_wiphy *aphy = hw->priv;
1707 struct ath_softc *sc = aphy->sc;
1708 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1709 struct ath_buf *bf;
1710 int r;
1711
1712 bf = ath_tx_get_buffer(sc);
1713 if (!bf) {
1714 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1715 return -1;
1716 }
1717
1718 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1719 if (unlikely(r)) {
1720 struct ath_txq *txq = txctl->txq;
1721
1722 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1723
1724 /* upon ath_tx_processq() this TX queue will be resumed, we
1725 * guarantee this will happen by knowing beforehand that
1726 * we will at least have to run TX completionon one buffer
1727 * on the queue */
1728 spin_lock_bh(&txq->axq_lock);
1729 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1730 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1731 txq->stopped = 1;
1732 }
1733 spin_unlock_bh(&txq->axq_lock);
1734
1735 spin_lock_bh(&sc->tx.txbuflock);
1736 list_add_tail(&bf->list, &sc->tx.txbuf);
1737 spin_unlock_bh(&sc->tx.txbuflock);
1738
1739 return r;
1740 }
1741
1742 ath_tx_start_dma(sc, bf, txctl);
1743
1744 return 0;
1745 }
1746
1747 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1748 {
1749 struct ath_wiphy *aphy = hw->priv;
1750 struct ath_softc *sc = aphy->sc;
1751 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1752 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1753 int padpos, padsize;
1754 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1755 struct ath_tx_control txctl;
1756
1757 memset(&txctl, 0, sizeof(struct ath_tx_control));
1758
1759 /*
1760 * As a temporary workaround, assign seq# here; this will likely need
1761 * to be cleaned up to work better with Beacon transmission and virtual
1762 * BSSes.
1763 */
1764 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1765 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1766 sc->tx.seq_no += 0x10;
1767 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1768 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1769 }
1770
1771 /* Add the padding after the header if this is not already done */
1772 padpos = ath9k_cmn_padpos(hdr->frame_control);
1773 padsize = padpos & 3;
1774 if (padsize && skb->len>padpos) {
1775 if (skb_headroom(skb) < padsize) {
1776 ath_print(common, ATH_DBG_XMIT,
1777 "TX CABQ padding failed\n");
1778 dev_kfree_skb_any(skb);
1779 return;
1780 }
1781 skb_push(skb, padsize);
1782 memmove(skb->data, skb->data + padsize, padpos);
1783 }
1784
1785 txctl.txq = sc->beacon.cabq;
1786
1787 ath_print(common, ATH_DBG_XMIT,
1788 "transmitting CABQ packet, skb: %p\n", skb);
1789
1790 if (ath_tx_start(hw, skb, &txctl) != 0) {
1791 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1792 goto exit;
1793 }
1794
1795 return;
1796 exit:
1797 dev_kfree_skb_any(skb);
1798 }
1799
1800 /*****************/
1801 /* TX Completion */
1802 /*****************/
1803
1804 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1805 struct ath_wiphy *aphy, int tx_flags)
1806 {
1807 struct ieee80211_hw *hw = sc->hw;
1808 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1809 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1810 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1811 int padpos, padsize;
1812
1813 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1814
1815 if (aphy)
1816 hw = aphy->hw;
1817
1818 if (tx_flags & ATH_TX_BAR)
1819 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1820
1821 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1822 /* Frame was ACKed */
1823 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1824 }
1825
1826 padpos = ath9k_cmn_padpos(hdr->frame_control);
1827 padsize = padpos & 3;
1828 if (padsize && skb->len>padpos+padsize) {
1829 /*
1830 * Remove MAC header padding before giving the frame back to
1831 * mac80211.
1832 */
1833 memmove(skb->data + padsize, skb->data, padpos);
1834 skb_pull(skb, padsize);
1835 }
1836
1837 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1838 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1839 ath_print(common, ATH_DBG_PS,
1840 "Going back to sleep after having "
1841 "received TX status (0x%lx)\n",
1842 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1843 PS_WAIT_FOR_CAB |
1844 PS_WAIT_FOR_PSPOLL_DATA |
1845 PS_WAIT_FOR_TX_ACK));
1846 }
1847
1848 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1849 ath9k_tx_status(hw, skb);
1850 else
1851 ieee80211_tx_status(hw, skb);
1852 }
1853
1854 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1855 struct ath_txq *txq,
1856 struct list_head *bf_q,
1857 int txok, int sendbar)
1858 {
1859 struct sk_buff *skb = bf->bf_mpdu;
1860 unsigned long flags;
1861 int tx_flags = 0;
1862
1863 if (sendbar)
1864 tx_flags = ATH_TX_BAR;
1865
1866 if (!txok) {
1867 tx_flags |= ATH_TX_ERROR;
1868
1869 if (bf_isxretried(bf))
1870 tx_flags |= ATH_TX_XRETRY;
1871 }
1872
1873 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1874 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1875 ath_debug_stat_tx(sc, txq, bf);
1876
1877 /*
1878 * Return the list of ath_buf of this mpdu to free queue
1879 */
1880 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1881 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1882 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1883 }
1884
1885 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1886 int txok)
1887 {
1888 struct ath_buf *bf_last = bf->bf_lastbf;
1889 struct ath_desc *ds = bf_last->bf_desc;
1890 u16 seq_st = 0;
1891 u32 ba[WME_BA_BMP_SIZE >> 5];
1892 int ba_index;
1893 int nbad = 0;
1894 int isaggr = 0;
1895
1896 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1897 return 0;
1898
1899 isaggr = bf_isaggr(bf);
1900 if (isaggr) {
1901 seq_st = ATH_DS_BA_SEQ(ds);
1902 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1903 }
1904
1905 while (bf) {
1906 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1907 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1908 nbad++;
1909
1910 bf = bf->bf_next;
1911 }
1912
1913 return nbad;
1914 }
1915
1916 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1917 int nbad, int txok, bool update_rc)
1918 {
1919 struct sk_buff *skb = bf->bf_mpdu;
1920 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1921 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1922 struct ieee80211_hw *hw = bf->aphy->hw;
1923 u8 i, tx_rateindex;
1924
1925 if (txok)
1926 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1927
1928 tx_rateindex = ds->ds_txstat.ts_rateindex;
1929 WARN_ON(tx_rateindex >= hw->max_rates);
1930
1931 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1932 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1933 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc)
1934 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1935
1936 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1937 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1938 if (ieee80211_is_data(hdr->frame_control)) {
1939 if (ds->ds_txstat.ts_flags &
1940 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
1941 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
1942 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) ||
1943 (ds->ds_txstat.ts_status & ATH9K_TXERR_FIFO))
1944 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
1945 tx_info->status.ampdu_len = bf->bf_nframes;
1946 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
1947 }
1948 }
1949
1950 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1951 tx_info->status.rates[i].count = 0;
1952 tx_info->status.rates[i].idx = -1;
1953 }
1954
1955 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1956 }
1957
1958 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1959 {
1960 int qnum;
1961
1962 spin_lock_bh(&txq->axq_lock);
1963 if (txq->stopped &&
1964 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1965 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1966 if (qnum != -1) {
1967 ath_mac80211_start_queue(sc, qnum);
1968 txq->stopped = 0;
1969 }
1970 }
1971 spin_unlock_bh(&txq->axq_lock);
1972 }
1973
1974 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1975 {
1976 struct ath_hw *ah = sc->sc_ah;
1977 struct ath_common *common = ath9k_hw_common(ah);
1978 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1979 struct list_head bf_head;
1980 struct ath_desc *ds;
1981 int txok;
1982 int status;
1983
1984 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1985 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1986 txq->axq_link);
1987
1988 for (;;) {
1989 spin_lock_bh(&txq->axq_lock);
1990 if (list_empty(&txq->axq_q)) {
1991 txq->axq_link = NULL;
1992 spin_unlock_bh(&txq->axq_lock);
1993 break;
1994 }
1995 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1996
1997 /*
1998 * There is a race condition that a BH gets scheduled
1999 * after sw writes TxE and before hw re-load the last
2000 * descriptor to get the newly chained one.
2001 * Software must keep the last DONE descriptor as a
2002 * holding descriptor - software does so by marking
2003 * it with the STALE flag.
2004 */
2005 bf_held = NULL;
2006 if (bf->bf_stale) {
2007 bf_held = bf;
2008 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2009 spin_unlock_bh(&txq->axq_lock);
2010 break;
2011 } else {
2012 bf = list_entry(bf_held->list.next,
2013 struct ath_buf, list);
2014 }
2015 }
2016
2017 lastbf = bf->bf_lastbf;
2018 ds = lastbf->bf_desc;
2019
2020 status = ath9k_hw_txprocdesc(ah, ds);
2021 if (status == -EINPROGRESS) {
2022 spin_unlock_bh(&txq->axq_lock);
2023 break;
2024 }
2025
2026 /*
2027 * We now know the nullfunc frame has been ACKed so we
2028 * can disable RX.
2029 */
2030 if (bf->bf_isnullfunc &&
2031 (ds->ds_txstat.ts_status & ATH9K_TX_ACKED)) {
2032 if ((sc->ps_flags & PS_ENABLED))
2033 ath9k_enable_ps(sc);
2034 else
2035 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2036 }
2037
2038 /*
2039 * Remove ath_buf's of the same transmit unit from txq,
2040 * however leave the last descriptor back as the holding
2041 * descriptor for hw.
2042 */
2043 lastbf->bf_stale = true;
2044 INIT_LIST_HEAD(&bf_head);
2045 if (!list_is_singular(&lastbf->list))
2046 list_cut_position(&bf_head,
2047 &txq->axq_q, lastbf->list.prev);
2048
2049 txq->axq_depth--;
2050 txok = !(ds->ds_txstat.ts_status & ATH9K_TXERR_MASK);
2051 txq->axq_tx_inprogress = false;
2052 spin_unlock_bh(&txq->axq_lock);
2053
2054 if (bf_held) {
2055 spin_lock_bh(&sc->tx.txbuflock);
2056 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2057 spin_unlock_bh(&sc->tx.txbuflock);
2058 }
2059
2060 if (!bf_isampdu(bf)) {
2061 /*
2062 * This frame is sent out as a single frame.
2063 * Use hardware retry status for this frame.
2064 */
2065 bf->bf_retries = ds->ds_txstat.ts_longretry;
2066 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2067 bf->bf_state.bf_type |= BUF_XRETRY;
2068 ath_tx_rc_status(bf, ds, 0, txok, true);
2069 }
2070
2071 if (bf_isampdu(bf))
2072 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2073 else
2074 ath_tx_complete_buf(sc, bf, txq, &bf_head, txok, 0);
2075
2076 ath_wake_mac80211_queue(sc, txq);
2077
2078 spin_lock_bh(&txq->axq_lock);
2079 if (sc->sc_flags & SC_OP_TXAGGR)
2080 ath_txq_schedule(sc, txq);
2081 spin_unlock_bh(&txq->axq_lock);
2082 }
2083 }
2084
2085 static void ath_tx_complete_poll_work(struct work_struct *work)
2086 {
2087 struct ath_softc *sc = container_of(work, struct ath_softc,
2088 tx_complete_work.work);
2089 struct ath_txq *txq;
2090 int i;
2091 bool needreset = false;
2092
2093 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2094 if (ATH_TXQ_SETUP(sc, i)) {
2095 txq = &sc->tx.txq[i];
2096 spin_lock_bh(&txq->axq_lock);
2097 if (txq->axq_depth) {
2098 if (txq->axq_tx_inprogress) {
2099 needreset = true;
2100 spin_unlock_bh(&txq->axq_lock);
2101 break;
2102 } else {
2103 txq->axq_tx_inprogress = true;
2104 }
2105 }
2106 spin_unlock_bh(&txq->axq_lock);
2107 }
2108
2109 if (needreset) {
2110 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2111 "tx hung, resetting the chip\n");
2112 ath9k_ps_wakeup(sc);
2113 ath_reset(sc, false);
2114 ath9k_ps_restore(sc);
2115 }
2116
2117 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2118 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2119 }
2120
2121
2122
2123 void ath_tx_tasklet(struct ath_softc *sc)
2124 {
2125 int i;
2126 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2127
2128 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2129
2130 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2131 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2132 ath_tx_processq(sc, &sc->tx.txq[i]);
2133 }
2134 }
2135
2136 /*****************/
2137 /* Init, Cleanup */
2138 /*****************/
2139
2140 int ath_tx_init(struct ath_softc *sc, int nbufs)
2141 {
2142 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2143 int error = 0;
2144
2145 spin_lock_init(&sc->tx.txbuflock);
2146
2147 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2148 "tx", nbufs, 1);
2149 if (error != 0) {
2150 ath_print(common, ATH_DBG_FATAL,
2151 "Failed to allocate tx descriptors: %d\n", error);
2152 goto err;
2153 }
2154
2155 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2156 "beacon", ATH_BCBUF, 1);
2157 if (error != 0) {
2158 ath_print(common, ATH_DBG_FATAL,
2159 "Failed to allocate beacon descriptors: %d\n", error);
2160 goto err;
2161 }
2162
2163 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2164
2165 err:
2166 if (error != 0)
2167 ath_tx_cleanup(sc);
2168
2169 return error;
2170 }
2171
2172 void ath_tx_cleanup(struct ath_softc *sc)
2173 {
2174 if (sc->beacon.bdma.dd_desc_len != 0)
2175 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2176
2177 if (sc->tx.txdma.dd_desc_len != 0)
2178 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2179 }
2180
2181 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2182 {
2183 struct ath_atx_tid *tid;
2184 struct ath_atx_ac *ac;
2185 int tidno, acno;
2186
2187 for (tidno = 0, tid = &an->tid[tidno];
2188 tidno < WME_NUM_TID;
2189 tidno++, tid++) {
2190 tid->an = an;
2191 tid->tidno = tidno;
2192 tid->seq_start = tid->seq_next = 0;
2193 tid->baw_size = WME_MAX_BA;
2194 tid->baw_head = tid->baw_tail = 0;
2195 tid->sched = false;
2196 tid->paused = false;
2197 tid->state &= ~AGGR_CLEANUP;
2198 INIT_LIST_HEAD(&tid->buf_q);
2199 acno = TID_TO_WME_AC(tidno);
2200 tid->ac = &an->ac[acno];
2201 tid->state &= ~AGGR_ADDBA_COMPLETE;
2202 tid->state &= ~AGGR_ADDBA_PROGRESS;
2203 }
2204
2205 for (acno = 0, ac = &an->ac[acno];
2206 acno < WME_NUM_AC; acno++, ac++) {
2207 ac->sched = false;
2208 INIT_LIST_HEAD(&ac->tid_q);
2209
2210 switch (acno) {
2211 case WME_AC_BE:
2212 ac->qnum = ath_tx_get_qnum(sc,
2213 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2214 break;
2215 case WME_AC_BK:
2216 ac->qnum = ath_tx_get_qnum(sc,
2217 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2218 break;
2219 case WME_AC_VI:
2220 ac->qnum = ath_tx_get_qnum(sc,
2221 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2222 break;
2223 case WME_AC_VO:
2224 ac->qnum = ath_tx_get_qnum(sc,
2225 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2226 break;
2227 }
2228 }
2229 }
2230
2231 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2232 {
2233 int i;
2234 struct ath_atx_ac *ac, *ac_tmp;
2235 struct ath_atx_tid *tid, *tid_tmp;
2236 struct ath_txq *txq;
2237
2238 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2239 if (ATH_TXQ_SETUP(sc, i)) {
2240 txq = &sc->tx.txq[i];
2241
2242 spin_lock_bh(&txq->axq_lock);
2243
2244 list_for_each_entry_safe(ac,
2245 ac_tmp, &txq->axq_acq, list) {
2246 tid = list_first_entry(&ac->tid_q,
2247 struct ath_atx_tid, list);
2248 if (tid && tid->an != an)
2249 continue;
2250 list_del(&ac->list);
2251 ac->sched = false;
2252
2253 list_for_each_entry_safe(tid,
2254 tid_tmp, &ac->tid_q, list) {
2255 list_del(&tid->list);
2256 tid->sched = false;
2257 ath_tid_drain(sc, txq, tid);
2258 tid->state &= ~AGGR_ADDBA_COMPLETE;
2259 tid->state &= ~AGGR_CLEANUP;
2260 }
2261 }
2262
2263 spin_unlock_bh(&txq->axq_lock);
2264 }
2265 }
2266 }
kernel-based virtual machine