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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6/kvm.git] / drivers / net / wireless / ath / ath5k / phy.c
bloba8adca62e527aa9734a888def15da196ce94370b
1 /*
2 * PHY functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 #include <linux/delay.h>
24
25 #include "ath5k.h"
26 #include "reg.h"
27 #include "base.h"
28 #include "rfbuffer.h"
29 #include "rfgain.h"
30
31 /*
32 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
33 */
34 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
35 const struct ath5k_rf_reg *rf_regs,
36 u32 val, u8 reg_id, bool set)
37 {
38 const struct ath5k_rf_reg *rfreg = NULL;
39 u8 offset, bank, num_bits, col, position;
40 u16 entry;
41 u32 mask, data, last_bit, bits_shifted, first_bit;
42 u32 *rfb;
43 s32 bits_left;
44 int i;
45
46 data = 0;
47 rfb = ah->ah_rf_banks;
48
49 for (i = 0; i < ah->ah_rf_regs_count; i++) {
50 if (rf_regs[i].index == reg_id) {
51 rfreg = &rf_regs[i];
52 break;
53 }
54 }
55
56 if (rfb == NULL || rfreg == NULL) {
57 ATH5K_PRINTF("Rf register not found!\n");
58 /* should not happen */
59 return 0;
60 }
61
62 bank = rfreg->bank;
63 num_bits = rfreg->field.len;
64 first_bit = rfreg->field.pos;
65 col = rfreg->field.col;
66
67 /* first_bit is an offset from bank's
68 * start. Since we have all banks on
69 * the same array, we use this offset
70 * to mark each bank's start */
71 offset = ah->ah_offset[bank];
72
73 /* Boundary check */
74 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
75 ATH5K_PRINTF("invalid values at offset %u\n", offset);
76 return 0;
77 }
78
79 entry = ((first_bit - 1) / 8) + offset;
80 position = (first_bit - 1) % 8;
81
82 if (set)
83 data = ath5k_hw_bitswap(val, num_bits);
84
85 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
86 position = 0, entry++) {
87
88 last_bit = (position + bits_left > 8) ? 8 :
89 position + bits_left;
90
91 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
92 (col * 8);
93
94 if (set) {
95 rfb[entry] &= ~mask;
96 rfb[entry] |= ((data << position) << (col * 8)) & mask;
97 data >>= (8 - position);
98 } else {
99 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
100 << bits_shifted;
101 bits_shifted += last_bit - position;
102 }
103
104 bits_left -= 8 - position;
105 }
106
107 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
108
109 return data;
110 }
111
112 /**********************\
113 * RF Gain optimization *
114 \**********************/
115
116 /*
117 * This code is used to optimize rf gain on different environments
118 * (temperature mostly) based on feedback from a power detector.
119 *
120 * It's only used on RF5111 and RF5112, later RF chips seem to have
121 * auto adjustment on hw -notice they have a much smaller BANK 7 and
122 * no gain optimization ladder-.
123 *
124 * For more infos check out this patent doc
125 * http://www.freepatentsonline.com/7400691.html
126 *
127 * This paper describes power drops as seen on the receiver due to
128 * probe packets
129 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
130 * %20of%20Power%20Control.pdf
131 *
132 * And this is the MadWiFi bug entry related to the above
133 * http://madwifi-project.org/ticket/1659
134 * with various measurements and diagrams
135 *
136 * TODO: Deal with power drops due to probes by setting an apropriate
137 * tx power on the probe packets ! Make this part of the calibration process.
138 */
139
140 /* Initialize ah_gain durring attach */
141 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
142 {
143 /* Initialize the gain optimization values */
144 switch (ah->ah_radio) {
145 case AR5K_RF5111:
146 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
147 ah->ah_gain.g_low = 20;
148 ah->ah_gain.g_high = 35;
149 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
150 break;
151 case AR5K_RF5112:
152 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
153 ah->ah_gain.g_low = 20;
154 ah->ah_gain.g_high = 85;
155 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
156 break;
157 default:
158 return -EINVAL;
159 }
160
161 return 0;
162 }
163
164 /* Schedule a gain probe check on the next transmited packet.
165 * That means our next packet is going to be sent with lower
166 * tx power and a Peak to Average Power Detector (PAPD) will try
167 * to measure the gain.
168 *
169 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
170 * just after we enable the probe so that we don't mess with
171 * standard traffic ? Maybe it's time to use sw interrupts and
172 * a probe tasklet !!!
173 */
174 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
175 {
176
177 /* Skip if gain calibration is inactive or
178 * we already handle a probe request */
179 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
180 return;
181
182 /* Send the packet with 2dB below max power as
183 * patent doc suggest */
184 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
185 AR5K_PHY_PAPD_PROBE_TXPOWER) |
186 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
187
188 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
189
190 }
191
192 /* Calculate gain_F measurement correction
193 * based on the current step for RF5112 rev. 2 */
194 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
195 {
196 u32 mix, step;
197 u32 *rf;
198 const struct ath5k_gain_opt *go;
199 const struct ath5k_gain_opt_step *g_step;
200 const struct ath5k_rf_reg *rf_regs;
201
202 /* Only RF5112 Rev. 2 supports it */
203 if ((ah->ah_radio != AR5K_RF5112) ||
204 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
205 return 0;
206
207 go = &rfgain_opt_5112;
208 rf_regs = rf_regs_5112a;
209 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
210
211 g_step = &go->go_step[ah->ah_gain.g_step_idx];
212
213 if (ah->ah_rf_banks == NULL)
214 return 0;
215
216 rf = ah->ah_rf_banks;
217 ah->ah_gain.g_f_corr = 0;
218
219 /* No VGA (Variable Gain Amplifier) override, skip */
220 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
221 return 0;
222
223 /* Mix gain stepping */
224 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
225
226 /* Mix gain override */
227 mix = g_step->gos_param[0];
228
229 switch (mix) {
230 case 3:
231 ah->ah_gain.g_f_corr = step * 2;
232 break;
233 case 2:
234 ah->ah_gain.g_f_corr = (step - 5) * 2;
235 break;
236 case 1:
237 ah->ah_gain.g_f_corr = step;
238 break;
239 default:
240 ah->ah_gain.g_f_corr = 0;
241 break;
242 }
243
244 return ah->ah_gain.g_f_corr;
245 }
246
247 /* Check if current gain_F measurement is in the range of our
248 * power detector windows. If we get a measurement outside range
249 * we know it's not accurate (detectors can't measure anything outside
250 * their detection window) so we must ignore it */
251 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
252 {
253 const struct ath5k_rf_reg *rf_regs;
254 u32 step, mix_ovr, level[4];
255 u32 *rf;
256
257 if (ah->ah_rf_banks == NULL)
258 return false;
259
260 rf = ah->ah_rf_banks;
261
262 if (ah->ah_radio == AR5K_RF5111) {
263
264 rf_regs = rf_regs_5111;
265 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
266
267 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
268 false);
269
270 level[0] = 0;
271 level[1] = (step == 63) ? 50 : step + 4;
272 level[2] = (step != 63) ? 64 : level[0];
273 level[3] = level[2] + 50 ;
274
275 ah->ah_gain.g_high = level[3] -
276 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
277 ah->ah_gain.g_low = level[0] +
278 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
279 } else {
280
281 rf_regs = rf_regs_5112;
282 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
283
284 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
285 false);
286
287 level[0] = level[2] = 0;
288
289 if (mix_ovr == 1) {
290 level[1] = level[3] = 83;
291 } else {
292 level[1] = level[3] = 107;
293 ah->ah_gain.g_high = 55;
294 }
295 }
296
297 return (ah->ah_gain.g_current >= level[0] &&
298 ah->ah_gain.g_current <= level[1]) ||
299 (ah->ah_gain.g_current >= level[2] &&
300 ah->ah_gain.g_current <= level[3]);
301 }
302
303 /* Perform gain_F adjustment by choosing the right set
304 * of parameters from rf gain optimization ladder */
305 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
306 {
307 const struct ath5k_gain_opt *go;
308 const struct ath5k_gain_opt_step *g_step;
309 int ret = 0;
310
311 switch (ah->ah_radio) {
312 case AR5K_RF5111:
313 go = &rfgain_opt_5111;
314 break;
315 case AR5K_RF5112:
316 go = &rfgain_opt_5112;
317 break;
318 default:
319 return 0;
320 }
321
322 g_step = &go->go_step[ah->ah_gain.g_step_idx];
323
324 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
325
326 /* Reached maximum */
327 if (ah->ah_gain.g_step_idx == 0)
328 return -1;
329
330 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
331 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
332 ah->ah_gain.g_step_idx > 0;
333 g_step = &go->go_step[ah->ah_gain.g_step_idx])
334 ah->ah_gain.g_target -= 2 *
335 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
336 g_step->gos_gain);
337
338 ret = 1;
339 goto done;
340 }
341
342 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
343
344 /* Reached minimum */
345 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
346 return -2;
347
348 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
349 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
350 ah->ah_gain.g_step_idx < go->go_steps_count-1;
351 g_step = &go->go_step[ah->ah_gain.g_step_idx])
352 ah->ah_gain.g_target -= 2 *
353 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
354 g_step->gos_gain);
355
356 ret = 2;
357 goto done;
358 }
359
360 done:
361 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
362 "ret %d, gain step %u, current gain %u, target gain %u\n",
363 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
364 ah->ah_gain.g_target);
365
366 return ret;
367 }
368
369 /* Main callback for thermal rf gain calibration engine
370 * Check for a new gain reading and schedule an adjustment
371 * if needed.
372 *
373 * TODO: Use sw interrupt to schedule reset if gain_F needs
374 * adjustment */
375 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
376 {
377 u32 data, type;
378 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
379
380 ATH5K_TRACE(ah->ah_sc);
381
382 if (ah->ah_rf_banks == NULL ||
383 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
384 return AR5K_RFGAIN_INACTIVE;
385
386 /* No check requested, either engine is inactive
387 * or an adjustment is already requested */
388 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
389 goto done;
390
391 /* Read the PAPD (Peak to Average Power Detector)
392 * register */
393 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
394
395 /* No probe is scheduled, read gain_F measurement */
396 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
397 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
398 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
399
400 /* If tx packet is CCK correct the gain_F measurement
401 * by cck ofdm gain delta */
402 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
403 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
404 ah->ah_gain.g_current +=
405 ee->ee_cck_ofdm_gain_delta;
406 else
407 ah->ah_gain.g_current +=
408 AR5K_GAIN_CCK_PROBE_CORR;
409 }
410
411 /* Further correct gain_F measurement for
412 * RF5112A radios */
413 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
414 ath5k_hw_rf_gainf_corr(ah);
415 ah->ah_gain.g_current =
416 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
417 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
418 0;
419 }
420
421 /* Check if measurement is ok and if we need
422 * to adjust gain, schedule a gain adjustment,
423 * else switch back to the acive state */
424 if (ath5k_hw_rf_check_gainf_readback(ah) &&
425 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
426 ath5k_hw_rf_gainf_adjust(ah)) {
427 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
428 } else {
429 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
430 }
431 }
432
433 done:
434 return ah->ah_gain.g_state;
435 }
436
437 /* Write initial rf gain table to set the RF sensitivity
438 * this one works on all RF chips and has nothing to do
439 * with gain_F calibration */
440 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
441 {
442 const struct ath5k_ini_rfgain *ath5k_rfg;
443 unsigned int i, size;
444
445 switch (ah->ah_radio) {
446 case AR5K_RF5111:
447 ath5k_rfg = rfgain_5111;
448 size = ARRAY_SIZE(rfgain_5111);
449 break;
450 case AR5K_RF5112:
451 ath5k_rfg = rfgain_5112;
452 size = ARRAY_SIZE(rfgain_5112);
453 break;
454 case AR5K_RF2413:
455 ath5k_rfg = rfgain_2413;
456 size = ARRAY_SIZE(rfgain_2413);
457 break;
458 case AR5K_RF2316:
459 ath5k_rfg = rfgain_2316;
460 size = ARRAY_SIZE(rfgain_2316);
461 break;
462 case AR5K_RF5413:
463 ath5k_rfg = rfgain_5413;
464 size = ARRAY_SIZE(rfgain_5413);
465 break;
466 case AR5K_RF2317:
467 case AR5K_RF2425:
468 ath5k_rfg = rfgain_2425;
469 size = ARRAY_SIZE(rfgain_2425);
470 break;
471 default:
472 return -EINVAL;
473 }
474
475 switch (freq) {
476 case AR5K_INI_RFGAIN_2GHZ:
477 case AR5K_INI_RFGAIN_5GHZ:
478 break;
479 default:
480 return -EINVAL;
481 }
482
483 for (i = 0; i < size; i++) {
484 AR5K_REG_WAIT(i);
485 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
486 (u32)ath5k_rfg[i].rfg_register);
487 }
488
489 return 0;
490 }
491
492
493
494 /********************\
495 * RF Registers setup *
496 \********************/
497
498
499 /*
500 * Setup RF registers by writing rf buffer on hw
501 */
502 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
503 unsigned int mode)
504 {
505 const struct ath5k_rf_reg *rf_regs;
506 const struct ath5k_ini_rfbuffer *ini_rfb;
507 const struct ath5k_gain_opt *go = NULL;
508 const struct ath5k_gain_opt_step *g_step;
509 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
510 u8 ee_mode = 0;
511 u32 *rfb;
512 int i, obdb = -1, bank = -1;
513
514 switch (ah->ah_radio) {
515 case AR5K_RF5111:
516 rf_regs = rf_regs_5111;
517 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
518 ini_rfb = rfb_5111;
519 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
520 go = &rfgain_opt_5111;
521 break;
522 case AR5K_RF5112:
523 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
524 rf_regs = rf_regs_5112a;
525 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
526 ini_rfb = rfb_5112a;
527 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
528 } else {
529 rf_regs = rf_regs_5112;
530 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
531 ini_rfb = rfb_5112;
532 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
533 }
534 go = &rfgain_opt_5112;
535 break;
536 case AR5K_RF2413:
537 rf_regs = rf_regs_2413;
538 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
539 ini_rfb = rfb_2413;
540 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
541 break;
542 case AR5K_RF2316:
543 rf_regs = rf_regs_2316;
544 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
545 ini_rfb = rfb_2316;
546 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
547 break;
548 case AR5K_RF5413:
549 rf_regs = rf_regs_5413;
550 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
551 ini_rfb = rfb_5413;
552 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
553 break;
554 case AR5K_RF2317:
555 rf_regs = rf_regs_2425;
556 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
557 ini_rfb = rfb_2317;
558 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
559 break;
560 case AR5K_RF2425:
561 rf_regs = rf_regs_2425;
562 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
563 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
564 ini_rfb = rfb_2425;
565 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
566 } else {
567 ini_rfb = rfb_2417;
568 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
569 }
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 /* If it's the first time we set rf buffer, allocate
576 * ah->ah_rf_banks based on ah->ah_rf_banks_size
577 * we set above */
578 if (ah->ah_rf_banks == NULL) {
579 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
580 GFP_KERNEL);
581 if (ah->ah_rf_banks == NULL) {
582 ATH5K_ERR(ah->ah_sc, "out of memory\n");
583 return -ENOMEM;
584 }
585 }
586
587 /* Copy values to modify them */
588 rfb = ah->ah_rf_banks;
589
590 for (i = 0; i < ah->ah_rf_banks_size; i++) {
591 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
592 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
593 return -EINVAL;
594 }
595
596 /* Bank changed, write down the offset */
597 if (bank != ini_rfb[i].rfb_bank) {
598 bank = ini_rfb[i].rfb_bank;
599 ah->ah_offset[bank] = i;
600 }
601
602 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
603 }
604
605 /* Set Output and Driver bias current (OB/DB) */
606 if (channel->hw_value & CHANNEL_2GHZ) {
607
608 if (channel->hw_value & CHANNEL_CCK)
609 ee_mode = AR5K_EEPROM_MODE_11B;
610 else
611 ee_mode = AR5K_EEPROM_MODE_11G;
612
613 /* For RF511X/RF211X combination we
614 * use b_OB and b_DB parameters stored
615 * in eeprom on ee->ee_ob[ee_mode][0]
616 *
617 * For all other chips we use OB/DB for 2Ghz
618 * stored in the b/g modal section just like
619 * 802.11a on ee->ee_ob[ee_mode][1] */
620 if ((ah->ah_radio == AR5K_RF5111) ||
621 (ah->ah_radio == AR5K_RF5112))
622 obdb = 0;
623 else
624 obdb = 1;
625
626 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
627 AR5K_RF_OB_2GHZ, true);
628
629 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
630 AR5K_RF_DB_2GHZ, true);
631
632 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
633 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
634 (ah->ah_radio == AR5K_RF5111)) {
635
636 /* For 11a, Turbo and XR we need to choose
637 * OB/DB based on frequency range */
638 ee_mode = AR5K_EEPROM_MODE_11A;
639 obdb = channel->center_freq >= 5725 ? 3 :
640 (channel->center_freq >= 5500 ? 2 :
641 (channel->center_freq >= 5260 ? 1 :
642 (channel->center_freq > 4000 ? 0 : -1)));
643
644 if (obdb < 0)
645 return -EINVAL;
646
647 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
648 AR5K_RF_OB_5GHZ, true);
649
650 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
651 AR5K_RF_DB_5GHZ, true);
652 }
653
654 g_step = &go->go_step[ah->ah_gain.g_step_idx];
655
656 /* Bank Modifications (chip-specific) */
657 if (ah->ah_radio == AR5K_RF5111) {
658
659 /* Set gain_F settings according to current step */
660 if (channel->hw_value & CHANNEL_OFDM) {
661
662 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
663 AR5K_PHY_FRAME_CTL_TX_CLIP,
664 g_step->gos_param[0]);
665
666 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
667 AR5K_RF_PWD_90, true);
668
669 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
670 AR5K_RF_PWD_84, true);
671
672 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
673 AR5K_RF_RFGAIN_SEL, true);
674
675 /* We programmed gain_F parameters, switch back
676 * to active state */
677 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
678
679 }
680
681 /* Bank 6/7 setup */
682
683 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
684 AR5K_RF_PWD_XPD, true);
685
686 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
687 AR5K_RF_XPD_GAIN, true);
688
689 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
690 AR5K_RF_GAIN_I, true);
691
692 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
693 AR5K_RF_PLO_SEL, true);
694
695 /* TODO: Half/quarter channel support */
696 }
697
698 if (ah->ah_radio == AR5K_RF5112) {
699
700 /* Set gain_F settings according to current step */
701 if (channel->hw_value & CHANNEL_OFDM) {
702
703 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
704 AR5K_RF_MIXGAIN_OVR, true);
705
706 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
707 AR5K_RF_PWD_138, true);
708
709 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
710 AR5K_RF_PWD_137, true);
711
712 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
713 AR5K_RF_PWD_136, true);
714
715 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
716 AR5K_RF_PWD_132, true);
717
718 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
719 AR5K_RF_PWD_131, true);
720
721 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
722 AR5K_RF_PWD_130, true);
723
724 /* We programmed gain_F parameters, switch back
725 * to active state */
726 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
727 }
728
729 /* Bank 6/7 setup */
730
731 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
732 AR5K_RF_XPD_SEL, true);
733
734 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
735 /* Rev. 1 supports only one xpd */
736 ath5k_hw_rfb_op(ah, rf_regs,
737 ee->ee_x_gain[ee_mode],
738 AR5K_RF_XPD_GAIN, true);
739
740 } else {
741 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
742 if (ee->ee_pd_gains[ee_mode] > 1) {
743 ath5k_hw_rfb_op(ah, rf_regs,
744 pdg_curve_to_idx[0],
745 AR5K_RF_PD_GAIN_LO, true);
746 ath5k_hw_rfb_op(ah, rf_regs,
747 pdg_curve_to_idx[1],
748 AR5K_RF_PD_GAIN_HI, true);
749 } else {
750 ath5k_hw_rfb_op(ah, rf_regs,
751 pdg_curve_to_idx[0],
752 AR5K_RF_PD_GAIN_LO, true);
753 ath5k_hw_rfb_op(ah, rf_regs,
754 pdg_curve_to_idx[0],
755 AR5K_RF_PD_GAIN_HI, true);
756 }
757
758 /* Lower synth voltage on Rev 2 */
759 ath5k_hw_rfb_op(ah, rf_regs, 2,
760 AR5K_RF_HIGH_VC_CP, true);
761
762 ath5k_hw_rfb_op(ah, rf_regs, 2,
763 AR5K_RF_MID_VC_CP, true);
764
765 ath5k_hw_rfb_op(ah, rf_regs, 2,
766 AR5K_RF_LOW_VC_CP, true);
767
768 ath5k_hw_rfb_op(ah, rf_regs, 2,
769 AR5K_RF_PUSH_UP, true);
770
771 /* Decrease power consumption on 5213+ BaseBand */
772 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
773 ath5k_hw_rfb_op(ah, rf_regs, 1,
774 AR5K_RF_PAD2GND, true);
775
776 ath5k_hw_rfb_op(ah, rf_regs, 1,
777 AR5K_RF_XB2_LVL, true);
778
779 ath5k_hw_rfb_op(ah, rf_regs, 1,
780 AR5K_RF_XB5_LVL, true);
781
782 ath5k_hw_rfb_op(ah, rf_regs, 1,
783 AR5K_RF_PWD_167, true);
784
785 ath5k_hw_rfb_op(ah, rf_regs, 1,
786 AR5K_RF_PWD_166, true);
787 }
788 }
789
790 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
791 AR5K_RF_GAIN_I, true);
792
793 /* TODO: Half/quarter channel support */
794
795 }
796
797 if (ah->ah_radio == AR5K_RF5413 &&
798 channel->hw_value & CHANNEL_2GHZ) {
799
800 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
801 true);
802
803 /* Set optimum value for early revisions (on pci-e chips) */
804 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
805 ah->ah_mac_srev < AR5K_SREV_AR5413)
806 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
807 AR5K_RF_PWD_ICLOBUF_2G, true);
808
809 }
810
811 /* Write RF banks on hw */
812 for (i = 0; i < ah->ah_rf_banks_size; i++) {
813 AR5K_REG_WAIT(i);
814 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
815 }
816
817 return 0;
818 }
819
820
821 /**************************\
822 PHY/RF channel functions
823 \**************************/
824
825 /*
826 * Check if a channel is supported
827 */
828 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
829 {
830 /* Check if the channel is in our supported range */
831 if (flags & CHANNEL_2GHZ) {
832 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
833 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
834 return true;
835 } else if (flags & CHANNEL_5GHZ)
836 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
837 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
838 return true;
839
840 return false;
841 }
842
843 /*
844 * Convertion needed for RF5110
845 */
846 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
847 {
848 u32 athchan;
849
850 /*
851 * Convert IEEE channel/MHz to an internal channel value used
852 * by the AR5210 chipset. This has not been verified with
853 * newer chipsets like the AR5212A who have a completely
854 * different RF/PHY part.
855 */
856 athchan = (ath5k_hw_bitswap(
857 (ieee80211_frequency_to_channel(
858 channel->center_freq) - 24) / 2, 5)
859 << 1) | (1 << 6) | 0x1;
860 return athchan;
861 }
862
863 /*
864 * Set channel on RF5110
865 */
866 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
867 struct ieee80211_channel *channel)
868 {
869 u32 data;
870
871 /*
872 * Set the channel and wait
873 */
874 data = ath5k_hw_rf5110_chan2athchan(channel);
875 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
876 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
877 mdelay(1);
878
879 return 0;
880 }
881
882 /*
883 * Convertion needed for 5111
884 */
885 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
886 struct ath5k_athchan_2ghz *athchan)
887 {
888 int channel;
889
890 /* Cast this value to catch negative channel numbers (>= -19) */
891 channel = (int)ieee;
892
893 /*
894 * Map 2GHz IEEE channel to 5GHz Atheros channel
895 */
896 if (channel <= 13) {
897 athchan->a2_athchan = 115 + channel;
898 athchan->a2_flags = 0x46;
899 } else if (channel == 14) {
900 athchan->a2_athchan = 124;
901 athchan->a2_flags = 0x44;
902 } else if (channel >= 15 && channel <= 26) {
903 athchan->a2_athchan = ((channel - 14) * 4) + 132;
904 athchan->a2_flags = 0x46;
905 } else
906 return -EINVAL;
907
908 return 0;
909 }
910
911 /*
912 * Set channel on 5111
913 */
914 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
915 struct ieee80211_channel *channel)
916 {
917 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
918 unsigned int ath5k_channel =
919 ieee80211_frequency_to_channel(channel->center_freq);
920 u32 data0, data1, clock;
921 int ret;
922
923 /*
924 * Set the channel on the RF5111 radio
925 */
926 data0 = data1 = 0;
927
928 if (channel->hw_value & CHANNEL_2GHZ) {
929 /* Map 2GHz channel to 5GHz Atheros channel ID */
930 ret = ath5k_hw_rf5111_chan2athchan(
931 ieee80211_frequency_to_channel(channel->center_freq),
932 &ath5k_channel_2ghz);
933 if (ret)
934 return ret;
935
936 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
937 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
938 << 5) | (1 << 4);
939 }
940
941 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
942 clock = 1;
943 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
944 (clock << 1) | (1 << 10) | 1;
945 } else {
946 clock = 0;
947 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
948 << 2) | (clock << 1) | (1 << 10) | 1;
949 }
950
951 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
952 AR5K_RF_BUFFER);
953 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
954 AR5K_RF_BUFFER_CONTROL_3);
955
956 return 0;
957 }
958
959 /*
960 * Set channel on 5112 and newer
961 */
962 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
963 struct ieee80211_channel *channel)
964 {
965 u32 data, data0, data1, data2;
966 u16 c;
967
968 data = data0 = data1 = data2 = 0;
969 c = channel->center_freq;
970
971 if (c < 4800) {
972 if (!((c - 2224) % 5)) {
973 data0 = ((2 * (c - 704)) - 3040) / 10;
974 data1 = 1;
975 } else if (!((c - 2192) % 5)) {
976 data0 = ((2 * (c - 672)) - 3040) / 10;
977 data1 = 0;
978 } else
979 return -EINVAL;
980
981 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
982 } else if ((c - (c % 5)) != 2 || c > 5435) {
983 if (!(c % 20) && c >= 5120) {
984 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
985 data2 = ath5k_hw_bitswap(3, 2);
986 } else if (!(c % 10)) {
987 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
988 data2 = ath5k_hw_bitswap(2, 2);
989 } else if (!(c % 5)) {
990 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
991 data2 = ath5k_hw_bitswap(1, 2);
992 } else
993 return -EINVAL;
994 } else {
995 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
996 data2 = ath5k_hw_bitswap(0, 2);
997 }
998
999 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1000
1001 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1002 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1003
1004 return 0;
1005 }
1006
1007 /*
1008 * Set the channel on the RF2425
1009 */
1010 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1011 struct ieee80211_channel *channel)
1012 {
1013 u32 data, data0, data2;
1014 u16 c;
1015
1016 data = data0 = data2 = 0;
1017 c = channel->center_freq;
1018
1019 if (c < 4800) {
1020 data0 = ath5k_hw_bitswap((c - 2272), 8);
1021 data2 = 0;
1022 /* ? 5GHz ? */
1023 } else if ((c - (c % 5)) != 2 || c > 5435) {
1024 if (!(c % 20) && c < 5120)
1025 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1026 else if (!(c % 10))
1027 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1028 else if (!(c % 5))
1029 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1030 else
1031 return -EINVAL;
1032 data2 = ath5k_hw_bitswap(1, 2);
1033 } else {
1034 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1035 data2 = ath5k_hw_bitswap(0, 2);
1036 }
1037
1038 data = (data0 << 4) | data2 << 2 | 0x1001;
1039
1040 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1041 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1042
1043 return 0;
1044 }
1045
1046 /*
1047 * Set a channel on the radio chip
1048 */
1049 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1050 {
1051 int ret;
1052 /*
1053 * Check bounds supported by the PHY (we don't care about regultory
1054 * restrictions at this point). Note: hw_value already has the band
1055 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1056 * of the band by that */
1057 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1058 ATH5K_ERR(ah->ah_sc,
1059 "channel frequency (%u MHz) out of supported "
1060 "band range\n",
1061 channel->center_freq);
1062 return -EINVAL;
1063 }
1064
1065 /*
1066 * Set the channel and wait
1067 */
1068 switch (ah->ah_radio) {
1069 case AR5K_RF5110:
1070 ret = ath5k_hw_rf5110_channel(ah, channel);
1071 break;
1072 case AR5K_RF5111:
1073 ret = ath5k_hw_rf5111_channel(ah, channel);
1074 break;
1075 case AR5K_RF2425:
1076 ret = ath5k_hw_rf2425_channel(ah, channel);
1077 break;
1078 default:
1079 ret = ath5k_hw_rf5112_channel(ah, channel);
1080 break;
1081 }
1082
1083 if (ret)
1084 return ret;
1085
1086 /* Set JAPAN setting for channel 14 */
1087 if (channel->center_freq == 2484) {
1088 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1089 AR5K_PHY_CCKTXCTL_JAPAN);
1090 } else {
1091 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1092 AR5K_PHY_CCKTXCTL_WORLD);
1093 }
1094
1095 ah->ah_current_channel = channel;
1096 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1097
1098 return 0;
1099 }
1100
1101 /*****************\
1102 PHY calibration
1103 \*****************/
1104
1105 void
1106 ath5k_hw_calibration_poll(struct ath5k_hw *ah)
1107 {
1108 /* Calibration interval in jiffies */
1109 unsigned long cal_intval;
1110
1111 cal_intval = msecs_to_jiffies(ah->ah_cal_intval * 1000);
1112
1113 /* Initialize timestamp if needed */
1114 if (!ah->ah_cal_tstamp)
1115 ah->ah_cal_tstamp = jiffies;
1116
1117 /* For now we always do full calibration
1118 * Mark software interrupt mask and fire software
1119 * interrupt (bit gets auto-cleared) */
1120 if (time_is_before_eq_jiffies(ah->ah_cal_tstamp + cal_intval)) {
1121 ah->ah_cal_tstamp = jiffies;
1122 ah->ah_swi_mask = AR5K_SWI_FULL_CALIBRATION;
1123 AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI);
1124 }
1125 }
1126
1127 static int sign_extend(int val, const int nbits)
1128 {
1129 int order = BIT(nbits-1);
1130 return (val ^ order) - order;
1131 }
1132
1133 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1134 {
1135 s32 val;
1136
1137 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1138 return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
1139 }
1140
1141 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1142 {
1143 int i;
1144
1145 ah->ah_nfcal_hist.index = 0;
1146 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1147 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1148 }
1149
1150 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1151 {
1152 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1153 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1154 hist->nfval[hist->index] = noise_floor;
1155 }
1156
1157 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1158 {
1159 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1160 s16 tmp;
1161 int i, j;
1162
1163 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1164 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1165 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1166 if (sort[j] > sort[j-1]) {
1167 tmp = sort[j];
1168 sort[j] = sort[j-1];
1169 sort[j-1] = tmp;
1170 }
1171 }
1172 }
1173 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1174 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1175 "cal %d:%d\n", i, sort[i]);
1176 }
1177 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1178 }
1179
1180 /*
1181 * When we tell the hardware to perform a noise floor calibration
1182 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1183 * sample-and-hold the minimum noise level seen at the antennas.
1184 * This value is then stored in a ring buffer of recently measured
1185 * noise floor values so we have a moving window of the last few
1186 * samples.
1187 *
1188 * The median of the values in the history is then loaded into the
1189 * hardware for its own use for RSSI and CCA measurements.
1190 */
1191 static void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1192 {
1193 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1194 u32 val;
1195 s16 nf, threshold;
1196 u8 ee_mode;
1197
1198 /* keep last value if calibration hasn't completed */
1199 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1200 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1201 "NF did not complete in calibration window\n");
1202
1203 return;
1204 }
1205
1206 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1207 case CHANNEL_A:
1208 case CHANNEL_T:
1209 case CHANNEL_XR:
1210 ee_mode = AR5K_EEPROM_MODE_11A;
1211 break;
1212 case CHANNEL_G:
1213 case CHANNEL_TG:
1214 ee_mode = AR5K_EEPROM_MODE_11G;
1215 break;
1216 default:
1217 case CHANNEL_B:
1218 ee_mode = AR5K_EEPROM_MODE_11B;
1219 break;
1220 }
1221
1222
1223 /* completed NF calibration, test threshold */
1224 nf = ath5k_hw_read_measured_noise_floor(ah);
1225 threshold = ee->ee_noise_floor_thr[ee_mode];
1226
1227 if (nf > threshold) {
1228 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1229 "noise floor failure detected; "
1230 "read %d, threshold %d\n",
1231 nf, threshold);
1232
1233 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1234 }
1235
1236 ath5k_hw_update_nfcal_hist(ah, nf);
1237 nf = ath5k_hw_get_median_noise_floor(ah);
1238
1239 /* load noise floor (in .5 dBm) so the hardware will use it */
1240 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1241 val |= (nf * 2) & AR5K_PHY_NF_M;
1242 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1243
1244 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1245 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1246
1247 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1248 0, false);
1249
1250 /*
1251 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1252 * so that we're not capped by the median we just loaded.
1253 * This will be used as the initial value for the next noise
1254 * floor calibration.
1255 */
1256 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1257 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1258 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1259 AR5K_PHY_AGCCTL_NF_EN |
1260 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1261 AR5K_PHY_AGCCTL_NF);
1262
1263 ah->ah_noise_floor = nf;
1264
1265 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1266 "noise floor calibrated: %d\n", nf);
1267 }
1268
1269 /*
1270 * Perform a PHY calibration on RF5110
1271 * -Fix BPSK/QAM Constellation (I/Q correction)
1272 * -Calculate Noise Floor
1273 */
1274 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1275 struct ieee80211_channel *channel)
1276 {
1277 u32 phy_sig, phy_agc, phy_sat, beacon;
1278 int ret;
1279
1280 /*
1281 * Disable beacons and RX/TX queues, wait
1282 */
1283 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1284 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1285 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1286 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1287
1288 mdelay(2);
1289
1290 /*
1291 * Set the channel (with AGC turned off)
1292 */
1293 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1294 udelay(10);
1295 ret = ath5k_hw_channel(ah, channel);
1296
1297 /*
1298 * Activate PHY and wait
1299 */
1300 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1301 mdelay(1);
1302
1303 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1304
1305 if (ret)
1306 return ret;
1307
1308 /*
1309 * Calibrate the radio chip
1310 */
1311
1312 /* Remember normal state */
1313 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1314 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1315 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1316
1317 /* Update radio registers */
1318 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1319 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1320
1321 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1322 AR5K_PHY_AGCCOARSE_LO)) |
1323 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1324 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1325
1326 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1327 AR5K_PHY_ADCSAT_THR)) |
1328 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1329 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1330
1331 udelay(20);
1332
1333 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1334 udelay(10);
1335 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1336 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1337
1338 mdelay(1);
1339
1340 /*
1341 * Enable calibration and wait until completion
1342 */
1343 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1344
1345 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1346 AR5K_PHY_AGCCTL_CAL, 0, false);
1347
1348 /* Reset to normal state */
1349 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1350 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1351 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1352
1353 if (ret) {
1354 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1355 channel->center_freq);
1356 return ret;
1357 }
1358
1359 ath5k_hw_update_noise_floor(ah);
1360
1361 /*
1362 * Re-enable RX/TX and beacons
1363 */
1364 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1365 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1366 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1367
1368 return 0;
1369 }
1370
1371 /*
1372 * Perform a PHY calibration on RF5111/5112 and newer chips
1373 */
1374 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1375 struct ieee80211_channel *channel)
1376 {
1377 u32 i_pwr, q_pwr;
1378 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1379 int i;
1380 ATH5K_TRACE(ah->ah_sc);
1381
1382 if (!ah->ah_calibration ||
1383 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1384 goto done;
1385
1386 /* Calibration has finished, get the results and re-run */
1387
1388 /* work around empty results which can apparently happen on 5212 */
1389 for (i = 0; i <= 10; i++) {
1390 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1391 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1392 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1393 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1394 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1395 if (i_pwr && q_pwr)
1396 break;
1397 }
1398
1399 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1400
1401 if (ah->ah_version == AR5K_AR5211)
1402 q_coffd = q_pwr >> 6;
1403 else
1404 q_coffd = q_pwr >> 7;
1405
1406 /* protect against divide by 0 and loss of sign bits */
1407 if (i_coffd == 0 || q_coffd < 2)
1408 goto done;
1409
1410 i_coff = (-iq_corr) / i_coffd;
1411 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1412
1413 q_coff = (i_pwr / q_coffd) - 128;
1414 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1415
1416 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1417 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1418 i_coff, q_coff, i_coffd, q_coffd);
1419
1420 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1421 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1422 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1423 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1424
1425 /* Re-enable calibration -if we don't we'll commit
1426 * the same values again and again */
1427 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1428 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1429 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1430
1431 done:
1432
1433 /* TODO: Separate noise floor calibration from I/Q calibration
1434 * since noise floor calibration interrupts rx path while I/Q
1435 * calibration doesn't. We don't need to run noise floor calibration
1436 * as often as I/Q calibration.*/
1437 ath5k_hw_update_noise_floor(ah);
1438
1439 /* Initiate a gain_F calibration */
1440 ath5k_hw_request_rfgain_probe(ah);
1441
1442 return 0;
1443 }
1444
1445 /*
1446 * Perform a PHY calibration
1447 */
1448 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1449 struct ieee80211_channel *channel)
1450 {
1451 int ret;
1452
1453 if (ah->ah_radio == AR5K_RF5110)
1454 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1455 else
1456 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1457
1458 return ret;
1459 }
1460
1461 /***************************\
1462 * Spur mitigation functions *
1463 \***************************/
1464
1465 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1466 struct ieee80211_channel *channel)
1467 {
1468 u8 refclk_freq;
1469
1470 if ((ah->ah_radio == AR5K_RF5112) ||
1471 (ah->ah_radio == AR5K_RF5413) ||
1472 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1473 refclk_freq = 40;
1474 else
1475 refclk_freq = 32;
1476
1477 if ((channel->center_freq % refclk_freq != 0) &&
1478 ((channel->center_freq % refclk_freq < 10) ||
1479 (channel->center_freq % refclk_freq > 22)))
1480 return true;
1481 else
1482 return false;
1483 }
1484
1485 void
1486 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1487 struct ieee80211_channel *channel)
1488 {
1489 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1490 u32 mag_mask[4] = {0, 0, 0, 0};
1491 u32 pilot_mask[2] = {0, 0};
1492 /* Note: fbin values are scaled up by 2 */
1493 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1494 s32 spur_delta_phase, spur_freq_sigma_delta;
1495 s32 spur_offset, num_symbols_x16;
1496 u8 num_symbol_offsets, i, freq_band;
1497
1498 /* Convert current frequency to fbin value (the same way channels
1499 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1500 * up by 2 so we can compare it later */
1501 if (channel->hw_value & CHANNEL_2GHZ) {
1502 chan_fbin = (channel->center_freq - 2300) * 10;
1503 freq_band = AR5K_EEPROM_BAND_2GHZ;
1504 } else {
1505 chan_fbin = (channel->center_freq - 4900) * 10;
1506 freq_band = AR5K_EEPROM_BAND_5GHZ;
1507 }
1508
1509 /* Check if any spur_chan_fbin from EEPROM is
1510 * within our current channel's spur detection range */
1511 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1512 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1513 /* XXX: Half/Quarter channels ?*/
1514 if (channel->hw_value & CHANNEL_TURBO)
1515 spur_detection_window *= 2;
1516
1517 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1518 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1519
1520 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1521 * so it's zero if we got nothing from EEPROM */
1522 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1523 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1524 break;
1525 }
1526
1527 if ((chan_fbin - spur_detection_window <=
1528 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1529 (chan_fbin + spur_detection_window >=
1530 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1531 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1532 break;
1533 }
1534 }
1535
1536 /* We need to enable spur filter for this channel */
1537 if (spur_chan_fbin) {
1538 spur_offset = spur_chan_fbin - chan_fbin;
1539 /*
1540 * Calculate deltas:
1541 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1542 * spur_delta_phase -> spur_offset / chip_freq << 11
1543 * Note: Both values have 100KHz resolution
1544 */
1545 /* XXX: Half/Quarter rate channels ? */
1546 switch (channel->hw_value) {
1547 case CHANNEL_A:
1548 /* Both sample_freq and chip_freq are 40MHz */
1549 spur_delta_phase = (spur_offset << 17) / 25;
1550 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1551 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1552 break;
1553 case CHANNEL_G:
1554 /* sample_freq -> 40MHz chip_freq -> 44MHz
1555 * (for b compatibility) */
1556 spur_freq_sigma_delta = (spur_offset << 8) / 55;
1557 spur_delta_phase = (spur_offset << 17) / 25;
1558 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1559 break;
1560 case CHANNEL_T:
1561 case CHANNEL_TG:
1562 /* Both sample_freq and chip_freq are 80MHz */
1563 spur_delta_phase = (spur_offset << 16) / 25;
1564 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1565 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1566 break;
1567 default:
1568 return;
1569 }
1570
1571 /* Calculate pilot and magnitude masks */
1572
1573 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1574 * and divide by symbol_width to find how many symbols we have
1575 * Note: number of symbols is scaled up by 16 */
1576 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1577
1578 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1579 if (!(num_symbols_x16 & 0xF))
1580 /* _X_ */
1581 num_symbol_offsets = 3;
1582 else
1583 /* _xx_ */
1584 num_symbol_offsets = 4;
1585
1586 for (i = 0; i < num_symbol_offsets; i++) {
1587
1588 /* Calculate pilot mask */
1589 s32 curr_sym_off =
1590 (num_symbols_x16 / 16) + i + 25;
1591
1592 /* Pilot magnitude mask seems to be a way to
1593 * declare the boundaries for our detection
1594 * window or something, it's 2 for the middle
1595 * value(s) where the symbol is expected to be
1596 * and 1 on the boundary values */
1597 u8 plt_mag_map =
1598 (i == 0 || i == (num_symbol_offsets - 1))
1599 ? 1 : 2;
1600
1601 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1602 if (curr_sym_off <= 25)
1603 pilot_mask[0] |= 1 << curr_sym_off;
1604 else if (curr_sym_off >= 27)
1605 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1606 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1607 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1608
1609 /* Calculate magnitude mask (for viterbi decoder) */
1610 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1611 mag_mask[0] |=
1612 plt_mag_map << (curr_sym_off + 1) * 2;
1613 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1614 mag_mask[1] |=
1615 plt_mag_map << (curr_sym_off - 15) * 2;
1616 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1617 mag_mask[2] |=
1618 plt_mag_map << (curr_sym_off - 31) * 2;
1619 else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1620 mag_mask[3] |=
1621 plt_mag_map << (curr_sym_off - 47) * 2;
1622
1623 }
1624
1625 /* Write settings on hw to enable spur filter */
1626 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1627 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1628 /* XXX: Self correlator also ? */
1629 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1630 AR5K_PHY_IQ_PILOT_MASK_EN |
1631 AR5K_PHY_IQ_CHAN_MASK_EN |
1632 AR5K_PHY_IQ_SPUR_FILT_EN);
1633
1634 /* Set delta phase and freq sigma delta */
1635 ath5k_hw_reg_write(ah,
1636 AR5K_REG_SM(spur_delta_phase,
1637 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1638 AR5K_REG_SM(spur_freq_sigma_delta,
1639 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1640 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1641 AR5K_PHY_TIMING_11);
1642
1643 /* Write pilot masks */
1644 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1645 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1646 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1647 pilot_mask[1]);
1648
1649 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1650 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1651 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1652 pilot_mask[1]);
1653
1654 /* Write magnitude masks */
1655 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1656 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1657 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1658 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1659 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1660 mag_mask[3]);
1661
1662 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1663 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1664 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1665 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1666 AR5K_PHY_BIN_MASK2_4_MASK_4,
1667 mag_mask[3]);
1668
1669 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1670 AR5K_PHY_IQ_SPUR_FILT_EN) {
1671 /* Clean up spur mitigation settings and disable fliter */
1672 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1673 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1674 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1675 AR5K_PHY_IQ_PILOT_MASK_EN |
1676 AR5K_PHY_IQ_CHAN_MASK_EN |
1677 AR5K_PHY_IQ_SPUR_FILT_EN);
1678 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1679
1680 /* Clear pilot masks */
1681 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1682 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1683 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1684 0);
1685
1686 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1687 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1688 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1689 0);
1690
1691 /* Clear magnitude masks */
1692 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1693 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1694 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1695 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1696 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1697 0);
1698
1699 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1700 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1701 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1702 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1703 AR5K_PHY_BIN_MASK2_4_MASK_4,
1704 0);
1705 }
1706 }
1707
1708 /********************\
1709 Misc PHY functions
1710 \********************/
1711
1712 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1713 {
1714 ATH5K_TRACE(ah->ah_sc);
1715 /*Just a try M.F.*/
1716 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1717
1718 return 0;
1719 }
1720
1721 /*
1722 * Get the PHY Chip revision
1723 */
1724 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1725 {
1726 unsigned int i;
1727 u32 srev;
1728 u16 ret;
1729
1730 ATH5K_TRACE(ah->ah_sc);
1731
1732 /*
1733 * Set the radio chip access register
1734 */
1735 switch (chan) {
1736 case CHANNEL_2GHZ:
1737 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1738 break;
1739 case CHANNEL_5GHZ:
1740 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1741 break;
1742 default:
1743 return 0;
1744 }
1745
1746 mdelay(2);
1747
1748 /* ...wait until PHY is ready and read the selected radio revision */
1749 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1750
1751 for (i = 0; i < 8; i++)
1752 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1753
1754 if (ah->ah_version == AR5K_AR5210) {
1755 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1756 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1757 } else {
1758 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1759 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1760 ((srev & 0x0f) << 4), 8);
1761 }
1762
1763 /* Reset to the 5GHz mode */
1764 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1765
1766 return ret;
1767 }
1768
1769 /*****************\
1770 * Antenna control *
1771 \*****************/
1772
1773 static void /*TODO:Boundary check*/
1774 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1775 {
1776 ATH5K_TRACE(ah->ah_sc);
1777
1778 if (ah->ah_version != AR5K_AR5210)
1779 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1780 }
1781
1782 /*
1783 * Enable/disable fast rx antenna diversity
1784 */
1785 static void
1786 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1787 {
1788 switch (ee_mode) {
1789 case AR5K_EEPROM_MODE_11G:
1790 /* XXX: This is set to
1791 * disabled on initvals !!! */
1792 case AR5K_EEPROM_MODE_11A:
1793 if (enable)
1794 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1795 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1796 else
1797 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1798 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1799 break;
1800 case AR5K_EEPROM_MODE_11B:
1801 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1802 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1803 break;
1804 default:
1805 return;
1806 }
1807
1808 if (enable) {
1809 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1810 AR5K_PHY_RESTART_DIV_GC, 0xc);
1811
1812 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1813 AR5K_PHY_FAST_ANT_DIV_EN);
1814 } else {
1815 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1816 AR5K_PHY_RESTART_DIV_GC, 0x8);
1817
1818 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1819 AR5K_PHY_FAST_ANT_DIV_EN);
1820 }
1821 }
1822
1823 /*
1824 * Set antenna operating mode
1825 */
1826 void
1827 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1828 {
1829 struct ieee80211_channel *channel = ah->ah_current_channel;
1830 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1831 bool use_def_for_sg;
1832 u8 def_ant, tx_ant, ee_mode;
1833 u32 sta_id1 = 0;
1834
1835 def_ant = ah->ah_def_ant;
1836
1837 ATH5K_TRACE(ah->ah_sc);
1838
1839 switch (channel->hw_value & CHANNEL_MODES) {
1840 case CHANNEL_A:
1841 case CHANNEL_T:
1842 case CHANNEL_XR:
1843 ee_mode = AR5K_EEPROM_MODE_11A;
1844 break;
1845 case CHANNEL_G:
1846 case CHANNEL_TG:
1847 ee_mode = AR5K_EEPROM_MODE_11G;
1848 break;
1849 case CHANNEL_B:
1850 ee_mode = AR5K_EEPROM_MODE_11B;
1851 break;
1852 default:
1853 ATH5K_ERR(ah->ah_sc,
1854 "invalid channel: %d\n", channel->center_freq);
1855 return;
1856 }
1857
1858 switch (ant_mode) {
1859 case AR5K_ANTMODE_DEFAULT:
1860 tx_ant = 0;
1861 use_def_for_tx = false;
1862 update_def_on_tx = false;
1863 use_def_for_rts = false;
1864 use_def_for_sg = false;
1865 fast_div = true;
1866 break;
1867 case AR5K_ANTMODE_FIXED_A:
1868 def_ant = 1;
1869 tx_ant = 1;
1870 use_def_for_tx = true;
1871 update_def_on_tx = false;
1872 use_def_for_rts = true;
1873 use_def_for_sg = true;
1874 fast_div = false;
1875 break;
1876 case AR5K_ANTMODE_FIXED_B:
1877 def_ant = 2;
1878 tx_ant = 2;
1879 use_def_for_tx = true;
1880 update_def_on_tx = false;
1881 use_def_for_rts = true;
1882 use_def_for_sg = true;
1883 fast_div = false;
1884 break;
1885 case AR5K_ANTMODE_SINGLE_AP:
1886 def_ant = 1; /* updated on tx */
1887 tx_ant = 0;
1888 use_def_for_tx = true;
1889 update_def_on_tx = true;
1890 use_def_for_rts = true;
1891 use_def_for_sg = true;
1892 fast_div = true;
1893 break;
1894 case AR5K_ANTMODE_SECTOR_AP:
1895 tx_ant = 1; /* variable */
1896 use_def_for_tx = false;
1897 update_def_on_tx = false;
1898 use_def_for_rts = true;
1899 use_def_for_sg = false;
1900 fast_div = false;
1901 break;
1902 case AR5K_ANTMODE_SECTOR_STA:
1903 tx_ant = 1; /* variable */
1904 use_def_for_tx = true;
1905 update_def_on_tx = false;
1906 use_def_for_rts = true;
1907 use_def_for_sg = false;
1908 fast_div = true;
1909 break;
1910 case AR5K_ANTMODE_DEBUG:
1911 def_ant = 1;
1912 tx_ant = 2;
1913 use_def_for_tx = false;
1914 update_def_on_tx = false;
1915 use_def_for_rts = false;
1916 use_def_for_sg = false;
1917 fast_div = false;
1918 break;
1919 default:
1920 return;
1921 }
1922
1923 ah->ah_tx_ant = tx_ant;
1924 ah->ah_ant_mode = ant_mode;
1925 ah->ah_def_ant = def_ant;
1926
1927 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1928 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1929 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1930 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1931
1932 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1933
1934 if (sta_id1)
1935 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1936
1937 /* Note: set diversity before default antenna
1938 * because it won't work correctly */
1939 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1940 ath5k_hw_set_def_antenna(ah, def_ant);
1941 }
1942
1943
1944 /****************\
1945 * TX power setup *
1946 \****************/
1947
1948 /*
1949 * Helper functions
1950 */
1951
1952 /*
1953 * Do linear interpolation between two given (x, y) points
1954 */
1955 static s16
1956 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1957 s16 y_left, s16 y_right)
1958 {
1959 s16 ratio, result;
1960
1961 /* Avoid divide by zero and skip interpolation
1962 * if we have the same point */
1963 if ((x_left == x_right) || (y_left == y_right))
1964 return y_left;
1965
1966 /*
1967 * Since we use ints and not fps, we need to scale up in
1968 * order to get a sane ratio value (or else we 'll eg. get
1969 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1970 * to have some accuracy both for 0.5 and 0.25 steps.
1971 */
1972 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1973
1974 /* Now scale down to be in range */
1975 result = y_left + (ratio * (target - x_left) / 100);
1976
1977 return result;
1978 }
1979
1980 /*
1981 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1982 *
1983 * Since we have the top of the curve and we draw the line below
1984 * until we reach 1 (1 pcdac step) we need to know which point
1985 * (x value) that is so that we don't go below y axis and have negative
1986 * pcdac values when creating the curve, or fill the table with zeroes.
1987 */
1988 static s16
1989 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1990 const s16 *pwrL, const s16 *pwrR)
1991 {
1992 s8 tmp;
1993 s16 min_pwrL, min_pwrR;
1994 s16 pwr_i;
1995
1996 /* Some vendors write the same pcdac value twice !!! */
1997 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
1998 return max(pwrL[0], pwrR[0]);
1999
2000 if (pwrL[0] == pwrL[1])
2001 min_pwrL = pwrL[0];
2002 else {
2003 pwr_i = pwrL[0];
2004 do {
2005 pwr_i--;
2006 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2007 pwrL[0], pwrL[1],
2008 stepL[0], stepL[1]);
2009 } while (tmp > 1);
2010
2011 min_pwrL = pwr_i;
2012 }
2013
2014 if (pwrR[0] == pwrR[1])
2015 min_pwrR = pwrR[0];
2016 else {
2017 pwr_i = pwrR[0];
2018 do {
2019 pwr_i--;
2020 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2021 pwrR[0], pwrR[1],
2022 stepR[0], stepR[1]);
2023 } while (tmp > 1);
2024
2025 min_pwrR = pwr_i;
2026 }
2027
2028 /* Keep the right boundary so that it works for both curves */
2029 return max(min_pwrL, min_pwrR);
2030 }
2031
2032 /*
2033 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2034 * Power to PCDAC curve.
2035 *
2036 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2037 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2038 * PCDAC/PDADC step for each curve is 64 but we can write more than
2039 * one curves on hw so we can go up to 128 (which is the max step we
2040 * can write on the final table).
2041 *
2042 * We write y values (PCDAC/PDADC steps) on hw.
2043 */
2044 static void
2045 ath5k_create_power_curve(s16 pmin, s16 pmax,
2046 const s16 *pwr, const u8 *vpd,
2047 u8 num_points,
2048 u8 *vpd_table, u8 type)
2049 {
2050 u8 idx[2] = { 0, 1 };
2051 s16 pwr_i = 2*pmin;
2052 int i;
2053
2054 if (num_points < 2)
2055 return;
2056
2057 /* We want the whole line, so adjust boundaries
2058 * to cover the entire power range. Note that
2059 * power values are already 0.25dB so no need
2060 * to multiply pwr_i by 2 */
2061 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2062 pwr_i = pmin;
2063 pmin = 0;
2064 pmax = 63;
2065 }
2066
2067 /* Find surrounding turning points (TPs)
2068 * and interpolate between them */
2069 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2070 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2071
2072 /* We passed the right TP, move to the next set of TPs
2073 * if we pass the last TP, extrapolate above using the last
2074 * two TPs for ratio */
2075 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2076 idx[0]++;
2077 idx[1]++;
2078 }
2079
2080 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2081 pwr[idx[0]], pwr[idx[1]],
2082 vpd[idx[0]], vpd[idx[1]]);
2083
2084 /* Increase by 0.5dB
2085 * (0.25 dB units) */
2086 pwr_i += 2;
2087 }
2088 }
2089
2090 /*
2091 * Get the surrounding per-channel power calibration piers
2092 * for a given frequency so that we can interpolate between
2093 * them and come up with an apropriate dataset for our current
2094 * channel.
2095 */
2096 static void
2097 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2098 struct ieee80211_channel *channel,
2099 struct ath5k_chan_pcal_info **pcinfo_l,
2100 struct ath5k_chan_pcal_info **pcinfo_r)
2101 {
2102 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2103 struct ath5k_chan_pcal_info *pcinfo;
2104 u8 idx_l, idx_r;
2105 u8 mode, max, i;
2106 u32 target = channel->center_freq;
2107
2108 idx_l = 0;
2109 idx_r = 0;
2110
2111 if (!(channel->hw_value & CHANNEL_OFDM)) {
2112 pcinfo = ee->ee_pwr_cal_b;
2113 mode = AR5K_EEPROM_MODE_11B;
2114 } else if (channel->hw_value & CHANNEL_2GHZ) {
2115 pcinfo = ee->ee_pwr_cal_g;
2116 mode = AR5K_EEPROM_MODE_11G;
2117 } else {
2118 pcinfo = ee->ee_pwr_cal_a;
2119 mode = AR5K_EEPROM_MODE_11A;
2120 }
2121 max = ee->ee_n_piers[mode] - 1;
2122
2123 /* Frequency is below our calibrated
2124 * range. Use the lowest power curve
2125 * we have */
2126 if (target < pcinfo[0].freq) {
2127 idx_l = idx_r = 0;
2128 goto done;
2129 }
2130
2131 /* Frequency is above our calibrated
2132 * range. Use the highest power curve
2133 * we have */
2134 if (target > pcinfo[max].freq) {
2135 idx_l = idx_r = max;
2136 goto done;
2137 }
2138
2139 /* Frequency is inside our calibrated
2140 * channel range. Pick the surrounding
2141 * calibration piers so that we can
2142 * interpolate */
2143 for (i = 0; i <= max; i++) {
2144
2145 /* Frequency matches one of our calibration
2146 * piers, no need to interpolate, just use
2147 * that calibration pier */
2148 if (pcinfo[i].freq == target) {
2149 idx_l = idx_r = i;
2150 goto done;
2151 }
2152
2153 /* We found a calibration pier that's above
2154 * frequency, use this pier and the previous
2155 * one to interpolate */
2156 if (target < pcinfo[i].freq) {
2157 idx_r = i;
2158 idx_l = idx_r - 1;
2159 goto done;
2160 }
2161 }
2162
2163 done:
2164 *pcinfo_l = &pcinfo[idx_l];
2165 *pcinfo_r = &pcinfo[idx_r];
2166
2167 return;
2168 }
2169
2170 /*
2171 * Get the surrounding per-rate power calibration data
2172 * for a given frequency and interpolate between power
2173 * values to set max target power supported by hw for
2174 * each rate.
2175 */
2176 static void
2177 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2178 struct ieee80211_channel *channel,
2179 struct ath5k_rate_pcal_info *rates)
2180 {
2181 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2182 struct ath5k_rate_pcal_info *rpinfo;
2183 u8 idx_l, idx_r;
2184 u8 mode, max, i;
2185 u32 target = channel->center_freq;
2186
2187 idx_l = 0;
2188 idx_r = 0;
2189
2190 if (!(channel->hw_value & CHANNEL_OFDM)) {
2191 rpinfo = ee->ee_rate_tpwr_b;
2192 mode = AR5K_EEPROM_MODE_11B;
2193 } else if (channel->hw_value & CHANNEL_2GHZ) {
2194 rpinfo = ee->ee_rate_tpwr_g;
2195 mode = AR5K_EEPROM_MODE_11G;
2196 } else {
2197 rpinfo = ee->ee_rate_tpwr_a;
2198 mode = AR5K_EEPROM_MODE_11A;
2199 }
2200 max = ee->ee_rate_target_pwr_num[mode] - 1;
2201
2202 /* Get the surrounding calibration
2203 * piers - same as above */
2204 if (target < rpinfo[0].freq) {
2205 idx_l = idx_r = 0;
2206 goto done;
2207 }
2208
2209 if (target > rpinfo[max].freq) {
2210 idx_l = idx_r = max;
2211 goto done;
2212 }
2213
2214 for (i = 0; i <= max; i++) {
2215
2216 if (rpinfo[i].freq == target) {
2217 idx_l = idx_r = i;
2218 goto done;
2219 }
2220
2221 if (target < rpinfo[i].freq) {
2222 idx_r = i;
2223 idx_l = idx_r - 1;
2224 goto done;
2225 }
2226 }
2227
2228 done:
2229 /* Now interpolate power value, based on the frequency */
2230 rates->freq = target;
2231
2232 rates->target_power_6to24 =
2233 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2234 rpinfo[idx_r].freq,
2235 rpinfo[idx_l].target_power_6to24,
2236 rpinfo[idx_r].target_power_6to24);
2237
2238 rates->target_power_36 =
2239 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2240 rpinfo[idx_r].freq,
2241 rpinfo[idx_l].target_power_36,
2242 rpinfo[idx_r].target_power_36);
2243
2244 rates->target_power_48 =
2245 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2246 rpinfo[idx_r].freq,
2247 rpinfo[idx_l].target_power_48,
2248 rpinfo[idx_r].target_power_48);
2249
2250 rates->target_power_54 =
2251 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2252 rpinfo[idx_r].freq,
2253 rpinfo[idx_l].target_power_54,
2254 rpinfo[idx_r].target_power_54);
2255 }
2256
2257 /*
2258 * Get the max edge power for this channel if
2259 * we have such data from EEPROM's Conformance Test
2260 * Limits (CTL), and limit max power if needed.
2261 */
2262 static void
2263 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2264 struct ieee80211_channel *channel)
2265 {
2266 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2267 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2268 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2269 u8 *ctl_val = ee->ee_ctl;
2270 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2271 s16 edge_pwr = 0;
2272 u8 rep_idx;
2273 u8 i, ctl_mode;
2274 u8 ctl_idx = 0xFF;
2275 u32 target = channel->center_freq;
2276
2277 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2278
2279 switch (channel->hw_value & CHANNEL_MODES) {
2280 case CHANNEL_A:
2281 ctl_mode |= AR5K_CTL_11A;
2282 break;
2283 case CHANNEL_G:
2284 ctl_mode |= AR5K_CTL_11G;
2285 break;
2286 case CHANNEL_B:
2287 ctl_mode |= AR5K_CTL_11B;
2288 break;
2289 case CHANNEL_T:
2290 ctl_mode |= AR5K_CTL_TURBO;
2291 break;
2292 case CHANNEL_TG:
2293 ctl_mode |= AR5K_CTL_TURBOG;
2294 break;
2295 case CHANNEL_XR:
2296 /* Fall through */
2297 default:
2298 return;
2299 }
2300
2301 for (i = 0; i < ee->ee_ctls; i++) {
2302 if (ctl_val[i] == ctl_mode) {
2303 ctl_idx = i;
2304 break;
2305 }
2306 }
2307
2308 /* If we have a CTL dataset available grab it and find the
2309 * edge power for our frequency */
2310 if (ctl_idx == 0xFF)
2311 return;
2312
2313 /* Edge powers are sorted by frequency from lower
2314 * to higher. Each CTL corresponds to 8 edge power
2315 * measurements. */
2316 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2317
2318 /* Don't do boundaries check because we
2319 * might have more that one bands defined
2320 * for this mode */
2321
2322 /* Get the edge power that's closer to our
2323 * frequency */
2324 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2325 rep_idx += i;
2326 if (target <= rep[rep_idx].freq)
2327 edge_pwr = (s16) rep[rep_idx].edge;
2328 }
2329
2330 if (edge_pwr)
2331 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2332 }
2333
2334
2335 /*
2336 * Power to PCDAC table functions
2337 */
2338
2339 /*
2340 * Fill Power to PCDAC table on RF5111
2341 *
2342 * No further processing is needed for RF5111, the only thing we have to
2343 * do is fill the values below and above calibration range since eeprom data
2344 * may not cover the entire PCDAC table.
2345 */
2346 static void
2347 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2348 s16 *table_max)
2349 {
2350 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2351 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2352 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2353 s16 min_pwr, max_pwr;
2354
2355 /* Get table boundaries */
2356 min_pwr = table_min[0];
2357 pcdac_0 = pcdac_tmp[0];
2358
2359 max_pwr = table_max[0];
2360 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2361
2362 /* Extrapolate below minimum using pcdac_0 */
2363 pcdac_i = 0;
2364 for (i = 0; i < min_pwr; i++)
2365 pcdac_out[pcdac_i++] = pcdac_0;
2366
2367 /* Copy values from pcdac_tmp */
2368 pwr_idx = min_pwr;
2369 for (i = 0 ; pwr_idx <= max_pwr &&
2370 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2371 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2372 pwr_idx++;
2373 }
2374
2375 /* Extrapolate above maximum */
2376 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2377 pcdac_out[pcdac_i++] = pcdac_n;
2378
2379 }
2380
2381 /*
2382 * Combine available XPD Curves and fill Linear Power to PCDAC table
2383 * on RF5112
2384 *
2385 * RFX112 can have up to 2 curves (one for low txpower range and one for
2386 * higher txpower range). We need to put them both on pcdac_out and place
2387 * them in the correct location. In case we only have one curve available
2388 * just fit it on pcdac_out (it's supposed to cover the entire range of
2389 * available pwr levels since it's always the higher power curve). Extrapolate
2390 * below and above final table if needed.
2391 */
2392 static void
2393 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2394 s16 *table_max, u8 pdcurves)
2395 {
2396 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2397 u8 *pcdac_low_pwr;
2398 u8 *pcdac_high_pwr;
2399 u8 *pcdac_tmp;
2400 u8 pwr;
2401 s16 max_pwr_idx;
2402 s16 min_pwr_idx;
2403 s16 mid_pwr_idx = 0;
2404 /* Edge flag turs on the 7nth bit on the PCDAC
2405 * to delcare the higher power curve (force values
2406 * to be greater than 64). If we only have one curve
2407 * we don't need to set this, if we have 2 curves and
2408 * fill the table backwards this can also be used to
2409 * switch from higher power curve to lower power curve */
2410 u8 edge_flag;
2411 int i;
2412
2413 /* When we have only one curve available
2414 * that's the higher power curve. If we have
2415 * two curves the first is the high power curve
2416 * and the next is the low power curve. */
2417 if (pdcurves > 1) {
2418 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2419 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2420 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2421 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2422
2423 /* If table size goes beyond 31.5dB, keep the
2424 * upper 31.5dB range when setting tx power.
2425 * Note: 126 = 31.5 dB in quarter dB steps */
2426 if (table_max[0] - table_min[1] > 126)
2427 min_pwr_idx = table_max[0] - 126;
2428 else
2429 min_pwr_idx = table_min[1];
2430
2431 /* Since we fill table backwards
2432 * start from high power curve */
2433 pcdac_tmp = pcdac_high_pwr;
2434
2435 edge_flag = 0x40;
2436 } else {
2437 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2438 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2439 min_pwr_idx = table_min[0];
2440 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2441 pcdac_tmp = pcdac_high_pwr;
2442 edge_flag = 0;
2443 }
2444
2445 /* This is used when setting tx power*/
2446 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2447
2448 /* Fill Power to PCDAC table backwards */
2449 pwr = max_pwr_idx;
2450 for (i = 63; i >= 0; i--) {
2451 /* Entering lower power range, reset
2452 * edge flag and set pcdac_tmp to lower
2453 * power curve.*/
2454 if (edge_flag == 0x40 &&
2455 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2456 edge_flag = 0x00;
2457 pcdac_tmp = pcdac_low_pwr;
2458 pwr = mid_pwr_idx/2;
2459 }
2460
2461 /* Don't go below 1, extrapolate below if we have
2462 * already swithced to the lower power curve -or
2463 * we only have one curve and edge_flag is zero
2464 * anyway */
2465 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2466 while (i >= 0) {
2467 pcdac_out[i] = pcdac_out[i + 1];
2468 i--;
2469 }
2470 break;
2471 }
2472
2473 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2474
2475 /* Extrapolate above if pcdac is greater than
2476 * 126 -this can happen because we OR pcdac_out
2477 * value with edge_flag on high power curve */
2478 if (pcdac_out[i] > 126)
2479 pcdac_out[i] = 126;
2480
2481 /* Decrease by a 0.5dB step */
2482 pwr--;
2483 }
2484 }
2485
2486 /* Write PCDAC values on hw */
2487 static void
2488 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2489 {
2490 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2491 int i;
2492
2493 /*
2494 * Write TX power values
2495 */
2496 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2497 ath5k_hw_reg_write(ah,
2498 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2499 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2500 AR5K_PHY_PCDAC_TXPOWER(i));
2501 }
2502 }
2503
2504
2505 /*
2506 * Power to PDADC table functions
2507 */
2508
2509 /*
2510 * Set the gain boundaries and create final Power to PDADC table
2511 *
2512 * We can have up to 4 pd curves, we need to do a simmilar process
2513 * as we do for RF5112. This time we don't have an edge_flag but we
2514 * set the gain boundaries on a separate register.
2515 */
2516 static void
2517 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2518 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2519 {
2520 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2521 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2522 u8 *pdadc_tmp;
2523 s16 pdadc_0;
2524 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2525 u8 pd_gain_overlap;
2526
2527 /* Note: Register value is initialized on initvals
2528 * there is no feedback from hw.
2529 * XXX: What about pd_gain_overlap from EEPROM ? */
2530 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2531 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2532
2533 /* Create final PDADC table */
2534 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2535 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2536
2537 if (pdg == pdcurves - 1)
2538 /* 2 dB boundary stretch for last
2539 * (higher power) curve */
2540 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2541 else
2542 /* Set gain boundary in the middle
2543 * between this curve and the next one */
2544 gain_boundaries[pdg] =
2545 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2546
2547 /* Sanity check in case our 2 db stretch got out of
2548 * range. */
2549 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2550 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2551
2552 /* For the first curve (lower power)
2553 * start from 0 dB */
2554 if (pdg == 0)
2555 pdadc_0 = 0;
2556 else
2557 /* For the other curves use the gain overlap */
2558 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2559 pd_gain_overlap;
2560
2561 /* Force each power step to be at least 0.5 dB */
2562 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2563 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2564 else
2565 pwr_step = 1;
2566
2567 /* If pdadc_0 is negative, we need to extrapolate
2568 * below this pdgain by a number of pwr_steps */
2569 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2570 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2571 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2572 pdadc_0++;
2573 }
2574
2575 /* Set last pwr level, using gain boundaries */
2576 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2577 /* Limit it to be inside pwr range */
2578 table_size = pwr_max[pdg] - pwr_min[pdg];
2579 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2580
2581 /* Fill pdadc_out table */
2582 while (pdadc_0 < max_idx)
2583 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2584
2585 /* Need to extrapolate above this pdgain? */
2586 if (pdadc_n <= max_idx)
2587 continue;
2588
2589 /* Force each power step to be at least 0.5 dB */
2590 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2591 pwr_step = pdadc_tmp[table_size - 1] -
2592 pdadc_tmp[table_size - 2];
2593 else
2594 pwr_step = 1;
2595
2596 /* Extrapolate above */
2597 while ((pdadc_0 < (s16) pdadc_n) &&
2598 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2599 s16 tmp = pdadc_tmp[table_size - 1] +
2600 (pdadc_0 - max_idx) * pwr_step;
2601 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2602 pdadc_0++;
2603 }
2604 }
2605
2606 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2607 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2608 pdg++;
2609 }
2610
2611 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2612 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2613 pdadc_i++;
2614 }
2615
2616 /* Set gain boundaries */
2617 ath5k_hw_reg_write(ah,
2618 AR5K_REG_SM(pd_gain_overlap,
2619 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2620 AR5K_REG_SM(gain_boundaries[0],
2621 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2622 AR5K_REG_SM(gain_boundaries[1],
2623 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2624 AR5K_REG_SM(gain_boundaries[2],
2625 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2626 AR5K_REG_SM(gain_boundaries[3],
2627 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2628 AR5K_PHY_TPC_RG5);
2629
2630 /* Used for setting rate power table */
2631 ah->ah_txpower.txp_min_idx = pwr_min[0];
2632
2633 }
2634
2635 /* Write PDADC values on hw */
2636 static void
2637 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2638 u8 pdcurves, u8 *pdg_to_idx)
2639 {
2640 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2641 u32 reg;
2642 u8 i;
2643
2644 /* Select the right pdgain curves */
2645
2646 /* Clear current settings */
2647 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2648 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2649 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2650 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2651 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2652
2653 /*
2654 * Use pd_gains curve from eeprom
2655 *
2656 * This overrides the default setting from initvals
2657 * in case some vendors (e.g. Zcomax) don't use the default
2658 * curves. If we don't honor their settings we 'll get a
2659 * 5dB (1 * gain overlap ?) drop.
2660 */
2661 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2662
2663 switch (pdcurves) {
2664 case 3:
2665 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2666 /* Fall through */
2667 case 2:
2668 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2669 /* Fall through */
2670 case 1:
2671 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2672 break;
2673 }
2674 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2675
2676 /*
2677 * Write TX power values
2678 */
2679 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2680 ath5k_hw_reg_write(ah,
2681 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2682 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2683 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2684 ((pdadc_out[4*i + 3] & 0xff) << 24),
2685 AR5K_PHY_PDADC_TXPOWER(i));
2686 }
2687 }
2688
2689
2690 /*
2691 * Common code for PCDAC/PDADC tables
2692 */
2693
2694 /*
2695 * This is the main function that uses all of the above
2696 * to set PCDAC/PDADC table on hw for the current channel.
2697 * This table is used for tx power calibration on the basband,
2698 * without it we get weird tx power levels and in some cases
2699 * distorted spectral mask
2700 */
2701 static int
2702 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2703 struct ieee80211_channel *channel,
2704 u8 ee_mode, u8 type)
2705 {
2706 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2707 struct ath5k_chan_pcal_info *pcinfo_L;
2708 struct ath5k_chan_pcal_info *pcinfo_R;
2709 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2710 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2711 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2712 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2713 u8 *tmpL;
2714 u8 *tmpR;
2715 u32 target = channel->center_freq;
2716 int pdg, i;
2717
2718 /* Get surounding freq piers for this channel */
2719 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2720 &pcinfo_L,
2721 &pcinfo_R);
2722
2723 /* Loop over pd gain curves on
2724 * surounding freq piers by index */
2725 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2726
2727 /* Fill curves in reverse order
2728 * from lower power (max gain)
2729 * to higher power. Use curve -> idx
2730 * backmapping we did on eeprom init */
2731 u8 idx = pdg_curve_to_idx[pdg];
2732
2733 /* Grab the needed curves by index */
2734 pdg_L = &pcinfo_L->pd_curves[idx];
2735 pdg_R = &pcinfo_R->pd_curves[idx];
2736
2737 /* Initialize the temp tables */
2738 tmpL = ah->ah_txpower.tmpL[pdg];
2739 tmpR = ah->ah_txpower.tmpR[pdg];
2740
2741 /* Set curve's x boundaries and create
2742 * curves so that they cover the same
2743 * range (if we don't do that one table
2744 * will have values on some range and the
2745 * other one won't have any so interpolation
2746 * will fail) */
2747 table_min[pdg] = min(pdg_L->pd_pwr[0],
2748 pdg_R->pd_pwr[0]) / 2;
2749
2750 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2751 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2752
2753 /* Now create the curves on surrounding channels
2754 * and interpolate if needed to get the final
2755 * curve for this gain on this channel */
2756 switch (type) {
2757 case AR5K_PWRTABLE_LINEAR_PCDAC:
2758 /* Override min/max so that we don't loose
2759 * accuracy (don't divide by 2) */
2760 table_min[pdg] = min(pdg_L->pd_pwr[0],
2761 pdg_R->pd_pwr[0]);
2762
2763 table_max[pdg] =
2764 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2765 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2766
2767 /* Override minimum so that we don't get
2768 * out of bounds while extrapolating
2769 * below. Don't do this when we have 2
2770 * curves and we are on the high power curve
2771 * because table_min is ok in this case */
2772 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2773
2774 table_min[pdg] =
2775 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2776 pdg_R->pd_step,
2777 pdg_L->pd_pwr,
2778 pdg_R->pd_pwr);
2779
2780 /* Don't go too low because we will
2781 * miss the upper part of the curve.
2782 * Note: 126 = 31.5dB (max power supported)
2783 * in 0.25dB units */
2784 if (table_max[pdg] - table_min[pdg] > 126)
2785 table_min[pdg] = table_max[pdg] - 126;
2786 }
2787
2788 /* Fall through */
2789 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2790 case AR5K_PWRTABLE_PWR_TO_PDADC:
2791
2792 ath5k_create_power_curve(table_min[pdg],
2793 table_max[pdg],
2794 pdg_L->pd_pwr,
2795 pdg_L->pd_step,
2796 pdg_L->pd_points, tmpL, type);
2797
2798 /* We are in a calibration
2799 * pier, no need to interpolate
2800 * between freq piers */
2801 if (pcinfo_L == pcinfo_R)
2802 continue;
2803
2804 ath5k_create_power_curve(table_min[pdg],
2805 table_max[pdg],
2806 pdg_R->pd_pwr,
2807 pdg_R->pd_step,
2808 pdg_R->pd_points, tmpR, type);
2809 break;
2810 default:
2811 return -EINVAL;
2812 }
2813
2814 /* Interpolate between curves
2815 * of surounding freq piers to
2816 * get the final curve for this
2817 * pd gain. Re-use tmpL for interpolation
2818 * output */
2819 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2820 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2821 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2822 (s16) pcinfo_L->freq,
2823 (s16) pcinfo_R->freq,
2824 (s16) tmpL[i],
2825 (s16) tmpR[i]);
2826 }
2827 }
2828
2829 /* Now we have a set of curves for this
2830 * channel on tmpL (x range is table_max - table_min
2831 * and y values are tmpL[pdg][]) sorted in the same
2832 * order as EEPROM (because we've used the backmapping).
2833 * So for RF5112 it's from higher power to lower power
2834 * and for RF2413 it's from lower power to higher power.
2835 * For RF5111 we only have one curve. */
2836
2837 /* Fill min and max power levels for this
2838 * channel by interpolating the values on
2839 * surounding channels to complete the dataset */
2840 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2841 (s16) pcinfo_L->freq,
2842 (s16) pcinfo_R->freq,
2843 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2844
2845 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2846 (s16) pcinfo_L->freq,
2847 (s16) pcinfo_R->freq,
2848 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2849
2850 /* We are ready to go, fill PCDAC/PDADC
2851 * table and write settings on hardware */
2852 switch (type) {
2853 case AR5K_PWRTABLE_LINEAR_PCDAC:
2854 /* For RF5112 we can have one or two curves
2855 * and each curve covers a certain power lvl
2856 * range so we need to do some more processing */
2857 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2858 ee->ee_pd_gains[ee_mode]);
2859
2860 /* Set txp.offset so that we can
2861 * match max power value with max
2862 * table index */
2863 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2864
2865 /* Write settings on hw */
2866 ath5k_setup_pcdac_table(ah);
2867 break;
2868 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2869 /* We are done for RF5111 since it has only
2870 * one curve, just fit the curve on the table */
2871 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2872
2873 /* No rate powertable adjustment for RF5111 */
2874 ah->ah_txpower.txp_min_idx = 0;
2875 ah->ah_txpower.txp_offset = 0;
2876
2877 /* Write settings on hw */
2878 ath5k_setup_pcdac_table(ah);
2879 break;
2880 case AR5K_PWRTABLE_PWR_TO_PDADC:
2881 /* Set PDADC boundaries and fill
2882 * final PDADC table */
2883 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2884 ee->ee_pd_gains[ee_mode]);
2885
2886 /* Write settings on hw */
2887 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2888
2889 /* Set txp.offset, note that table_min
2890 * can be negative */
2891 ah->ah_txpower.txp_offset = table_min[0];
2892 break;
2893 default:
2894 return -EINVAL;
2895 }
2896
2897 return 0;
2898 }
2899
2900
2901 /*
2902 * Per-rate tx power setting
2903 *
2904 * This is the code that sets the desired tx power (below
2905 * maximum) on hw for each rate (we also have TPC that sets
2906 * power per packet). We do that by providing an index on the
2907 * PCDAC/PDADC table we set up.
2908 */
2909
2910 /*
2911 * Set rate power table
2912 *
2913 * For now we only limit txpower based on maximum tx power
2914 * supported by hw (what's inside rate_info). We need to limit
2915 * this even more, based on regulatory domain etc.
2916 *
2917 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2918 * and is indexed as follows:
2919 * rates[0] - rates[7] -> OFDM rates
2920 * rates[8] - rates[14] -> CCK rates
2921 * rates[15] -> XR rates (they all have the same power)
2922 */
2923 static void
2924 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2925 struct ath5k_rate_pcal_info *rate_info,
2926 u8 ee_mode)
2927 {
2928 unsigned int i;
2929 u16 *rates;
2930
2931 /* max_pwr is power level we got from driver/user in 0.5dB
2932 * units, switch to 0.25dB units so we can compare */
2933 max_pwr *= 2;
2934 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2935
2936 /* apply rate limits */
2937 rates = ah->ah_txpower.txp_rates_power_table;
2938
2939 /* OFDM rates 6 to 24Mb/s */
2940 for (i = 0; i < 5; i++)
2941 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2942
2943 /* Rest OFDM rates */
2944 rates[5] = min(rates[0], rate_info->target_power_36);
2945 rates[6] = min(rates[0], rate_info->target_power_48);
2946 rates[7] = min(rates[0], rate_info->target_power_54);
2947
2948 /* CCK rates */
2949 /* 1L */
2950 rates[8] = min(rates[0], rate_info->target_power_6to24);
2951 /* 2L */
2952 rates[9] = min(rates[0], rate_info->target_power_36);
2953 /* 2S */
2954 rates[10] = min(rates[0], rate_info->target_power_36);
2955 /* 5L */
2956 rates[11] = min(rates[0], rate_info->target_power_48);
2957 /* 5S */
2958 rates[12] = min(rates[0], rate_info->target_power_48);
2959 /* 11L */
2960 rates[13] = min(rates[0], rate_info->target_power_54);
2961 /* 11S */
2962 rates[14] = min(rates[0], rate_info->target_power_54);
2963
2964 /* XR rates */
2965 rates[15] = min(rates[0], rate_info->target_power_6to24);
2966
2967 /* CCK rates have different peak to average ratio
2968 * so we have to tweak their power so that gainf
2969 * correction works ok. For this we use OFDM to
2970 * CCK delta from eeprom */
2971 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2972 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2973 for (i = 8; i <= 15; i++)
2974 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2975
2976 /* Now that we have all rates setup use table offset to
2977 * match the power range set by user with the power indices
2978 * on PCDAC/PDADC table */
2979 for (i = 0; i < 16; i++) {
2980 rates[i] += ah->ah_txpower.txp_offset;
2981 /* Don't get out of bounds */
2982 if (rates[i] > 63)
2983 rates[i] = 63;
2984 }
2985
2986 /* Min/max in 0.25dB units */
2987 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2988 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
2989 ah->ah_txpower.txp_ofdm = rates[7];
2990 }
2991
2992
2993 /*
2994 * Set transmition power
2995 */
2996 int
2997 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2998 u8 ee_mode, u8 txpower)
2999 {
3000 struct ath5k_rate_pcal_info rate_info;
3001 u8 type;
3002 int ret;
3003
3004 ATH5K_TRACE(ah->ah_sc);
3005 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3006 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3007 return -EINVAL;
3008 }
3009
3010 /* Reset TX power values */
3011 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3012 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3013 ah->ah_txpower.txp_min_pwr = 0;
3014 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3015
3016 /* Initialize TX power table */
3017 switch (ah->ah_radio) {
3018 case AR5K_RF5111:
3019 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3020 break;
3021 case AR5K_RF5112:
3022 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3023 break;
3024 case AR5K_RF2413:
3025 case AR5K_RF5413:
3026 case AR5K_RF2316:
3027 case AR5K_RF2317:
3028 case AR5K_RF2425:
3029 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3030 break;
3031 default:
3032 return -EINVAL;
3033 }
3034
3035 /* FIXME: Only on channel/mode change */
3036 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3037 if (ret)
3038 return ret;
3039
3040 /* Limit max power if we have a CTL available */
3041 ath5k_get_max_ctl_power(ah, channel);
3042
3043 /* FIXME: Tx power limit for this regdomain
3044 * XXX: Mac80211/CRDA will do that anyway ? */
3045
3046 /* FIXME: Antenna reduction stuff */
3047
3048 /* FIXME: Limit power on turbo modes */
3049
3050 /* FIXME: TPC scale reduction */
3051
3052 /* Get surounding channels for per-rate power table
3053 * calibration */
3054 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3055
3056 /* Setup rate power table */
3057 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3058
3059 /* Write rate power table on hw */
3060 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3061 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3062 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3063
3064 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3065 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3066 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3067
3068 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3069 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3070 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3071
3072 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3073 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3074 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3075
3076 /* FIXME: TPC support */
3077 if (ah->ah_txpower.txp_tpc) {
3078 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3079 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3080
3081 ath5k_hw_reg_write(ah,
3082 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3083 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3084 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3085 AR5K_TPC);
3086 } else {
3087 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3088 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3089 }
3090
3091 return 0;
3092 }
3093
3094 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3095 {
3096 /*Just a try M.F.*/
3097 struct ieee80211_channel *channel = ah->ah_current_channel;
3098 u8 ee_mode;
3099
3100 ATH5K_TRACE(ah->ah_sc);
3101
3102 switch (channel->hw_value & CHANNEL_MODES) {
3103 case CHANNEL_A:
3104 case CHANNEL_T:
3105 case CHANNEL_XR:
3106 ee_mode = AR5K_EEPROM_MODE_11A;
3107 break;
3108 case CHANNEL_G:
3109 case CHANNEL_TG:
3110 ee_mode = AR5K_EEPROM_MODE_11G;
3111 break;
3112 case CHANNEL_B:
3113 ee_mode = AR5K_EEPROM_MODE_11B;
3114 break;
3115 default:
3116 ATH5K_ERR(ah->ah_sc,
3117 "invalid channel: %d\n", channel->center_freq);
3118 return -EINVAL;
3119 }
3120
3121 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3122 "changing txpower to %d\n", txpower);
3123
3124 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3125 }
kernel-based virtual machine