drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/aer.h>
  35
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_dcb.h"
  39 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  40 #define IXGBE_FCOE
  41 #include "ixgbe_fcoe.h"
  42 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  43 #ifdef CONFIG_IXGBE_DCA
  44 #include <linux/dca.h>
  45 #endif
  46
  47 #define PFX "ixgbe: "
  48 #define DPRINTK(nlevel, klevel, fmt, args...) \
  49         ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
  50         printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
  51                 __func__ , ## args)))
  52
  53 /* TX/RX descriptor defines */
  54 #define IXGBE_DEFAULT_TXD                  1024
  55 #define IXGBE_MAX_TXD                      4096
  56 #define IXGBE_MIN_TXD                        64
  57
  58 #define IXGBE_DEFAULT_RXD                  1024
  59 #define IXGBE_MAX_RXD                      4096
  60 #define IXGBE_MIN_RXD                        64
  61
  62 /* flow control */
  63 #define IXGBE_DEFAULT_FCRTL             0x10000
  64 #define IXGBE_MIN_FCRTL                    0x40
  65 #define IXGBE_MAX_FCRTL                 0x7FF80
  66 #define IXGBE_DEFAULT_FCRTH             0x20000
  67 #define IXGBE_MIN_FCRTH                   0x600
  68 #define IXGBE_MAX_FCRTH                 0x7FFF0
  69 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  70 #define IXGBE_MIN_FCPAUSE                     0
  71 #define IXGBE_MAX_FCPAUSE                0xFFFF
  72
  73 /* Supported Rx Buffer Sizes */
  74 #define IXGBE_RXBUFFER_64    64     /* Used for packet split */
  75 #define IXGBE_RXBUFFER_128   128    /* Used for packet split */
  76 #define IXGBE_RXBUFFER_256   256    /* Used for packet split */
  77 #define IXGBE_RXBUFFER_2048  2048
  78 #define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */
  79
  80 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
  81
  82 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  83
  84 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  85 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  86
  87 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  88 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  89 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  90 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  91 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 4)
  92 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 5)
  93 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
  94 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
  95 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
  96
  97 /* wrapper around a pointer to a socket buffer,
  98  * so a DMA handle can be stored along with the buffer */
  99 struct ixgbe_tx_buffer {
 100         struct sk_buff *skb;
 101         dma_addr_t dma;
 102         unsigned long time_stamp;
 103         u16 length;
 104         u16 next_to_watch;
 105 };
 106
 107 struct ixgbe_rx_buffer {
 108         struct sk_buff *skb;
 109         dma_addr_t dma;
 110         struct page *page;
 111         dma_addr_t page_dma;
 112         unsigned int page_offset;
 113 };
 114
 115 struct ixgbe_queue_stats {
 116         u64 packets;
 117         u64 bytes;
 118 };
 119
 120 struct ixgbe_ring {
 121         void *desc;                     /* descriptor ring memory */
 122         dma_addr_t dma;                 /* phys. address of descriptor ring */
 123         unsigned int size;              /* length in bytes */
 124         unsigned int count;             /* amount of descriptors */
 125         unsigned int next_to_use;
 126         unsigned int next_to_clean;
 127
 128         int queue_index; /* needed for multiqueue queue management */
 129         union {
 130                 struct ixgbe_tx_buffer *tx_buffer_info;
 131                 struct ixgbe_rx_buffer *rx_buffer_info;
 132         };
 133
 134         u16 head;
 135         u16 tail;
 136
 137         unsigned int total_bytes;
 138         unsigned int total_packets;
 139
 140         u16 reg_idx; /* holds the special value that gets the hardware register
 141                       * offset associated with this ring, which is different
 142                       * for DCB and RSS modes */
 143
 144 #ifdef CONFIG_IXGBE_DCA
 145         /* cpu for tx queue */
 146         int cpu;
 147 #endif
 148         struct ixgbe_queue_stats stats;
 149         u64 v_idx; /* maps directly to the index for this ring in the hardware
 150                     * vector array, can also be used for finding the bit in EICR
 151                     * and friends that represents the vector for this ring */
 152
 153
 154         u16 work_limit;                /* max work per interrupt */
 155         u16 rx_buf_len;
 156         u64 rsc_count;                 /* stat for coalesced packets */
 157 };
 158
 159 enum ixgbe_ring_f_enum {
 160         RING_F_NONE = 0,
 161         RING_F_DCB,
 162         RING_F_VMDQ,
 163         RING_F_RSS,
 164
 165         RING_F_ARRAY_SIZE      /* must be last in enum set */
 166 };
 167
 168 #define IXGBE_MAX_DCB_INDICES   8
 169 #define IXGBE_MAX_RSS_INDICES  16
 170 #define IXGBE_MAX_VMDQ_INDICES 16
 171 struct ixgbe_ring_feature {
 172         int indices;
 173         int mask;
 174 };
 175
 176 #define MAX_RX_QUEUES 128
 177 #define MAX_TX_QUEUES 128
 178
 179 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 180                               ? 8 : 1)
 181 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 182
 183 /* MAX_MSIX_Q_VECTORS of these are allocated,
 184  * but we only use one per queue-specific vector.
 185  */
 186 struct ixgbe_q_vector {
 187         struct ixgbe_adapter *adapter;
 188         struct napi_struct napi;
 189         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 190         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 191         u8 rxr_count;     /* Rx ring count assigned to this vector */
 192         u8 txr_count;     /* Tx ring count assigned to this vector */
 193         u8 tx_itr;
 194         u8 rx_itr;
 195         u32 eitr;
 196         u32 v_idx;        /* vector index in list */
 197 };
 198
 199 /* Helper macros to switch between ints/sec and what the register uses.
 200  * And yes, it's the same math going both ways.  The lowest value
 201  * supported by all of the ixgbe hardware is 8.
 202  */
 203 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 204         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
 205 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 206
 207 #define IXGBE_DESC_UNUSED(R) \
 208         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 209         (R)->next_to_clean - (R)->next_to_use - 1)
 210
 211 #define IXGBE_RX_DESC_ADV(R, i)     \
 212         (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
 213 #define IXGBE_TX_DESC_ADV(R, i)     \
 214         (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
 215 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 216         (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
 217
 218 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 219
 220 #define OTHER_VECTOR 1
 221 #define NON_Q_VECTORS (OTHER_VECTOR)
 222
 223 #define MAX_MSIX_VECTORS_82599 64
 224 #define MAX_MSIX_Q_VECTORS_82599 64
 225 #define MAX_MSIX_VECTORS_82598 18
 226 #define MAX_MSIX_Q_VECTORS_82598 16
 227
 228 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 229 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 230
 231 #define MIN_MSIX_Q_VECTORS 2
 232 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 233
 234 /* board specific private data structure */
 235 struct ixgbe_adapter {
 236         struct timer_list watchdog_timer;
 237         struct vlan_group *vlgrp;
 238         u16 bd_number;
 239         struct work_struct reset_task;
 240         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 241         char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
 242         struct ixgbe_dcb_config dcb_cfg;
 243         struct ixgbe_dcb_config temp_dcb_cfg;
 244         u8 dcb_set_bitmap;
 245
 246         /* Interrupt Throttle Rate */
 247         u32 itr_setting;
 248         u16 eitr_low;
 249         u16 eitr_high;
 250
 251         /* TX */
 252         struct ixgbe_ring *tx_ring;     /* One per active queue */
 253         int num_tx_queues;
 254         u64 restart_queue;
 255         u64 hw_csum_tx_good;
 256         u64 lsc_int;
 257         u64 hw_tso_ctxt;
 258         u64 hw_tso6_ctxt;
 259         u32 tx_timeout_count;
 260         bool detect_tx_hung;
 261
 262         /* RX */
 263         struct ixgbe_ring *rx_ring;     /* One per active queue */
 264         int num_rx_queues;
 265         u64 hw_csum_rx_error;
 266         u64 hw_rx_no_dma_resources;
 267         u64 hw_csum_rx_good;
 268         u64 non_eop_descs;
 269         int num_msix_vectors;
 270         int max_msix_q_vectors;         /* true count of q_vectors for device */
 271         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 272         struct msix_entry *msix_entries;
 273
 274         u64 rx_hdr_split;
 275         u32 alloc_rx_page_failed;
 276         u32 alloc_rx_buff_failed;
 277
 278         /* Some features need tri-state capability,
 279          * thus the additional *_CAPABLE flags.
 280          */
 281         u32 flags;
 282 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 283 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 284 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 285 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 286 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 287 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 288 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 289 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 290 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 291 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 292 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 293 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 294 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 295 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 296 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 297 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 298 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 299 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 300 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 301 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 302 #define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
 303 #define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 24)
 304 #define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 25)
 305 #define IXGBE_FLAG_RSC_CAPABLE                  (u32)(1 << 26)
 306 #define IXGBE_FLAG_RSC_ENABLED                  (u32)(1 << 27)
 307 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 29)
 308
 309 /* default to trying for four seconds */
 310 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 311
 312         /* OS defined structs */
 313         struct net_device *netdev;
 314         struct pci_dev *pdev;
 315         struct net_device_stats net_stats;
 316
 317         /* structs defined in ixgbe_hw.h */
 318         struct ixgbe_hw hw;
 319         u16 msg_enable;
 320         struct ixgbe_hw_stats stats;
 321
 322         /* Interrupt Throttle Rate */
 323         u32 eitr_param;
 324
 325         unsigned long state;
 326         u64 tx_busy;
 327         unsigned int tx_ring_count;
 328         unsigned int rx_ring_count;
 329
 330         u32 link_speed;
 331         bool link_up;
 332         unsigned long link_check_timeout;
 333
 334         struct work_struct watchdog_task;
 335         struct work_struct sfp_task;
 336         struct timer_list sfp_timer;
 337         struct work_struct multispeed_fiber_task;
 338         struct work_struct sfp_config_module_task;
 339 #ifdef IXGBE_FCOE
 340         struct ixgbe_fcoe fcoe;
 341 #endif /* IXGBE_FCOE */
 342         u64 rsc_count;
 343         u32 wol;
 344         u16 eeprom_version;
 345 };
 346
 347 enum ixbge_state_t {
 348         __IXGBE_TESTING,
 349         __IXGBE_RESETTING,
 350         __IXGBE_DOWN,
 351         __IXGBE_SFP_MODULE_NOT_FOUND
 352 };
 353
 354 enum ixgbe_boards {
 355         board_82598,
 356         board_82599,
 357 };
 358
 359 extern struct ixgbe_info ixgbe_82598_info;
 360 extern struct ixgbe_info ixgbe_82599_info;
 361 #ifdef CONFIG_IXGBE_DCB
 362 extern struct dcbnl_rtnl_ops dcbnl_ops;
 363 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 364                               struct ixgbe_dcb_config *dst_dcb_cfg,
 365                               int tc_max);
 366 #endif
 367
 368 extern char ixgbe_driver_name[];
 369 extern const char ixgbe_driver_version[];
 370
 371 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 372 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 373 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 374 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 375 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 376 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 377 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 378 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 379 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 380 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 381 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 382 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 383 extern void ixgbe_write_eitr(struct ixgbe_adapter *, int, u32);
 384 #ifdef IXGBE_FCOE
 385 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 386 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
 387                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 388                      u32 tx_flags, u8 *hdr_len);
 389 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 390 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 391                           union ixgbe_adv_rx_desc *rx_desc,
 392                           struct sk_buff *skb);
 393 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 394                               struct scatterlist *sgl, unsigned int sgc);
 395 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 396 #endif /* IXGBE_FCOE */
 397
 398 #endif /* _IXGBE_H_ */