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i386: move kernel/cpu/mtrr
[linux-2.6/kvm.git] / drivers / net / r8169.c
blobc76dd29c8e9a1ef8f17d60067c08a2c970d788e8
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #ifdef CONFIG_R8169_NAPI
32 #define NAPI_SUFFIX "-NAPI"
33 #else
34 #define NAPI_SUFFIX ""
35 #endif
36
37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38 #define MODULENAME "r8169"
39 #define PFX MODULENAME ": "
40
41 #ifdef RTL8169_DEBUG
42 #define assert(expr) \
43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
47 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
48 #else
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
52
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
55
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59 #ifdef CONFIG_R8169_NAPI
60 #define rtl8169_rx_skb netif_receive_skb
61 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
62 #define rtl8169_rx_quota(count, quota) min(count, quota)
63 #else
64 #define rtl8169_rx_skb netif_rx
65 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
66 #define rtl8169_rx_quota(count, quota) count
67 #endif
68
69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
70 static const int max_interrupt_work = 20;
71
72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
74 static const int multicast_filter_limit = 32;
75
76 /* MAC address length */
77 #define MAC_ADDR_LEN 6
78
79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86
87 #define R8169_REGS_SIZE 256
88 #define R8169_NAPI_WEIGHT 64
89 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
92 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
94
95 #define RTL8169_TX_TIMEOUT (6*HZ)
96 #define RTL8169_PHY_TIMEOUT (10*HZ)
97
98 /* write/read MMIO register */
99 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102 #define RTL_R8(reg) readb (ioaddr + (reg))
103 #define RTL_R16(reg) readw (ioaddr + (reg))
104 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
105
106 enum mac_version {
107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
118 };
119
120 enum phy_version {
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
127 };
128
129 #define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131
132 static const struct {
133 const char *name;
134 u8 mac_version;
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136 } rtl_chip_info[] = {
137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
148 };
149 #undef _R
150
151 enum cfg_version {
152 RTL_CFG_0 = 0x00,
153 RTL_CFG_1,
154 RTL_CFG_2
155 };
156
157 static void rtl_hw_start_8169(struct net_device *);
158 static void rtl_hw_start_8168(struct net_device *);
159 static void rtl_hw_start_8101(struct net_device *);
160
161 static struct pci_device_id rtl8169_pci_tbl[] = {
162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
172 {0,},
173 };
174
175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176
177 static int rx_copybreak = 200;
178 static int use_dac;
179 static struct {
180 u32 msg_enable;
181 } debug = { -1 };
182
183 enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
185 MAC4 = 4,
186 MAR0 = 8, /* Multicast filter. */
187 CounterAddrLow = 0x10,
188 CounterAddrHigh = 0x14,
189 TxDescStartAddrLow = 0x20,
190 TxDescStartAddrHigh = 0x24,
191 TxHDescStartAddrLow = 0x28,
192 TxHDescStartAddrHigh = 0x2c,
193 FLASH = 0x30,
194 ERSR = 0x36,
195 ChipCmd = 0x37,
196 TxPoll = 0x38,
197 IntrMask = 0x3c,
198 IntrStatus = 0x3e,
199 TxConfig = 0x40,
200 RxConfig = 0x44,
201 RxMissed = 0x4c,
202 Cfg9346 = 0x50,
203 Config0 = 0x51,
204 Config1 = 0x52,
205 Config2 = 0x53,
206 Config3 = 0x54,
207 Config4 = 0x55,
208 Config5 = 0x56,
209 MultiIntr = 0x5c,
210 PHYAR = 0x60,
211 TBICSR = 0x64,
212 TBI_ANAR = 0x68,
213 TBI_LPAR = 0x6a,
214 PHYstatus = 0x6c,
215 RxMaxSize = 0xda,
216 CPlusCmd = 0xe0,
217 IntrMitigate = 0xe2,
218 RxDescAddrLow = 0xe4,
219 RxDescAddrHigh = 0xe8,
220 EarlyTxThres = 0xec,
221 FuncEvent = 0xf0,
222 FuncEventMask = 0xf4,
223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
225 };
226
227 enum rtl_register_content {
228 /* InterruptStatusBits */
229 SYSErr = 0x8000,
230 PCSTimeout = 0x4000,
231 SWInt = 0x0100,
232 TxDescUnavail = 0x0080,
233 RxFIFOOver = 0x0040,
234 LinkChg = 0x0020,
235 RxOverflow = 0x0010,
236 TxErr = 0x0008,
237 TxOK = 0x0004,
238 RxErr = 0x0002,
239 RxOK = 0x0001,
240
241 /* RxStatusDesc */
242 RxFOVF = (1 << 23),
243 RxRWT = (1 << 22),
244 RxRES = (1 << 21),
245 RxRUNT = (1 << 20),
246 RxCRC = (1 << 19),
247
248 /* ChipCmdBits */
249 CmdReset = 0x10,
250 CmdRxEnb = 0x08,
251 CmdTxEnb = 0x04,
252 RxBufEmpty = 0x01,
253
254 /* TXPoll register p.5 */
255 HPQ = 0x80, /* Poll cmd on the high prio queue */
256 NPQ = 0x40, /* Poll cmd on the low prio queue */
257 FSWInt = 0x01, /* Forced software interrupt */
258
259 /* Cfg9346Bits */
260 Cfg9346_Lock = 0x00,
261 Cfg9346_Unlock = 0xc0,
262
263 /* rx_mode_bits */
264 AcceptErr = 0x20,
265 AcceptRunt = 0x10,
266 AcceptBroadcast = 0x08,
267 AcceptMulticast = 0x04,
268 AcceptMyPhys = 0x02,
269 AcceptAllPhys = 0x01,
270
271 /* RxConfigBits */
272 RxCfgFIFOShift = 13,
273 RxCfgDMAShift = 8,
274
275 /* TxConfigBits */
276 TxInterFrameGapShift = 24,
277 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
278
279 /* Config1 register p.24 */
280 PMEnable = (1 << 0), /* Power Management Enable */
281
282 /* Config2 register p. 25 */
283 PCI_Clock_66MHz = 0x01,
284 PCI_Clock_33MHz = 0x00,
285
286 /* Config3 register p.25 */
287 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
288 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
289
290 /* Config5 register p.27 */
291 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
292 MWF = (1 << 5), /* Accept Multicast wakeup frame */
293 UWF = (1 << 4), /* Accept Unicast wakeup frame */
294 LanWake = (1 << 1), /* LanWake enable/disable */
295 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
296
297 /* TBICSR p.28 */
298 TBIReset = 0x80000000,
299 TBILoopback = 0x40000000,
300 TBINwEnable = 0x20000000,
301 TBINwRestart = 0x10000000,
302 TBILinkOk = 0x02000000,
303 TBINwComplete = 0x01000000,
304
305 /* CPlusCmd p.31 */
306 PktCntrDisable = (1 << 7), // 8168
307 RxVlan = (1 << 6),
308 RxChkSum = (1 << 5),
309 PCIDAC = (1 << 4),
310 PCIMulRW = (1 << 3),
311 INTT_0 = 0x0000, // 8168
312 INTT_1 = 0x0001, // 8168
313 INTT_2 = 0x0002, // 8168
314 INTT_3 = 0x0003, // 8168
315
316 /* rtl8169_PHYstatus */
317 TBI_Enable = 0x80,
318 TxFlowCtrl = 0x40,
319 RxFlowCtrl = 0x20,
320 _1000bpsF = 0x10,
321 _100bps = 0x08,
322 _10bps = 0x04,
323 LinkStatus = 0x02,
324 FullDup = 0x01,
325
326 /* _TBICSRBit */
327 TBILinkOK = 0x02000000,
328
329 /* DumpCounterCommand */
330 CounterDump = 0x8,
331 };
332
333 enum desc_status_bit {
334 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
335 RingEnd = (1 << 30), /* End of descriptor ring */
336 FirstFrag = (1 << 29), /* First segment of a packet */
337 LastFrag = (1 << 28), /* Final segment of a packet */
338
339 /* Tx private */
340 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
341 MSSShift = 16, /* MSS value position */
342 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
343 IPCS = (1 << 18), /* Calculate IP checksum */
344 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
345 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
346 TxVlanTag = (1 << 17), /* Add VLAN tag */
347
348 /* Rx private */
349 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
350 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
351
352 #define RxProtoUDP (PID1)
353 #define RxProtoTCP (PID0)
354 #define RxProtoIP (PID1 | PID0)
355 #define RxProtoMask RxProtoIP
356
357 IPFail = (1 << 16), /* IP checksum failed */
358 UDPFail = (1 << 15), /* UDP/IP checksum failed */
359 TCPFail = (1 << 14), /* TCP/IP checksum failed */
360 RxVlanTag = (1 << 16), /* VLAN tag available */
361 };
362
363 #define RsvdMask 0x3fffc000
364
365 struct TxDesc {
366 __le32 opts1;
367 __le32 opts2;
368 __le64 addr;
369 };
370
371 struct RxDesc {
372 __le32 opts1;
373 __le32 opts2;
374 __le64 addr;
375 };
376
377 struct ring_info {
378 struct sk_buff *skb;
379 u32 len;
380 u8 __pad[sizeof(void *) - sizeof(u32)];
381 };
382
383 struct rtl8169_private {
384 void __iomem *mmio_addr; /* memory map physical address */
385 struct pci_dev *pci_dev; /* Index of PCI device */
386 struct net_device *dev;
387 struct net_device_stats stats; /* statistics of net device */
388 spinlock_t lock; /* spin lock flag */
389 u32 msg_enable;
390 int chipset;
391 int mac_version;
392 int phy_version;
393 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
394 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
395 u32 dirty_rx;
396 u32 dirty_tx;
397 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
398 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
399 dma_addr_t TxPhyAddr;
400 dma_addr_t RxPhyAddr;
401 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
402 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
403 unsigned align;
404 unsigned rx_buf_sz;
405 struct timer_list timer;
406 u16 cp_cmd;
407 u16 intr_event;
408 u16 napi_event;
409 u16 intr_mask;
410 int phy_auto_nego_reg;
411 int phy_1000_ctrl_reg;
412 #ifdef CONFIG_R8169_VLAN
413 struct vlan_group *vlgrp;
414 #endif
415 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
416 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
417 void (*phy_reset_enable)(void __iomem *);
418 void (*hw_start)(struct net_device *);
419 unsigned int (*phy_reset_pending)(void __iomem *);
420 unsigned int (*link_ok)(void __iomem *);
421 struct delayed_work task;
422 unsigned wol_enabled : 1;
423 };
424
425 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
426 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
427 module_param(rx_copybreak, int, 0);
428 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
429 module_param(use_dac, int, 0);
430 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
431 module_param_named(debug, debug.msg_enable, int, 0);
432 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
433 MODULE_LICENSE("GPL");
434 MODULE_VERSION(RTL8169_VERSION);
435
436 static int rtl8169_open(struct net_device *dev);
437 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
438 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
439 static int rtl8169_init_ring(struct net_device *dev);
440 static void rtl_hw_start(struct net_device *dev);
441 static int rtl8169_close(struct net_device *dev);
442 static void rtl_set_rx_mode(struct net_device *dev);
443 static void rtl8169_tx_timeout(struct net_device *dev);
444 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
445 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
446 void __iomem *);
447 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
448 static void rtl8169_down(struct net_device *dev);
449 static void rtl8169_rx_clear(struct rtl8169_private *tp);
450
451 #ifdef CONFIG_R8169_NAPI
452 static int rtl8169_poll(struct net_device *dev, int *budget);
453 #endif
454
455 static const unsigned int rtl8169_rx_config =
456 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
457
458 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
459 {
460 int i;
461
462 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
463
464 for (i = 20; i > 0; i--) {
465 /*
466 * Check if the RTL8169 has completed writing to the specified
467 * MII register.
468 */
469 if (!(RTL_R32(PHYAR) & 0x80000000))
470 break;
471 udelay(25);
472 }
473 }
474
475 static int mdio_read(void __iomem *ioaddr, int reg_addr)
476 {
477 int i, value = -1;
478
479 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
480
481 for (i = 20; i > 0; i--) {
482 /*
483 * Check if the RTL8169 has completed retrieving data from
484 * the specified MII register.
485 */
486 if (RTL_R32(PHYAR) & 0x80000000) {
487 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
488 break;
489 }
490 udelay(25);
491 }
492 return value;
493 }
494
495 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
496 {
497 RTL_W16(IntrMask, 0x0000);
498
499 RTL_W16(IntrStatus, 0xffff);
500 }
501
502 static void rtl8169_asic_down(void __iomem *ioaddr)
503 {
504 RTL_W8(ChipCmd, 0x00);
505 rtl8169_irq_mask_and_ack(ioaddr);
506 RTL_R16(CPlusCmd);
507 }
508
509 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
510 {
511 return RTL_R32(TBICSR) & TBIReset;
512 }
513
514 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
515 {
516 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
517 }
518
519 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
520 {
521 return RTL_R32(TBICSR) & TBILinkOk;
522 }
523
524 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
525 {
526 return RTL_R8(PHYstatus) & LinkStatus;
527 }
528
529 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
530 {
531 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
532 }
533
534 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
535 {
536 unsigned int val;
537
538 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
539 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
540 }
541
542 static void rtl8169_check_link_status(struct net_device *dev,
543 struct rtl8169_private *tp,
544 void __iomem *ioaddr)
545 {
546 unsigned long flags;
547
548 spin_lock_irqsave(&tp->lock, flags);
549 if (tp->link_ok(ioaddr)) {
550 netif_carrier_on(dev);
551 if (netif_msg_ifup(tp))
552 printk(KERN_INFO PFX "%s: link up\n", dev->name);
553 } else {
554 if (netif_msg_ifdown(tp))
555 printk(KERN_INFO PFX "%s: link down\n", dev->name);
556 netif_carrier_off(dev);
557 }
558 spin_unlock_irqrestore(&tp->lock, flags);
559 }
560
561 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
562 {
563 struct rtl8169_private *tp = netdev_priv(dev);
564 void __iomem *ioaddr = tp->mmio_addr;
565 u8 options;
566
567 wol->wolopts = 0;
568
569 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
570 wol->supported = WAKE_ANY;
571
572 spin_lock_irq(&tp->lock);
573
574 options = RTL_R8(Config1);
575 if (!(options & PMEnable))
576 goto out_unlock;
577
578 options = RTL_R8(Config3);
579 if (options & LinkUp)
580 wol->wolopts |= WAKE_PHY;
581 if (options & MagicPacket)
582 wol->wolopts |= WAKE_MAGIC;
583
584 options = RTL_R8(Config5);
585 if (options & UWF)
586 wol->wolopts |= WAKE_UCAST;
587 if (options & BWF)
588 wol->wolopts |= WAKE_BCAST;
589 if (options & MWF)
590 wol->wolopts |= WAKE_MCAST;
591
592 out_unlock:
593 spin_unlock_irq(&tp->lock);
594 }
595
596 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
597 {
598 struct rtl8169_private *tp = netdev_priv(dev);
599 void __iomem *ioaddr = tp->mmio_addr;
600 unsigned int i;
601 static struct {
602 u32 opt;
603 u16 reg;
604 u8 mask;
605 } cfg[] = {
606 { WAKE_ANY, Config1, PMEnable },
607 { WAKE_PHY, Config3, LinkUp },
608 { WAKE_MAGIC, Config3, MagicPacket },
609 { WAKE_UCAST, Config5, UWF },
610 { WAKE_BCAST, Config5, BWF },
611 { WAKE_MCAST, Config5, MWF },
612 { WAKE_ANY, Config5, LanWake }
613 };
614
615 spin_lock_irq(&tp->lock);
616
617 RTL_W8(Cfg9346, Cfg9346_Unlock);
618
619 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
620 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
621 if (wol->wolopts & cfg[i].opt)
622 options |= cfg[i].mask;
623 RTL_W8(cfg[i].reg, options);
624 }
625
626 RTL_W8(Cfg9346, Cfg9346_Lock);
627
628 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
629
630 spin_unlock_irq(&tp->lock);
631
632 return 0;
633 }
634
635 static void rtl8169_get_drvinfo(struct net_device *dev,
636 struct ethtool_drvinfo *info)
637 {
638 struct rtl8169_private *tp = netdev_priv(dev);
639
640 strcpy(info->driver, MODULENAME);
641 strcpy(info->version, RTL8169_VERSION);
642 strcpy(info->bus_info, pci_name(tp->pci_dev));
643 }
644
645 static int rtl8169_get_regs_len(struct net_device *dev)
646 {
647 return R8169_REGS_SIZE;
648 }
649
650 static int rtl8169_set_speed_tbi(struct net_device *dev,
651 u8 autoneg, u16 speed, u8 duplex)
652 {
653 struct rtl8169_private *tp = netdev_priv(dev);
654 void __iomem *ioaddr = tp->mmio_addr;
655 int ret = 0;
656 u32 reg;
657
658 reg = RTL_R32(TBICSR);
659 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
660 (duplex == DUPLEX_FULL)) {
661 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
662 } else if (autoneg == AUTONEG_ENABLE)
663 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
664 else {
665 if (netif_msg_link(tp)) {
666 printk(KERN_WARNING "%s: "
667 "incorrect speed setting refused in TBI mode\n",
668 dev->name);
669 }
670 ret = -EOPNOTSUPP;
671 }
672
673 return ret;
674 }
675
676 static int rtl8169_set_speed_xmii(struct net_device *dev,
677 u8 autoneg, u16 speed, u8 duplex)
678 {
679 struct rtl8169_private *tp = netdev_priv(dev);
680 void __iomem *ioaddr = tp->mmio_addr;
681 int auto_nego, giga_ctrl;
682
683 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
684 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
685 ADVERTISE_100HALF | ADVERTISE_100FULL);
686 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
687 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
688
689 if (autoneg == AUTONEG_ENABLE) {
690 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
691 ADVERTISE_100HALF | ADVERTISE_100FULL);
692 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
693 } else {
694 if (speed == SPEED_10)
695 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
696 else if (speed == SPEED_100)
697 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
698 else if (speed == SPEED_1000)
699 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
700
701 if (duplex == DUPLEX_HALF)
702 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
703
704 if (duplex == DUPLEX_FULL)
705 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
706
707 /* This tweak comes straight from Realtek's driver. */
708 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
709 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
710 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
711 }
712 }
713
714 /* The 8100e/8101e do Fast Ethernet only. */
715 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
716 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
717 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
718 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
719 netif_msg_link(tp)) {
720 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
721 dev->name);
722 }
723 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
724 }
725
726 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
727
728 if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
729 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
730 mdio_write(ioaddr, 0x1f, 0x0000);
731 mdio_write(ioaddr, 0x0e, 0x0000);
732 }
733
734 tp->phy_auto_nego_reg = auto_nego;
735 tp->phy_1000_ctrl_reg = giga_ctrl;
736
737 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
738 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
739 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
740 return 0;
741 }
742
743 static int rtl8169_set_speed(struct net_device *dev,
744 u8 autoneg, u16 speed, u8 duplex)
745 {
746 struct rtl8169_private *tp = netdev_priv(dev);
747 int ret;
748
749 ret = tp->set_speed(dev, autoneg, speed, duplex);
750
751 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
752 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
753
754 return ret;
755 }
756
757 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
758 {
759 struct rtl8169_private *tp = netdev_priv(dev);
760 unsigned long flags;
761 int ret;
762
763 spin_lock_irqsave(&tp->lock, flags);
764 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
765 spin_unlock_irqrestore(&tp->lock, flags);
766
767 return ret;
768 }
769
770 static u32 rtl8169_get_rx_csum(struct net_device *dev)
771 {
772 struct rtl8169_private *tp = netdev_priv(dev);
773
774 return tp->cp_cmd & RxChkSum;
775 }
776
777 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
778 {
779 struct rtl8169_private *tp = netdev_priv(dev);
780 void __iomem *ioaddr = tp->mmio_addr;
781 unsigned long flags;
782
783 spin_lock_irqsave(&tp->lock, flags);
784
785 if (data)
786 tp->cp_cmd |= RxChkSum;
787 else
788 tp->cp_cmd &= ~RxChkSum;
789
790 RTL_W16(CPlusCmd, tp->cp_cmd);
791 RTL_R16(CPlusCmd);
792
793 spin_unlock_irqrestore(&tp->lock, flags);
794
795 return 0;
796 }
797
798 #ifdef CONFIG_R8169_VLAN
799
800 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
801 struct sk_buff *skb)
802 {
803 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
804 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
805 }
806
807 static void rtl8169_vlan_rx_register(struct net_device *dev,
808 struct vlan_group *grp)
809 {
810 struct rtl8169_private *tp = netdev_priv(dev);
811 void __iomem *ioaddr = tp->mmio_addr;
812 unsigned long flags;
813
814 spin_lock_irqsave(&tp->lock, flags);
815 tp->vlgrp = grp;
816 if (tp->vlgrp)
817 tp->cp_cmd |= RxVlan;
818 else
819 tp->cp_cmd &= ~RxVlan;
820 RTL_W16(CPlusCmd, tp->cp_cmd);
821 RTL_R16(CPlusCmd);
822 spin_unlock_irqrestore(&tp->lock, flags);
823 }
824
825 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
826 struct sk_buff *skb)
827 {
828 u32 opts2 = le32_to_cpu(desc->opts2);
829 int ret;
830
831 if (tp->vlgrp && (opts2 & RxVlanTag)) {
832 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
833 ret = 0;
834 } else
835 ret = -1;
836 desc->opts2 = 0;
837 return ret;
838 }
839
840 #else /* !CONFIG_R8169_VLAN */
841
842 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
843 struct sk_buff *skb)
844 {
845 return 0;
846 }
847
848 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
849 struct sk_buff *skb)
850 {
851 return -1;
852 }
853
854 #endif
855
856 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
857 {
858 struct rtl8169_private *tp = netdev_priv(dev);
859 void __iomem *ioaddr = tp->mmio_addr;
860 u32 status;
861
862 cmd->supported =
863 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
864 cmd->port = PORT_FIBRE;
865 cmd->transceiver = XCVR_INTERNAL;
866
867 status = RTL_R32(TBICSR);
868 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
869 cmd->autoneg = !!(status & TBINwEnable);
870
871 cmd->speed = SPEED_1000;
872 cmd->duplex = DUPLEX_FULL; /* Always set */
873 }
874
875 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
876 {
877 struct rtl8169_private *tp = netdev_priv(dev);
878 void __iomem *ioaddr = tp->mmio_addr;
879 u8 status;
880
881 cmd->supported = SUPPORTED_10baseT_Half |
882 SUPPORTED_10baseT_Full |
883 SUPPORTED_100baseT_Half |
884 SUPPORTED_100baseT_Full |
885 SUPPORTED_1000baseT_Full |
886 SUPPORTED_Autoneg |
887 SUPPORTED_TP;
888
889 cmd->autoneg = 1;
890 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
891
892 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
893 cmd->advertising |= ADVERTISED_10baseT_Half;
894 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
895 cmd->advertising |= ADVERTISED_10baseT_Full;
896 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
897 cmd->advertising |= ADVERTISED_100baseT_Half;
898 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
899 cmd->advertising |= ADVERTISED_100baseT_Full;
900 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
901 cmd->advertising |= ADVERTISED_1000baseT_Full;
902
903 status = RTL_R8(PHYstatus);
904
905 if (status & _1000bpsF)
906 cmd->speed = SPEED_1000;
907 else if (status & _100bps)
908 cmd->speed = SPEED_100;
909 else if (status & _10bps)
910 cmd->speed = SPEED_10;
911
912 if (status & TxFlowCtrl)
913 cmd->advertising |= ADVERTISED_Asym_Pause;
914 if (status & RxFlowCtrl)
915 cmd->advertising |= ADVERTISED_Pause;
916
917 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
918 DUPLEX_FULL : DUPLEX_HALF;
919 }
920
921 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
922 {
923 struct rtl8169_private *tp = netdev_priv(dev);
924 unsigned long flags;
925
926 spin_lock_irqsave(&tp->lock, flags);
927
928 tp->get_settings(dev, cmd);
929
930 spin_unlock_irqrestore(&tp->lock, flags);
931 return 0;
932 }
933
934 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
935 void *p)
936 {
937 struct rtl8169_private *tp = netdev_priv(dev);
938 unsigned long flags;
939
940 if (regs->len > R8169_REGS_SIZE)
941 regs->len = R8169_REGS_SIZE;
942
943 spin_lock_irqsave(&tp->lock, flags);
944 memcpy_fromio(p, tp->mmio_addr, regs->len);
945 spin_unlock_irqrestore(&tp->lock, flags);
946 }
947
948 static u32 rtl8169_get_msglevel(struct net_device *dev)
949 {
950 struct rtl8169_private *tp = netdev_priv(dev);
951
952 return tp->msg_enable;
953 }
954
955 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
956 {
957 struct rtl8169_private *tp = netdev_priv(dev);
958
959 tp->msg_enable = value;
960 }
961
962 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
963 "tx_packets",
964 "rx_packets",
965 "tx_errors",
966 "rx_errors",
967 "rx_missed",
968 "align_errors",
969 "tx_single_collisions",
970 "tx_multi_collisions",
971 "unicast",
972 "broadcast",
973 "multicast",
974 "tx_aborted",
975 "tx_underrun",
976 };
977
978 struct rtl8169_counters {
979 u64 tx_packets;
980 u64 rx_packets;
981 u64 tx_errors;
982 u32 rx_errors;
983 u16 rx_missed;
984 u16 align_errors;
985 u32 tx_one_collision;
986 u32 tx_multi_collision;
987 u64 rx_unicast;
988 u64 rx_broadcast;
989 u32 rx_multicast;
990 u16 tx_aborted;
991 u16 tx_underun;
992 };
993
994 static int rtl8169_get_stats_count(struct net_device *dev)
995 {
996 return ARRAY_SIZE(rtl8169_gstrings);
997 }
998
999 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1000 struct ethtool_stats *stats, u64 *data)
1001 {
1002 struct rtl8169_private *tp = netdev_priv(dev);
1003 void __iomem *ioaddr = tp->mmio_addr;
1004 struct rtl8169_counters *counters;
1005 dma_addr_t paddr;
1006 u32 cmd;
1007
1008 ASSERT_RTNL();
1009
1010 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1011 if (!counters)
1012 return;
1013
1014 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1015 cmd = (u64)paddr & DMA_32BIT_MASK;
1016 RTL_W32(CounterAddrLow, cmd);
1017 RTL_W32(CounterAddrLow, cmd | CounterDump);
1018
1019 while (RTL_R32(CounterAddrLow) & CounterDump) {
1020 if (msleep_interruptible(1))
1021 break;
1022 }
1023
1024 RTL_W32(CounterAddrLow, 0);
1025 RTL_W32(CounterAddrHigh, 0);
1026
1027 data[0] = le64_to_cpu(counters->tx_packets);
1028 data[1] = le64_to_cpu(counters->rx_packets);
1029 data[2] = le64_to_cpu(counters->tx_errors);
1030 data[3] = le32_to_cpu(counters->rx_errors);
1031 data[4] = le16_to_cpu(counters->rx_missed);
1032 data[5] = le16_to_cpu(counters->align_errors);
1033 data[6] = le32_to_cpu(counters->tx_one_collision);
1034 data[7] = le32_to_cpu(counters->tx_multi_collision);
1035 data[8] = le64_to_cpu(counters->rx_unicast);
1036 data[9] = le64_to_cpu(counters->rx_broadcast);
1037 data[10] = le32_to_cpu(counters->rx_multicast);
1038 data[11] = le16_to_cpu(counters->tx_aborted);
1039 data[12] = le16_to_cpu(counters->tx_underun);
1040
1041 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1042 }
1043
1044 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1045 {
1046 switch(stringset) {
1047 case ETH_SS_STATS:
1048 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1049 break;
1050 }
1051 }
1052
1053 static const struct ethtool_ops rtl8169_ethtool_ops = {
1054 .get_drvinfo = rtl8169_get_drvinfo,
1055 .get_regs_len = rtl8169_get_regs_len,
1056 .get_link = ethtool_op_get_link,
1057 .get_settings = rtl8169_get_settings,
1058 .set_settings = rtl8169_set_settings,
1059 .get_msglevel = rtl8169_get_msglevel,
1060 .set_msglevel = rtl8169_set_msglevel,
1061 .get_rx_csum = rtl8169_get_rx_csum,
1062 .set_rx_csum = rtl8169_set_rx_csum,
1063 .get_tx_csum = ethtool_op_get_tx_csum,
1064 .set_tx_csum = ethtool_op_set_tx_csum,
1065 .get_sg = ethtool_op_get_sg,
1066 .set_sg = ethtool_op_set_sg,
1067 .get_tso = ethtool_op_get_tso,
1068 .set_tso = ethtool_op_set_tso,
1069 .get_regs = rtl8169_get_regs,
1070 .get_wol = rtl8169_get_wol,
1071 .set_wol = rtl8169_set_wol,
1072 .get_strings = rtl8169_get_strings,
1073 .get_stats_count = rtl8169_get_stats_count,
1074 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1075 };
1076
1077 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1078 int bitnum, int bitval)
1079 {
1080 int val;
1081
1082 val = mdio_read(ioaddr, reg);
1083 val = (bitval == 1) ?
1084 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1085 mdio_write(ioaddr, reg, val & 0xffff);
1086 }
1087
1088 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1089 void __iomem *ioaddr)
1090 {
1091 /*
1092 * The driver currently handles the 8168Bf and the 8168Be identically
1093 * but they can be identified more specifically through the test below
1094 * if needed:
1095 *
1096 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1097 *
1098 * Same thing for the 8101Eb and the 8101Ec:
1099 *
1100 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1101 */
1102 const struct {
1103 u32 mask;
1104 int mac_version;
1105 } mac_info[] = {
1106 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1107 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1108 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1109 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1110 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1111 { 0x98000000, RTL_GIGA_MAC_VER_06 },
1112 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1113 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1114 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1115 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1116 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1117 }, *p = mac_info;
1118 u32 reg;
1119
1120 reg = RTL_R32(TxConfig) & 0xfc800000;
1121 while ((reg & p->mask) != p->mask)
1122 p++;
1123 tp->mac_version = p->mac_version;
1124 }
1125
1126 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1127 {
1128 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1129 }
1130
1131 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1132 void __iomem *ioaddr)
1133 {
1134 const struct {
1135 u16 mask;
1136 u16 set;
1137 int phy_version;
1138 } phy_info[] = {
1139 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1140 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1141 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1142 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1143 }, *p = phy_info;
1144 u16 reg;
1145
1146 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1147 while ((reg & p->mask) != p->set)
1148 p++;
1149 tp->phy_version = p->phy_version;
1150 }
1151
1152 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1153 {
1154 struct {
1155 int version;
1156 char *msg;
1157 u32 reg;
1158 } phy_print[] = {
1159 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1160 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1161 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1162 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1163 { 0, NULL, 0x0000 }
1164 }, *p;
1165
1166 for (p = phy_print; p->msg; p++) {
1167 if (tp->phy_version == p->version) {
1168 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1169 return;
1170 }
1171 }
1172 dprintk("phy_version == Unknown\n");
1173 }
1174
1175 static void rtl8169_hw_phy_config(struct net_device *dev)
1176 {
1177 struct rtl8169_private *tp = netdev_priv(dev);
1178 void __iomem *ioaddr = tp->mmio_addr;
1179 struct {
1180 u16 regs[5]; /* Beware of bit-sign propagation */
1181 } phy_magic[5] = { {
1182 { 0x0000, //w 4 15 12 0
1183 0x00a1, //w 3 15 0 00a1
1184 0x0008, //w 2 15 0 0008
1185 0x1020, //w 1 15 0 1020
1186 0x1000 } },{ //w 0 15 0 1000
1187 { 0x7000, //w 4 15 12 7
1188 0xff41, //w 3 15 0 ff41
1189 0xde60, //w 2 15 0 de60
1190 0x0140, //w 1 15 0 0140
1191 0x0077 } },{ //w 0 15 0 0077
1192 { 0xa000, //w 4 15 12 a
1193 0xdf01, //w 3 15 0 df01
1194 0xdf20, //w 2 15 0 df20
1195 0xff95, //w 1 15 0 ff95
1196 0xfa00 } },{ //w 0 15 0 fa00
1197 { 0xb000, //w 4 15 12 b
1198 0xff41, //w 3 15 0 ff41
1199 0xde20, //w 2 15 0 de20
1200 0x0140, //w 1 15 0 0140
1201 0x00bb } },{ //w 0 15 0 00bb
1202 { 0xf000, //w 4 15 12 f
1203 0xdf01, //w 3 15 0 df01
1204 0xdf20, //w 2 15 0 df20
1205 0xff95, //w 1 15 0 ff95
1206 0xbf00 } //w 0 15 0 bf00
1207 }
1208 }, *p = phy_magic;
1209 unsigned int i;
1210
1211 rtl8169_print_mac_version(tp);
1212 rtl8169_print_phy_version(tp);
1213
1214 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1215 return;
1216 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1217 return;
1218
1219 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1220 dprintk("Do final_reg2.cfg\n");
1221
1222 /* Shazam ! */
1223
1224 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1225 mdio_write(ioaddr, 31, 0x0002);
1226 mdio_write(ioaddr, 1, 0x90d0);
1227 mdio_write(ioaddr, 31, 0x0000);
1228 return;
1229 }
1230
1231 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1232 (tp->mac_version != RTL_GIGA_MAC_VER_03))
1233 return;
1234
1235 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1236 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1237 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1238 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1239
1240 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1241 int val, pos = 4;
1242
1243 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1244 mdio_write(ioaddr, pos, val);
1245 while (--pos >= 0)
1246 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1247 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1248 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1249 }
1250 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1251 }
1252
1253 static void rtl8169_phy_timer(unsigned long __opaque)
1254 {
1255 struct net_device *dev = (struct net_device *)__opaque;
1256 struct rtl8169_private *tp = netdev_priv(dev);
1257 struct timer_list *timer = &tp->timer;
1258 void __iomem *ioaddr = tp->mmio_addr;
1259 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1260
1261 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1262 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1263
1264 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1265 return;
1266
1267 spin_lock_irq(&tp->lock);
1268
1269 if (tp->phy_reset_pending(ioaddr)) {
1270 /*
1271 * A busy loop could burn quite a few cycles on nowadays CPU.
1272 * Let's delay the execution of the timer for a few ticks.
1273 */
1274 timeout = HZ/10;
1275 goto out_mod_timer;
1276 }
1277
1278 if (tp->link_ok(ioaddr))
1279 goto out_unlock;
1280
1281 if (netif_msg_link(tp))
1282 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1283
1284 tp->phy_reset_enable(ioaddr);
1285
1286 out_mod_timer:
1287 mod_timer(timer, jiffies + timeout);
1288 out_unlock:
1289 spin_unlock_irq(&tp->lock);
1290 }
1291
1292 static inline void rtl8169_delete_timer(struct net_device *dev)
1293 {
1294 struct rtl8169_private *tp = netdev_priv(dev);
1295 struct timer_list *timer = &tp->timer;
1296
1297 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1298 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1299 return;
1300
1301 del_timer_sync(timer);
1302 }
1303
1304 static inline void rtl8169_request_timer(struct net_device *dev)
1305 {
1306 struct rtl8169_private *tp = netdev_priv(dev);
1307 struct timer_list *timer = &tp->timer;
1308
1309 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1310 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1311 return;
1312
1313 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1314 }
1315
1316 #ifdef CONFIG_NET_POLL_CONTROLLER
1317 /*
1318 * Polling 'interrupt' - used by things like netconsole to send skbs
1319 * without having to re-enable interrupts. It's not called while
1320 * the interrupt routine is executing.
1321 */
1322 static void rtl8169_netpoll(struct net_device *dev)
1323 {
1324 struct rtl8169_private *tp = netdev_priv(dev);
1325 struct pci_dev *pdev = tp->pci_dev;
1326
1327 disable_irq(pdev->irq);
1328 rtl8169_interrupt(pdev->irq, dev);
1329 enable_irq(pdev->irq);
1330 }
1331 #endif
1332
1333 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1334 void __iomem *ioaddr)
1335 {
1336 iounmap(ioaddr);
1337 pci_release_regions(pdev);
1338 pci_disable_device(pdev);
1339 free_netdev(dev);
1340 }
1341
1342 static void rtl8169_phy_reset(struct net_device *dev,
1343 struct rtl8169_private *tp)
1344 {
1345 void __iomem *ioaddr = tp->mmio_addr;
1346 unsigned int i;
1347
1348 tp->phy_reset_enable(ioaddr);
1349 for (i = 0; i < 100; i++) {
1350 if (!tp->phy_reset_pending(ioaddr))
1351 return;
1352 msleep(1);
1353 }
1354 if (netif_msg_link(tp))
1355 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1356 }
1357
1358 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1359 {
1360 void __iomem *ioaddr = tp->mmio_addr;
1361
1362 rtl8169_hw_phy_config(dev);
1363
1364 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1365 RTL_W8(0x82, 0x01);
1366
1367 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1368
1369 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1370 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1371
1372 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1373 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1374 RTL_W8(0x82, 0x01);
1375 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1376 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1377 }
1378
1379 rtl8169_phy_reset(dev, tp);
1380
1381 /*
1382 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1383 * only 8101. Don't panic.
1384 */
1385 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1386
1387 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1388 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1389 }
1390
1391 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1392 {
1393 void __iomem *ioaddr = tp->mmio_addr;
1394 u32 high;
1395 u32 low;
1396
1397 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1398 high = addr[4] | (addr[5] << 8);
1399
1400 spin_lock_irq(&tp->lock);
1401
1402 RTL_W8(Cfg9346, Cfg9346_Unlock);
1403 RTL_W32(MAC0, low);
1404 RTL_W32(MAC4, high);
1405 RTL_W8(Cfg9346, Cfg9346_Lock);
1406
1407 spin_unlock_irq(&tp->lock);
1408 }
1409
1410 static int rtl_set_mac_address(struct net_device *dev, void *p)
1411 {
1412 struct rtl8169_private *tp = netdev_priv(dev);
1413 struct sockaddr *addr = p;
1414
1415 if (!is_valid_ether_addr(addr->sa_data))
1416 return -EADDRNOTAVAIL;
1417
1418 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1419
1420 rtl_rar_set(tp, dev->dev_addr);
1421
1422 return 0;
1423 }
1424
1425 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1426 {
1427 struct rtl8169_private *tp = netdev_priv(dev);
1428 struct mii_ioctl_data *data = if_mii(ifr);
1429
1430 if (!netif_running(dev))
1431 return -ENODEV;
1432
1433 switch (cmd) {
1434 case SIOCGMIIPHY:
1435 data->phy_id = 32; /* Internal PHY */
1436 return 0;
1437
1438 case SIOCGMIIREG:
1439 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1440 return 0;
1441
1442 case SIOCSMIIREG:
1443 if (!capable(CAP_NET_ADMIN))
1444 return -EPERM;
1445 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1446 return 0;
1447 }
1448 return -EOPNOTSUPP;
1449 }
1450
1451 static const struct rtl_cfg_info {
1452 void (*hw_start)(struct net_device *);
1453 unsigned int region;
1454 unsigned int align;
1455 u16 intr_event;
1456 u16 napi_event;
1457 } rtl_cfg_infos [] = {
1458 [RTL_CFG_0] = {
1459 .hw_start = rtl_hw_start_8169,
1460 .region = 1,
1461 .align = 0,
1462 .intr_event = SYSErr | LinkChg | RxOverflow |
1463 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1464 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1465 },
1466 [RTL_CFG_1] = {
1467 .hw_start = rtl_hw_start_8168,
1468 .region = 2,
1469 .align = 8,
1470 .intr_event = SYSErr | LinkChg | RxOverflow |
1471 TxErr | TxOK | RxOK | RxErr,
1472 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1473 },
1474 [RTL_CFG_2] = {
1475 .hw_start = rtl_hw_start_8101,
1476 .region = 2,
1477 .align = 8,
1478 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1479 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1480 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1481 }
1482 };
1483
1484 static int __devinit
1485 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1486 {
1487 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1488 const unsigned int region = cfg->region;
1489 struct rtl8169_private *tp;
1490 struct net_device *dev;
1491 void __iomem *ioaddr;
1492 unsigned int i;
1493 int rc;
1494
1495 if (netif_msg_drv(&debug)) {
1496 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1497 MODULENAME, RTL8169_VERSION);
1498 }
1499
1500 dev = alloc_etherdev(sizeof (*tp));
1501 if (!dev) {
1502 if (netif_msg_drv(&debug))
1503 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1504 rc = -ENOMEM;
1505 goto out;
1506 }
1507
1508 SET_MODULE_OWNER(dev);
1509 SET_NETDEV_DEV(dev, &pdev->dev);
1510 tp = netdev_priv(dev);
1511 tp->dev = dev;
1512 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1513
1514 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1515 rc = pci_enable_device(pdev);
1516 if (rc < 0) {
1517 if (netif_msg_probe(tp))
1518 dev_err(&pdev->dev, "enable failure\n");
1519 goto err_out_free_dev_1;
1520 }
1521
1522 rc = pci_set_mwi(pdev);
1523 if (rc < 0)
1524 goto err_out_disable_2;
1525
1526 /* make sure PCI base addr 1 is MMIO */
1527 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1528 if (netif_msg_probe(tp)) {
1529 dev_err(&pdev->dev,
1530 "region #%d not an MMIO resource, aborting\n",
1531 region);
1532 }
1533 rc = -ENODEV;
1534 goto err_out_mwi_3;
1535 }
1536
1537 /* check for weird/broken PCI region reporting */
1538 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1539 if (netif_msg_probe(tp)) {
1540 dev_err(&pdev->dev,
1541 "Invalid PCI region size(s), aborting\n");
1542 }
1543 rc = -ENODEV;
1544 goto err_out_mwi_3;
1545 }
1546
1547 rc = pci_request_regions(pdev, MODULENAME);
1548 if (rc < 0) {
1549 if (netif_msg_probe(tp))
1550 dev_err(&pdev->dev, "could not request regions.\n");
1551 goto err_out_mwi_3;
1552 }
1553
1554 tp->cp_cmd = PCIMulRW | RxChkSum;
1555
1556 if ((sizeof(dma_addr_t) > 4) &&
1557 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1558 tp->cp_cmd |= PCIDAC;
1559 dev->features |= NETIF_F_HIGHDMA;
1560 } else {
1561 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1562 if (rc < 0) {
1563 if (netif_msg_probe(tp)) {
1564 dev_err(&pdev->dev,
1565 "DMA configuration failed.\n");
1566 }
1567 goto err_out_free_res_4;
1568 }
1569 }
1570
1571 pci_set_master(pdev);
1572
1573 /* ioremap MMIO region */
1574 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1575 if (!ioaddr) {
1576 if (netif_msg_probe(tp))
1577 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1578 rc = -EIO;
1579 goto err_out_free_res_4;
1580 }
1581
1582 /* Unneeded ? Don't mess with Mrs. Murphy. */
1583 rtl8169_irq_mask_and_ack(ioaddr);
1584
1585 /* Soft reset the chip. */
1586 RTL_W8(ChipCmd, CmdReset);
1587
1588 /* Check that the chip has finished the reset. */
1589 for (i = 0; i < 100; i++) {
1590 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1591 break;
1592 msleep_interruptible(1);
1593 }
1594
1595 /* Identify chip attached to board */
1596 rtl8169_get_mac_version(tp, ioaddr);
1597 rtl8169_get_phy_version(tp, ioaddr);
1598
1599 rtl8169_print_mac_version(tp);
1600 rtl8169_print_phy_version(tp);
1601
1602 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1603 if (tp->mac_version == rtl_chip_info[i].mac_version)
1604 break;
1605 }
1606 if (i < 0) {
1607 /* Unknown chip: assume array element #0, original RTL-8169 */
1608 if (netif_msg_probe(tp)) {
1609 dev_printk(KERN_DEBUG, &pdev->dev,
1610 "unknown chip version, assuming %s\n",
1611 rtl_chip_info[0].name);
1612 }
1613 i++;
1614 }
1615 tp->chipset = i;
1616
1617 RTL_W8(Cfg9346, Cfg9346_Unlock);
1618 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1619 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1620 RTL_W8(Cfg9346, Cfg9346_Lock);
1621
1622 if (RTL_R8(PHYstatus) & TBI_Enable) {
1623 tp->set_speed = rtl8169_set_speed_tbi;
1624 tp->get_settings = rtl8169_gset_tbi;
1625 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1626 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1627 tp->link_ok = rtl8169_tbi_link_ok;
1628
1629 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1630 } else {
1631 tp->set_speed = rtl8169_set_speed_xmii;
1632 tp->get_settings = rtl8169_gset_xmii;
1633 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1634 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1635 tp->link_ok = rtl8169_xmii_link_ok;
1636
1637 dev->do_ioctl = rtl8169_ioctl;
1638 }
1639
1640 /* Get MAC address. FIXME: read EEPROM */
1641 for (i = 0; i < MAC_ADDR_LEN; i++)
1642 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1643 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1644
1645 dev->open = rtl8169_open;
1646 dev->hard_start_xmit = rtl8169_start_xmit;
1647 dev->get_stats = rtl8169_get_stats;
1648 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1649 dev->stop = rtl8169_close;
1650 dev->tx_timeout = rtl8169_tx_timeout;
1651 dev->set_multicast_list = rtl_set_rx_mode;
1652 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1653 dev->irq = pdev->irq;
1654 dev->base_addr = (unsigned long) ioaddr;
1655 dev->change_mtu = rtl8169_change_mtu;
1656 dev->set_mac_address = rtl_set_mac_address;
1657
1658 #ifdef CONFIG_R8169_NAPI
1659 dev->poll = rtl8169_poll;
1660 dev->weight = R8169_NAPI_WEIGHT;
1661 #endif
1662
1663 #ifdef CONFIG_R8169_VLAN
1664 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1665 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1666 #endif
1667
1668 #ifdef CONFIG_NET_POLL_CONTROLLER
1669 dev->poll_controller = rtl8169_netpoll;
1670 #endif
1671
1672 tp->intr_mask = 0xffff;
1673 tp->pci_dev = pdev;
1674 tp->mmio_addr = ioaddr;
1675 tp->align = cfg->align;
1676 tp->hw_start = cfg->hw_start;
1677 tp->intr_event = cfg->intr_event;
1678 tp->napi_event = cfg->napi_event;
1679
1680 init_timer(&tp->timer);
1681 tp->timer.data = (unsigned long) dev;
1682 tp->timer.function = rtl8169_phy_timer;
1683
1684 spin_lock_init(&tp->lock);
1685
1686 rc = register_netdev(dev);
1687 if (rc < 0)
1688 goto err_out_unmap_5;
1689
1690 pci_set_drvdata(pdev, dev);
1691
1692 if (netif_msg_probe(tp)) {
1693 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1694
1695 printk(KERN_INFO "%s: %s at 0x%lx, "
1696 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1697 "XID %08x IRQ %d\n",
1698 dev->name,
1699 rtl_chip_info[tp->chipset].name,
1700 dev->base_addr,
1701 dev->dev_addr[0], dev->dev_addr[1],
1702 dev->dev_addr[2], dev->dev_addr[3],
1703 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1704 }
1705
1706 rtl8169_init_phy(dev, tp);
1707
1708 out:
1709 return rc;
1710
1711 err_out_unmap_5:
1712 iounmap(ioaddr);
1713 err_out_free_res_4:
1714 pci_release_regions(pdev);
1715 err_out_mwi_3:
1716 pci_clear_mwi(pdev);
1717 err_out_disable_2:
1718 pci_disable_device(pdev);
1719 err_out_free_dev_1:
1720 free_netdev(dev);
1721 goto out;
1722 }
1723
1724 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1725 {
1726 struct net_device *dev = pci_get_drvdata(pdev);
1727 struct rtl8169_private *tp = netdev_priv(dev);
1728
1729 flush_scheduled_work();
1730
1731 unregister_netdev(dev);
1732 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1733 pci_set_drvdata(pdev, NULL);
1734 }
1735
1736 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1737 struct net_device *dev)
1738 {
1739 unsigned int mtu = dev->mtu;
1740
1741 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1742 }
1743
1744 static int rtl8169_open(struct net_device *dev)
1745 {
1746 struct rtl8169_private *tp = netdev_priv(dev);
1747 struct pci_dev *pdev = tp->pci_dev;
1748 int retval = -ENOMEM;
1749
1750
1751 rtl8169_set_rxbufsize(tp, dev);
1752
1753 /*
1754 * Rx and Tx desscriptors needs 256 bytes alignment.
1755 * pci_alloc_consistent provides more.
1756 */
1757 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1758 &tp->TxPhyAddr);
1759 if (!tp->TxDescArray)
1760 goto out;
1761
1762 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1763 &tp->RxPhyAddr);
1764 if (!tp->RxDescArray)
1765 goto err_free_tx_0;
1766
1767 retval = rtl8169_init_ring(dev);
1768 if (retval < 0)
1769 goto err_free_rx_1;
1770
1771 INIT_DELAYED_WORK(&tp->task, NULL);
1772
1773 smp_mb();
1774
1775 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1776 dev->name, dev);
1777 if (retval < 0)
1778 goto err_release_ring_2;
1779
1780 rtl_hw_start(dev);
1781
1782 rtl8169_request_timer(dev);
1783
1784 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1785 out:
1786 return retval;
1787
1788 err_release_ring_2:
1789 rtl8169_rx_clear(tp);
1790 err_free_rx_1:
1791 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1792 tp->RxPhyAddr);
1793 err_free_tx_0:
1794 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1795 tp->TxPhyAddr);
1796 goto out;
1797 }
1798
1799 static void rtl8169_hw_reset(void __iomem *ioaddr)
1800 {
1801 /* Disable interrupts */
1802 rtl8169_irq_mask_and_ack(ioaddr);
1803
1804 /* Reset the chipset */
1805 RTL_W8(ChipCmd, CmdReset);
1806
1807 /* PCI commit */
1808 RTL_R8(ChipCmd);
1809 }
1810
1811 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1812 {
1813 void __iomem *ioaddr = tp->mmio_addr;
1814 u32 cfg = rtl8169_rx_config;
1815
1816 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1817 RTL_W32(RxConfig, cfg);
1818
1819 /* Set DMA burst size and Interframe Gap Time */
1820 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1821 (InterFrameGap << TxInterFrameGapShift));
1822 }
1823
1824 static void rtl_hw_start(struct net_device *dev)
1825 {
1826 struct rtl8169_private *tp = netdev_priv(dev);
1827 void __iomem *ioaddr = tp->mmio_addr;
1828 unsigned int i;
1829
1830 /* Soft reset the chip. */
1831 RTL_W8(ChipCmd, CmdReset);
1832
1833 /* Check that the chip has finished the reset. */
1834 for (i = 0; i < 100; i++) {
1835 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1836 break;
1837 msleep_interruptible(1);
1838 }
1839
1840 tp->hw_start(dev);
1841
1842 netif_start_queue(dev);
1843 }
1844
1845
1846 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1847 void __iomem *ioaddr)
1848 {
1849 /*
1850 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1851 * register to be written before TxDescAddrLow to work.
1852 * Switching from MMIO to I/O access fixes the issue as well.
1853 */
1854 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1855 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1856 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1857 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1858 }
1859
1860 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1861 {
1862 u16 cmd;
1863
1864 cmd = RTL_R16(CPlusCmd);
1865 RTL_W16(CPlusCmd, cmd);
1866 return cmd;
1867 }
1868
1869 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1870 {
1871 /* Low hurts. Let's disable the filtering. */
1872 RTL_W16(RxMaxSize, 16383);
1873 }
1874
1875 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1876 {
1877 struct {
1878 u32 mac_version;
1879 u32 clk;
1880 u32 val;
1881 } cfg2_info [] = {
1882 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1883 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1884 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1885 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1886 }, *p = cfg2_info;
1887 unsigned int i;
1888 u32 clk;
1889
1890 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1891 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1892 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1893 RTL_W32(0x7c, p->val);
1894 break;
1895 }
1896 }
1897 }
1898
1899 static void rtl_hw_start_8169(struct net_device *dev)
1900 {
1901 struct rtl8169_private *tp = netdev_priv(dev);
1902 void __iomem *ioaddr = tp->mmio_addr;
1903 struct pci_dev *pdev = tp->pci_dev;
1904
1905 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1906 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1907 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1908 }
1909
1910 RTL_W8(Cfg9346, Cfg9346_Unlock);
1911 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1912 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1913 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1914 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1915 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1916
1917 RTL_W8(EarlyTxThres, EarlyTxThld);
1918
1919 rtl_set_rx_max_size(ioaddr);
1920
1921 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1922 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1923 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1924 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1925 rtl_set_rx_tx_config_registers(tp);
1926
1927 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1928
1929 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1930 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1931 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1932 "Bit-3 and bit-14 MUST be 1\n");
1933 tp->cp_cmd |= (1 << 14);
1934 }
1935
1936 RTL_W16(CPlusCmd, tp->cp_cmd);
1937
1938 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1939
1940 /*
1941 * Undocumented corner. Supposedly:
1942 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1943 */
1944 RTL_W16(IntrMitigate, 0x0000);
1945
1946 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1947
1948 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1949 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1950 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1951 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1952 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1953 rtl_set_rx_tx_config_registers(tp);
1954 }
1955
1956 RTL_W8(Cfg9346, Cfg9346_Lock);
1957
1958 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1959 RTL_R8(IntrMask);
1960
1961 RTL_W32(RxMissed, 0);
1962
1963 rtl_set_rx_mode(dev);
1964
1965 /* no early-rx interrupts */
1966 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1967
1968 /* Enable all known interrupts by setting the interrupt mask. */
1969 RTL_W16(IntrMask, tp->intr_event);
1970 }
1971
1972 static void rtl_hw_start_8168(struct net_device *dev)
1973 {
1974 struct rtl8169_private *tp = netdev_priv(dev);
1975 void __iomem *ioaddr = tp->mmio_addr;
1976 struct pci_dev *pdev = tp->pci_dev;
1977 u8 ctl;
1978
1979 RTL_W8(Cfg9346, Cfg9346_Unlock);
1980
1981 RTL_W8(EarlyTxThres, EarlyTxThld);
1982
1983 rtl_set_rx_max_size(ioaddr);
1984
1985 rtl_set_rx_tx_config_registers(tp);
1986
1987 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1988
1989 RTL_W16(CPlusCmd, tp->cp_cmd);
1990
1991 /* Tx performance tweak. */
1992 pci_read_config_byte(pdev, 0x69, &ctl);
1993 ctl = (ctl & ~0x70) | 0x50;
1994 pci_write_config_byte(pdev, 0x69, ctl);
1995
1996 RTL_W16(IntrMitigate, 0x5151);
1997
1998 /* Work around for RxFIFO overflow. */
1999 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2000 tp->intr_event |= RxFIFOOver | PCSTimeout;
2001 tp->intr_event &= ~RxOverflow;
2002 }
2003
2004 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2005
2006 RTL_W8(Cfg9346, Cfg9346_Lock);
2007
2008 RTL_R8(IntrMask);
2009
2010 RTL_W32(RxMissed, 0);
2011
2012 rtl_set_rx_mode(dev);
2013
2014 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2015
2016 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2017
2018 RTL_W16(IntrMask, tp->intr_event);
2019 }
2020
2021 static void rtl_hw_start_8101(struct net_device *dev)
2022 {
2023 struct rtl8169_private *tp = netdev_priv(dev);
2024 void __iomem *ioaddr = tp->mmio_addr;
2025 struct pci_dev *pdev = tp->pci_dev;
2026
2027 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2028 pci_write_config_word(pdev, 0x68, 0x00);
2029 pci_write_config_word(pdev, 0x69, 0x08);
2030 }
2031
2032 RTL_W8(Cfg9346, Cfg9346_Unlock);
2033
2034 RTL_W8(EarlyTxThres, EarlyTxThld);
2035
2036 rtl_set_rx_max_size(ioaddr);
2037
2038 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2039
2040 RTL_W16(CPlusCmd, tp->cp_cmd);
2041
2042 RTL_W16(IntrMitigate, 0x0000);
2043
2044 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2045
2046 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2047 rtl_set_rx_tx_config_registers(tp);
2048
2049 RTL_W8(Cfg9346, Cfg9346_Lock);
2050
2051 RTL_R8(IntrMask);
2052
2053 RTL_W32(RxMissed, 0);
2054
2055 rtl_set_rx_mode(dev);
2056
2057 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2058
2059 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2060
2061 RTL_W16(IntrMask, tp->intr_event);
2062 }
2063
2064 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2065 {
2066 struct rtl8169_private *tp = netdev_priv(dev);
2067 int ret = 0;
2068
2069 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2070 return -EINVAL;
2071
2072 dev->mtu = new_mtu;
2073
2074 if (!netif_running(dev))
2075 goto out;
2076
2077 rtl8169_down(dev);
2078
2079 rtl8169_set_rxbufsize(tp, dev);
2080
2081 ret = rtl8169_init_ring(dev);
2082 if (ret < 0)
2083 goto out;
2084
2085 netif_poll_enable(dev);
2086
2087 rtl_hw_start(dev);
2088
2089 rtl8169_request_timer(dev);
2090
2091 out:
2092 return ret;
2093 }
2094
2095 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2096 {
2097 desc->addr = 0x0badbadbadbadbadull;
2098 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2099 }
2100
2101 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2102 struct sk_buff **sk_buff, struct RxDesc *desc)
2103 {
2104 struct pci_dev *pdev = tp->pci_dev;
2105
2106 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2107 PCI_DMA_FROMDEVICE);
2108 dev_kfree_skb(*sk_buff);
2109 *sk_buff = NULL;
2110 rtl8169_make_unusable_by_asic(desc);
2111 }
2112
2113 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2114 {
2115 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2116
2117 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2118 }
2119
2120 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2121 u32 rx_buf_sz)
2122 {
2123 desc->addr = cpu_to_le64(mapping);
2124 wmb();
2125 rtl8169_mark_to_asic(desc, rx_buf_sz);
2126 }
2127
2128 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2129 struct net_device *dev,
2130 struct RxDesc *desc, int rx_buf_sz,
2131 unsigned int align)
2132 {
2133 struct sk_buff *skb;
2134 dma_addr_t mapping;
2135 unsigned int pad;
2136
2137 pad = align ? align : NET_IP_ALIGN;
2138
2139 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2140 if (!skb)
2141 goto err_out;
2142
2143 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2144
2145 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2146 PCI_DMA_FROMDEVICE);
2147
2148 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2149 out:
2150 return skb;
2151
2152 err_out:
2153 rtl8169_make_unusable_by_asic(desc);
2154 goto out;
2155 }
2156
2157 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2158 {
2159 unsigned int i;
2160
2161 for (i = 0; i < NUM_RX_DESC; i++) {
2162 if (tp->Rx_skbuff[i]) {
2163 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2164 tp->RxDescArray + i);
2165 }
2166 }
2167 }
2168
2169 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2170 u32 start, u32 end)
2171 {
2172 u32 cur;
2173
2174 for (cur = start; end - cur != 0; cur++) {
2175 struct sk_buff *skb;
2176 unsigned int i = cur % NUM_RX_DESC;
2177
2178 WARN_ON((s32)(end - cur) < 0);
2179
2180 if (tp->Rx_skbuff[i])
2181 continue;
2182
2183 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2184 tp->RxDescArray + i,
2185 tp->rx_buf_sz, tp->align);
2186 if (!skb)
2187 break;
2188
2189 tp->Rx_skbuff[i] = skb;
2190 }
2191 return cur - start;
2192 }
2193
2194 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2195 {
2196 desc->opts1 |= cpu_to_le32(RingEnd);
2197 }
2198
2199 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2200 {
2201 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2202 }
2203
2204 static int rtl8169_init_ring(struct net_device *dev)
2205 {
2206 struct rtl8169_private *tp = netdev_priv(dev);
2207
2208 rtl8169_init_ring_indexes(tp);
2209
2210 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2211 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2212
2213 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2214 goto err_out;
2215
2216 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2217
2218 return 0;
2219
2220 err_out:
2221 rtl8169_rx_clear(tp);
2222 return -ENOMEM;
2223 }
2224
2225 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2226 struct TxDesc *desc)
2227 {
2228 unsigned int len = tx_skb->len;
2229
2230 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2231 desc->opts1 = 0x00;
2232 desc->opts2 = 0x00;
2233 desc->addr = 0x00;
2234 tx_skb->len = 0;
2235 }
2236
2237 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2238 {
2239 unsigned int i;
2240
2241 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2242 unsigned int entry = i % NUM_TX_DESC;
2243 struct ring_info *tx_skb = tp->tx_skb + entry;
2244 unsigned int len = tx_skb->len;
2245
2246 if (len) {
2247 struct sk_buff *skb = tx_skb->skb;
2248
2249 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2250 tp->TxDescArray + entry);
2251 if (skb) {
2252 dev_kfree_skb(skb);
2253 tx_skb->skb = NULL;
2254 }
2255 tp->stats.tx_dropped++;
2256 }
2257 }
2258 tp->cur_tx = tp->dirty_tx = 0;
2259 }
2260
2261 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2262 {
2263 struct rtl8169_private *tp = netdev_priv(dev);
2264
2265 PREPARE_DELAYED_WORK(&tp->task, task);
2266 schedule_delayed_work(&tp->task, 4);
2267 }
2268
2269 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2270 {
2271 struct rtl8169_private *tp = netdev_priv(dev);
2272 void __iomem *ioaddr = tp->mmio_addr;
2273
2274 synchronize_irq(dev->irq);
2275
2276 /* Wait for any pending NAPI task to complete */
2277 netif_poll_disable(dev);
2278
2279 rtl8169_irq_mask_and_ack(ioaddr);
2280
2281 netif_poll_enable(dev);
2282 }
2283
2284 static void rtl8169_reinit_task(struct work_struct *work)
2285 {
2286 struct rtl8169_private *tp =
2287 container_of(work, struct rtl8169_private, task.work);
2288 struct net_device *dev = tp->dev;
2289 int ret;
2290
2291 rtnl_lock();
2292
2293 if (!netif_running(dev))
2294 goto out_unlock;
2295
2296 rtl8169_wait_for_quiescence(dev);
2297 rtl8169_close(dev);
2298
2299 ret = rtl8169_open(dev);
2300 if (unlikely(ret < 0)) {
2301 if (net_ratelimit() && netif_msg_drv(tp)) {
2302 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2303 " Rescheduling.\n", dev->name, ret);
2304 }
2305 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2306 }
2307
2308 out_unlock:
2309 rtnl_unlock();
2310 }
2311
2312 static void rtl8169_reset_task(struct work_struct *work)
2313 {
2314 struct rtl8169_private *tp =
2315 container_of(work, struct rtl8169_private, task.work);
2316 struct net_device *dev = tp->dev;
2317
2318 rtnl_lock();
2319
2320 if (!netif_running(dev))
2321 goto out_unlock;
2322
2323 rtl8169_wait_for_quiescence(dev);
2324
2325 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2326 rtl8169_tx_clear(tp);
2327
2328 if (tp->dirty_rx == tp->cur_rx) {
2329 rtl8169_init_ring_indexes(tp);
2330 rtl_hw_start(dev);
2331 netif_wake_queue(dev);
2332 } else {
2333 if (net_ratelimit() && netif_msg_intr(tp)) {
2334 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2335 dev->name);
2336 }
2337 rtl8169_schedule_work(dev, rtl8169_reset_task);
2338 }
2339
2340 out_unlock:
2341 rtnl_unlock();
2342 }
2343
2344 static void rtl8169_tx_timeout(struct net_device *dev)
2345 {
2346 struct rtl8169_private *tp = netdev_priv(dev);
2347
2348 rtl8169_hw_reset(tp->mmio_addr);
2349
2350 /* Let's wait a bit while any (async) irq lands on */
2351 rtl8169_schedule_work(dev, rtl8169_reset_task);
2352 }
2353
2354 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2355 u32 opts1)
2356 {
2357 struct skb_shared_info *info = skb_shinfo(skb);
2358 unsigned int cur_frag, entry;
2359 struct TxDesc * uninitialized_var(txd);
2360
2361 entry = tp->cur_tx;
2362 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2363 skb_frag_t *frag = info->frags + cur_frag;
2364 dma_addr_t mapping;
2365 u32 status, len;
2366 void *addr;
2367
2368 entry = (entry + 1) % NUM_TX_DESC;
2369
2370 txd = tp->TxDescArray + entry;
2371 len = frag->size;
2372 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2373 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2374
2375 /* anti gcc 2.95.3 bugware (sic) */
2376 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2377
2378 txd->opts1 = cpu_to_le32(status);
2379 txd->addr = cpu_to_le64(mapping);
2380
2381 tp->tx_skb[entry].len = len;
2382 }
2383
2384 if (cur_frag) {
2385 tp->tx_skb[entry].skb = skb;
2386 txd->opts1 |= cpu_to_le32(LastFrag);
2387 }
2388
2389 return cur_frag;
2390 }
2391
2392 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2393 {
2394 if (dev->features & NETIF_F_TSO) {
2395 u32 mss = skb_shinfo(skb)->gso_size;
2396
2397 if (mss)
2398 return LargeSend | ((mss & MSSMask) << MSSShift);
2399 }
2400 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2401 const struct iphdr *ip = ip_hdr(skb);
2402
2403 if (ip->protocol == IPPROTO_TCP)
2404 return IPCS | TCPCS;
2405 else if (ip->protocol == IPPROTO_UDP)
2406 return IPCS | UDPCS;
2407 WARN_ON(1); /* we need a WARN() */
2408 }
2409 return 0;
2410 }
2411
2412 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2413 {
2414 struct rtl8169_private *tp = netdev_priv(dev);
2415 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2416 struct TxDesc *txd = tp->TxDescArray + entry;
2417 void __iomem *ioaddr = tp->mmio_addr;
2418 dma_addr_t mapping;
2419 u32 status, len;
2420 u32 opts1;
2421 int ret = NETDEV_TX_OK;
2422
2423 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2424 if (netif_msg_drv(tp)) {
2425 printk(KERN_ERR
2426 "%s: BUG! Tx Ring full when queue awake!\n",
2427 dev->name);
2428 }
2429 goto err_stop;
2430 }
2431
2432 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2433 goto err_stop;
2434
2435 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2436
2437 frags = rtl8169_xmit_frags(tp, skb, opts1);
2438 if (frags) {
2439 len = skb_headlen(skb);
2440 opts1 |= FirstFrag;
2441 } else {
2442 len = skb->len;
2443
2444 if (unlikely(len < ETH_ZLEN)) {
2445 if (skb_padto(skb, ETH_ZLEN))
2446 goto err_update_stats;
2447 len = ETH_ZLEN;
2448 }
2449
2450 opts1 |= FirstFrag | LastFrag;
2451 tp->tx_skb[entry].skb = skb;
2452 }
2453
2454 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2455
2456 tp->tx_skb[entry].len = len;
2457 txd->addr = cpu_to_le64(mapping);
2458 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2459
2460 wmb();
2461
2462 /* anti gcc 2.95.3 bugware (sic) */
2463 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2464 txd->opts1 = cpu_to_le32(status);
2465
2466 dev->trans_start = jiffies;
2467
2468 tp->cur_tx += frags + 1;
2469
2470 smp_wmb();
2471
2472 RTL_W8(TxPoll, NPQ); /* set polling bit */
2473
2474 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2475 netif_stop_queue(dev);
2476 smp_rmb();
2477 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2478 netif_wake_queue(dev);
2479 }
2480
2481 out:
2482 return ret;
2483
2484 err_stop:
2485 netif_stop_queue(dev);
2486 ret = NETDEV_TX_BUSY;
2487 err_update_stats:
2488 tp->stats.tx_dropped++;
2489 goto out;
2490 }
2491
2492 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2493 {
2494 struct rtl8169_private *tp = netdev_priv(dev);
2495 struct pci_dev *pdev = tp->pci_dev;
2496 void __iomem *ioaddr = tp->mmio_addr;
2497 u16 pci_status, pci_cmd;
2498
2499 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2500 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2501
2502 if (netif_msg_intr(tp)) {
2503 printk(KERN_ERR
2504 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2505 dev->name, pci_cmd, pci_status);
2506 }
2507
2508 /*
2509 * The recovery sequence below admits a very elaborated explanation:
2510 * - it seems to work;
2511 * - I did not see what else could be done;
2512 * - it makes iop3xx happy.
2513 *
2514 * Feel free to adjust to your needs.
2515 */
2516 if (pdev->broken_parity_status)
2517 pci_cmd &= ~PCI_COMMAND_PARITY;
2518 else
2519 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2520
2521 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2522
2523 pci_write_config_word(pdev, PCI_STATUS,
2524 pci_status & (PCI_STATUS_DETECTED_PARITY |
2525 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2526 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2527
2528 /* The infamous DAC f*ckup only happens at boot time */
2529 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2530 if (netif_msg_intr(tp))
2531 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2532 tp->cp_cmd &= ~PCIDAC;
2533 RTL_W16(CPlusCmd, tp->cp_cmd);
2534 dev->features &= ~NETIF_F_HIGHDMA;
2535 }
2536
2537 rtl8169_hw_reset(ioaddr);
2538
2539 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2540 }
2541
2542 static void rtl8169_tx_interrupt(struct net_device *dev,
2543 struct rtl8169_private *tp,
2544 void __iomem *ioaddr)
2545 {
2546 unsigned int dirty_tx, tx_left;
2547
2548 dirty_tx = tp->dirty_tx;
2549 smp_rmb();
2550 tx_left = tp->cur_tx - dirty_tx;
2551
2552 while (tx_left > 0) {
2553 unsigned int entry = dirty_tx % NUM_TX_DESC;
2554 struct ring_info *tx_skb = tp->tx_skb + entry;
2555 u32 len = tx_skb->len;
2556 u32 status;
2557
2558 rmb();
2559 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2560 if (status & DescOwn)
2561 break;
2562
2563 tp->stats.tx_bytes += len;
2564 tp->stats.tx_packets++;
2565
2566 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2567
2568 if (status & LastFrag) {
2569 dev_kfree_skb_irq(tx_skb->skb);
2570 tx_skb->skb = NULL;
2571 }
2572 dirty_tx++;
2573 tx_left--;
2574 }
2575
2576 if (tp->dirty_tx != dirty_tx) {
2577 tp->dirty_tx = dirty_tx;
2578 smp_wmb();
2579 if (netif_queue_stopped(dev) &&
2580 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2581 netif_wake_queue(dev);
2582 }
2583 /*
2584 * 8168 hack: TxPoll requests are lost when the Tx packets are
2585 * too close. Let's kick an extra TxPoll request when a burst
2586 * of start_xmit activity is detected (if it is not detected,
2587 * it is slow enough). -- FR
2588 */
2589 smp_rmb();
2590 if (tp->cur_tx != dirty_tx)
2591 RTL_W8(TxPoll, NPQ);
2592 }
2593 }
2594
2595 static inline int rtl8169_fragmented_frame(u32 status)
2596 {
2597 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2598 }
2599
2600 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2601 {
2602 u32 opts1 = le32_to_cpu(desc->opts1);
2603 u32 status = opts1 & RxProtoMask;
2604
2605 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2606 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2607 ((status == RxProtoIP) && !(opts1 & IPFail)))
2608 skb->ip_summed = CHECKSUM_UNNECESSARY;
2609 else
2610 skb->ip_summed = CHECKSUM_NONE;
2611 }
2612
2613 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2614 struct rtl8169_private *tp, int pkt_size,
2615 dma_addr_t addr)
2616 {
2617 struct sk_buff *skb;
2618 bool done = false;
2619
2620 if (pkt_size >= rx_copybreak)
2621 goto out;
2622
2623 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2624 if (!skb)
2625 goto out;
2626
2627 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2628 PCI_DMA_FROMDEVICE);
2629 skb_reserve(skb, NET_IP_ALIGN);
2630 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2631 *sk_buff = skb;
2632 done = true;
2633 out:
2634 return done;
2635 }
2636
2637 static int rtl8169_rx_interrupt(struct net_device *dev,
2638 struct rtl8169_private *tp,
2639 void __iomem *ioaddr)
2640 {
2641 unsigned int cur_rx, rx_left;
2642 unsigned int delta, count;
2643
2644 cur_rx = tp->cur_rx;
2645 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2646 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2647
2648 for (; rx_left > 0; rx_left--, cur_rx++) {
2649 unsigned int entry = cur_rx % NUM_RX_DESC;
2650 struct RxDesc *desc = tp->RxDescArray + entry;
2651 u32 status;
2652
2653 rmb();
2654 status = le32_to_cpu(desc->opts1);
2655
2656 if (status & DescOwn)
2657 break;
2658 if (unlikely(status & RxRES)) {
2659 if (netif_msg_rx_err(tp)) {
2660 printk(KERN_INFO
2661 "%s: Rx ERROR. status = %08x\n",
2662 dev->name, status);
2663 }
2664 tp->stats.rx_errors++;
2665 if (status & (RxRWT | RxRUNT))
2666 tp->stats.rx_length_errors++;
2667 if (status & RxCRC)
2668 tp->stats.rx_crc_errors++;
2669 if (status & RxFOVF) {
2670 rtl8169_schedule_work(dev, rtl8169_reset_task);
2671 tp->stats.rx_fifo_errors++;
2672 }
2673 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2674 } else {
2675 struct sk_buff *skb = tp->Rx_skbuff[entry];
2676 dma_addr_t addr = le64_to_cpu(desc->addr);
2677 int pkt_size = (status & 0x00001FFF) - 4;
2678 struct pci_dev *pdev = tp->pci_dev;
2679
2680 /*
2681 * The driver does not support incoming fragmented
2682 * frames. They are seen as a symptom of over-mtu
2683 * sized frames.
2684 */
2685 if (unlikely(rtl8169_fragmented_frame(status))) {
2686 tp->stats.rx_dropped++;
2687 tp->stats.rx_length_errors++;
2688 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2689 continue;
2690 }
2691
2692 rtl8169_rx_csum(skb, desc);
2693
2694 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2695 pci_dma_sync_single_for_device(pdev, addr,
2696 pkt_size, PCI_DMA_FROMDEVICE);
2697 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2698 } else {
2699 pci_unmap_single(pdev, addr, pkt_size,
2700 PCI_DMA_FROMDEVICE);
2701 tp->Rx_skbuff[entry] = NULL;
2702 }
2703
2704 skb_put(skb, pkt_size);
2705 skb->protocol = eth_type_trans(skb, dev);
2706
2707 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2708 rtl8169_rx_skb(skb);
2709
2710 dev->last_rx = jiffies;
2711 tp->stats.rx_bytes += pkt_size;
2712 tp->stats.rx_packets++;
2713 }
2714
2715 /* Work around for AMD plateform. */
2716 if ((desc->opts2 & 0xfffe000) &&
2717 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2718 desc->opts2 = 0;
2719 cur_rx++;
2720 }
2721 }
2722
2723 count = cur_rx - tp->cur_rx;
2724 tp->cur_rx = cur_rx;
2725
2726 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2727 if (!delta && count && netif_msg_intr(tp))
2728 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2729 tp->dirty_rx += delta;
2730
2731 /*
2732 * FIXME: until there is periodic timer to try and refill the ring,
2733 * a temporary shortage may definitely kill the Rx process.
2734 * - disable the asic to try and avoid an overflow and kick it again
2735 * after refill ?
2736 * - how do others driver handle this condition (Uh oh...).
2737 */
2738 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2739 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2740
2741 return count;
2742 }
2743
2744 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2745 {
2746 struct net_device *dev = dev_instance;
2747 struct rtl8169_private *tp = netdev_priv(dev);
2748 int boguscnt = max_interrupt_work;
2749 void __iomem *ioaddr = tp->mmio_addr;
2750 int status;
2751 int handled = 0;
2752
2753 do {
2754 status = RTL_R16(IntrStatus);
2755
2756 /* hotplug/major error/no more work/shared irq */
2757 if ((status == 0xFFFF) || !status)
2758 break;
2759
2760 handled = 1;
2761
2762 if (unlikely(!netif_running(dev))) {
2763 rtl8169_asic_down(ioaddr);
2764 goto out;
2765 }
2766
2767 status &= tp->intr_mask;
2768 RTL_W16(IntrStatus,
2769 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2770
2771 if (!(status & tp->intr_event))
2772 break;
2773
2774 /* Work around for rx fifo overflow */
2775 if (unlikely(status & RxFIFOOver) &&
2776 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2777 netif_stop_queue(dev);
2778 rtl8169_tx_timeout(dev);
2779 break;
2780 }
2781
2782 if (unlikely(status & SYSErr)) {
2783 rtl8169_pcierr_interrupt(dev);
2784 break;
2785 }
2786
2787 if (status & LinkChg)
2788 rtl8169_check_link_status(dev, tp, ioaddr);
2789
2790 #ifdef CONFIG_R8169_NAPI
2791 if (status & tp->napi_event) {
2792 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2793 tp->intr_mask = ~tp->napi_event;
2794
2795 if (likely(netif_rx_schedule_prep(dev)))
2796 __netif_rx_schedule(dev);
2797 else if (netif_msg_intr(tp)) {
2798 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2799 dev->name, status);
2800 }
2801 }
2802 break;
2803 #else
2804 /* Rx interrupt */
2805 if (status & (RxOK | RxOverflow | RxFIFOOver))
2806 rtl8169_rx_interrupt(dev, tp, ioaddr);
2807
2808 /* Tx interrupt */
2809 if (status & (TxOK | TxErr))
2810 rtl8169_tx_interrupt(dev, tp, ioaddr);
2811 #endif
2812
2813 boguscnt--;
2814 } while (boguscnt > 0);
2815
2816 if (boguscnt <= 0) {
2817 if (netif_msg_intr(tp) && net_ratelimit() ) {
2818 printk(KERN_WARNING
2819 "%s: Too much work at interrupt!\n", dev->name);
2820 }
2821 /* Clear all interrupt sources. */
2822 RTL_W16(IntrStatus, 0xffff);
2823 }
2824 out:
2825 return IRQ_RETVAL(handled);
2826 }
2827
2828 #ifdef CONFIG_R8169_NAPI
2829 static int rtl8169_poll(struct net_device *dev, int *budget)
2830 {
2831 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2832 struct rtl8169_private *tp = netdev_priv(dev);
2833 void __iomem *ioaddr = tp->mmio_addr;
2834
2835 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2836 rtl8169_tx_interrupt(dev, tp, ioaddr);
2837
2838 *budget -= work_done;
2839 dev->quota -= work_done;
2840
2841 if (work_done < work_to_do) {
2842 netif_rx_complete(dev);
2843 tp->intr_mask = 0xffff;
2844 /*
2845 * 20040426: the barrier is not strictly required but the
2846 * behavior of the irq handler could be less predictable
2847 * without it. Btw, the lack of flush for the posted pci
2848 * write is safe - FR
2849 */
2850 smp_wmb();
2851 RTL_W16(IntrMask, tp->intr_event);
2852 }
2853
2854 return (work_done >= work_to_do);
2855 }
2856 #endif
2857
2858 static void rtl8169_down(struct net_device *dev)
2859 {
2860 struct rtl8169_private *tp = netdev_priv(dev);
2861 void __iomem *ioaddr = tp->mmio_addr;
2862 unsigned int poll_locked = 0;
2863 unsigned int intrmask;
2864
2865 rtl8169_delete_timer(dev);
2866
2867 netif_stop_queue(dev);
2868
2869 core_down:
2870 spin_lock_irq(&tp->lock);
2871
2872 rtl8169_asic_down(ioaddr);
2873
2874 /* Update the error counts. */
2875 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2876 RTL_W32(RxMissed, 0);
2877
2878 spin_unlock_irq(&tp->lock);
2879
2880 synchronize_irq(dev->irq);
2881
2882 if (!poll_locked) {
2883 netif_poll_disable(dev);
2884 poll_locked++;
2885 }
2886
2887 /* Give a racing hard_start_xmit a few cycles to complete. */
2888 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2889
2890 /*
2891 * And now for the 50k$ question: are IRQ disabled or not ?
2892 *
2893 * Two paths lead here:
2894 * 1) dev->close
2895 * -> netif_running() is available to sync the current code and the
2896 * IRQ handler. See rtl8169_interrupt for details.
2897 * 2) dev->change_mtu
2898 * -> rtl8169_poll can not be issued again and re-enable the
2899 * interruptions. Let's simply issue the IRQ down sequence again.
2900 *
2901 * No loop if hotpluged or major error (0xffff).
2902 */
2903 intrmask = RTL_R16(IntrMask);
2904 if (intrmask && (intrmask != 0xffff))
2905 goto core_down;
2906
2907 rtl8169_tx_clear(tp);
2908
2909 rtl8169_rx_clear(tp);
2910 }
2911
2912 static int rtl8169_close(struct net_device *dev)
2913 {
2914 struct rtl8169_private *tp = netdev_priv(dev);
2915 struct pci_dev *pdev = tp->pci_dev;
2916
2917 rtl8169_down(dev);
2918
2919 free_irq(dev->irq, dev);
2920
2921 netif_poll_enable(dev);
2922
2923 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2924 tp->RxPhyAddr);
2925 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2926 tp->TxPhyAddr);
2927 tp->TxDescArray = NULL;
2928 tp->RxDescArray = NULL;
2929
2930 return 0;
2931 }
2932
2933 static void rtl_set_rx_mode(struct net_device *dev)
2934 {
2935 struct rtl8169_private *tp = netdev_priv(dev);
2936 void __iomem *ioaddr = tp->mmio_addr;
2937 unsigned long flags;
2938 u32 mc_filter[2]; /* Multicast hash filter */
2939 int rx_mode;
2940 u32 tmp = 0;
2941
2942 if (dev->flags & IFF_PROMISC) {
2943 /* Unconditionally log net taps. */
2944 if (netif_msg_link(tp)) {
2945 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2946 dev->name);
2947 }
2948 rx_mode =
2949 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2950 AcceptAllPhys;
2951 mc_filter[1] = mc_filter[0] = 0xffffffff;
2952 } else if ((dev->mc_count > multicast_filter_limit)
2953 || (dev->flags & IFF_ALLMULTI)) {
2954 /* Too many to filter perfectly -- accept all multicasts. */
2955 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2956 mc_filter[1] = mc_filter[0] = 0xffffffff;
2957 } else {
2958 struct dev_mc_list *mclist;
2959 unsigned int i;
2960
2961 rx_mode = AcceptBroadcast | AcceptMyPhys;
2962 mc_filter[1] = mc_filter[0] = 0;
2963 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2964 i++, mclist = mclist->next) {
2965 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2966 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2967 rx_mode |= AcceptMulticast;
2968 }
2969 }
2970
2971 spin_lock_irqsave(&tp->lock, flags);
2972
2973 tmp = rtl8169_rx_config | rx_mode |
2974 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2975
2976 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2977 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2978 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2979 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2980 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2981 mc_filter[0] = 0xffffffff;
2982 mc_filter[1] = 0xffffffff;
2983 }
2984
2985 RTL_W32(MAR0 + 0, mc_filter[0]);
2986 RTL_W32(MAR0 + 4, mc_filter[1]);
2987
2988 RTL_W32(RxConfig, tmp);
2989
2990 spin_unlock_irqrestore(&tp->lock, flags);
2991 }
2992
2993 /**
2994 * rtl8169_get_stats - Get rtl8169 read/write statistics
2995 * @dev: The Ethernet Device to get statistics for
2996 *
2997 * Get TX/RX statistics for rtl8169
2998 */
2999 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3000 {
3001 struct rtl8169_private *tp = netdev_priv(dev);
3002 void __iomem *ioaddr = tp->mmio_addr;
3003 unsigned long flags;
3004
3005 if (netif_running(dev)) {
3006 spin_lock_irqsave(&tp->lock, flags);
3007 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3008 RTL_W32(RxMissed, 0);
3009 spin_unlock_irqrestore(&tp->lock, flags);
3010 }
3011
3012 return &tp->stats;
3013 }
3014
3015 #ifdef CONFIG_PM
3016
3017 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3018 {
3019 struct net_device *dev = pci_get_drvdata(pdev);
3020 struct rtl8169_private *tp = netdev_priv(dev);
3021 void __iomem *ioaddr = tp->mmio_addr;
3022
3023 if (!netif_running(dev))
3024 goto out_pci_suspend;
3025
3026 netif_device_detach(dev);
3027 netif_stop_queue(dev);
3028
3029 spin_lock_irq(&tp->lock);
3030
3031 rtl8169_asic_down(ioaddr);
3032
3033 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3034 RTL_W32(RxMissed, 0);
3035
3036 spin_unlock_irq(&tp->lock);
3037
3038 out_pci_suspend:
3039 pci_save_state(pdev);
3040 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
3041 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3042
3043 return 0;
3044 }
3045
3046 static int rtl8169_resume(struct pci_dev *pdev)
3047 {
3048 struct net_device *dev = pci_get_drvdata(pdev);
3049
3050 pci_set_power_state(pdev, PCI_D0);
3051 pci_restore_state(pdev);
3052 pci_enable_wake(pdev, PCI_D0, 0);
3053
3054 if (!netif_running(dev))
3055 goto out;
3056
3057 netif_device_attach(dev);
3058
3059 rtl8169_schedule_work(dev, rtl8169_reset_task);
3060 out:
3061 return 0;
3062 }
3063
3064 #endif /* CONFIG_PM */
3065
3066 static struct pci_driver rtl8169_pci_driver = {
3067 .name = MODULENAME,
3068 .id_table = rtl8169_pci_tbl,
3069 .probe = rtl8169_init_one,
3070 .remove = __devexit_p(rtl8169_remove_one),
3071 #ifdef CONFIG_PM
3072 .suspend = rtl8169_suspend,
3073 .resume = rtl8169_resume,
3074 #endif
3075 };
3076
3077 static int __init rtl8169_init_module(void)
3078 {
3079 return pci_register_driver(&rtl8169_pci_driver);
3080 }
3081
3082 static void __exit rtl8169_cleanup_module(void)
3083 {
3084 pci_unregister_driver(&rtl8169_pci_driver);
3085 }
3086
3087 module_init(rtl8169_init_module);
3088 module_exit(rtl8169_cleanup_module);
kernel-based virtual machine