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ixgbe: Use the instance of net_device_stats from net_device.
[linux-2.6/kvm.git] / drivers / net / ixgbe / ixgbe_main.c
blobc91d50e54427ac429b0acd7827df0b5c4d67ff6c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
44
45 #include "ixgbe.h"
46 #include "ixgbe_common.h"
47
48 char ixgbe_driver_name[] = "ixgbe";
49 static const char ixgbe_driver_string[] =
50 "Intel(R) 10 Gigabit PCI Express Network Driver";
51
52 #define DRV_VERSION "2.0.44-k2"
53 const char ixgbe_driver_version[] = DRV_VERSION;
54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
55
56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
57 [board_82598] = &ixgbe_82598_info,
58 [board_82599] = &ixgbe_82599_info,
59 };
60
61 /* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69 static struct pci_device_id ixgbe_pci_tbl[] = {
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
73 board_82598 },
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
95 board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
97 board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
101 board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
103 board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
105 board_82599 },
106
107 /* required last entry */
108 {0, }
109 };
110 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
111
112 #ifdef CONFIG_IXGBE_DCA
113 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
114 void *p);
115 static struct notifier_block dca_notifier = {
116 .notifier_call = ixgbe_notify_dca,
117 .next = NULL,
118 .priority = 0
119 };
120 #endif
121
122 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
123 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
124 MODULE_LICENSE("GPL");
125 MODULE_VERSION(DRV_VERSION);
126
127 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
128
129 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
130 {
131 u32 ctrl_ext;
132
133 /* Let firmware take over control of h/w */
134 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
136 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
137 }
138
139 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
140 {
141 u32 ctrl_ext;
142
143 /* Let firmware know the driver has taken over */
144 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
145 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
146 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
147 }
148
149 /*
150 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
151 * @adapter: pointer to adapter struct
152 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
153 * @queue: queue to map the corresponding interrupt to
154 * @msix_vector: the vector to map to the corresponding queue
155 *
156 */
157 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
158 u8 queue, u8 msix_vector)
159 {
160 u32 ivar, index;
161 struct ixgbe_hw *hw = &adapter->hw;
162 switch (hw->mac.type) {
163 case ixgbe_mac_82598EB:
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 if (direction == -1)
166 direction = 0;
167 index = (((direction * 64) + queue) >> 2) & 0x1F;
168 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
169 ivar &= ~(0xFF << (8 * (queue & 0x3)));
170 ivar |= (msix_vector << (8 * (queue & 0x3)));
171 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
172 break;
173 case ixgbe_mac_82599EB:
174 if (direction == -1) {
175 /* other causes */
176 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
177 index = ((queue & 1) * 8);
178 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
179 ivar &= ~(0xFF << index);
180 ivar |= (msix_vector << index);
181 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
182 break;
183 } else {
184 /* tx or rx causes */
185 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
186 index = ((16 * (queue & 1)) + (8 * direction));
187 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
188 ivar &= ~(0xFF << index);
189 ivar |= (msix_vector << index);
190 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
191 break;
192 }
193 default:
194 break;
195 }
196 }
197
198 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
199 u64 qmask)
200 {
201 u32 mask;
202
203 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
204 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
205 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
206 } else {
207 mask = (qmask & 0xFFFFFFFF);
208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
209 mask = (qmask >> 32);
210 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
211 }
212 }
213
214 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
215 struct ixgbe_tx_buffer
216 *tx_buffer_info)
217 {
218 tx_buffer_info->dma = 0;
219 if (tx_buffer_info->skb) {
220 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
221 DMA_TO_DEVICE);
222 dev_kfree_skb_any(tx_buffer_info->skb);
223 tx_buffer_info->skb = NULL;
224 }
225 tx_buffer_info->time_stamp = 0;
226 /* tx_buffer_info must be completely set up in the transmit path */
227 }
228
229 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
230 struct ixgbe_ring *tx_ring,
231 unsigned int eop)
232 {
233 struct ixgbe_hw *hw = &adapter->hw;
234
235 /* Detect a transmit hang in hardware, this serializes the
236 * check with the clearing of time_stamp and movement of eop */
237 adapter->detect_tx_hung = false;
238 if (tx_ring->tx_buffer_info[eop].time_stamp &&
239 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
240 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
241 /* detected Tx unit hang */
242 union ixgbe_adv_tx_desc *tx_desc;
243 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
244 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
245 " Tx Queue <%d>\n"
246 " TDH, TDT <%x>, <%x>\n"
247 " next_to_use <%x>\n"
248 " next_to_clean <%x>\n"
249 "tx_buffer_info[next_to_clean]\n"
250 " time_stamp <%lx>\n"
251 " jiffies <%lx>\n",
252 tx_ring->queue_index,
253 IXGBE_READ_REG(hw, tx_ring->head),
254 IXGBE_READ_REG(hw, tx_ring->tail),
255 tx_ring->next_to_use, eop,
256 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
257 return true;
258 }
259
260 return false;
261 }
262
263 #define IXGBE_MAX_TXD_PWR 14
264 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
265
266 /* Tx Descriptors needed, worst case */
267 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
268 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
269 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
270 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
271
272 static void ixgbe_tx_timeout(struct net_device *netdev);
273
274 /**
275 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
276 * @q_vector: structure containing interrupt and ring information
277 * @tx_ring: tx ring to clean
278 **/
279 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
280 struct ixgbe_ring *tx_ring)
281 {
282 struct ixgbe_adapter *adapter = q_vector->adapter;
283 struct net_device *netdev = adapter->netdev;
284 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
285 struct ixgbe_tx_buffer *tx_buffer_info;
286 unsigned int i, eop, count = 0;
287 unsigned int total_bytes = 0, total_packets = 0;
288
289 i = tx_ring->next_to_clean;
290 eop = tx_ring->tx_buffer_info[i].next_to_watch;
291 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
292
293 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
294 (count < tx_ring->work_limit)) {
295 bool cleaned = false;
296 for ( ; !cleaned; count++) {
297 struct sk_buff *skb;
298 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
299 tx_buffer_info = &tx_ring->tx_buffer_info[i];
300 cleaned = (i == eop);
301 skb = tx_buffer_info->skb;
302
303 if (cleaned && skb) {
304 unsigned int segs, bytecount;
305 unsigned int hlen = skb_headlen(skb);
306
307 /* gso_segs is currently only valid for tcp */
308 segs = skb_shinfo(skb)->gso_segs ?: 1;
309 #ifdef IXGBE_FCOE
310 /* adjust for FCoE Sequence Offload */
311 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
312 && (skb->protocol == htons(ETH_P_FCOE)) &&
313 skb_is_gso(skb)) {
314 hlen = skb_transport_offset(skb) +
315 sizeof(struct fc_frame_header) +
316 sizeof(struct fcoe_crc_eof);
317 segs = DIV_ROUND_UP(skb->len - hlen,
318 skb_shinfo(skb)->gso_size);
319 }
320 #endif /* IXGBE_FCOE */
321 /* multiply data chunks by size of headers */
322 bytecount = ((segs - 1) * hlen) + skb->len;
323 total_packets += segs;
324 total_bytes += bytecount;
325 }
326
327 ixgbe_unmap_and_free_tx_resource(adapter,
328 tx_buffer_info);
329
330 tx_desc->wb.status = 0;
331
332 i++;
333 if (i == tx_ring->count)
334 i = 0;
335 }
336
337 eop = tx_ring->tx_buffer_info[i].next_to_watch;
338 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
339 }
340
341 tx_ring->next_to_clean = i;
342
343 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
344 if (unlikely(count && netif_carrier_ok(netdev) &&
345 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
346 /* Make sure that anybody stopping the queue after this
347 * sees the new next_to_clean.
348 */
349 smp_mb();
350 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
351 !test_bit(__IXGBE_DOWN, &adapter->state)) {
352 netif_wake_subqueue(netdev, tx_ring->queue_index);
353 ++adapter->restart_queue;
354 }
355 }
356
357 if (adapter->detect_tx_hung) {
358 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
359 /* schedule immediate reset if we believe we hung */
360 DPRINTK(PROBE, INFO,
361 "tx hang %d detected, resetting adapter\n",
362 adapter->tx_timeout_count + 1);
363 ixgbe_tx_timeout(adapter->netdev);
364 }
365 }
366
367 /* re-arm the interrupt */
368 if (count >= tx_ring->work_limit)
369 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
370
371 tx_ring->total_bytes += total_bytes;
372 tx_ring->total_packets += total_packets;
373 tx_ring->stats.packets += total_packets;
374 tx_ring->stats.bytes += total_bytes;
375 netdev->stats.tx_bytes += total_bytes;
376 netdev->stats.tx_packets += total_packets;
377 return (count < tx_ring->work_limit);
378 }
379
380 #ifdef CONFIG_IXGBE_DCA
381 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
382 struct ixgbe_ring *rx_ring)
383 {
384 u32 rxctrl;
385 int cpu = get_cpu();
386 int q = rx_ring - adapter->rx_ring;
387
388 if (rx_ring->cpu != cpu) {
389 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
390 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
391 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
392 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
393 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
394 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
395 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
396 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
397 }
398 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
399 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
400 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
401 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
402 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
404 rx_ring->cpu = cpu;
405 }
406 put_cpu();
407 }
408
409 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
410 struct ixgbe_ring *tx_ring)
411 {
412 u32 txctrl;
413 int cpu = get_cpu();
414 int q = tx_ring - adapter->tx_ring;
415
416 if (tx_ring->cpu != cpu) {
417 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
418 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
419 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
420 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
421 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
422 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
423 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
424 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
425 }
426 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
428 tx_ring->cpu = cpu;
429 }
430 put_cpu();
431 }
432
433 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
434 {
435 int i;
436
437 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
438 return;
439
440 /* always use CB2 mode, difference is masked in the CB driver */
441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
442
443 for (i = 0; i < adapter->num_tx_queues; i++) {
444 adapter->tx_ring[i].cpu = -1;
445 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
446 }
447 for (i = 0; i < adapter->num_rx_queues; i++) {
448 adapter->rx_ring[i].cpu = -1;
449 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
450 }
451 }
452
453 static int __ixgbe_notify_dca(struct device *dev, void *data)
454 {
455 struct net_device *netdev = dev_get_drvdata(dev);
456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
457 unsigned long event = *(unsigned long *)data;
458
459 switch (event) {
460 case DCA_PROVIDER_ADD:
461 /* if we're already enabled, don't do it again */
462 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
463 break;
464 if (dca_add_requester(dev) == 0) {
465 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
466 ixgbe_setup_dca(adapter);
467 break;
468 }
469 /* Fall Through since DCA is disabled. */
470 case DCA_PROVIDER_REMOVE:
471 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
472 dca_remove_requester(dev);
473 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
475 }
476 break;
477 }
478
479 return 0;
480 }
481
482 #endif /* CONFIG_IXGBE_DCA */
483 /**
484 * ixgbe_receive_skb - Send a completed packet up the stack
485 * @adapter: board private structure
486 * @skb: packet to send up
487 * @status: hardware indication of status of receive
488 * @rx_ring: rx descriptor ring (for a specific queue) to setup
489 * @rx_desc: rx descriptor
490 **/
491 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
492 struct sk_buff *skb, u8 status,
493 struct ixgbe_ring *ring,
494 union ixgbe_adv_rx_desc *rx_desc)
495 {
496 struct ixgbe_adapter *adapter = q_vector->adapter;
497 struct napi_struct *napi = &q_vector->napi;
498 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
499 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
500
501 skb_record_rx_queue(skb, ring->queue_index);
502 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
503 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
504 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
505 else
506 napi_gro_receive(napi, skb);
507 } else {
508 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
509 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
510 else
511 netif_rx(skb);
512 }
513 }
514
515 /**
516 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
517 * @adapter: address of board private structure
518 * @status_err: hardware indication of status of receive
519 * @skb: skb currently being received and modified
520 **/
521 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
522 union ixgbe_adv_rx_desc *rx_desc,
523 struct sk_buff *skb)
524 {
525 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
526
527 skb->ip_summed = CHECKSUM_NONE;
528
529 /* Rx csum disabled */
530 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
531 return;
532
533 /* if IP and error */
534 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
535 (status_err & IXGBE_RXDADV_ERR_IPE)) {
536 adapter->hw_csum_rx_error++;
537 return;
538 }
539
540 if (!(status_err & IXGBE_RXD_STAT_L4CS))
541 return;
542
543 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
544 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
545
546 /*
547 * 82599 errata, UDP frames with a 0 checksum can be marked as
548 * checksum errors.
549 */
550 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
551 (adapter->hw.mac.type == ixgbe_mac_82599EB))
552 return;
553
554 adapter->hw_csum_rx_error++;
555 return;
556 }
557
558 /* It must be a TCP or UDP packet with a valid checksum */
559 skb->ip_summed = CHECKSUM_UNNECESSARY;
560 adapter->hw_csum_rx_good++;
561 }
562
563 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
564 struct ixgbe_ring *rx_ring, u32 val)
565 {
566 /*
567 * Force memory writes to complete before letting h/w
568 * know there are new descriptors to fetch. (Only
569 * applicable for weak-ordered memory model archs,
570 * such as IA-64).
571 */
572 wmb();
573 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
574 }
575
576 /**
577 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
578 * @adapter: address of board private structure
579 **/
580 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
581 struct ixgbe_ring *rx_ring,
582 int cleaned_count)
583 {
584 struct pci_dev *pdev = adapter->pdev;
585 union ixgbe_adv_rx_desc *rx_desc;
586 struct ixgbe_rx_buffer *bi;
587 unsigned int i;
588
589 i = rx_ring->next_to_use;
590 bi = &rx_ring->rx_buffer_info[i];
591
592 while (cleaned_count--) {
593 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
594
595 if (!bi->page_dma &&
596 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
597 if (!bi->page) {
598 bi->page = alloc_page(GFP_ATOMIC);
599 if (!bi->page) {
600 adapter->alloc_rx_page_failed++;
601 goto no_buffers;
602 }
603 bi->page_offset = 0;
604 } else {
605 /* use a half page if we're re-using */
606 bi->page_offset ^= (PAGE_SIZE / 2);
607 }
608
609 bi->page_dma = pci_map_page(pdev, bi->page,
610 bi->page_offset,
611 (PAGE_SIZE / 2),
612 PCI_DMA_FROMDEVICE);
613 }
614
615 if (!bi->skb) {
616 struct sk_buff *skb;
617 skb = netdev_alloc_skb(adapter->netdev,
618 (rx_ring->rx_buf_len +
619 NET_IP_ALIGN));
620
621 if (!skb) {
622 adapter->alloc_rx_buff_failed++;
623 goto no_buffers;
624 }
625
626 /*
627 * Make buffer alignment 2 beyond a 16 byte boundary
628 * this will result in a 16 byte aligned IP header after
629 * the 14 byte MAC header is removed
630 */
631 skb_reserve(skb, NET_IP_ALIGN);
632
633 bi->skb = skb;
634 bi->dma = pci_map_single(pdev, skb->data,
635 rx_ring->rx_buf_len,
636 PCI_DMA_FROMDEVICE);
637 }
638 /* Refresh the desc even if buffer_addrs didn't change because
639 * each write-back erases this info. */
640 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
641 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
642 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
643 } else {
644 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
645 }
646
647 i++;
648 if (i == rx_ring->count)
649 i = 0;
650 bi = &rx_ring->rx_buffer_info[i];
651 }
652
653 no_buffers:
654 if (rx_ring->next_to_use != i) {
655 rx_ring->next_to_use = i;
656 if (i-- == 0)
657 i = (rx_ring->count - 1);
658
659 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
660 }
661 }
662
663 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
664 {
665 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
666 }
667
668 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
669 {
670 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
671 }
672
673 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
674 {
675 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
676 IXGBE_RXDADV_RSCCNT_MASK) >>
677 IXGBE_RXDADV_RSCCNT_SHIFT;
678 }
679
680 /**
681 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
682 * @skb: pointer to the last skb in the rsc queue
683 *
684 * This function changes a queue full of hw rsc buffers into a completed
685 * packet. It uses the ->prev pointers to find the first packet and then
686 * turns it into the frag list owner.
687 **/
688 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
689 {
690 unsigned int frag_list_size = 0;
691
692 while (skb->prev) {
693 struct sk_buff *prev = skb->prev;
694 frag_list_size += skb->len;
695 skb->prev = NULL;
696 skb = prev;
697 }
698
699 skb_shinfo(skb)->frag_list = skb->next;
700 skb->next = NULL;
701 skb->len += frag_list_size;
702 skb->data_len += frag_list_size;
703 skb->truesize += frag_list_size;
704 return skb;
705 }
706
707 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
708 struct ixgbe_ring *rx_ring,
709 int *work_done, int work_to_do)
710 {
711 struct ixgbe_adapter *adapter = q_vector->adapter;
712 struct net_device *netdev = adapter->netdev;
713 struct pci_dev *pdev = adapter->pdev;
714 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
715 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
716 struct sk_buff *skb;
717 unsigned int i, rsc_count = 0;
718 u32 len, staterr;
719 u16 hdr_info;
720 bool cleaned = false;
721 int cleaned_count = 0;
722 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
723 #ifdef IXGBE_FCOE
724 int ddp_bytes = 0;
725 #endif /* IXGBE_FCOE */
726
727 i = rx_ring->next_to_clean;
728 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
729 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
730 rx_buffer_info = &rx_ring->rx_buffer_info[i];
731
732 while (staterr & IXGBE_RXD_STAT_DD) {
733 u32 upper_len = 0;
734 if (*work_done >= work_to_do)
735 break;
736 (*work_done)++;
737
738 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
739 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
740 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
741 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
742 if (hdr_info & IXGBE_RXDADV_SPH)
743 adapter->rx_hdr_split++;
744 if (len > IXGBE_RX_HDR_SIZE)
745 len = IXGBE_RX_HDR_SIZE;
746 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
747 } else {
748 len = le16_to_cpu(rx_desc->wb.upper.length);
749 }
750
751 cleaned = true;
752 skb = rx_buffer_info->skb;
753 prefetch(skb->data - NET_IP_ALIGN);
754 rx_buffer_info->skb = NULL;
755
756 if (rx_buffer_info->dma) {
757 pci_unmap_single(pdev, rx_buffer_info->dma,
758 rx_ring->rx_buf_len,
759 PCI_DMA_FROMDEVICE);
760 rx_buffer_info->dma = 0;
761 skb_put(skb, len);
762 }
763
764 if (upper_len) {
765 pci_unmap_page(pdev, rx_buffer_info->page_dma,
766 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
767 rx_buffer_info->page_dma = 0;
768 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
769 rx_buffer_info->page,
770 rx_buffer_info->page_offset,
771 upper_len);
772
773 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
774 (page_count(rx_buffer_info->page) != 1))
775 rx_buffer_info->page = NULL;
776 else
777 get_page(rx_buffer_info->page);
778
779 skb->len += upper_len;
780 skb->data_len += upper_len;
781 skb->truesize += upper_len;
782 }
783
784 i++;
785 if (i == rx_ring->count)
786 i = 0;
787
788 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
789 prefetch(next_rxd);
790 cleaned_count++;
791
792 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
793 rsc_count = ixgbe_get_rsc_count(rx_desc);
794
795 if (rsc_count) {
796 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
797 IXGBE_RXDADV_NEXTP_SHIFT;
798 next_buffer = &rx_ring->rx_buffer_info[nextp];
799 rx_ring->rsc_count += (rsc_count - 1);
800 } else {
801 next_buffer = &rx_ring->rx_buffer_info[i];
802 }
803
804 if (staterr & IXGBE_RXD_STAT_EOP) {
805 if (skb->prev)
806 skb = ixgbe_transform_rsc_queue(skb);
807 rx_ring->stats.packets++;
808 rx_ring->stats.bytes += skb->len;
809 } else {
810 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
811 rx_buffer_info->skb = next_buffer->skb;
812 rx_buffer_info->dma = next_buffer->dma;
813 next_buffer->skb = skb;
814 next_buffer->dma = 0;
815 } else {
816 skb->next = next_buffer->skb;
817 skb->next->prev = skb;
818 }
819 adapter->non_eop_descs++;
820 goto next_desc;
821 }
822
823 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
824 dev_kfree_skb_irq(skb);
825 goto next_desc;
826 }
827
828 ixgbe_rx_checksum(adapter, rx_desc, skb);
829
830 /* probably a little skewed due to removing CRC */
831 total_rx_bytes += skb->len;
832 total_rx_packets++;
833
834 skb->protocol = eth_type_trans(skb, adapter->netdev);
835 #ifdef IXGBE_FCOE
836 /* if ddp, not passing to ULD unless for FCP_RSP or error */
837 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
838 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
839 if (!ddp_bytes)
840 goto next_desc;
841 }
842 #endif /* IXGBE_FCOE */
843 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
844
845 next_desc:
846 rx_desc->wb.upper.status_error = 0;
847
848 /* return some buffers to hardware, one at a time is too slow */
849 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
850 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
851 cleaned_count = 0;
852 }
853
854 /* use prefetched values */
855 rx_desc = next_rxd;
856 rx_buffer_info = &rx_ring->rx_buffer_info[i];
857
858 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
859 }
860
861 rx_ring->next_to_clean = i;
862 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
863
864 if (cleaned_count)
865 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
866
867 #ifdef IXGBE_FCOE
868 /* include DDPed FCoE data */
869 if (ddp_bytes > 0) {
870 unsigned int mss;
871
872 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
873 sizeof(struct fc_frame_header) -
874 sizeof(struct fcoe_crc_eof);
875 if (mss > 512)
876 mss &= ~511;
877 total_rx_bytes += ddp_bytes;
878 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
879 }
880 #endif /* IXGBE_FCOE */
881
882 rx_ring->total_packets += total_rx_packets;
883 rx_ring->total_bytes += total_rx_bytes;
884 netdev->stats.rx_bytes += total_rx_bytes;
885 netdev->stats.rx_packets += total_rx_packets;
886
887 return cleaned;
888 }
889
890 static int ixgbe_clean_rxonly(struct napi_struct *, int);
891 /**
892 * ixgbe_configure_msix - Configure MSI-X hardware
893 * @adapter: board private structure
894 *
895 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
896 * interrupts.
897 **/
898 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
899 {
900 struct ixgbe_q_vector *q_vector;
901 int i, j, q_vectors, v_idx, r_idx;
902 u32 mask;
903
904 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
905
906 /*
907 * Populate the IVAR table and set the ITR values to the
908 * corresponding register.
909 */
910 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
911 q_vector = adapter->q_vector[v_idx];
912 /* XXX for_each_bit(...) */
913 r_idx = find_first_bit(q_vector->rxr_idx,
914 adapter->num_rx_queues);
915
916 for (i = 0; i < q_vector->rxr_count; i++) {
917 j = adapter->rx_ring[r_idx].reg_idx;
918 ixgbe_set_ivar(adapter, 0, j, v_idx);
919 r_idx = find_next_bit(q_vector->rxr_idx,
920 adapter->num_rx_queues,
921 r_idx + 1);
922 }
923 r_idx = find_first_bit(q_vector->txr_idx,
924 adapter->num_tx_queues);
925
926 for (i = 0; i < q_vector->txr_count; i++) {
927 j = adapter->tx_ring[r_idx].reg_idx;
928 ixgbe_set_ivar(adapter, 1, j, v_idx);
929 r_idx = find_next_bit(q_vector->txr_idx,
930 adapter->num_tx_queues,
931 r_idx + 1);
932 }
933
934 if (q_vector->txr_count && !q_vector->rxr_count)
935 /* tx only */
936 q_vector->eitr = adapter->tx_eitr_param;
937 else if (q_vector->rxr_count)
938 /* rx or mixed */
939 q_vector->eitr = adapter->rx_eitr_param;
940
941 ixgbe_write_eitr(q_vector);
942 }
943
944 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
945 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
946 v_idx);
947 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
948 ixgbe_set_ivar(adapter, -1, 1, v_idx);
949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
950
951 /* set up to autoclear timer, and the vectors */
952 mask = IXGBE_EIMS_ENABLE_MASK;
953 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
954 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
955 }
956
957 enum latency_range {
958 lowest_latency = 0,
959 low_latency = 1,
960 bulk_latency = 2,
961 latency_invalid = 255
962 };
963
964 /**
965 * ixgbe_update_itr - update the dynamic ITR value based on statistics
966 * @adapter: pointer to adapter
967 * @eitr: eitr setting (ints per sec) to give last timeslice
968 * @itr_setting: current throttle rate in ints/second
969 * @packets: the number of packets during this measurement interval
970 * @bytes: the number of bytes during this measurement interval
971 *
972 * Stores a new ITR value based on packets and byte
973 * counts during the last interrupt. The advantage of per interrupt
974 * computation is faster updates and more accurate ITR for the current
975 * traffic pattern. Constants in this function were computed
976 * based on theoretical maximum wire speed and thresholds were set based
977 * on testing data as well as attempting to minimize response time
978 * while increasing bulk throughput.
979 * this functionality is controlled by the InterruptThrottleRate module
980 * parameter (see ixgbe_param.c)
981 **/
982 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
983 u32 eitr, u8 itr_setting,
984 int packets, int bytes)
985 {
986 unsigned int retval = itr_setting;
987 u32 timepassed_us;
988 u64 bytes_perint;
989
990 if (packets == 0)
991 goto update_itr_done;
992
993
994 /* simple throttlerate management
995 * 0-20MB/s lowest (100000 ints/s)
996 * 20-100MB/s low (20000 ints/s)
997 * 100-1249MB/s bulk (8000 ints/s)
998 */
999 /* what was last interrupt timeslice? */
1000 timepassed_us = 1000000/eitr;
1001 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1002
1003 switch (itr_setting) {
1004 case lowest_latency:
1005 if (bytes_perint > adapter->eitr_low)
1006 retval = low_latency;
1007 break;
1008 case low_latency:
1009 if (bytes_perint > adapter->eitr_high)
1010 retval = bulk_latency;
1011 else if (bytes_perint <= adapter->eitr_low)
1012 retval = lowest_latency;
1013 break;
1014 case bulk_latency:
1015 if (bytes_perint <= adapter->eitr_high)
1016 retval = low_latency;
1017 break;
1018 }
1019
1020 update_itr_done:
1021 return retval;
1022 }
1023
1024 /**
1025 * ixgbe_write_eitr - write EITR register in hardware specific way
1026 * @q_vector: structure containing interrupt and ring information
1027 *
1028 * This function is made to be called by ethtool and by the driver
1029 * when it needs to update EITR registers at runtime. Hardware
1030 * specific quirks/differences are taken care of here.
1031 */
1032 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1033 {
1034 struct ixgbe_adapter *adapter = q_vector->adapter;
1035 struct ixgbe_hw *hw = &adapter->hw;
1036 int v_idx = q_vector->v_idx;
1037 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1038
1039 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1040 /* must write high and low 16 bits to reset counter */
1041 itr_reg |= (itr_reg << 16);
1042 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1043 /*
1044 * set the WDIS bit to not clear the timer bits and cause an
1045 * immediate assertion of the interrupt
1046 */
1047 itr_reg |= IXGBE_EITR_CNT_WDIS;
1048 }
1049 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1050 }
1051
1052 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1053 {
1054 struct ixgbe_adapter *adapter = q_vector->adapter;
1055 u32 new_itr;
1056 u8 current_itr, ret_itr;
1057 int i, r_idx;
1058 struct ixgbe_ring *rx_ring, *tx_ring;
1059
1060 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1061 for (i = 0; i < q_vector->txr_count; i++) {
1062 tx_ring = &(adapter->tx_ring[r_idx]);
1063 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1064 q_vector->tx_itr,
1065 tx_ring->total_packets,
1066 tx_ring->total_bytes);
1067 /* if the result for this queue would decrease interrupt
1068 * rate for this vector then use that result */
1069 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1070 q_vector->tx_itr - 1 : ret_itr);
1071 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1072 r_idx + 1);
1073 }
1074
1075 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1076 for (i = 0; i < q_vector->rxr_count; i++) {
1077 rx_ring = &(adapter->rx_ring[r_idx]);
1078 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1079 q_vector->rx_itr,
1080 rx_ring->total_packets,
1081 rx_ring->total_bytes);
1082 /* if the result for this queue would decrease interrupt
1083 * rate for this vector then use that result */
1084 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1085 q_vector->rx_itr - 1 : ret_itr);
1086 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1087 r_idx + 1);
1088 }
1089
1090 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1091
1092 switch (current_itr) {
1093 /* counts and packets in update_itr are dependent on these numbers */
1094 case lowest_latency:
1095 new_itr = 100000;
1096 break;
1097 case low_latency:
1098 new_itr = 20000; /* aka hwitr = ~200 */
1099 break;
1100 case bulk_latency:
1101 default:
1102 new_itr = 8000;
1103 break;
1104 }
1105
1106 if (new_itr != q_vector->eitr) {
1107 /* do an exponential smoothing */
1108 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1109
1110 /* save the algorithm value here, not the smoothed one */
1111 q_vector->eitr = new_itr;
1112
1113 ixgbe_write_eitr(q_vector);
1114 }
1115
1116 return;
1117 }
1118
1119 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1120 {
1121 struct ixgbe_hw *hw = &adapter->hw;
1122
1123 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1124 (eicr & IXGBE_EICR_GPI_SDP1)) {
1125 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1126 /* write to clear the interrupt */
1127 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1128 }
1129 }
1130
1131 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1132 {
1133 struct ixgbe_hw *hw = &adapter->hw;
1134
1135 if (eicr & IXGBE_EICR_GPI_SDP1) {
1136 /* Clear the interrupt */
1137 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1138 schedule_work(&adapter->multispeed_fiber_task);
1139 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1140 /* Clear the interrupt */
1141 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1142 schedule_work(&adapter->sfp_config_module_task);
1143 } else {
1144 /* Interrupt isn't for us... */
1145 return;
1146 }
1147 }
1148
1149 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1150 {
1151 struct ixgbe_hw *hw = &adapter->hw;
1152
1153 adapter->lsc_int++;
1154 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1155 adapter->link_check_timeout = jiffies;
1156 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1157 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1158 schedule_work(&adapter->watchdog_task);
1159 }
1160 }
1161
1162 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1163 {
1164 struct net_device *netdev = data;
1165 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1166 struct ixgbe_hw *hw = &adapter->hw;
1167 u32 eicr;
1168
1169 /*
1170 * Workaround for Silicon errata. Use clear-by-write instead
1171 * of clear-by-read. Reading with EICS will return the
1172 * interrupt causes without clearing, which later be done
1173 * with the write to EICR.
1174 */
1175 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1176 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1177
1178 if (eicr & IXGBE_EICR_LSC)
1179 ixgbe_check_lsc(adapter);
1180
1181 if (hw->mac.type == ixgbe_mac_82598EB)
1182 ixgbe_check_fan_failure(adapter, eicr);
1183
1184 if (hw->mac.type == ixgbe_mac_82599EB) {
1185 ixgbe_check_sfp_event(adapter, eicr);
1186
1187 /* Handle Flow Director Full threshold interrupt */
1188 if (eicr & IXGBE_EICR_FLOW_DIR) {
1189 int i;
1190 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1191 /* Disable transmits before FDIR Re-initialization */
1192 netif_tx_stop_all_queues(netdev);
1193 for (i = 0; i < adapter->num_tx_queues; i++) {
1194 struct ixgbe_ring *tx_ring =
1195 &adapter->tx_ring[i];
1196 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1197 &tx_ring->reinit_state))
1198 schedule_work(&adapter->fdir_reinit_task);
1199 }
1200 }
1201 }
1202 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1203 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1204
1205 return IRQ_HANDLED;
1206 }
1207
1208 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1209 u64 qmask)
1210 {
1211 u32 mask;
1212
1213 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1214 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1216 } else {
1217 mask = (qmask & 0xFFFFFFFF);
1218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1219 mask = (qmask >> 32);
1220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1221 }
1222 /* skip the flush */
1223 }
1224
1225 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1226 u64 qmask)
1227 {
1228 u32 mask;
1229
1230 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1231 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1233 } else {
1234 mask = (qmask & 0xFFFFFFFF);
1235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1236 mask = (qmask >> 32);
1237 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1238 }
1239 /* skip the flush */
1240 }
1241
1242 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1243 {
1244 struct ixgbe_q_vector *q_vector = data;
1245 struct ixgbe_adapter *adapter = q_vector->adapter;
1246 struct ixgbe_ring *tx_ring;
1247 int i, r_idx;
1248
1249 if (!q_vector->txr_count)
1250 return IRQ_HANDLED;
1251
1252 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1253 for (i = 0; i < q_vector->txr_count; i++) {
1254 tx_ring = &(adapter->tx_ring[r_idx]);
1255 tx_ring->total_bytes = 0;
1256 tx_ring->total_packets = 0;
1257 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1258 r_idx + 1);
1259 }
1260
1261 /* disable interrupts on this vector only */
1262 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1263 napi_schedule(&q_vector->napi);
1264
1265 return IRQ_HANDLED;
1266 }
1267
1268 /**
1269 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1270 * @irq: unused
1271 * @data: pointer to our q_vector struct for this interrupt vector
1272 **/
1273 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1274 {
1275 struct ixgbe_q_vector *q_vector = data;
1276 struct ixgbe_adapter *adapter = q_vector->adapter;
1277 struct ixgbe_ring *rx_ring;
1278 int r_idx;
1279 int i;
1280
1281 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1282 for (i = 0; i < q_vector->rxr_count; i++) {
1283 rx_ring = &(adapter->rx_ring[r_idx]);
1284 rx_ring->total_bytes = 0;
1285 rx_ring->total_packets = 0;
1286 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1287 r_idx + 1);
1288 }
1289
1290 if (!q_vector->rxr_count)
1291 return IRQ_HANDLED;
1292
1293 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1294 rx_ring = &(adapter->rx_ring[r_idx]);
1295 /* disable interrupts on this vector only */
1296 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1297 napi_schedule(&q_vector->napi);
1298
1299 return IRQ_HANDLED;
1300 }
1301
1302 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1303 {
1304 struct ixgbe_q_vector *q_vector = data;
1305 struct ixgbe_adapter *adapter = q_vector->adapter;
1306 struct ixgbe_ring *ring;
1307 int r_idx;
1308 int i;
1309
1310 if (!q_vector->txr_count && !q_vector->rxr_count)
1311 return IRQ_HANDLED;
1312
1313 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1314 for (i = 0; i < q_vector->txr_count; i++) {
1315 ring = &(adapter->tx_ring[r_idx]);
1316 ring->total_bytes = 0;
1317 ring->total_packets = 0;
1318 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1319 r_idx + 1);
1320 }
1321
1322 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1323 for (i = 0; i < q_vector->rxr_count; i++) {
1324 ring = &(adapter->rx_ring[r_idx]);
1325 ring->total_bytes = 0;
1326 ring->total_packets = 0;
1327 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1328 r_idx + 1);
1329 }
1330
1331 /* disable interrupts on this vector only */
1332 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1333 napi_schedule(&q_vector->napi);
1334
1335 return IRQ_HANDLED;
1336 }
1337
1338 /**
1339 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1340 * @napi: napi struct with our devices info in it
1341 * @budget: amount of work driver is allowed to do this pass, in packets
1342 *
1343 * This function is optimized for cleaning one queue only on a single
1344 * q_vector!!!
1345 **/
1346 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1347 {
1348 struct ixgbe_q_vector *q_vector =
1349 container_of(napi, struct ixgbe_q_vector, napi);
1350 struct ixgbe_adapter *adapter = q_vector->adapter;
1351 struct ixgbe_ring *rx_ring = NULL;
1352 int work_done = 0;
1353 long r_idx;
1354
1355 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1356 rx_ring = &(adapter->rx_ring[r_idx]);
1357 #ifdef CONFIG_IXGBE_DCA
1358 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1359 ixgbe_update_rx_dca(adapter, rx_ring);
1360 #endif
1361
1362 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1363
1364 /* If all Rx work done, exit the polling mode */
1365 if (work_done < budget) {
1366 napi_complete(napi);
1367 if (adapter->rx_itr_setting & 1)
1368 ixgbe_set_itr_msix(q_vector);
1369 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1370 ixgbe_irq_enable_queues(adapter,
1371 ((u64)1 << q_vector->v_idx));
1372 }
1373
1374 return work_done;
1375 }
1376
1377 /**
1378 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1379 * @napi: napi struct with our devices info in it
1380 * @budget: amount of work driver is allowed to do this pass, in packets
1381 *
1382 * This function will clean more than one rx queue associated with a
1383 * q_vector.
1384 **/
1385 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1386 {
1387 struct ixgbe_q_vector *q_vector =
1388 container_of(napi, struct ixgbe_q_vector, napi);
1389 struct ixgbe_adapter *adapter = q_vector->adapter;
1390 struct ixgbe_ring *ring = NULL;
1391 int work_done = 0, i;
1392 long r_idx;
1393 bool tx_clean_complete = true;
1394
1395 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1396 for (i = 0; i < q_vector->txr_count; i++) {
1397 ring = &(adapter->tx_ring[r_idx]);
1398 #ifdef CONFIG_IXGBE_DCA
1399 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1400 ixgbe_update_tx_dca(adapter, ring);
1401 #endif
1402 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1403 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1404 r_idx + 1);
1405 }
1406
1407 /* attempt to distribute budget to each queue fairly, but don't allow
1408 * the budget to go below 1 because we'll exit polling */
1409 budget /= (q_vector->rxr_count ?: 1);
1410 budget = max(budget, 1);
1411 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1412 for (i = 0; i < q_vector->rxr_count; i++) {
1413 ring = &(adapter->rx_ring[r_idx]);
1414 #ifdef CONFIG_IXGBE_DCA
1415 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1416 ixgbe_update_rx_dca(adapter, ring);
1417 #endif
1418 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1419 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1420 r_idx + 1);
1421 }
1422
1423 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1424 ring = &(adapter->rx_ring[r_idx]);
1425 /* If all Rx work done, exit the polling mode */
1426 if (work_done < budget) {
1427 napi_complete(napi);
1428 if (adapter->rx_itr_setting & 1)
1429 ixgbe_set_itr_msix(q_vector);
1430 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1431 ixgbe_irq_enable_queues(adapter,
1432 ((u64)1 << q_vector->v_idx));
1433 return 0;
1434 }
1435
1436 return work_done;
1437 }
1438
1439 /**
1440 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1441 * @napi: napi struct with our devices info in it
1442 * @budget: amount of work driver is allowed to do this pass, in packets
1443 *
1444 * This function is optimized for cleaning one queue only on a single
1445 * q_vector!!!
1446 **/
1447 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1448 {
1449 struct ixgbe_q_vector *q_vector =
1450 container_of(napi, struct ixgbe_q_vector, napi);
1451 struct ixgbe_adapter *adapter = q_vector->adapter;
1452 struct ixgbe_ring *tx_ring = NULL;
1453 int work_done = 0;
1454 long r_idx;
1455
1456 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1457 tx_ring = &(adapter->tx_ring[r_idx]);
1458 #ifdef CONFIG_IXGBE_DCA
1459 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1460 ixgbe_update_tx_dca(adapter, tx_ring);
1461 #endif
1462
1463 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1464 work_done = budget;
1465
1466 /* If all Tx work done, exit the polling mode */
1467 if (work_done < budget) {
1468 napi_complete(napi);
1469 if (adapter->tx_itr_setting & 1)
1470 ixgbe_set_itr_msix(q_vector);
1471 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1472 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1473 }
1474
1475 return work_done;
1476 }
1477
1478 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1479 int r_idx)
1480 {
1481 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1482
1483 set_bit(r_idx, q_vector->rxr_idx);
1484 q_vector->rxr_count++;
1485 }
1486
1487 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1488 int t_idx)
1489 {
1490 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1491
1492 set_bit(t_idx, q_vector->txr_idx);
1493 q_vector->txr_count++;
1494 }
1495
1496 /**
1497 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1498 * @adapter: board private structure to initialize
1499 * @vectors: allotted vector count for descriptor rings
1500 *
1501 * This function maps descriptor rings to the queue-specific vectors
1502 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1503 * one vector per ring/queue, but on a constrained vector budget, we
1504 * group the rings as "efficiently" as possible. You would add new
1505 * mapping configurations in here.
1506 **/
1507 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1508 int vectors)
1509 {
1510 int v_start = 0;
1511 int rxr_idx = 0, txr_idx = 0;
1512 int rxr_remaining = adapter->num_rx_queues;
1513 int txr_remaining = adapter->num_tx_queues;
1514 int i, j;
1515 int rqpv, tqpv;
1516 int err = 0;
1517
1518 /* No mapping required if MSI-X is disabled. */
1519 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1520 goto out;
1521
1522 /*
1523 * The ideal configuration...
1524 * We have enough vectors to map one per queue.
1525 */
1526 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1527 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1528 map_vector_to_rxq(adapter, v_start, rxr_idx);
1529
1530 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1531 map_vector_to_txq(adapter, v_start, txr_idx);
1532
1533 goto out;
1534 }
1535
1536 /*
1537 * If we don't have enough vectors for a 1-to-1
1538 * mapping, we'll have to group them so there are
1539 * multiple queues per vector.
1540 */
1541 /* Re-adjusting *qpv takes care of the remainder. */
1542 for (i = v_start; i < vectors; i++) {
1543 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1544 for (j = 0; j < rqpv; j++) {
1545 map_vector_to_rxq(adapter, i, rxr_idx);
1546 rxr_idx++;
1547 rxr_remaining--;
1548 }
1549 }
1550 for (i = v_start; i < vectors; i++) {
1551 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1552 for (j = 0; j < tqpv; j++) {
1553 map_vector_to_txq(adapter, i, txr_idx);
1554 txr_idx++;
1555 txr_remaining--;
1556 }
1557 }
1558
1559 out:
1560 return err;
1561 }
1562
1563 /**
1564 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1565 * @adapter: board private structure
1566 *
1567 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1568 * interrupts from the kernel.
1569 **/
1570 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1571 {
1572 struct net_device *netdev = adapter->netdev;
1573 irqreturn_t (*handler)(int, void *);
1574 int i, vector, q_vectors, err;
1575 int ri=0, ti=0;
1576
1577 /* Decrement for Other and TCP Timer vectors */
1578 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1579
1580 /* Map the Tx/Rx rings to the vectors we were allotted. */
1581 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1582 if (err)
1583 goto out;
1584
1585 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1586 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1587 &ixgbe_msix_clean_many)
1588 for (vector = 0; vector < q_vectors; vector++) {
1589 handler = SET_HANDLER(adapter->q_vector[vector]);
1590
1591 if(handler == &ixgbe_msix_clean_rx) {
1592 sprintf(adapter->name[vector], "%s-%s-%d",
1593 netdev->name, "rx", ri++);
1594 }
1595 else if(handler == &ixgbe_msix_clean_tx) {
1596 sprintf(adapter->name[vector], "%s-%s-%d",
1597 netdev->name, "tx", ti++);
1598 }
1599 else
1600 sprintf(adapter->name[vector], "%s-%s-%d",
1601 netdev->name, "TxRx", vector);
1602
1603 err = request_irq(adapter->msix_entries[vector].vector,
1604 handler, 0, adapter->name[vector],
1605 adapter->q_vector[vector]);
1606 if (err) {
1607 DPRINTK(PROBE, ERR,
1608 "request_irq failed for MSIX interrupt "
1609 "Error: %d\n", err);
1610 goto free_queue_irqs;
1611 }
1612 }
1613
1614 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1615 err = request_irq(adapter->msix_entries[vector].vector,
1616 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1617 if (err) {
1618 DPRINTK(PROBE, ERR,
1619 "request_irq for msix_lsc failed: %d\n", err);
1620 goto free_queue_irqs;
1621 }
1622
1623 return 0;
1624
1625 free_queue_irqs:
1626 for (i = vector - 1; i >= 0; i--)
1627 free_irq(adapter->msix_entries[--vector].vector,
1628 adapter->q_vector[i]);
1629 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1630 pci_disable_msix(adapter->pdev);
1631 kfree(adapter->msix_entries);
1632 adapter->msix_entries = NULL;
1633 out:
1634 return err;
1635 }
1636
1637 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1638 {
1639 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1640 u8 current_itr;
1641 u32 new_itr = q_vector->eitr;
1642 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1643 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1644
1645 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1646 q_vector->tx_itr,
1647 tx_ring->total_packets,
1648 tx_ring->total_bytes);
1649 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1650 q_vector->rx_itr,
1651 rx_ring->total_packets,
1652 rx_ring->total_bytes);
1653
1654 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1655
1656 switch (current_itr) {
1657 /* counts and packets in update_itr are dependent on these numbers */
1658 case lowest_latency:
1659 new_itr = 100000;
1660 break;
1661 case low_latency:
1662 new_itr = 20000; /* aka hwitr = ~200 */
1663 break;
1664 case bulk_latency:
1665 new_itr = 8000;
1666 break;
1667 default:
1668 break;
1669 }
1670
1671 if (new_itr != q_vector->eitr) {
1672 /* do an exponential smoothing */
1673 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1674
1675 /* save the algorithm value here, not the smoothed one */
1676 q_vector->eitr = new_itr;
1677
1678 ixgbe_write_eitr(q_vector);
1679 }
1680
1681 return;
1682 }
1683
1684 /**
1685 * ixgbe_irq_enable - Enable default interrupt generation settings
1686 * @adapter: board private structure
1687 **/
1688 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1689 {
1690 u32 mask;
1691
1692 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1693 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1694 mask |= IXGBE_EIMS_GPI_SDP1;
1695 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1696 mask |= IXGBE_EIMS_ECC;
1697 mask |= IXGBE_EIMS_GPI_SDP1;
1698 mask |= IXGBE_EIMS_GPI_SDP2;
1699 }
1700 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1701 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1702 mask |= IXGBE_EIMS_FLOW_DIR;
1703
1704 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1705 ixgbe_irq_enable_queues(adapter, ~0);
1706 IXGBE_WRITE_FLUSH(&adapter->hw);
1707 }
1708
1709 /**
1710 * ixgbe_intr - legacy mode Interrupt Handler
1711 * @irq: interrupt number
1712 * @data: pointer to a network interface device structure
1713 **/
1714 static irqreturn_t ixgbe_intr(int irq, void *data)
1715 {
1716 struct net_device *netdev = data;
1717 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1718 struct ixgbe_hw *hw = &adapter->hw;
1719 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1720 u32 eicr;
1721
1722 /*
1723 * Workaround for silicon errata. Mask the interrupts
1724 * before the read of EICR.
1725 */
1726 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1727
1728 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1729 * therefore no explict interrupt disable is necessary */
1730 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1731 if (!eicr) {
1732 /* shared interrupt alert!
1733 * make sure interrupts are enabled because the read will
1734 * have disabled interrupts due to EIAM */
1735 ixgbe_irq_enable(adapter);
1736 return IRQ_NONE; /* Not our interrupt */
1737 }
1738
1739 if (eicr & IXGBE_EICR_LSC)
1740 ixgbe_check_lsc(adapter);
1741
1742 if (hw->mac.type == ixgbe_mac_82599EB)
1743 ixgbe_check_sfp_event(adapter, eicr);
1744
1745 ixgbe_check_fan_failure(adapter, eicr);
1746
1747 if (napi_schedule_prep(&(q_vector->napi))) {
1748 adapter->tx_ring[0].total_packets = 0;
1749 adapter->tx_ring[0].total_bytes = 0;
1750 adapter->rx_ring[0].total_packets = 0;
1751 adapter->rx_ring[0].total_bytes = 0;
1752 /* would disable interrupts here but EIAM disabled it */
1753 __napi_schedule(&(q_vector->napi));
1754 }
1755
1756 return IRQ_HANDLED;
1757 }
1758
1759 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1760 {
1761 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1762
1763 for (i = 0; i < q_vectors; i++) {
1764 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1765 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1766 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1767 q_vector->rxr_count = 0;
1768 q_vector->txr_count = 0;
1769 }
1770 }
1771
1772 /**
1773 * ixgbe_request_irq - initialize interrupts
1774 * @adapter: board private structure
1775 *
1776 * Attempts to configure interrupts using the best available
1777 * capabilities of the hardware and kernel.
1778 **/
1779 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1780 {
1781 struct net_device *netdev = adapter->netdev;
1782 int err;
1783
1784 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1785 err = ixgbe_request_msix_irqs(adapter);
1786 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1787 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1788 netdev->name, netdev);
1789 } else {
1790 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1791 netdev->name, netdev);
1792 }
1793
1794 if (err)
1795 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1796
1797 return err;
1798 }
1799
1800 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1801 {
1802 struct net_device *netdev = adapter->netdev;
1803
1804 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1805 int i, q_vectors;
1806
1807 q_vectors = adapter->num_msix_vectors;
1808
1809 i = q_vectors - 1;
1810 free_irq(adapter->msix_entries[i].vector, netdev);
1811
1812 i--;
1813 for (; i >= 0; i--) {
1814 free_irq(adapter->msix_entries[i].vector,
1815 adapter->q_vector[i]);
1816 }
1817
1818 ixgbe_reset_q_vectors(adapter);
1819 } else {
1820 free_irq(adapter->pdev->irq, netdev);
1821 }
1822 }
1823
1824 /**
1825 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1826 * @adapter: board private structure
1827 **/
1828 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1829 {
1830 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1832 } else {
1833 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1836 }
1837 IXGBE_WRITE_FLUSH(&adapter->hw);
1838 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1839 int i;
1840 for (i = 0; i < adapter->num_msix_vectors; i++)
1841 synchronize_irq(adapter->msix_entries[i].vector);
1842 } else {
1843 synchronize_irq(adapter->pdev->irq);
1844 }
1845 }
1846
1847 /**
1848 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1849 *
1850 **/
1851 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1852 {
1853 struct ixgbe_hw *hw = &adapter->hw;
1854
1855 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1856 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1857
1858 ixgbe_set_ivar(adapter, 0, 0, 0);
1859 ixgbe_set_ivar(adapter, 1, 0, 0);
1860
1861 map_vector_to_rxq(adapter, 0, 0);
1862 map_vector_to_txq(adapter, 0, 0);
1863
1864 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1865 }
1866
1867 /**
1868 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1869 * @adapter: board private structure
1870 *
1871 * Configure the Tx unit of the MAC after a reset.
1872 **/
1873 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1874 {
1875 u64 tdba;
1876 struct ixgbe_hw *hw = &adapter->hw;
1877 u32 i, j, tdlen, txctrl;
1878
1879 /* Setup the HW Tx Head and Tail descriptor pointers */
1880 for (i = 0; i < adapter->num_tx_queues; i++) {
1881 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1882 j = ring->reg_idx;
1883 tdba = ring->dma;
1884 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1885 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1886 (tdba & DMA_BIT_MASK(32)));
1887 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1888 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1889 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1890 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1891 adapter->tx_ring[i].head = IXGBE_TDH(j);
1892 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1893 /*
1894 * Disable Tx Head Writeback RO bit, since this hoses
1895 * bookkeeping if things aren't delivered in order.
1896 */
1897 switch (hw->mac.type) {
1898 case ixgbe_mac_82598EB:
1899 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1900 break;
1901 case ixgbe_mac_82599EB:
1902 default:
1903 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1904 break;
1905 }
1906 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1907 switch (hw->mac.type) {
1908 case ixgbe_mac_82598EB:
1909 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1910 break;
1911 case ixgbe_mac_82599EB:
1912 default:
1913 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1914 break;
1915 }
1916 }
1917 if (hw->mac.type == ixgbe_mac_82599EB) {
1918 /* We enable 8 traffic classes, DCB only */
1919 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1920 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1921 IXGBE_MTQC_8TC_8TQ));
1922 }
1923 }
1924
1925 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1926
1927 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1928 struct ixgbe_ring *rx_ring)
1929 {
1930 u32 srrctl;
1931 int index;
1932 struct ixgbe_ring_feature *feature = adapter->ring_feature;
1933
1934 index = rx_ring->reg_idx;
1935 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1936 unsigned long mask;
1937 mask = (unsigned long) feature[RING_F_RSS].mask;
1938 index = index & mask;
1939 }
1940 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1941
1942 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1943 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1944
1945 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1946 IXGBE_SRRCTL_BSIZEHDR_MASK;
1947
1948 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1949 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1950 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1951 #else
1952 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1953 #endif
1954 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1955 } else {
1956 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1957 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1958 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1959 }
1960
1961 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1962 }
1963
1964 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1965 {
1966 u32 mrqc = 0;
1967 int mask;
1968
1969 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1970 return mrqc;
1971
1972 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1973 #ifdef CONFIG_IXGBE_DCB
1974 | IXGBE_FLAG_DCB_ENABLED
1975 #endif
1976 );
1977
1978 switch (mask) {
1979 case (IXGBE_FLAG_RSS_ENABLED):
1980 mrqc = IXGBE_MRQC_RSSEN;
1981 break;
1982 #ifdef CONFIG_IXGBE_DCB
1983 case (IXGBE_FLAG_DCB_ENABLED):
1984 mrqc = IXGBE_MRQC_RT8TCEN;
1985 break;
1986 #endif /* CONFIG_IXGBE_DCB */
1987 default:
1988 break;
1989 }
1990
1991 return mrqc;
1992 }
1993
1994 /**
1995 * ixgbe_configure_rscctl - enable RSC for the indicated ring
1996 * @adapter: address of board private structure
1997 * @index: index of ring to set
1998 * @rx_buf_len: rx buffer length
1999 **/
2000 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2001 int rx_buf_len)
2002 {
2003 struct ixgbe_ring *rx_ring;
2004 struct ixgbe_hw *hw = &adapter->hw;
2005 int j;
2006 u32 rscctrl;
2007
2008 rx_ring = &adapter->rx_ring[index];
2009 j = rx_ring->reg_idx;
2010 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2011 rscctrl |= IXGBE_RSCCTL_RSCEN;
2012 /*
2013 * we must limit the number of descriptors so that the
2014 * total size of max desc * buf_len is not greater
2015 * than 65535
2016 */
2017 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2018 #if (MAX_SKB_FRAGS > 16)
2019 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2020 #elif (MAX_SKB_FRAGS > 8)
2021 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2022 #elif (MAX_SKB_FRAGS > 4)
2023 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2024 #else
2025 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2026 #endif
2027 } else {
2028 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2029 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2030 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2031 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2032 else
2033 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2034 }
2035 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2036 }
2037
2038 /**
2039 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2040 * @adapter: board private structure
2041 *
2042 * Configure the Rx unit of the MAC after a reset.
2043 **/
2044 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2045 {
2046 u64 rdba;
2047 struct ixgbe_hw *hw = &adapter->hw;
2048 struct ixgbe_ring *rx_ring;
2049 struct net_device *netdev = adapter->netdev;
2050 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2051 int i, j;
2052 u32 rdlen, rxctrl, rxcsum;
2053 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2054 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2055 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2056 u32 fctrl, hlreg0;
2057 u32 reta = 0, mrqc = 0;
2058 u32 rdrxctl;
2059 int rx_buf_len;
2060
2061 /* Decide whether to use packet split mode or not */
2062 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2063
2064 /* Set the RX buffer length according to the mode */
2065 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2066 rx_buf_len = IXGBE_RX_HDR_SIZE;
2067 if (hw->mac.type == ixgbe_mac_82599EB) {
2068 /* PSRTYPE must be initialized in 82599 */
2069 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2070 IXGBE_PSRTYPE_UDPHDR |
2071 IXGBE_PSRTYPE_IPV4HDR |
2072 IXGBE_PSRTYPE_IPV6HDR |
2073 IXGBE_PSRTYPE_L2HDR;
2074 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2075 }
2076 } else {
2077 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2078 (netdev->mtu <= ETH_DATA_LEN))
2079 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2080 else
2081 rx_buf_len = ALIGN(max_frame, 1024);
2082 }
2083
2084 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2085 fctrl |= IXGBE_FCTRL_BAM;
2086 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2087 fctrl |= IXGBE_FCTRL_PMCF;
2088 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2089
2090 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2091 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2092 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2093 else
2094 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2095 #ifdef IXGBE_FCOE
2096 if (netdev->features & NETIF_F_FCOE_MTU)
2097 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2098 #endif
2099 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2100
2101 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2102 /* disable receives while setting up the descriptors */
2103 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2104 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2105
2106 /*
2107 * Setup the HW Rx Head and Tail Descriptor Pointers and
2108 * the Base and Length of the Rx Descriptor Ring
2109 */
2110 for (i = 0; i < adapter->num_rx_queues; i++) {
2111 rx_ring = &adapter->rx_ring[i];
2112 rdba = rx_ring->dma;
2113 j = rx_ring->reg_idx;
2114 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2115 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2116 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2117 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2118 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2119 rx_ring->head = IXGBE_RDH(j);
2120 rx_ring->tail = IXGBE_RDT(j);
2121 rx_ring->rx_buf_len = rx_buf_len;
2122
2123 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2124 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2125 else
2126 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2127
2128 #ifdef IXGBE_FCOE
2129 if (netdev->features & NETIF_F_FCOE_MTU) {
2130 struct ixgbe_ring_feature *f;
2131 f = &adapter->ring_feature[RING_F_FCOE];
2132 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2133 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2134 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2135 rx_ring->rx_buf_len =
2136 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2137 }
2138 }
2139
2140 #endif /* IXGBE_FCOE */
2141 ixgbe_configure_srrctl(adapter, rx_ring);
2142 }
2143
2144 if (hw->mac.type == ixgbe_mac_82598EB) {
2145 /*
2146 * For VMDq support of different descriptor types or
2147 * buffer sizes through the use of multiple SRRCTL
2148 * registers, RDRXCTL.MVMEN must be set to 1
2149 *
2150 * also, the manual doesn't mention it clearly but DCA hints
2151 * will only use queue 0's tags unless this bit is set. Side
2152 * effects of setting this bit are only that SRRCTL must be
2153 * fully programmed [0..15]
2154 */
2155 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2156 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2157 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2158 }
2159
2160 /* Program MRQC for the distribution of queues */
2161 mrqc = ixgbe_setup_mrqc(adapter);
2162
2163 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2164 /* Fill out redirection table */
2165 for (i = 0, j = 0; i < 128; i++, j++) {
2166 if (j == adapter->ring_feature[RING_F_RSS].indices)
2167 j = 0;
2168 /* reta = 4-byte sliding window of
2169 * 0x00..(indices-1)(indices-1)00..etc. */
2170 reta = (reta << 8) | (j * 0x11);
2171 if ((i & 3) == 3)
2172 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2173 }
2174
2175 /* Fill out hash function seeds */
2176 for (i = 0; i < 10; i++)
2177 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2178
2179 if (hw->mac.type == ixgbe_mac_82598EB)
2180 mrqc |= IXGBE_MRQC_RSSEN;
2181 /* Perform hash on these packet types */
2182 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2183 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2184 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2185 | IXGBE_MRQC_RSS_FIELD_IPV6
2186 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2187 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2188 }
2189 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2190
2191 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2192
2193 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2194 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2195 /* Disable indicating checksum in descriptor, enables
2196 * RSS hash */
2197 rxcsum |= IXGBE_RXCSUM_PCSD;
2198 }
2199 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2200 /* Enable IPv4 payload checksum for UDP fragments
2201 * if PCSD is not set */
2202 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2203 }
2204
2205 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2206
2207 if (hw->mac.type == ixgbe_mac_82599EB) {
2208 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2209 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2210 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2211 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2212 }
2213
2214 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2215 /* Enable 82599 HW-RSC */
2216 for (i = 0; i < adapter->num_rx_queues; i++)
2217 ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2218
2219 /* Disable RSC for ACK packets */
2220 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2221 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2222 }
2223 }
2224
2225 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2226 {
2227 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2228 struct ixgbe_hw *hw = &adapter->hw;
2229
2230 /* add VID to filter table */
2231 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2232 }
2233
2234 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2235 {
2236 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2237 struct ixgbe_hw *hw = &adapter->hw;
2238
2239 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2240 ixgbe_irq_disable(adapter);
2241
2242 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2243
2244 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2245 ixgbe_irq_enable(adapter);
2246
2247 /* remove VID from filter table */
2248 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2249 }
2250
2251 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2252 struct vlan_group *grp)
2253 {
2254 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2255 u32 ctrl;
2256 int i, j;
2257
2258 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2259 ixgbe_irq_disable(adapter);
2260 adapter->vlgrp = grp;
2261
2262 /*
2263 * For a DCB driver, always enable VLAN tag stripping so we can
2264 * still receive traffic from a DCB-enabled host even if we're
2265 * not in DCB mode.
2266 */
2267 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2268 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2269 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2270 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2271 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2272 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2273 ctrl |= IXGBE_VLNCTRL_VFE;
2274 /* enable VLAN tag insert/strip */
2275 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2276 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2278 for (i = 0; i < adapter->num_rx_queues; i++) {
2279 j = adapter->rx_ring[i].reg_idx;
2280 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2281 ctrl |= IXGBE_RXDCTL_VME;
2282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2283 }
2284 }
2285 ixgbe_vlan_rx_add_vid(netdev, 0);
2286
2287 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2288 ixgbe_irq_enable(adapter);
2289 }
2290
2291 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2292 {
2293 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2294
2295 if (adapter->vlgrp) {
2296 u16 vid;
2297 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2298 if (!vlan_group_get_device(adapter->vlgrp, vid))
2299 continue;
2300 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2301 }
2302 }
2303 }
2304
2305 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2306 {
2307 struct dev_mc_list *mc_ptr;
2308 u8 *addr = *mc_addr_ptr;
2309 *vmdq = 0;
2310
2311 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2312 if (mc_ptr->next)
2313 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2314 else
2315 *mc_addr_ptr = NULL;
2316
2317 return addr;
2318 }
2319
2320 /**
2321 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2322 * @netdev: network interface device structure
2323 *
2324 * The set_rx_method entry point is called whenever the unicast/multicast
2325 * address list or the network interface flags are updated. This routine is
2326 * responsible for configuring the hardware for proper unicast, multicast and
2327 * promiscuous mode.
2328 **/
2329 static void ixgbe_set_rx_mode(struct net_device *netdev)
2330 {
2331 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2332 struct ixgbe_hw *hw = &adapter->hw;
2333 u32 fctrl, vlnctrl;
2334 u8 *addr_list = NULL;
2335 int addr_count = 0;
2336
2337 /* Check for Promiscuous and All Multicast modes */
2338
2339 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2340 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2341
2342 if (netdev->flags & IFF_PROMISC) {
2343 hw->addr_ctrl.user_set_promisc = 1;
2344 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2345 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2346 } else {
2347 if (netdev->flags & IFF_ALLMULTI) {
2348 fctrl |= IXGBE_FCTRL_MPE;
2349 fctrl &= ~IXGBE_FCTRL_UPE;
2350 } else {
2351 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2352 }
2353 vlnctrl |= IXGBE_VLNCTRL_VFE;
2354 hw->addr_ctrl.user_set_promisc = 0;
2355 }
2356
2357 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2358 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2359
2360 /* reprogram secondary unicast list */
2361 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2362
2363 /* reprogram multicast list */
2364 addr_count = netdev->mc_count;
2365 if (addr_count)
2366 addr_list = netdev->mc_list->dmi_addr;
2367 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2368 ixgbe_addr_list_itr);
2369 }
2370
2371 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2372 {
2373 int q_idx;
2374 struct ixgbe_q_vector *q_vector;
2375 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2376
2377 /* legacy and MSI only use one vector */
2378 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2379 q_vectors = 1;
2380
2381 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2382 struct napi_struct *napi;
2383 q_vector = adapter->q_vector[q_idx];
2384 napi = &q_vector->napi;
2385 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2386 if (!q_vector->rxr_count || !q_vector->txr_count) {
2387 if (q_vector->txr_count == 1)
2388 napi->poll = &ixgbe_clean_txonly;
2389 else if (q_vector->rxr_count == 1)
2390 napi->poll = &ixgbe_clean_rxonly;
2391 }
2392 }
2393
2394 napi_enable(napi);
2395 }
2396 }
2397
2398 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2399 {
2400 int q_idx;
2401 struct ixgbe_q_vector *q_vector;
2402 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2403
2404 /* legacy and MSI only use one vector */
2405 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2406 q_vectors = 1;
2407
2408 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2409 q_vector = adapter->q_vector[q_idx];
2410 napi_disable(&q_vector->napi);
2411 }
2412 }
2413
2414 #ifdef CONFIG_IXGBE_DCB
2415 /*
2416 * ixgbe_configure_dcb - Configure DCB hardware
2417 * @adapter: ixgbe adapter struct
2418 *
2419 * This is called by the driver on open to configure the DCB hardware.
2420 * This is also called by the gennetlink interface when reconfiguring
2421 * the DCB state.
2422 */
2423 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2424 {
2425 struct ixgbe_hw *hw = &adapter->hw;
2426 u32 txdctl, vlnctrl;
2427 int i, j;
2428
2429 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2430 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2431 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2432
2433 /* reconfigure the hardware */
2434 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2435
2436 for (i = 0; i < adapter->num_tx_queues; i++) {
2437 j = adapter->tx_ring[i].reg_idx;
2438 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2439 /* PThresh workaround for Tx hang with DFP enabled. */
2440 txdctl |= 32;
2441 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2442 }
2443 /* Enable VLAN tag insert/strip */
2444 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2445 if (hw->mac.type == ixgbe_mac_82598EB) {
2446 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2447 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2448 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2449 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2450 vlnctrl |= IXGBE_VLNCTRL_VFE;
2451 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2452 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2453 for (i = 0; i < adapter->num_rx_queues; i++) {
2454 j = adapter->rx_ring[i].reg_idx;
2455 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2456 vlnctrl |= IXGBE_RXDCTL_VME;
2457 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2458 }
2459 }
2460 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2461 }
2462
2463 #endif
2464 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2465 {
2466 struct net_device *netdev = adapter->netdev;
2467 struct ixgbe_hw *hw = &adapter->hw;
2468 int i;
2469
2470 ixgbe_set_rx_mode(netdev);
2471
2472 ixgbe_restore_vlan(adapter);
2473 #ifdef CONFIG_IXGBE_DCB
2474 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2475 netif_set_gso_max_size(netdev, 32768);
2476 ixgbe_configure_dcb(adapter);
2477 } else {
2478 netif_set_gso_max_size(netdev, 65536);
2479 }
2480 #else
2481 netif_set_gso_max_size(netdev, 65536);
2482 #endif
2483
2484 #ifdef IXGBE_FCOE
2485 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2486 ixgbe_configure_fcoe(adapter);
2487
2488 #endif /* IXGBE_FCOE */
2489 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2490 for (i = 0; i < adapter->num_tx_queues; i++)
2491 adapter->tx_ring[i].atr_sample_rate =
2492 adapter->atr_sample_rate;
2493 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2494 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2495 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2496 }
2497
2498 ixgbe_configure_tx(adapter);
2499 ixgbe_configure_rx(adapter);
2500 for (i = 0; i < adapter->num_rx_queues; i++)
2501 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2502 (adapter->rx_ring[i].count - 1));
2503 }
2504
2505 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2506 {
2507 switch (hw->phy.type) {
2508 case ixgbe_phy_sfp_avago:
2509 case ixgbe_phy_sfp_ftl:
2510 case ixgbe_phy_sfp_intel:
2511 case ixgbe_phy_sfp_unknown:
2512 case ixgbe_phy_tw_tyco:
2513 case ixgbe_phy_tw_unknown:
2514 return true;
2515 default:
2516 return false;
2517 }
2518 }
2519
2520 /**
2521 * ixgbe_sfp_link_config - set up SFP+ link
2522 * @adapter: pointer to private adapter struct
2523 **/
2524 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2525 {
2526 struct ixgbe_hw *hw = &adapter->hw;
2527
2528 if (hw->phy.multispeed_fiber) {
2529 /*
2530 * In multispeed fiber setups, the device may not have
2531 * had a physical connection when the driver loaded.
2532 * If that's the case, the initial link configuration
2533 * couldn't get the MAC into 10G or 1G mode, so we'll
2534 * never have a link status change interrupt fire.
2535 * We need to try and force an autonegotiation
2536 * session, then bring up link.
2537 */
2538 hw->mac.ops.setup_sfp(hw);
2539 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2540 schedule_work(&adapter->multispeed_fiber_task);
2541 } else {
2542 /*
2543 * Direct Attach Cu and non-multispeed fiber modules
2544 * still need to be configured properly prior to
2545 * attempting link.
2546 */
2547 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2548 schedule_work(&adapter->sfp_config_module_task);
2549 }
2550 }
2551
2552 /**
2553 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2554 * @hw: pointer to private hardware struct
2555 *
2556 * Returns 0 on success, negative on failure
2557 **/
2558 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2559 {
2560 u32 autoneg;
2561 bool negotiation, link_up = false;
2562 u32 ret = IXGBE_ERR_LINK_SETUP;
2563
2564 if (hw->mac.ops.check_link)
2565 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2566
2567 if (ret)
2568 goto link_cfg_out;
2569
2570 if (hw->mac.ops.get_link_capabilities)
2571 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2572 if (ret)
2573 goto link_cfg_out;
2574
2575 if (hw->mac.ops.setup_link)
2576 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2577 link_cfg_out:
2578 return ret;
2579 }
2580
2581 #define IXGBE_MAX_RX_DESC_POLL 10
2582 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2583 int rxr)
2584 {
2585 int j = adapter->rx_ring[rxr].reg_idx;
2586 int k;
2587
2588 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2589 if (IXGBE_READ_REG(&adapter->hw,
2590 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2591 break;
2592 else
2593 msleep(1);
2594 }
2595 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2596 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2597 "not set within the polling period\n", rxr);
2598 }
2599 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2600 (adapter->rx_ring[rxr].count - 1));
2601 }
2602
2603 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2604 {
2605 struct net_device *netdev = adapter->netdev;
2606 struct ixgbe_hw *hw = &adapter->hw;
2607 int i, j = 0;
2608 int num_rx_rings = adapter->num_rx_queues;
2609 int err;
2610 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2611 u32 txdctl, rxdctl, mhadd;
2612 u32 dmatxctl;
2613 u32 gpie;
2614
2615 ixgbe_get_hw_control(adapter);
2616
2617 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2618 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2619 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2620 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2621 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2622 } else {
2623 /* MSI only */
2624 gpie = 0;
2625 }
2626 /* XXX: to interrupt immediately for EICS writes, enable this */
2627 /* gpie |= IXGBE_GPIE_EIMEN; */
2628 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2629 }
2630
2631 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2632 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2633 * specifically only auto mask tx and rx interrupts */
2634 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2635 }
2636
2637 /* Enable fan failure interrupt if media type is copper */
2638 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2639 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2640 gpie |= IXGBE_SDP1_GPIEN;
2641 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2642 }
2643
2644 if (hw->mac.type == ixgbe_mac_82599EB) {
2645 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2646 gpie |= IXGBE_SDP1_GPIEN;
2647 gpie |= IXGBE_SDP2_GPIEN;
2648 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2649 }
2650
2651 #ifdef IXGBE_FCOE
2652 /* adjust max frame to be able to do baby jumbo for FCoE */
2653 if ((netdev->features & NETIF_F_FCOE_MTU) &&
2654 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2655 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2656
2657 #endif /* IXGBE_FCOE */
2658 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2659 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2660 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2661 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2662
2663 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2664 }
2665
2666 for (i = 0; i < adapter->num_tx_queues; i++) {
2667 j = adapter->tx_ring[i].reg_idx;
2668 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2669 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2670 txdctl |= (8 << 16);
2671 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2672 }
2673
2674 if (hw->mac.type == ixgbe_mac_82599EB) {
2675 /* DMATXCTL.EN must be set after all Tx queue config is done */
2676 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2677 dmatxctl |= IXGBE_DMATXCTL_TE;
2678 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2679 }
2680 for (i = 0; i < adapter->num_tx_queues; i++) {
2681 j = adapter->tx_ring[i].reg_idx;
2682 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2683 txdctl |= IXGBE_TXDCTL_ENABLE;
2684 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2685 }
2686
2687 for (i = 0; i < num_rx_rings; i++) {
2688 j = adapter->rx_ring[i].reg_idx;
2689 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2690 /* enable PTHRESH=32 descriptors (half the internal cache)
2691 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2692 * this also removes a pesky rx_no_buffer_count increment */
2693 rxdctl |= 0x0020;
2694 rxdctl |= IXGBE_RXDCTL_ENABLE;
2695 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2696 if (hw->mac.type == ixgbe_mac_82599EB)
2697 ixgbe_rx_desc_queue_enable(adapter, i);
2698 }
2699 /* enable all receives */
2700 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2701 if (hw->mac.type == ixgbe_mac_82598EB)
2702 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2703 else
2704 rxdctl |= IXGBE_RXCTRL_RXEN;
2705 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2706
2707 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2708 ixgbe_configure_msix(adapter);
2709 else
2710 ixgbe_configure_msi_and_legacy(adapter);
2711
2712 clear_bit(__IXGBE_DOWN, &adapter->state);
2713 ixgbe_napi_enable_all(adapter);
2714
2715 /* clear any pending interrupts, may auto mask */
2716 IXGBE_READ_REG(hw, IXGBE_EICR);
2717
2718 ixgbe_irq_enable(adapter);
2719
2720 /*
2721 * If this adapter has a fan, check to see if we had a failure
2722 * before we enabled the interrupt.
2723 */
2724 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2725 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2726 if (esdp & IXGBE_ESDP_SDP1)
2727 DPRINTK(DRV, CRIT,
2728 "Fan has stopped, replace the adapter\n");
2729 }
2730
2731 /*
2732 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2733 * arrived before interrupts were enabled but after probe. Such
2734 * devices wouldn't have their type identified yet. We need to
2735 * kick off the SFP+ module setup first, then try to bring up link.
2736 * If we're not hot-pluggable SFP+, we just need to configure link
2737 * and bring it up.
2738 */
2739 if (hw->phy.type == ixgbe_phy_unknown) {
2740 err = hw->phy.ops.identify(hw);
2741 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2742 /*
2743 * Take the device down and schedule the sfp tasklet
2744 * which will unregister_netdev and log it.
2745 */
2746 ixgbe_down(adapter);
2747 schedule_work(&adapter->sfp_config_module_task);
2748 return err;
2749 }
2750 }
2751
2752 if (ixgbe_is_sfp(hw)) {
2753 ixgbe_sfp_link_config(adapter);
2754 } else {
2755 err = ixgbe_non_sfp_link_config(hw);
2756 if (err)
2757 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2758 }
2759
2760 for (i = 0; i < adapter->num_tx_queues; i++)
2761 set_bit(__IXGBE_FDIR_INIT_DONE,
2762 &(adapter->tx_ring[i].reinit_state));
2763
2764 /* enable transmits */
2765 netif_tx_start_all_queues(netdev);
2766
2767 /* bring the link up in the watchdog, this could race with our first
2768 * link up interrupt but shouldn't be a problem */
2769 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2770 adapter->link_check_timeout = jiffies;
2771 mod_timer(&adapter->watchdog_timer, jiffies);
2772 return 0;
2773 }
2774
2775 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2776 {
2777 WARN_ON(in_interrupt());
2778 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2779 msleep(1);
2780 ixgbe_down(adapter);
2781 ixgbe_up(adapter);
2782 clear_bit(__IXGBE_RESETTING, &adapter->state);
2783 }
2784
2785 int ixgbe_up(struct ixgbe_adapter *adapter)
2786 {
2787 /* hardware has been reset, we need to reload some things */
2788 ixgbe_configure(adapter);
2789
2790 return ixgbe_up_complete(adapter);
2791 }
2792
2793 void ixgbe_reset(struct ixgbe_adapter *adapter)
2794 {
2795 struct ixgbe_hw *hw = &adapter->hw;
2796 int err;
2797
2798 err = hw->mac.ops.init_hw(hw);
2799 switch (err) {
2800 case 0:
2801 case IXGBE_ERR_SFP_NOT_PRESENT:
2802 break;
2803 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2804 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2805 break;
2806 case IXGBE_ERR_EEPROM_VERSION:
2807 /* We are running on a pre-production device, log a warning */
2808 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2809 "adapter/LOM. Please be aware there may be issues "
2810 "associated with your hardware. If you are "
2811 "experiencing problems please contact your Intel or "
2812 "hardware representative who provided you with this "
2813 "hardware.\n");
2814 break;
2815 default:
2816 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2817 }
2818
2819 /* reprogram the RAR[0] in case user changed it. */
2820 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2821 }
2822
2823 /**
2824 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2825 * @adapter: board private structure
2826 * @rx_ring: ring to free buffers from
2827 **/
2828 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2829 struct ixgbe_ring *rx_ring)
2830 {
2831 struct pci_dev *pdev = adapter->pdev;
2832 unsigned long size;
2833 unsigned int i;
2834
2835 /* Free all the Rx ring sk_buffs */
2836
2837 for (i = 0; i < rx_ring->count; i++) {
2838 struct ixgbe_rx_buffer *rx_buffer_info;
2839
2840 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2841 if (rx_buffer_info->dma) {
2842 pci_unmap_single(pdev, rx_buffer_info->dma,
2843 rx_ring->rx_buf_len,
2844 PCI_DMA_FROMDEVICE);
2845 rx_buffer_info->dma = 0;
2846 }
2847 if (rx_buffer_info->skb) {
2848 struct sk_buff *skb = rx_buffer_info->skb;
2849 rx_buffer_info->skb = NULL;
2850 do {
2851 struct sk_buff *this = skb;
2852 skb = skb->prev;
2853 dev_kfree_skb(this);
2854 } while (skb);
2855 }
2856 if (!rx_buffer_info->page)
2857 continue;
2858 if (rx_buffer_info->page_dma) {
2859 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2860 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2861 rx_buffer_info->page_dma = 0;
2862 }
2863 put_page(rx_buffer_info->page);
2864 rx_buffer_info->page = NULL;
2865 rx_buffer_info->page_offset = 0;
2866 }
2867
2868 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2869 memset(rx_ring->rx_buffer_info, 0, size);
2870
2871 /* Zero out the descriptor ring */
2872 memset(rx_ring->desc, 0, rx_ring->size);
2873
2874 rx_ring->next_to_clean = 0;
2875 rx_ring->next_to_use = 0;
2876
2877 if (rx_ring->head)
2878 writel(0, adapter->hw.hw_addr + rx_ring->head);
2879 if (rx_ring->tail)
2880 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2881 }
2882
2883 /**
2884 * ixgbe_clean_tx_ring - Free Tx Buffers
2885 * @adapter: board private structure
2886 * @tx_ring: ring to be cleaned
2887 **/
2888 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2889 struct ixgbe_ring *tx_ring)
2890 {
2891 struct ixgbe_tx_buffer *tx_buffer_info;
2892 unsigned long size;
2893 unsigned int i;
2894
2895 /* Free all the Tx ring sk_buffs */
2896
2897 for (i = 0; i < tx_ring->count; i++) {
2898 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2899 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2900 }
2901
2902 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2903 memset(tx_ring->tx_buffer_info, 0, size);
2904
2905 /* Zero out the descriptor ring */
2906 memset(tx_ring->desc, 0, tx_ring->size);
2907
2908 tx_ring->next_to_use = 0;
2909 tx_ring->next_to_clean = 0;
2910
2911 if (tx_ring->head)
2912 writel(0, adapter->hw.hw_addr + tx_ring->head);
2913 if (tx_ring->tail)
2914 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2915 }
2916
2917 /**
2918 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2919 * @adapter: board private structure
2920 **/
2921 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2922 {
2923 int i;
2924
2925 for (i = 0; i < adapter->num_rx_queues; i++)
2926 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2927 }
2928
2929 /**
2930 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2931 * @adapter: board private structure
2932 **/
2933 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2934 {
2935 int i;
2936
2937 for (i = 0; i < adapter->num_tx_queues; i++)
2938 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2939 }
2940
2941 void ixgbe_down(struct ixgbe_adapter *adapter)
2942 {
2943 struct net_device *netdev = adapter->netdev;
2944 struct ixgbe_hw *hw = &adapter->hw;
2945 u32 rxctrl;
2946 u32 txdctl;
2947 int i, j;
2948
2949 /* signal that we are down to the interrupt handler */
2950 set_bit(__IXGBE_DOWN, &adapter->state);
2951
2952 /* disable receives */
2953 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2954 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2955
2956 netif_tx_disable(netdev);
2957
2958 IXGBE_WRITE_FLUSH(hw);
2959 msleep(10);
2960
2961 netif_tx_stop_all_queues(netdev);
2962
2963 ixgbe_irq_disable(adapter);
2964
2965 ixgbe_napi_disable_all(adapter);
2966
2967 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2968 del_timer_sync(&adapter->sfp_timer);
2969 del_timer_sync(&adapter->watchdog_timer);
2970 cancel_work_sync(&adapter->watchdog_task);
2971
2972 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2973 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2974 cancel_work_sync(&adapter->fdir_reinit_task);
2975
2976 /* disable transmits in the hardware now that interrupts are off */
2977 for (i = 0; i < adapter->num_tx_queues; i++) {
2978 j = adapter->tx_ring[i].reg_idx;
2979 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2980 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2981 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2982 }
2983 /* Disable the Tx DMA engine on 82599 */
2984 if (hw->mac.type == ixgbe_mac_82599EB)
2985 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2986 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2987 ~IXGBE_DMATXCTL_TE));
2988
2989 netif_carrier_off(netdev);
2990
2991 if (!pci_channel_offline(adapter->pdev))
2992 ixgbe_reset(adapter);
2993 ixgbe_clean_all_tx_rings(adapter);
2994 ixgbe_clean_all_rx_rings(adapter);
2995
2996 #ifdef CONFIG_IXGBE_DCA
2997 /* since we reset the hardware DCA settings were cleared */
2998 ixgbe_setup_dca(adapter);
2999 #endif
3000 }
3001
3002 /**
3003 * ixgbe_poll - NAPI Rx polling callback
3004 * @napi: structure for representing this polling device
3005 * @budget: how many packets driver is allowed to clean
3006 *
3007 * This function is used for legacy and MSI, NAPI mode
3008 **/
3009 static int ixgbe_poll(struct napi_struct *napi, int budget)
3010 {
3011 struct ixgbe_q_vector *q_vector =
3012 container_of(napi, struct ixgbe_q_vector, napi);
3013 struct ixgbe_adapter *adapter = q_vector->adapter;
3014 int tx_clean_complete, work_done = 0;
3015
3016 #ifdef CONFIG_IXGBE_DCA
3017 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3018 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3019 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3020 }
3021 #endif
3022
3023 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3024 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3025
3026 if (!tx_clean_complete)
3027 work_done = budget;
3028
3029 /* If budget not fully consumed, exit the polling mode */
3030 if (work_done < budget) {
3031 napi_complete(napi);
3032 if (adapter->rx_itr_setting & 1)
3033 ixgbe_set_itr(adapter);
3034 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3035 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3036 }
3037 return work_done;
3038 }
3039
3040 /**
3041 * ixgbe_tx_timeout - Respond to a Tx Hang
3042 * @netdev: network interface device structure
3043 **/
3044 static void ixgbe_tx_timeout(struct net_device *netdev)
3045 {
3046 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3047
3048 /* Do the reset outside of interrupt context */
3049 schedule_work(&adapter->reset_task);
3050 }
3051
3052 static void ixgbe_reset_task(struct work_struct *work)
3053 {
3054 struct ixgbe_adapter *adapter;
3055 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3056
3057 /* If we're already down or resetting, just bail */
3058 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3059 test_bit(__IXGBE_RESETTING, &adapter->state))
3060 return;
3061
3062 adapter->tx_timeout_count++;
3063
3064 ixgbe_reinit_locked(adapter);
3065 }
3066
3067 #ifdef CONFIG_IXGBE_DCB
3068 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3069 {
3070 bool ret = false;
3071 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3072
3073 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3074 return ret;
3075
3076 f->mask = 0x7 << 3;
3077 adapter->num_rx_queues = f->indices;
3078 adapter->num_tx_queues = f->indices;
3079 ret = true;
3080
3081 return ret;
3082 }
3083 #endif
3084
3085 /**
3086 * ixgbe_set_rss_queues: Allocate queues for RSS
3087 * @adapter: board private structure to initialize
3088 *
3089 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3090 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3091 *
3092 **/
3093 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3094 {
3095 bool ret = false;
3096 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3097
3098 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3099 f->mask = 0xF;
3100 adapter->num_rx_queues = f->indices;
3101 adapter->num_tx_queues = f->indices;
3102 ret = true;
3103 } else {
3104 ret = false;
3105 }
3106
3107 return ret;
3108 }
3109
3110 /**
3111 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3112 * @adapter: board private structure to initialize
3113 *
3114 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3115 * to the original CPU that initiated the Tx session. This runs in addition
3116 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3117 * Rx load across CPUs using RSS.
3118 *
3119 **/
3120 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3121 {
3122 bool ret = false;
3123 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3124
3125 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3126 f_fdir->mask = 0;
3127
3128 /* Flow Director must have RSS enabled */
3129 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3130 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3131 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3132 adapter->num_tx_queues = f_fdir->indices;
3133 adapter->num_rx_queues = f_fdir->indices;
3134 ret = true;
3135 } else {
3136 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3137 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3138 }
3139 return ret;
3140 }
3141
3142 #ifdef IXGBE_FCOE
3143 /**
3144 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3145 * @adapter: board private structure to initialize
3146 *
3147 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3148 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3149 * rx queues out of the max number of rx queues, instead, it is used as the
3150 * index of the first rx queue used by FCoE.
3151 *
3152 **/
3153 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3154 {
3155 bool ret = false;
3156 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3157
3158 f->indices = min((int)num_online_cpus(), f->indices);
3159 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3160 adapter->num_rx_queues = 1;
3161 adapter->num_tx_queues = 1;
3162 #ifdef CONFIG_IXGBE_DCB
3163 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3164 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3165 ixgbe_set_dcb_queues(adapter);
3166 }
3167 #endif
3168 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3169 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3170 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3171 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3172 ixgbe_set_fdir_queues(adapter);
3173 else
3174 ixgbe_set_rss_queues(adapter);
3175 }
3176 /* adding FCoE rx rings to the end */
3177 f->mask = adapter->num_rx_queues;
3178 adapter->num_rx_queues += f->indices;
3179 adapter->num_tx_queues += f->indices;
3180
3181 ret = true;
3182 }
3183
3184 return ret;
3185 }
3186
3187 #endif /* IXGBE_FCOE */
3188 /*
3189 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3190 * @adapter: board private structure to initialize
3191 *
3192 * This is the top level queue allocation routine. The order here is very
3193 * important, starting with the "most" number of features turned on at once,
3194 * and ending with the smallest set of features. This way large combinations
3195 * can be allocated if they're turned on, and smaller combinations are the
3196 * fallthrough conditions.
3197 *
3198 **/
3199 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3200 {
3201 #ifdef IXGBE_FCOE
3202 if (ixgbe_set_fcoe_queues(adapter))
3203 goto done;
3204
3205 #endif /* IXGBE_FCOE */
3206 #ifdef CONFIG_IXGBE_DCB
3207 if (ixgbe_set_dcb_queues(adapter))
3208 goto done;
3209
3210 #endif
3211 if (ixgbe_set_fdir_queues(adapter))
3212 goto done;
3213
3214 if (ixgbe_set_rss_queues(adapter))
3215 goto done;
3216
3217 /* fallback to base case */
3218 adapter->num_rx_queues = 1;
3219 adapter->num_tx_queues = 1;
3220
3221 done:
3222 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3223 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3224 }
3225
3226 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3227 int vectors)
3228 {
3229 int err, vector_threshold;
3230
3231 /* We'll want at least 3 (vector_threshold):
3232 * 1) TxQ[0] Cleanup
3233 * 2) RxQ[0] Cleanup
3234 * 3) Other (Link Status Change, etc.)
3235 * 4) TCP Timer (optional)
3236 */
3237 vector_threshold = MIN_MSIX_COUNT;
3238
3239 /* The more we get, the more we will assign to Tx/Rx Cleanup
3240 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3241 * Right now, we simply care about how many we'll get; we'll
3242 * set them up later while requesting irq's.
3243 */
3244 while (vectors >= vector_threshold) {
3245 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3246 vectors);
3247 if (!err) /* Success in acquiring all requested vectors. */
3248 break;
3249 else if (err < 0)
3250 vectors = 0; /* Nasty failure, quit now */
3251 else /* err == number of vectors we should try again with */
3252 vectors = err;
3253 }
3254
3255 if (vectors < vector_threshold) {
3256 /* Can't allocate enough MSI-X interrupts? Oh well.
3257 * This just means we'll go with either a single MSI
3258 * vector or fall back to legacy interrupts.
3259 */
3260 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3261 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3262 kfree(adapter->msix_entries);
3263 adapter->msix_entries = NULL;
3264 } else {
3265 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3266 /*
3267 * Adjust for only the vectors we'll use, which is minimum
3268 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3269 * vectors we were allocated.
3270 */
3271 adapter->num_msix_vectors = min(vectors,
3272 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3273 }
3274 }
3275
3276 /**
3277 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3278 * @adapter: board private structure to initialize
3279 *
3280 * Cache the descriptor ring offsets for RSS to the assigned rings.
3281 *
3282 **/
3283 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3284 {
3285 int i;
3286 bool ret = false;
3287
3288 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3289 for (i = 0; i < adapter->num_rx_queues; i++)
3290 adapter->rx_ring[i].reg_idx = i;
3291 for (i = 0; i < adapter->num_tx_queues; i++)
3292 adapter->tx_ring[i].reg_idx = i;
3293 ret = true;
3294 } else {
3295 ret = false;
3296 }
3297
3298 return ret;
3299 }
3300
3301 #ifdef CONFIG_IXGBE_DCB
3302 /**
3303 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3304 * @adapter: board private structure to initialize
3305 *
3306 * Cache the descriptor ring offsets for DCB to the assigned rings.
3307 *
3308 **/
3309 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3310 {
3311 int i;
3312 bool ret = false;
3313 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3314
3315 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3316 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3317 /* the number of queues is assumed to be symmetric */
3318 for (i = 0; i < dcb_i; i++) {
3319 adapter->rx_ring[i].reg_idx = i << 3;
3320 adapter->tx_ring[i].reg_idx = i << 2;
3321 }
3322 ret = true;
3323 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3324 if (dcb_i == 8) {
3325 /*
3326 * Tx TC0 starts at: descriptor queue 0
3327 * Tx TC1 starts at: descriptor queue 32
3328 * Tx TC2 starts at: descriptor queue 64
3329 * Tx TC3 starts at: descriptor queue 80
3330 * Tx TC4 starts at: descriptor queue 96
3331 * Tx TC5 starts at: descriptor queue 104
3332 * Tx TC6 starts at: descriptor queue 112
3333 * Tx TC7 starts at: descriptor queue 120
3334 *
3335 * Rx TC0-TC7 are offset by 16 queues each
3336 */
3337 for (i = 0; i < 3; i++) {
3338 adapter->tx_ring[i].reg_idx = i << 5;
3339 adapter->rx_ring[i].reg_idx = i << 4;
3340 }
3341 for ( ; i < 5; i++) {
3342 adapter->tx_ring[i].reg_idx =
3343 ((i + 2) << 4);
3344 adapter->rx_ring[i].reg_idx = i << 4;
3345 }
3346 for ( ; i < dcb_i; i++) {
3347 adapter->tx_ring[i].reg_idx =
3348 ((i + 8) << 3);
3349 adapter->rx_ring[i].reg_idx = i << 4;
3350 }
3351
3352 ret = true;
3353 } else if (dcb_i == 4) {
3354 /*
3355 * Tx TC0 starts at: descriptor queue 0
3356 * Tx TC1 starts at: descriptor queue 64
3357 * Tx TC2 starts at: descriptor queue 96
3358 * Tx TC3 starts at: descriptor queue 112
3359 *
3360 * Rx TC0-TC3 are offset by 32 queues each
3361 */
3362 adapter->tx_ring[0].reg_idx = 0;
3363 adapter->tx_ring[1].reg_idx = 64;
3364 adapter->tx_ring[2].reg_idx = 96;
3365 adapter->tx_ring[3].reg_idx = 112;
3366 for (i = 0 ; i < dcb_i; i++)
3367 adapter->rx_ring[i].reg_idx = i << 5;
3368
3369 ret = true;
3370 } else {
3371 ret = false;
3372 }
3373 } else {
3374 ret = false;
3375 }
3376 } else {
3377 ret = false;
3378 }
3379
3380 return ret;
3381 }
3382 #endif
3383
3384 /**
3385 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3386 * @adapter: board private structure to initialize
3387 *
3388 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3389 *
3390 **/
3391 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3392 {
3393 int i;
3394 bool ret = false;
3395
3396 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3397 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3398 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3399 for (i = 0; i < adapter->num_rx_queues; i++)
3400 adapter->rx_ring[i].reg_idx = i;
3401 for (i = 0; i < adapter->num_tx_queues; i++)
3402 adapter->tx_ring[i].reg_idx = i;
3403 ret = true;
3404 }
3405
3406 return ret;
3407 }
3408
3409 #ifdef IXGBE_FCOE
3410 /**
3411 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3412 * @adapter: board private structure to initialize
3413 *
3414 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3415 *
3416 */
3417 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3418 {
3419 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3420 bool ret = false;
3421 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3422
3423 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3424 #ifdef CONFIG_IXGBE_DCB
3425 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3426 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3427
3428 ixgbe_cache_ring_dcb(adapter);
3429 /* find out queues in TC for FCoE */
3430 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3431 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3432 /*
3433 * In 82599, the number of Tx queues for each traffic
3434 * class for both 8-TC and 4-TC modes are:
3435 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3436 * 8 TCs: 32 32 16 16 8 8 8 8
3437 * 4 TCs: 64 64 32 32
3438 * We have max 8 queues for FCoE, where 8 the is
3439 * FCoE redirection table size. If TC for FCoE is
3440 * less than or equal to TC3, we have enough queues
3441 * to add max of 8 queues for FCoE, so we start FCoE
3442 * tx descriptor from the next one, i.e., reg_idx + 1.
3443 * If TC for FCoE is above TC3, implying 8 TC mode,
3444 * and we need 8 for FCoE, we have to take all queues
3445 * in that traffic class for FCoE.
3446 */
3447 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3448 fcoe_tx_i--;
3449 }
3450 #endif /* CONFIG_IXGBE_DCB */
3451 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3452 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3453 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3454 ixgbe_cache_ring_fdir(adapter);
3455 else
3456 ixgbe_cache_ring_rss(adapter);
3457
3458 fcoe_rx_i = f->mask;
3459 fcoe_tx_i = f->mask;
3460 }
3461 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3462 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3463 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3464 }
3465 ret = true;
3466 }
3467 return ret;
3468 }
3469
3470 #endif /* IXGBE_FCOE */
3471 /**
3472 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3473 * @adapter: board private structure to initialize
3474 *
3475 * Once we know the feature-set enabled for the device, we'll cache
3476 * the register offset the descriptor ring is assigned to.
3477 *
3478 * Note, the order the various feature calls is important. It must start with
3479 * the "most" features enabled at the same time, then trickle down to the
3480 * least amount of features turned on at once.
3481 **/
3482 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3483 {
3484 /* start with default case */
3485 adapter->rx_ring[0].reg_idx = 0;
3486 adapter->tx_ring[0].reg_idx = 0;
3487
3488 #ifdef IXGBE_FCOE
3489 if (ixgbe_cache_ring_fcoe(adapter))
3490 return;
3491
3492 #endif /* IXGBE_FCOE */
3493 #ifdef CONFIG_IXGBE_DCB
3494 if (ixgbe_cache_ring_dcb(adapter))
3495 return;
3496
3497 #endif
3498 if (ixgbe_cache_ring_fdir(adapter))
3499 return;
3500
3501 if (ixgbe_cache_ring_rss(adapter))
3502 return;
3503 }
3504
3505 /**
3506 * ixgbe_alloc_queues - Allocate memory for all rings
3507 * @adapter: board private structure to initialize
3508 *
3509 * We allocate one ring per queue at run-time since we don't know the
3510 * number of queues at compile-time. The polling_netdev array is
3511 * intended for Multiqueue, but should work fine with a single queue.
3512 **/
3513 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3514 {
3515 int i;
3516
3517 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3518 sizeof(struct ixgbe_ring), GFP_KERNEL);
3519 if (!adapter->tx_ring)
3520 goto err_tx_ring_allocation;
3521
3522 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3523 sizeof(struct ixgbe_ring), GFP_KERNEL);
3524 if (!adapter->rx_ring)
3525 goto err_rx_ring_allocation;
3526
3527 for (i = 0; i < adapter->num_tx_queues; i++) {
3528 adapter->tx_ring[i].count = adapter->tx_ring_count;
3529 adapter->tx_ring[i].queue_index = i;
3530 }
3531
3532 for (i = 0; i < adapter->num_rx_queues; i++) {
3533 adapter->rx_ring[i].count = adapter->rx_ring_count;
3534 adapter->rx_ring[i].queue_index = i;
3535 }
3536
3537 ixgbe_cache_ring_register(adapter);
3538
3539 return 0;
3540
3541 err_rx_ring_allocation:
3542 kfree(adapter->tx_ring);
3543 err_tx_ring_allocation:
3544 return -ENOMEM;
3545 }
3546
3547 /**
3548 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3549 * @adapter: board private structure to initialize
3550 *
3551 * Attempt to configure the interrupts using the best available
3552 * capabilities of the hardware and the kernel.
3553 **/
3554 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3555 {
3556 struct ixgbe_hw *hw = &adapter->hw;
3557 int err = 0;
3558 int vector, v_budget;
3559
3560 /*
3561 * It's easy to be greedy for MSI-X vectors, but it really
3562 * doesn't do us much good if we have a lot more vectors
3563 * than CPU's. So let's be conservative and only ask for
3564 * (roughly) twice the number of vectors as there are CPU's.
3565 */
3566 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3567 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3568
3569 /*
3570 * At the same time, hardware can only support a maximum of
3571 * hw.mac->max_msix_vectors vectors. With features
3572 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3573 * descriptor queues supported by our device. Thus, we cap it off in
3574 * those rare cases where the cpu count also exceeds our vector limit.
3575 */
3576 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3577
3578 /* A failure in MSI-X entry allocation isn't fatal, but it does
3579 * mean we disable MSI-X capabilities of the adapter. */
3580 adapter->msix_entries = kcalloc(v_budget,
3581 sizeof(struct msix_entry), GFP_KERNEL);
3582 if (adapter->msix_entries) {
3583 for (vector = 0; vector < v_budget; vector++)
3584 adapter->msix_entries[vector].entry = vector;
3585
3586 ixgbe_acquire_msix_vectors(adapter, v_budget);
3587
3588 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3589 goto out;
3590 }
3591
3592 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3593 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3594 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3595 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3596 adapter->atr_sample_rate = 0;
3597 ixgbe_set_num_queues(adapter);
3598
3599 err = pci_enable_msi(adapter->pdev);
3600 if (!err) {
3601 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3602 } else {
3603 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3604 "falling back to legacy. Error: %d\n", err);
3605 /* reset err */
3606 err = 0;
3607 }
3608
3609 out:
3610 return err;
3611 }
3612
3613 /**
3614 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3615 * @adapter: board private structure to initialize
3616 *
3617 * We allocate one q_vector per queue interrupt. If allocation fails we
3618 * return -ENOMEM.
3619 **/
3620 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3621 {
3622 int q_idx, num_q_vectors;
3623 struct ixgbe_q_vector *q_vector;
3624 int napi_vectors;
3625 int (*poll)(struct napi_struct *, int);
3626
3627 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3628 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3629 napi_vectors = adapter->num_rx_queues;
3630 poll = &ixgbe_clean_rxtx_many;
3631 } else {
3632 num_q_vectors = 1;
3633 napi_vectors = 1;
3634 poll = &ixgbe_poll;
3635 }
3636
3637 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3638 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3639 if (!q_vector)
3640 goto err_out;
3641 q_vector->adapter = adapter;
3642 if (q_vector->txr_count && !q_vector->rxr_count)
3643 q_vector->eitr = adapter->tx_eitr_param;
3644 else
3645 q_vector->eitr = adapter->rx_eitr_param;
3646 q_vector->v_idx = q_idx;
3647 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3648 adapter->q_vector[q_idx] = q_vector;
3649 }
3650
3651 return 0;
3652
3653 err_out:
3654 while (q_idx) {
3655 q_idx--;
3656 q_vector = adapter->q_vector[q_idx];
3657 netif_napi_del(&q_vector->napi);
3658 kfree(q_vector);
3659 adapter->q_vector[q_idx] = NULL;
3660 }
3661 return -ENOMEM;
3662 }
3663
3664 /**
3665 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3666 * @adapter: board private structure to initialize
3667 *
3668 * This function frees the memory allocated to the q_vectors. In addition if
3669 * NAPI is enabled it will delete any references to the NAPI struct prior
3670 * to freeing the q_vector.
3671 **/
3672 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3673 {
3674 int q_idx, num_q_vectors;
3675
3676 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3677 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3678 else
3679 num_q_vectors = 1;
3680
3681 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3682 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3683 adapter->q_vector[q_idx] = NULL;
3684 netif_napi_del(&q_vector->napi);
3685 kfree(q_vector);
3686 }
3687 }
3688
3689 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3690 {
3691 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3692 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3693 pci_disable_msix(adapter->pdev);
3694 kfree(adapter->msix_entries);
3695 adapter->msix_entries = NULL;
3696 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3697 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3698 pci_disable_msi(adapter->pdev);
3699 }
3700 return;
3701 }
3702
3703 /**
3704 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3705 * @adapter: board private structure to initialize
3706 *
3707 * We determine which interrupt scheme to use based on...
3708 * - Kernel support (MSI, MSI-X)
3709 * - which can be user-defined (via MODULE_PARAM)
3710 * - Hardware queue count (num_*_queues)
3711 * - defined by miscellaneous hardware support/features (RSS, etc.)
3712 **/
3713 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3714 {
3715 int err;
3716
3717 /* Number of supported queues */
3718 ixgbe_set_num_queues(adapter);
3719
3720 err = ixgbe_set_interrupt_capability(adapter);
3721 if (err) {
3722 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3723 goto err_set_interrupt;
3724 }
3725
3726 err = ixgbe_alloc_q_vectors(adapter);
3727 if (err) {
3728 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3729 "vectors\n");
3730 goto err_alloc_q_vectors;
3731 }
3732
3733 err = ixgbe_alloc_queues(adapter);
3734 if (err) {
3735 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3736 goto err_alloc_queues;
3737 }
3738
3739 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3740 "Tx Queue count = %u\n",
3741 (adapter->num_rx_queues > 1) ? "Enabled" :
3742 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3743
3744 set_bit(__IXGBE_DOWN, &adapter->state);
3745
3746 return 0;
3747
3748 err_alloc_queues:
3749 ixgbe_free_q_vectors(adapter);
3750 err_alloc_q_vectors:
3751 ixgbe_reset_interrupt_capability(adapter);
3752 err_set_interrupt:
3753 return err;
3754 }
3755
3756 /**
3757 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3758 * @adapter: board private structure to clear interrupt scheme on
3759 *
3760 * We go through and clear interrupt specific resources and reset the structure
3761 * to pre-load conditions
3762 **/
3763 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3764 {
3765 kfree(adapter->tx_ring);
3766 kfree(adapter->rx_ring);
3767 adapter->tx_ring = NULL;
3768 adapter->rx_ring = NULL;
3769
3770 ixgbe_free_q_vectors(adapter);
3771 ixgbe_reset_interrupt_capability(adapter);
3772 }
3773
3774 /**
3775 * ixgbe_sfp_timer - worker thread to find a missing module
3776 * @data: pointer to our adapter struct
3777 **/
3778 static void ixgbe_sfp_timer(unsigned long data)
3779 {
3780 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3781
3782 /*
3783 * Do the sfp_timer outside of interrupt context due to the
3784 * delays that sfp+ detection requires
3785 */
3786 schedule_work(&adapter->sfp_task);
3787 }
3788
3789 /**
3790 * ixgbe_sfp_task - worker thread to find a missing module
3791 * @work: pointer to work_struct containing our data
3792 **/
3793 static void ixgbe_sfp_task(struct work_struct *work)
3794 {
3795 struct ixgbe_adapter *adapter = container_of(work,
3796 struct ixgbe_adapter,
3797 sfp_task);
3798 struct ixgbe_hw *hw = &adapter->hw;
3799
3800 if ((hw->phy.type == ixgbe_phy_nl) &&
3801 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3802 s32 ret = hw->phy.ops.identify_sfp(hw);
3803 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3804 goto reschedule;
3805 ret = hw->phy.ops.reset(hw);
3806 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3807 dev_err(&adapter->pdev->dev, "failed to initialize "
3808 "because an unsupported SFP+ module type "
3809 "was detected.\n"
3810 "Reload the driver after installing a "
3811 "supported module.\n");
3812 unregister_netdev(adapter->netdev);
3813 } else {
3814 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3815 hw->phy.sfp_type);
3816 }
3817 /* don't need this routine any more */
3818 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3819 }
3820 return;
3821 reschedule:
3822 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3823 mod_timer(&adapter->sfp_timer,
3824 round_jiffies(jiffies + (2 * HZ)));
3825 }
3826
3827 /**
3828 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3829 * @adapter: board private structure to initialize
3830 *
3831 * ixgbe_sw_init initializes the Adapter private data structure.
3832 * Fields are initialized based on PCI device information and
3833 * OS network device settings (MTU size).
3834 **/
3835 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3836 {
3837 struct ixgbe_hw *hw = &adapter->hw;
3838 struct pci_dev *pdev = adapter->pdev;
3839 unsigned int rss;
3840 #ifdef CONFIG_IXGBE_DCB
3841 int j;
3842 struct tc_configuration *tc;
3843 #endif
3844
3845 /* PCI config space info */
3846
3847 hw->vendor_id = pdev->vendor;
3848 hw->device_id = pdev->device;
3849 hw->revision_id = pdev->revision;
3850 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3851 hw->subsystem_device_id = pdev->subsystem_device;
3852
3853 /* Set capability flags */
3854 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3855 adapter->ring_feature[RING_F_RSS].indices = rss;
3856 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3857 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3858 if (hw->mac.type == ixgbe_mac_82598EB) {
3859 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3860 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3861 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3862 } else if (hw->mac.type == ixgbe_mac_82599EB) {
3863 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3864 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3865 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3866 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3867 adapter->ring_feature[RING_F_FDIR].indices =
3868 IXGBE_MAX_FDIR_INDICES;
3869 adapter->atr_sample_rate = 20;
3870 adapter->fdir_pballoc = 0;
3871 #ifdef IXGBE_FCOE
3872 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3873 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3874 adapter->ring_feature[RING_F_FCOE].indices = 0;
3875 /* Default traffic class to use for FCoE */
3876 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3877 #endif /* IXGBE_FCOE */
3878 }
3879
3880 #ifdef CONFIG_IXGBE_DCB
3881 /* Configure DCB traffic classes */
3882 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3883 tc = &adapter->dcb_cfg.tc_config[j];
3884 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3885 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3886 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3887 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3888 tc->dcb_pfc = pfc_disabled;
3889 }
3890 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3891 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3892 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3893 adapter->dcb_cfg.pfc_mode_enable = false;
3894 adapter->dcb_cfg.round_robin_enable = false;
3895 adapter->dcb_set_bitmap = 0x00;
3896 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3897 adapter->ring_feature[RING_F_DCB].indices);
3898
3899 #endif
3900
3901 /* default flow control settings */
3902 hw->fc.requested_mode = ixgbe_fc_full;
3903 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
3904 #ifdef CONFIG_DCB
3905 adapter->last_lfc_mode = hw->fc.current_mode;
3906 #endif
3907 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3908 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3909 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3910 hw->fc.send_xon = true;
3911 hw->fc.disable_fc_autoneg = false;
3912
3913 /* enable itr by default in dynamic mode */
3914 adapter->rx_itr_setting = 1;
3915 adapter->rx_eitr_param = 20000;
3916 adapter->tx_itr_setting = 1;
3917 adapter->tx_eitr_param = 10000;
3918
3919 /* set defaults for eitr in MegaBytes */
3920 adapter->eitr_low = 10;
3921 adapter->eitr_high = 20;
3922
3923 /* set default ring sizes */
3924 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3925 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3926
3927 /* initialize eeprom parameters */
3928 if (ixgbe_init_eeprom_params_generic(hw)) {
3929 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3930 return -EIO;
3931 }
3932
3933 /* enable rx csum by default */
3934 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3935
3936 set_bit(__IXGBE_DOWN, &adapter->state);
3937
3938 return 0;
3939 }
3940
3941 /**
3942 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3943 * @adapter: board private structure
3944 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3945 *
3946 * Return 0 on success, negative on failure
3947 **/
3948 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3949 struct ixgbe_ring *tx_ring)
3950 {
3951 struct pci_dev *pdev = adapter->pdev;
3952 int size;
3953
3954 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3955 tx_ring->tx_buffer_info = vmalloc(size);
3956 if (!tx_ring->tx_buffer_info)
3957 goto err;
3958 memset(tx_ring->tx_buffer_info, 0, size);
3959
3960 /* round up to nearest 4K */
3961 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3962 tx_ring->size = ALIGN(tx_ring->size, 4096);
3963
3964 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3965 &tx_ring->dma);
3966 if (!tx_ring->desc)
3967 goto err;
3968
3969 tx_ring->next_to_use = 0;
3970 tx_ring->next_to_clean = 0;
3971 tx_ring->work_limit = tx_ring->count;
3972 return 0;
3973
3974 err:
3975 vfree(tx_ring->tx_buffer_info);
3976 tx_ring->tx_buffer_info = NULL;
3977 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3978 "descriptor ring\n");
3979 return -ENOMEM;
3980 }
3981
3982 /**
3983 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3984 * @adapter: board private structure
3985 *
3986 * If this function returns with an error, then it's possible one or
3987 * more of the rings is populated (while the rest are not). It is the
3988 * callers duty to clean those orphaned rings.
3989 *
3990 * Return 0 on success, negative on failure
3991 **/
3992 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3993 {
3994 int i, err = 0;
3995
3996 for (i = 0; i < adapter->num_tx_queues; i++) {
3997 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3998 if (!err)
3999 continue;
4000 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4001 break;
4002 }
4003
4004 return err;
4005 }
4006
4007 /**
4008 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4009 * @adapter: board private structure
4010 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4011 *
4012 * Returns 0 on success, negative on failure
4013 **/
4014 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4015 struct ixgbe_ring *rx_ring)
4016 {
4017 struct pci_dev *pdev = adapter->pdev;
4018 int size;
4019
4020 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4021 rx_ring->rx_buffer_info = vmalloc(size);
4022 if (!rx_ring->rx_buffer_info) {
4023 DPRINTK(PROBE, ERR,
4024 "vmalloc allocation failed for the rx desc ring\n");
4025 goto alloc_failed;
4026 }
4027 memset(rx_ring->rx_buffer_info, 0, size);
4028
4029 /* Round up to nearest 4K */
4030 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4031 rx_ring->size = ALIGN(rx_ring->size, 4096);
4032
4033 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4034
4035 if (!rx_ring->desc) {
4036 DPRINTK(PROBE, ERR,
4037 "Memory allocation failed for the rx desc ring\n");
4038 vfree(rx_ring->rx_buffer_info);
4039 goto alloc_failed;
4040 }
4041
4042 rx_ring->next_to_clean = 0;
4043 rx_ring->next_to_use = 0;
4044
4045 return 0;
4046
4047 alloc_failed:
4048 return -ENOMEM;
4049 }
4050
4051 /**
4052 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4053 * @adapter: board private structure
4054 *
4055 * If this function returns with an error, then it's possible one or
4056 * more of the rings is populated (while the rest are not). It is the
4057 * callers duty to clean those orphaned rings.
4058 *
4059 * Return 0 on success, negative on failure
4060 **/
4061
4062 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4063 {
4064 int i, err = 0;
4065
4066 for (i = 0; i < adapter->num_rx_queues; i++) {
4067 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4068 if (!err)
4069 continue;
4070 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4071 break;
4072 }
4073
4074 return err;
4075 }
4076
4077 /**
4078 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4079 * @adapter: board private structure
4080 * @tx_ring: Tx descriptor ring for a specific queue
4081 *
4082 * Free all transmit software resources
4083 **/
4084 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4085 struct ixgbe_ring *tx_ring)
4086 {
4087 struct pci_dev *pdev = adapter->pdev;
4088
4089 ixgbe_clean_tx_ring(adapter, tx_ring);
4090
4091 vfree(tx_ring->tx_buffer_info);
4092 tx_ring->tx_buffer_info = NULL;
4093
4094 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4095
4096 tx_ring->desc = NULL;
4097 }
4098
4099 /**
4100 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4101 * @adapter: board private structure
4102 *
4103 * Free all transmit software resources
4104 **/
4105 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4106 {
4107 int i;
4108
4109 for (i = 0; i < adapter->num_tx_queues; i++)
4110 if (adapter->tx_ring[i].desc)
4111 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4112 }
4113
4114 /**
4115 * ixgbe_free_rx_resources - Free Rx Resources
4116 * @adapter: board private structure
4117 * @rx_ring: ring to clean the resources from
4118 *
4119 * Free all receive software resources
4120 **/
4121 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4122 struct ixgbe_ring *rx_ring)
4123 {
4124 struct pci_dev *pdev = adapter->pdev;
4125
4126 ixgbe_clean_rx_ring(adapter, rx_ring);
4127
4128 vfree(rx_ring->rx_buffer_info);
4129 rx_ring->rx_buffer_info = NULL;
4130
4131 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4132
4133 rx_ring->desc = NULL;
4134 }
4135
4136 /**
4137 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4138 * @adapter: board private structure
4139 *
4140 * Free all receive software resources
4141 **/
4142 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4143 {
4144 int i;
4145
4146 for (i = 0; i < adapter->num_rx_queues; i++)
4147 if (adapter->rx_ring[i].desc)
4148 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4149 }
4150
4151 /**
4152 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4153 * @netdev: network interface device structure
4154 * @new_mtu: new value for maximum frame size
4155 *
4156 * Returns 0 on success, negative on failure
4157 **/
4158 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4159 {
4160 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4161 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4162
4163 /* MTU < 68 is an error and causes problems on some kernels */
4164 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4165 return -EINVAL;
4166
4167 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4168 netdev->mtu, new_mtu);
4169 /* must set new MTU before calling down or up */
4170 netdev->mtu = new_mtu;
4171
4172 if (netif_running(netdev))
4173 ixgbe_reinit_locked(adapter);
4174
4175 return 0;
4176 }
4177
4178 /**
4179 * ixgbe_open - Called when a network interface is made active
4180 * @netdev: network interface device structure
4181 *
4182 * Returns 0 on success, negative value on failure
4183 *
4184 * The open entry point is called when a network interface is made
4185 * active by the system (IFF_UP). At this point all resources needed
4186 * for transmit and receive operations are allocated, the interrupt
4187 * handler is registered with the OS, the watchdog timer is started,
4188 * and the stack is notified that the interface is ready.
4189 **/
4190 static int ixgbe_open(struct net_device *netdev)
4191 {
4192 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4193 int err;
4194
4195 /* disallow open during test */
4196 if (test_bit(__IXGBE_TESTING, &adapter->state))
4197 return -EBUSY;
4198
4199 netif_carrier_off(netdev);
4200
4201 /* allocate transmit descriptors */
4202 err = ixgbe_setup_all_tx_resources(adapter);
4203 if (err)
4204 goto err_setup_tx;
4205
4206 /* allocate receive descriptors */
4207 err = ixgbe_setup_all_rx_resources(adapter);
4208 if (err)
4209 goto err_setup_rx;
4210
4211 ixgbe_configure(adapter);
4212
4213 err = ixgbe_request_irq(adapter);
4214 if (err)
4215 goto err_req_irq;
4216
4217 err = ixgbe_up_complete(adapter);
4218 if (err)
4219 goto err_up;
4220
4221 netif_tx_start_all_queues(netdev);
4222
4223 return 0;
4224
4225 err_up:
4226 ixgbe_release_hw_control(adapter);
4227 ixgbe_free_irq(adapter);
4228 err_req_irq:
4229 err_setup_rx:
4230 ixgbe_free_all_rx_resources(adapter);
4231 err_setup_tx:
4232 ixgbe_free_all_tx_resources(adapter);
4233 ixgbe_reset(adapter);
4234
4235 return err;
4236 }
4237
4238 /**
4239 * ixgbe_close - Disables a network interface
4240 * @netdev: network interface device structure
4241 *
4242 * Returns 0, this is not allowed to fail
4243 *
4244 * The close entry point is called when an interface is de-activated
4245 * by the OS. The hardware is still under the drivers control, but
4246 * needs to be disabled. A global MAC reset is issued to stop the
4247 * hardware, and all transmit and receive resources are freed.
4248 **/
4249 static int ixgbe_close(struct net_device *netdev)
4250 {
4251 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4252
4253 ixgbe_down(adapter);
4254 ixgbe_free_irq(adapter);
4255
4256 ixgbe_free_all_tx_resources(adapter);
4257 ixgbe_free_all_rx_resources(adapter);
4258
4259 ixgbe_release_hw_control(adapter);
4260
4261 return 0;
4262 }
4263
4264 #ifdef CONFIG_PM
4265 static int ixgbe_resume(struct pci_dev *pdev)
4266 {
4267 struct net_device *netdev = pci_get_drvdata(pdev);
4268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4269 u32 err;
4270
4271 pci_set_power_state(pdev, PCI_D0);
4272 pci_restore_state(pdev);
4273
4274 err = pci_enable_device_mem(pdev);
4275 if (err) {
4276 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4277 "suspend\n");
4278 return err;
4279 }
4280 pci_set_master(pdev);
4281
4282 pci_wake_from_d3(pdev, false);
4283
4284 err = ixgbe_init_interrupt_scheme(adapter);
4285 if (err) {
4286 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4287 "device\n");
4288 return err;
4289 }
4290
4291 ixgbe_reset(adapter);
4292
4293 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4294
4295 if (netif_running(netdev)) {
4296 err = ixgbe_open(adapter->netdev);
4297 if (err)
4298 return err;
4299 }
4300
4301 netif_device_attach(netdev);
4302
4303 return 0;
4304 }
4305 #endif /* CONFIG_PM */
4306
4307 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4308 {
4309 struct net_device *netdev = pci_get_drvdata(pdev);
4310 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4311 struct ixgbe_hw *hw = &adapter->hw;
4312 u32 ctrl, fctrl;
4313 u32 wufc = adapter->wol;
4314 #ifdef CONFIG_PM
4315 int retval = 0;
4316 #endif
4317
4318 netif_device_detach(netdev);
4319
4320 if (netif_running(netdev)) {
4321 ixgbe_down(adapter);
4322 ixgbe_free_irq(adapter);
4323 ixgbe_free_all_tx_resources(adapter);
4324 ixgbe_free_all_rx_resources(adapter);
4325 }
4326 ixgbe_clear_interrupt_scheme(adapter);
4327
4328 #ifdef CONFIG_PM
4329 retval = pci_save_state(pdev);
4330 if (retval)
4331 return retval;
4332
4333 #endif
4334 if (wufc) {
4335 ixgbe_set_rx_mode(netdev);
4336
4337 /* turn on all-multi mode if wake on multicast is enabled */
4338 if (wufc & IXGBE_WUFC_MC) {
4339 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4340 fctrl |= IXGBE_FCTRL_MPE;
4341 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4342 }
4343
4344 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4345 ctrl |= IXGBE_CTRL_GIO_DIS;
4346 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4347
4348 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4349 } else {
4350 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4351 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4352 }
4353
4354 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4355 pci_wake_from_d3(pdev, true);
4356 else
4357 pci_wake_from_d3(pdev, false);
4358
4359 *enable_wake = !!wufc;
4360
4361 ixgbe_release_hw_control(adapter);
4362
4363 pci_disable_device(pdev);
4364
4365 return 0;
4366 }
4367
4368 #ifdef CONFIG_PM
4369 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4370 {
4371 int retval;
4372 bool wake;
4373
4374 retval = __ixgbe_shutdown(pdev, &wake);
4375 if (retval)
4376 return retval;
4377
4378 if (wake) {
4379 pci_prepare_to_sleep(pdev);
4380 } else {
4381 pci_wake_from_d3(pdev, false);
4382 pci_set_power_state(pdev, PCI_D3hot);
4383 }
4384
4385 return 0;
4386 }
4387 #endif /* CONFIG_PM */
4388
4389 static void ixgbe_shutdown(struct pci_dev *pdev)
4390 {
4391 bool wake;
4392
4393 __ixgbe_shutdown(pdev, &wake);
4394
4395 if (system_state == SYSTEM_POWER_OFF) {
4396 pci_wake_from_d3(pdev, wake);
4397 pci_set_power_state(pdev, PCI_D3hot);
4398 }
4399 }
4400
4401 /**
4402 * ixgbe_update_stats - Update the board statistics counters.
4403 * @adapter: board private structure
4404 **/
4405 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4406 {
4407 struct net_device *netdev = adapter->netdev;
4408 struct ixgbe_hw *hw = &adapter->hw;
4409 u64 total_mpc = 0;
4410 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4411
4412 if (hw->mac.type == ixgbe_mac_82599EB) {
4413 u64 rsc_count = 0;
4414 for (i = 0; i < 16; i++)
4415 adapter->hw_rx_no_dma_resources +=
4416 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4417 for (i = 0; i < adapter->num_rx_queues; i++)
4418 rsc_count += adapter->rx_ring[i].rsc_count;
4419 adapter->rsc_count = rsc_count;
4420 }
4421
4422 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4423 for (i = 0; i < 8; i++) {
4424 /* for packet buffers not used, the register should read 0 */
4425 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4426 missed_rx += mpc;
4427 adapter->stats.mpc[i] += mpc;
4428 total_mpc += adapter->stats.mpc[i];
4429 if (hw->mac.type == ixgbe_mac_82598EB)
4430 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4431 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4432 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4433 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4434 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4435 if (hw->mac.type == ixgbe_mac_82599EB) {
4436 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4437 IXGBE_PXONRXCNT(i));
4438 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4439 IXGBE_PXOFFRXCNT(i));
4440 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4441 } else {
4442 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4443 IXGBE_PXONRXC(i));
4444 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4445 IXGBE_PXOFFRXC(i));
4446 }
4447 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4448 IXGBE_PXONTXC(i));
4449 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4450 IXGBE_PXOFFTXC(i));
4451 }
4452 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4453 /* work around hardware counting issue */
4454 adapter->stats.gprc -= missed_rx;
4455
4456 /* 82598 hardware only has a 32 bit counter in the high register */
4457 if (hw->mac.type == ixgbe_mac_82599EB) {
4458 u64 tmp;
4459 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4460 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4461 adapter->stats.gorc += (tmp << 32);
4462 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4463 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4464 adapter->stats.gotc += (tmp << 32);
4465 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4466 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4467 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4468 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4469 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4470 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4471 #ifdef IXGBE_FCOE
4472 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4473 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4474 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4475 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4476 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4477 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4478 #endif /* IXGBE_FCOE */
4479 } else {
4480 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4481 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4482 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4483 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4484 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4485 }
4486 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4487 adapter->stats.bprc += bprc;
4488 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4489 if (hw->mac.type == ixgbe_mac_82598EB)
4490 adapter->stats.mprc -= bprc;
4491 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4492 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4493 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4494 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4495 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4496 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4497 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4498 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4499 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4500 adapter->stats.lxontxc += lxon;
4501 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4502 adapter->stats.lxofftxc += lxoff;
4503 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4504 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4505 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4506 /*
4507 * 82598 errata - tx of flow control packets is included in tx counters
4508 */
4509 xon_off_tot = lxon + lxoff;
4510 adapter->stats.gptc -= xon_off_tot;
4511 adapter->stats.mptc -= xon_off_tot;
4512 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4513 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4514 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4515 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4516 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4517 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4518 adapter->stats.ptc64 -= xon_off_tot;
4519 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4520 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4521 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4522 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4523 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4524 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4525
4526 /* Fill out the OS statistics structure */
4527 netdev->stats.multicast = adapter->stats.mprc;
4528
4529 /* Rx Errors */
4530 netdev->stats.rx_errors = adapter->stats.crcerrs +
4531 adapter->stats.rlec;
4532 netdev->stats.rx_dropped = 0;
4533 netdev->stats.rx_length_errors = adapter->stats.rlec;
4534 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4535 netdev->stats.rx_missed_errors = total_mpc;
4536 }
4537
4538 /**
4539 * ixgbe_watchdog - Timer Call-back
4540 * @data: pointer to adapter cast into an unsigned long
4541 **/
4542 static void ixgbe_watchdog(unsigned long data)
4543 {
4544 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4545 struct ixgbe_hw *hw = &adapter->hw;
4546 u64 eics = 0;
4547 int i;
4548
4549 /*
4550 * Do the watchdog outside of interrupt context due to the lovely
4551 * delays that some of the newer hardware requires
4552 */
4553
4554 if (test_bit(__IXGBE_DOWN, &adapter->state))
4555 goto watchdog_short_circuit;
4556
4557 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4558 /*
4559 * for legacy and MSI interrupts don't set any bits
4560 * that are enabled for EIAM, because this operation
4561 * would set *both* EIMS and EICS for any bit in EIAM
4562 */
4563 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4564 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4565 goto watchdog_reschedule;
4566 }
4567
4568 /* get one bit for every active tx/rx interrupt vector */
4569 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4570 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4571 if (qv->rxr_count || qv->txr_count)
4572 eics |= ((u64)1 << i);
4573 }
4574
4575 /* Cause software interrupt to ensure rx rings are cleaned */
4576 ixgbe_irq_rearm_queues(adapter, eics);
4577
4578 watchdog_reschedule:
4579 /* Reset the timer */
4580 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4581
4582 watchdog_short_circuit:
4583 schedule_work(&adapter->watchdog_task);
4584 }
4585
4586 /**
4587 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4588 * @work: pointer to work_struct containing our data
4589 **/
4590 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4591 {
4592 struct ixgbe_adapter *adapter = container_of(work,
4593 struct ixgbe_adapter,
4594 multispeed_fiber_task);
4595 struct ixgbe_hw *hw = &adapter->hw;
4596 u32 autoneg;
4597 bool negotiation;
4598
4599 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4600 autoneg = hw->phy.autoneg_advertised;
4601 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4602 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4603 if (hw->mac.ops.setup_link)
4604 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4605 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4606 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4607 }
4608
4609 /**
4610 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4611 * @work: pointer to work_struct containing our data
4612 **/
4613 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4614 {
4615 struct ixgbe_adapter *adapter = container_of(work,
4616 struct ixgbe_adapter,
4617 sfp_config_module_task);
4618 struct ixgbe_hw *hw = &adapter->hw;
4619 u32 err;
4620
4621 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4622
4623 /* Time for electrical oscillations to settle down */
4624 msleep(100);
4625 err = hw->phy.ops.identify_sfp(hw);
4626
4627 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4628 dev_err(&adapter->pdev->dev, "failed to initialize because "
4629 "an unsupported SFP+ module type was detected.\n"
4630 "Reload the driver after installing a supported "
4631 "module.\n");
4632 unregister_netdev(adapter->netdev);
4633 return;
4634 }
4635 hw->mac.ops.setup_sfp(hw);
4636
4637 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4638 /* This will also work for DA Twinax connections */
4639 schedule_work(&adapter->multispeed_fiber_task);
4640 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4641 }
4642
4643 /**
4644 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4645 * @work: pointer to work_struct containing our data
4646 **/
4647 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4648 {
4649 struct ixgbe_adapter *adapter = container_of(work,
4650 struct ixgbe_adapter,
4651 fdir_reinit_task);
4652 struct ixgbe_hw *hw = &adapter->hw;
4653 int i;
4654
4655 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4656 for (i = 0; i < adapter->num_tx_queues; i++)
4657 set_bit(__IXGBE_FDIR_INIT_DONE,
4658 &(adapter->tx_ring[i].reinit_state));
4659 } else {
4660 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4661 "ignored adding FDIR ATR filters \n");
4662 }
4663 /* Done FDIR Re-initialization, enable transmits */
4664 netif_tx_start_all_queues(adapter->netdev);
4665 }
4666
4667 /**
4668 * ixgbe_watchdog_task - worker thread to bring link up
4669 * @work: pointer to work_struct containing our data
4670 **/
4671 static void ixgbe_watchdog_task(struct work_struct *work)
4672 {
4673 struct ixgbe_adapter *adapter = container_of(work,
4674 struct ixgbe_adapter,
4675 watchdog_task);
4676 struct net_device *netdev = adapter->netdev;
4677 struct ixgbe_hw *hw = &adapter->hw;
4678 u32 link_speed = adapter->link_speed;
4679 bool link_up = adapter->link_up;
4680 int i;
4681 struct ixgbe_ring *tx_ring;
4682 int some_tx_pending = 0;
4683
4684 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4685
4686 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4687 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4688 if (link_up) {
4689 #ifdef CONFIG_DCB
4690 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4691 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4692 hw->mac.ops.fc_enable(hw, i);
4693 } else {
4694 hw->mac.ops.fc_enable(hw, 0);
4695 }
4696 #else
4697 hw->mac.ops.fc_enable(hw, 0);
4698 #endif
4699 }
4700
4701 if (link_up ||
4702 time_after(jiffies, (adapter->link_check_timeout +
4703 IXGBE_TRY_LINK_TIMEOUT))) {
4704 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4705 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4706 }
4707 adapter->link_up = link_up;
4708 adapter->link_speed = link_speed;
4709 }
4710
4711 if (link_up) {
4712 if (!netif_carrier_ok(netdev)) {
4713 bool flow_rx, flow_tx;
4714
4715 if (hw->mac.type == ixgbe_mac_82599EB) {
4716 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4717 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4718 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4719 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4720 } else {
4721 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4722 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4723 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4724 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4725 }
4726
4727 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4728 "Flow Control: %s\n",
4729 netdev->name,
4730 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4731 "10 Gbps" :
4732 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4733 "1 Gbps" : "unknown speed")),
4734 ((flow_rx && flow_tx) ? "RX/TX" :
4735 (flow_rx ? "RX" :
4736 (flow_tx ? "TX" : "None"))));
4737
4738 netif_carrier_on(netdev);
4739 } else {
4740 /* Force detection of hung controller */
4741 adapter->detect_tx_hung = true;
4742 }
4743 } else {
4744 adapter->link_up = false;
4745 adapter->link_speed = 0;
4746 if (netif_carrier_ok(netdev)) {
4747 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4748 netdev->name);
4749 netif_carrier_off(netdev);
4750 }
4751 }
4752
4753 if (!netif_carrier_ok(netdev)) {
4754 for (i = 0; i < adapter->num_tx_queues; i++) {
4755 tx_ring = &adapter->tx_ring[i];
4756 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4757 some_tx_pending = 1;
4758 break;
4759 }
4760 }
4761
4762 if (some_tx_pending) {
4763 /* We've lost link, so the controller stops DMA,
4764 * but we've got queued Tx work that's never going
4765 * to get done, so reset controller to flush Tx.
4766 * (Do the reset outside of interrupt context).
4767 */
4768 schedule_work(&adapter->reset_task);
4769 }
4770 }
4771
4772 ixgbe_update_stats(adapter);
4773 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4774 }
4775
4776 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4777 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4778 u32 tx_flags, u8 *hdr_len)
4779 {
4780 struct ixgbe_adv_tx_context_desc *context_desc;
4781 unsigned int i;
4782 int err;
4783 struct ixgbe_tx_buffer *tx_buffer_info;
4784 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4785 u32 mss_l4len_idx, l4len;
4786
4787 if (skb_is_gso(skb)) {
4788 if (skb_header_cloned(skb)) {
4789 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4790 if (err)
4791 return err;
4792 }
4793 l4len = tcp_hdrlen(skb);
4794 *hdr_len += l4len;
4795
4796 if (skb->protocol == htons(ETH_P_IP)) {
4797 struct iphdr *iph = ip_hdr(skb);
4798 iph->tot_len = 0;
4799 iph->check = 0;
4800 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4801 iph->daddr, 0,
4802 IPPROTO_TCP,
4803 0);
4804 adapter->hw_tso_ctxt++;
4805 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4806 ipv6_hdr(skb)->payload_len = 0;
4807 tcp_hdr(skb)->check =
4808 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4809 &ipv6_hdr(skb)->daddr,
4810 0, IPPROTO_TCP, 0);
4811 adapter->hw_tso6_ctxt++;
4812 }
4813
4814 i = tx_ring->next_to_use;
4815
4816 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4817 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4818
4819 /* VLAN MACLEN IPLEN */
4820 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4821 vlan_macip_lens |=
4822 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4823 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4824 IXGBE_ADVTXD_MACLEN_SHIFT);
4825 *hdr_len += skb_network_offset(skb);
4826 vlan_macip_lens |=
4827 (skb_transport_header(skb) - skb_network_header(skb));
4828 *hdr_len +=
4829 (skb_transport_header(skb) - skb_network_header(skb));
4830 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4831 context_desc->seqnum_seed = 0;
4832
4833 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4834 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4835 IXGBE_ADVTXD_DTYP_CTXT);
4836
4837 if (skb->protocol == htons(ETH_P_IP))
4838 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4839 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4840 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4841
4842 /* MSS L4LEN IDX */
4843 mss_l4len_idx =
4844 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4845 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4846 /* use index 1 for TSO */
4847 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4848 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4849
4850 tx_buffer_info->time_stamp = jiffies;
4851 tx_buffer_info->next_to_watch = i;
4852
4853 i++;
4854 if (i == tx_ring->count)
4855 i = 0;
4856 tx_ring->next_to_use = i;
4857
4858 return true;
4859 }
4860 return false;
4861 }
4862
4863 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4864 struct ixgbe_ring *tx_ring,
4865 struct sk_buff *skb, u32 tx_flags)
4866 {
4867 struct ixgbe_adv_tx_context_desc *context_desc;
4868 unsigned int i;
4869 struct ixgbe_tx_buffer *tx_buffer_info;
4870 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4871
4872 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4873 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4874 i = tx_ring->next_to_use;
4875 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4876 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4877
4878 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4879 vlan_macip_lens |=
4880 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4881 vlan_macip_lens |= (skb_network_offset(skb) <<
4882 IXGBE_ADVTXD_MACLEN_SHIFT);
4883 if (skb->ip_summed == CHECKSUM_PARTIAL)
4884 vlan_macip_lens |= (skb_transport_header(skb) -
4885 skb_network_header(skb));
4886
4887 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4888 context_desc->seqnum_seed = 0;
4889
4890 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4891 IXGBE_ADVTXD_DTYP_CTXT);
4892
4893 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4894 switch (skb->protocol) {
4895 case cpu_to_be16(ETH_P_IP):
4896 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4897 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4898 type_tucmd_mlhl |=
4899 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4900 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4901 type_tucmd_mlhl |=
4902 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4903 break;
4904 case cpu_to_be16(ETH_P_IPV6):
4905 /* XXX what about other V6 headers?? */
4906 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4907 type_tucmd_mlhl |=
4908 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4909 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4910 type_tucmd_mlhl |=
4911 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4912 break;
4913 default:
4914 if (unlikely(net_ratelimit())) {
4915 DPRINTK(PROBE, WARNING,
4916 "partial checksum but proto=%x!\n",
4917 skb->protocol);
4918 }
4919 break;
4920 }
4921 }
4922
4923 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4924 /* use index zero for tx checksum offload */
4925 context_desc->mss_l4len_idx = 0;
4926
4927 tx_buffer_info->time_stamp = jiffies;
4928 tx_buffer_info->next_to_watch = i;
4929
4930 adapter->hw_csum_tx_good++;
4931 i++;
4932 if (i == tx_ring->count)
4933 i = 0;
4934 tx_ring->next_to_use = i;
4935
4936 return true;
4937 }
4938
4939 return false;
4940 }
4941
4942 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4943 struct ixgbe_ring *tx_ring,
4944 struct sk_buff *skb, u32 tx_flags,
4945 unsigned int first)
4946 {
4947 struct ixgbe_tx_buffer *tx_buffer_info;
4948 unsigned int len;
4949 unsigned int total = skb->len;
4950 unsigned int offset = 0, size, count = 0, i;
4951 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4952 unsigned int f;
4953 dma_addr_t *map;
4954
4955 i = tx_ring->next_to_use;
4956
4957 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4958 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4959 return 0;
4960 }
4961
4962 map = skb_shinfo(skb)->dma_maps;
4963
4964 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4965 /* excluding fcoe_crc_eof for FCoE */
4966 total -= sizeof(struct fcoe_crc_eof);
4967
4968 len = min(skb_headlen(skb), total);
4969 while (len) {
4970 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4971 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4972
4973 tx_buffer_info->length = size;
4974 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4975 tx_buffer_info->time_stamp = jiffies;
4976 tx_buffer_info->next_to_watch = i;
4977
4978 len -= size;
4979 total -= size;
4980 offset += size;
4981 count++;
4982
4983 if (len) {
4984 i++;
4985 if (i == tx_ring->count)
4986 i = 0;
4987 }
4988 }
4989
4990 for (f = 0; f < nr_frags; f++) {
4991 struct skb_frag_struct *frag;
4992
4993 frag = &skb_shinfo(skb)->frags[f];
4994 len = min((unsigned int)frag->size, total);
4995 offset = 0;
4996
4997 while (len) {
4998 i++;
4999 if (i == tx_ring->count)
5000 i = 0;
5001
5002 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5003 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5004
5005 tx_buffer_info->length = size;
5006 tx_buffer_info->dma = map[f] + offset;
5007 tx_buffer_info->time_stamp = jiffies;
5008 tx_buffer_info->next_to_watch = i;
5009
5010 len -= size;
5011 total -= size;
5012 offset += size;
5013 count++;
5014 }
5015 if (total == 0)
5016 break;
5017 }
5018
5019 tx_ring->tx_buffer_info[i].skb = skb;
5020 tx_ring->tx_buffer_info[first].next_to_watch = i;
5021
5022 return count;
5023 }
5024
5025 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5026 struct ixgbe_ring *tx_ring,
5027 int tx_flags, int count, u32 paylen, u8 hdr_len)
5028 {
5029 union ixgbe_adv_tx_desc *tx_desc = NULL;
5030 struct ixgbe_tx_buffer *tx_buffer_info;
5031 u32 olinfo_status = 0, cmd_type_len = 0;
5032 unsigned int i;
5033 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5034
5035 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5036
5037 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5038
5039 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5040 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5041
5042 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5043 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5044
5045 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5046 IXGBE_ADVTXD_POPTS_SHIFT;
5047
5048 /* use index 1 context for tso */
5049 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5050 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5051 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5052 IXGBE_ADVTXD_POPTS_SHIFT;
5053
5054 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5055 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5056 IXGBE_ADVTXD_POPTS_SHIFT;
5057
5058 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5059 olinfo_status |= IXGBE_ADVTXD_CC;
5060 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5061 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5062 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5063 }
5064
5065 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5066
5067 i = tx_ring->next_to_use;
5068 while (count--) {
5069 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5070 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5071 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5072 tx_desc->read.cmd_type_len =
5073 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5074 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5075 i++;
5076 if (i == tx_ring->count)
5077 i = 0;
5078 }
5079
5080 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5081
5082 /*
5083 * Force memory writes to complete before letting h/w
5084 * know there are new descriptors to fetch. (Only
5085 * applicable for weak-ordered memory model archs,
5086 * such as IA-64).
5087 */
5088 wmb();
5089
5090 tx_ring->next_to_use = i;
5091 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5092 }
5093
5094 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5095 int queue, u32 tx_flags)
5096 {
5097 /* Right now, we support IPv4 only */
5098 struct ixgbe_atr_input atr_input;
5099 struct tcphdr *th;
5100 struct iphdr *iph = ip_hdr(skb);
5101 struct ethhdr *eth = (struct ethhdr *)skb->data;
5102 u16 vlan_id, src_port, dst_port, flex_bytes;
5103 u32 src_ipv4_addr, dst_ipv4_addr;
5104 u8 l4type = 0;
5105
5106 /* check if we're UDP or TCP */
5107 if (iph->protocol == IPPROTO_TCP) {
5108 th = tcp_hdr(skb);
5109 src_port = th->source;
5110 dst_port = th->dest;
5111 l4type |= IXGBE_ATR_L4TYPE_TCP;
5112 /* l4type IPv4 type is 0, no need to assign */
5113 } else {
5114 /* Unsupported L4 header, just bail here */
5115 return;
5116 }
5117
5118 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5119
5120 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5121 IXGBE_TX_FLAGS_VLAN_SHIFT;
5122 src_ipv4_addr = iph->saddr;
5123 dst_ipv4_addr = iph->daddr;
5124 flex_bytes = eth->h_proto;
5125
5126 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5127 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5128 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5129 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5130 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5131 /* src and dst are inverted, think how the receiver sees them */
5132 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5133 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5134
5135 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5136 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5137 }
5138
5139 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5140 struct ixgbe_ring *tx_ring, int size)
5141 {
5142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5143
5144 netif_stop_subqueue(netdev, tx_ring->queue_index);
5145 /* Herbert's original patch had:
5146 * smp_mb__after_netif_stop_queue();
5147 * but since that doesn't exist yet, just open code it. */
5148 smp_mb();
5149
5150 /* We need to check again in a case another CPU has just
5151 * made room available. */
5152 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5153 return -EBUSY;
5154
5155 /* A reprieve! - use start_queue because it doesn't call schedule */
5156 netif_start_subqueue(netdev, tx_ring->queue_index);
5157 ++adapter->restart_queue;
5158 return 0;
5159 }
5160
5161 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5162 struct ixgbe_ring *tx_ring, int size)
5163 {
5164 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5165 return 0;
5166 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5167 }
5168
5169 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5170 {
5171 struct ixgbe_adapter *adapter = netdev_priv(dev);
5172
5173 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5174 return smp_processor_id();
5175
5176 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5177 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5178
5179 return skb_tx_hash(dev, skb);
5180 }
5181
5182 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5183 struct net_device *netdev)
5184 {
5185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5186 struct ixgbe_ring *tx_ring;
5187 unsigned int first;
5188 unsigned int tx_flags = 0;
5189 u8 hdr_len = 0;
5190 int r_idx = 0, tso;
5191 int count = 0;
5192 unsigned int f;
5193
5194 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5195 tx_flags |= vlan_tx_tag_get(skb);
5196 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5197 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5198 tx_flags |= (skb->queue_mapping << 13);
5199 }
5200 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5201 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5202 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5203 if (skb->priority != TC_PRIO_CONTROL) {
5204 tx_flags |= (skb->queue_mapping << 13);
5205 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5206 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5207 } else {
5208 skb->queue_mapping =
5209 adapter->ring_feature[RING_F_DCB].indices-1;
5210 }
5211 }
5212
5213 r_idx = skb->queue_mapping;
5214 tx_ring = &adapter->tx_ring[r_idx];
5215
5216 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5217 (skb->protocol == htons(ETH_P_FCOE))) {
5218 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5219 #ifdef IXGBE_FCOE
5220 r_idx = smp_processor_id();
5221 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5222 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5223 tx_ring = &adapter->tx_ring[r_idx];
5224 #endif
5225 }
5226 /* four things can cause us to need a context descriptor */
5227 if (skb_is_gso(skb) ||
5228 (skb->ip_summed == CHECKSUM_PARTIAL) ||
5229 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5230 (tx_flags & IXGBE_TX_FLAGS_FCOE))
5231 count++;
5232
5233 count += TXD_USE_COUNT(skb_headlen(skb));
5234 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5235 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5236
5237 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5238 adapter->tx_busy++;
5239 return NETDEV_TX_BUSY;
5240 }
5241
5242 first = tx_ring->next_to_use;
5243 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5244 #ifdef IXGBE_FCOE
5245 /* setup tx offload for FCoE */
5246 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5247 if (tso < 0) {
5248 dev_kfree_skb_any(skb);
5249 return NETDEV_TX_OK;
5250 }
5251 if (tso)
5252 tx_flags |= IXGBE_TX_FLAGS_FSO;
5253 #endif /* IXGBE_FCOE */
5254 } else {
5255 if (skb->protocol == htons(ETH_P_IP))
5256 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5257 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5258 if (tso < 0) {
5259 dev_kfree_skb_any(skb);
5260 return NETDEV_TX_OK;
5261 }
5262
5263 if (tso)
5264 tx_flags |= IXGBE_TX_FLAGS_TSO;
5265 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5266 (skb->ip_summed == CHECKSUM_PARTIAL))
5267 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5268 }
5269
5270 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5271 if (count) {
5272 /* add the ATR filter if ATR is on */
5273 if (tx_ring->atr_sample_rate) {
5274 ++tx_ring->atr_count;
5275 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5276 test_bit(__IXGBE_FDIR_INIT_DONE,
5277 &tx_ring->reinit_state)) {
5278 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5279 tx_flags);
5280 tx_ring->atr_count = 0;
5281 }
5282 }
5283 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5284 hdr_len);
5285 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5286
5287 } else {
5288 dev_kfree_skb_any(skb);
5289 tx_ring->tx_buffer_info[first].time_stamp = 0;
5290 tx_ring->next_to_use = first;
5291 }
5292
5293 return NETDEV_TX_OK;
5294 }
5295
5296 /**
5297 * ixgbe_get_stats - Get System Network Statistics
5298 * @netdev: network interface device structure
5299 *
5300 * Returns the address of the device statistics structure.
5301 * The statistics are actually updated from the timer callback.
5302 **/
5303 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5304 {
5305 /* only return the current stats */
5306 return &netdev->stats;
5307 }
5308
5309 /**
5310 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5311 * @netdev: network interface device structure
5312 * @p: pointer to an address structure
5313 *
5314 * Returns 0 on success, negative on failure
5315 **/
5316 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5317 {
5318 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5319 struct ixgbe_hw *hw = &adapter->hw;
5320 struct sockaddr *addr = p;
5321
5322 if (!is_valid_ether_addr(addr->sa_data))
5323 return -EADDRNOTAVAIL;
5324
5325 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5326 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5327
5328 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5329
5330 return 0;
5331 }
5332
5333 static int
5334 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5335 {
5336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5337 struct ixgbe_hw *hw = &adapter->hw;
5338 u16 value;
5339 int rc;
5340
5341 if (prtad != hw->phy.mdio.prtad)
5342 return -EINVAL;
5343 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5344 if (!rc)
5345 rc = value;
5346 return rc;
5347 }
5348
5349 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5350 u16 addr, u16 value)
5351 {
5352 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5353 struct ixgbe_hw *hw = &adapter->hw;
5354
5355 if (prtad != hw->phy.mdio.prtad)
5356 return -EINVAL;
5357 return hw->phy.ops.write_reg(hw, addr, devad, value);
5358 }
5359
5360 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5361 {
5362 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5363
5364 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5365 }
5366
5367 /**
5368 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5369 * netdev->dev_addrs
5370 * @netdev: network interface device structure
5371 *
5372 * Returns non-zero on failure
5373 **/
5374 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5375 {
5376 int err = 0;
5377 struct ixgbe_adapter *adapter = netdev_priv(dev);
5378 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5379
5380 if (is_valid_ether_addr(mac->san_addr)) {
5381 rtnl_lock();
5382 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5383 rtnl_unlock();
5384 }
5385 return err;
5386 }
5387
5388 /**
5389 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5390 * netdev->dev_addrs
5391 * @netdev: network interface device structure
5392 *
5393 * Returns non-zero on failure
5394 **/
5395 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5396 {
5397 int err = 0;
5398 struct ixgbe_adapter *adapter = netdev_priv(dev);
5399 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5400
5401 if (is_valid_ether_addr(mac->san_addr)) {
5402 rtnl_lock();
5403 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5404 rtnl_unlock();
5405 }
5406 return err;
5407 }
5408
5409 #ifdef CONFIG_NET_POLL_CONTROLLER
5410 /*
5411 * Polling 'interrupt' - used by things like netconsole to send skbs
5412 * without having to re-enable interrupts. It's not called while
5413 * the interrupt routine is executing.
5414 */
5415 static void ixgbe_netpoll(struct net_device *netdev)
5416 {
5417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5418 int i;
5419
5420 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5421 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5422 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5423 for (i = 0; i < num_q_vectors; i++) {
5424 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5425 ixgbe_msix_clean_many(0, q_vector);
5426 }
5427 } else {
5428 ixgbe_intr(adapter->pdev->irq, netdev);
5429 }
5430 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5431 }
5432 #endif
5433
5434 static const struct net_device_ops ixgbe_netdev_ops = {
5435 .ndo_open = ixgbe_open,
5436 .ndo_stop = ixgbe_close,
5437 .ndo_start_xmit = ixgbe_xmit_frame,
5438 .ndo_select_queue = ixgbe_select_queue,
5439 .ndo_get_stats = ixgbe_get_stats,
5440 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5441 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5442 .ndo_validate_addr = eth_validate_addr,
5443 .ndo_set_mac_address = ixgbe_set_mac,
5444 .ndo_change_mtu = ixgbe_change_mtu,
5445 .ndo_tx_timeout = ixgbe_tx_timeout,
5446 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5447 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5448 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5449 .ndo_do_ioctl = ixgbe_ioctl,
5450 #ifdef CONFIG_NET_POLL_CONTROLLER
5451 .ndo_poll_controller = ixgbe_netpoll,
5452 #endif
5453 #ifdef IXGBE_FCOE
5454 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5455 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5456 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5457 .ndo_fcoe_disable = ixgbe_fcoe_disable,
5458 #endif /* IXGBE_FCOE */
5459 };
5460
5461 /**
5462 * ixgbe_probe - Device Initialization Routine
5463 * @pdev: PCI device information struct
5464 * @ent: entry in ixgbe_pci_tbl
5465 *
5466 * Returns 0 on success, negative on failure
5467 *
5468 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5469 * The OS initialization, configuring of the adapter private structure,
5470 * and a hardware reset occur.
5471 **/
5472 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5473 const struct pci_device_id *ent)
5474 {
5475 struct net_device *netdev;
5476 struct ixgbe_adapter *adapter = NULL;
5477 struct ixgbe_hw *hw;
5478 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5479 static int cards_found;
5480 int i, err, pci_using_dac;
5481 #ifdef IXGBE_FCOE
5482 u16 device_caps;
5483 #endif
5484 u32 part_num, eec;
5485
5486 err = pci_enable_device_mem(pdev);
5487 if (err)
5488 return err;
5489
5490 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5491 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5492 pci_using_dac = 1;
5493 } else {
5494 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5495 if (err) {
5496 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5497 if (err) {
5498 dev_err(&pdev->dev, "No usable DMA "
5499 "configuration, aborting\n");
5500 goto err_dma;
5501 }
5502 }
5503 pci_using_dac = 0;
5504 }
5505
5506 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5507 IORESOURCE_MEM), ixgbe_driver_name);
5508 if (err) {
5509 dev_err(&pdev->dev,
5510 "pci_request_selected_regions failed 0x%x\n", err);
5511 goto err_pci_reg;
5512 }
5513
5514 pci_enable_pcie_error_reporting(pdev);
5515
5516 pci_set_master(pdev);
5517 pci_save_state(pdev);
5518
5519 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5520 if (!netdev) {
5521 err = -ENOMEM;
5522 goto err_alloc_etherdev;
5523 }
5524
5525 SET_NETDEV_DEV(netdev, &pdev->dev);
5526
5527 pci_set_drvdata(pdev, netdev);
5528 adapter = netdev_priv(netdev);
5529
5530 adapter->netdev = netdev;
5531 adapter->pdev = pdev;
5532 hw = &adapter->hw;
5533 hw->back = adapter;
5534 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5535
5536 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5537 pci_resource_len(pdev, 0));
5538 if (!hw->hw_addr) {
5539 err = -EIO;
5540 goto err_ioremap;
5541 }
5542
5543 for (i = 1; i <= 5; i++) {
5544 if (pci_resource_len(pdev, i) == 0)
5545 continue;
5546 }
5547
5548 netdev->netdev_ops = &ixgbe_netdev_ops;
5549 ixgbe_set_ethtool_ops(netdev);
5550 netdev->watchdog_timeo = 5 * HZ;
5551 strcpy(netdev->name, pci_name(pdev));
5552
5553 adapter->bd_number = cards_found;
5554
5555 /* Setup hw api */
5556 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5557 hw->mac.type = ii->mac;
5558
5559 /* EEPROM */
5560 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5561 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5562 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5563 if (!(eec & (1 << 8)))
5564 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5565
5566 /* PHY */
5567 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5568 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5569 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5570 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5571 hw->phy.mdio.mmds = 0;
5572 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5573 hw->phy.mdio.dev = netdev;
5574 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5575 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5576
5577 /* set up this timer and work struct before calling get_invariants
5578 * which might start the timer
5579 */
5580 init_timer(&adapter->sfp_timer);
5581 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5582 adapter->sfp_timer.data = (unsigned long) adapter;
5583
5584 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5585
5586 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5587 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5588
5589 /* a new SFP+ module arrival, called from GPI SDP2 context */
5590 INIT_WORK(&adapter->sfp_config_module_task,
5591 ixgbe_sfp_config_module_task);
5592
5593 ii->get_invariants(hw);
5594
5595 /* setup the private structure */
5596 err = ixgbe_sw_init(adapter);
5597 if (err)
5598 goto err_sw_init;
5599
5600 /*
5601 * If there is a fan on this device and it has failed log the
5602 * failure.
5603 */
5604 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5605 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5606 if (esdp & IXGBE_ESDP_SDP1)
5607 DPRINTK(PROBE, CRIT,
5608 "Fan has stopped, replace the adapter\n");
5609 }
5610
5611 /* reset_hw fills in the perm_addr as well */
5612 err = hw->mac.ops.reset_hw(hw);
5613 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5614 hw->mac.type == ixgbe_mac_82598EB) {
5615 /*
5616 * Start a kernel thread to watch for a module to arrive.
5617 * Only do this for 82598, since 82599 will generate
5618 * interrupts on module arrival.
5619 */
5620 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5621 mod_timer(&adapter->sfp_timer,
5622 round_jiffies(jiffies + (2 * HZ)));
5623 err = 0;
5624 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5625 dev_err(&adapter->pdev->dev, "failed to initialize because "
5626 "an unsupported SFP+ module type was detected.\n"
5627 "Reload the driver after installing a supported "
5628 "module.\n");
5629 goto err_sw_init;
5630 } else if (err) {
5631 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5632 goto err_sw_init;
5633 }
5634
5635 netdev->features = NETIF_F_SG |
5636 NETIF_F_IP_CSUM |
5637 NETIF_F_HW_VLAN_TX |
5638 NETIF_F_HW_VLAN_RX |
5639 NETIF_F_HW_VLAN_FILTER;
5640
5641 netdev->features |= NETIF_F_IPV6_CSUM;
5642 netdev->features |= NETIF_F_TSO;
5643 netdev->features |= NETIF_F_TSO6;
5644 netdev->features |= NETIF_F_GRO;
5645
5646 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5647 netdev->features |= NETIF_F_SCTP_CSUM;
5648
5649 netdev->vlan_features |= NETIF_F_TSO;
5650 netdev->vlan_features |= NETIF_F_TSO6;
5651 netdev->vlan_features |= NETIF_F_IP_CSUM;
5652 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5653 netdev->vlan_features |= NETIF_F_SG;
5654
5655 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5656 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5657
5658 #ifdef CONFIG_IXGBE_DCB
5659 netdev->dcbnl_ops = &dcbnl_ops;
5660 #endif
5661
5662 #ifdef IXGBE_FCOE
5663 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5664 if (hw->mac.ops.get_device_caps) {
5665 hw->mac.ops.get_device_caps(hw, &device_caps);
5666 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5667 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5668 }
5669 }
5670 #endif /* IXGBE_FCOE */
5671 if (pci_using_dac)
5672 netdev->features |= NETIF_F_HIGHDMA;
5673
5674 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5675 netdev->features |= NETIF_F_LRO;
5676
5677 /* make sure the EEPROM is good */
5678 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5679 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5680 err = -EIO;
5681 goto err_eeprom;
5682 }
5683
5684 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5685 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5686
5687 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5688 dev_err(&pdev->dev, "invalid MAC address\n");
5689 err = -EIO;
5690 goto err_eeprom;
5691 }
5692
5693 init_timer(&adapter->watchdog_timer);
5694 adapter->watchdog_timer.function = &ixgbe_watchdog;
5695 adapter->watchdog_timer.data = (unsigned long)adapter;
5696
5697 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5698 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5699
5700 err = ixgbe_init_interrupt_scheme(adapter);
5701 if (err)
5702 goto err_sw_init;
5703
5704 switch (pdev->device) {
5705 case IXGBE_DEV_ID_82599_KX4:
5706 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5707 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5708 /* Enable ACPI wakeup in GRC */
5709 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5710 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5711 break;
5712 default:
5713 adapter->wol = 0;
5714 break;
5715 }
5716 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5717
5718 /* pick up the PCI bus settings for reporting later */
5719 hw->mac.ops.get_bus_info(hw);
5720
5721 /* print bus type/speed/width info */
5722 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5723 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5724 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5725 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5726 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5727 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5728 "Unknown"),
5729 netdev->dev_addr);
5730 ixgbe_read_pba_num_generic(hw, &part_num);
5731 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5732 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5733 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5734 (part_num >> 8), (part_num & 0xff));
5735 else
5736 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5737 hw->mac.type, hw->phy.type,
5738 (part_num >> 8), (part_num & 0xff));
5739
5740 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5741 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5742 "this card is not sufficient for optimal "
5743 "performance.\n");
5744 dev_warn(&pdev->dev, "For optimal performance a x8 "
5745 "PCI-Express slot is required.\n");
5746 }
5747
5748 /* save off EEPROM version number */
5749 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5750
5751 /* reset the hardware with the new settings */
5752 err = hw->mac.ops.start_hw(hw);
5753
5754 if (err == IXGBE_ERR_EEPROM_VERSION) {
5755 /* We are running on a pre-production device, log a warning */
5756 dev_warn(&pdev->dev, "This device is a pre-production "
5757 "adapter/LOM. Please be aware there may be issues "
5758 "associated with your hardware. If you are "
5759 "experiencing problems please contact your Intel or "
5760 "hardware representative who provided you with this "
5761 "hardware.\n");
5762 }
5763 strcpy(netdev->name, "eth%d");
5764 err = register_netdev(netdev);
5765 if (err)
5766 goto err_register;
5767
5768 /* carrier off reporting is important to ethtool even BEFORE open */
5769 netif_carrier_off(netdev);
5770
5771 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5772 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5773 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5774
5775 #ifdef CONFIG_IXGBE_DCA
5776 if (dca_add_requester(&pdev->dev) == 0) {
5777 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5778 ixgbe_setup_dca(adapter);
5779 }
5780 #endif
5781 /* add san mac addr to netdev */
5782 ixgbe_add_sanmac_netdev(netdev);
5783
5784 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5785 cards_found++;
5786 return 0;
5787
5788 err_register:
5789 ixgbe_release_hw_control(adapter);
5790 ixgbe_clear_interrupt_scheme(adapter);
5791 err_sw_init:
5792 err_eeprom:
5793 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5794 del_timer_sync(&adapter->sfp_timer);
5795 cancel_work_sync(&adapter->sfp_task);
5796 cancel_work_sync(&adapter->multispeed_fiber_task);
5797 cancel_work_sync(&adapter->sfp_config_module_task);
5798 iounmap(hw->hw_addr);
5799 err_ioremap:
5800 free_netdev(netdev);
5801 err_alloc_etherdev:
5802 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5803 IORESOURCE_MEM));
5804 err_pci_reg:
5805 err_dma:
5806 pci_disable_device(pdev);
5807 return err;
5808 }
5809
5810 /**
5811 * ixgbe_remove - Device Removal Routine
5812 * @pdev: PCI device information struct
5813 *
5814 * ixgbe_remove is called by the PCI subsystem to alert the driver
5815 * that it should release a PCI device. The could be caused by a
5816 * Hot-Plug event, or because the driver is going to be removed from
5817 * memory.
5818 **/
5819 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5820 {
5821 struct net_device *netdev = pci_get_drvdata(pdev);
5822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5823
5824 set_bit(__IXGBE_DOWN, &adapter->state);
5825 /* clear the module not found bit to make sure the worker won't
5826 * reschedule
5827 */
5828 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5829 del_timer_sync(&adapter->watchdog_timer);
5830
5831 del_timer_sync(&adapter->sfp_timer);
5832 cancel_work_sync(&adapter->watchdog_task);
5833 cancel_work_sync(&adapter->sfp_task);
5834 cancel_work_sync(&adapter->multispeed_fiber_task);
5835 cancel_work_sync(&adapter->sfp_config_module_task);
5836 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5837 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5838 cancel_work_sync(&adapter->fdir_reinit_task);
5839 flush_scheduled_work();
5840
5841 #ifdef CONFIG_IXGBE_DCA
5842 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5843 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5844 dca_remove_requester(&pdev->dev);
5845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5846 }
5847
5848 #endif
5849 #ifdef IXGBE_FCOE
5850 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5851 ixgbe_cleanup_fcoe(adapter);
5852
5853 #endif /* IXGBE_FCOE */
5854
5855 /* remove the added san mac */
5856 ixgbe_del_sanmac_netdev(netdev);
5857
5858 if (netdev->reg_state == NETREG_REGISTERED)
5859 unregister_netdev(netdev);
5860
5861 ixgbe_clear_interrupt_scheme(adapter);
5862
5863 ixgbe_release_hw_control(adapter);
5864
5865 iounmap(adapter->hw.hw_addr);
5866 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5867 IORESOURCE_MEM));
5868
5869 DPRINTK(PROBE, INFO, "complete\n");
5870
5871 free_netdev(netdev);
5872
5873 pci_disable_pcie_error_reporting(pdev);
5874
5875 pci_disable_device(pdev);
5876 }
5877
5878 /**
5879 * ixgbe_io_error_detected - called when PCI error is detected
5880 * @pdev: Pointer to PCI device
5881 * @state: The current pci connection state
5882 *
5883 * This function is called after a PCI bus error affecting
5884 * this device has been detected.
5885 */
5886 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5887 pci_channel_state_t state)
5888 {
5889 struct net_device *netdev = pci_get_drvdata(pdev);
5890 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5891
5892 netif_device_detach(netdev);
5893
5894 if (state == pci_channel_io_perm_failure)
5895 return PCI_ERS_RESULT_DISCONNECT;
5896
5897 if (netif_running(netdev))
5898 ixgbe_down(adapter);
5899 pci_disable_device(pdev);
5900
5901 /* Request a slot reset. */
5902 return PCI_ERS_RESULT_NEED_RESET;
5903 }
5904
5905 /**
5906 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5907 * @pdev: Pointer to PCI device
5908 *
5909 * Restart the card from scratch, as if from a cold-boot.
5910 */
5911 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5912 {
5913 struct net_device *netdev = pci_get_drvdata(pdev);
5914 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5915 pci_ers_result_t result;
5916 int err;
5917
5918 if (pci_enable_device_mem(pdev)) {
5919 DPRINTK(PROBE, ERR,
5920 "Cannot re-enable PCI device after reset.\n");
5921 result = PCI_ERS_RESULT_DISCONNECT;
5922 } else {
5923 pci_set_master(pdev);
5924 pci_restore_state(pdev);
5925
5926 pci_wake_from_d3(pdev, false);
5927
5928 ixgbe_reset(adapter);
5929 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5930 result = PCI_ERS_RESULT_RECOVERED;
5931 }
5932
5933 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5934 if (err) {
5935 dev_err(&pdev->dev,
5936 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5937 /* non-fatal, continue */
5938 }
5939
5940 return result;
5941 }
5942
5943 /**
5944 * ixgbe_io_resume - called when traffic can start flowing again.
5945 * @pdev: Pointer to PCI device
5946 *
5947 * This callback is called when the error recovery driver tells us that
5948 * its OK to resume normal operation.
5949 */
5950 static void ixgbe_io_resume(struct pci_dev *pdev)
5951 {
5952 struct net_device *netdev = pci_get_drvdata(pdev);
5953 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5954
5955 if (netif_running(netdev)) {
5956 if (ixgbe_up(adapter)) {
5957 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5958 return;
5959 }
5960 }
5961
5962 netif_device_attach(netdev);
5963 }
5964
5965 static struct pci_error_handlers ixgbe_err_handler = {
5966 .error_detected = ixgbe_io_error_detected,
5967 .slot_reset = ixgbe_io_slot_reset,
5968 .resume = ixgbe_io_resume,
5969 };
5970
5971 static struct pci_driver ixgbe_driver = {
5972 .name = ixgbe_driver_name,
5973 .id_table = ixgbe_pci_tbl,
5974 .probe = ixgbe_probe,
5975 .remove = __devexit_p(ixgbe_remove),
5976 #ifdef CONFIG_PM
5977 .suspend = ixgbe_suspend,
5978 .resume = ixgbe_resume,
5979 #endif
5980 .shutdown = ixgbe_shutdown,
5981 .err_handler = &ixgbe_err_handler
5982 };
5983
5984 /**
5985 * ixgbe_init_module - Driver Registration Routine
5986 *
5987 * ixgbe_init_module is the first routine called when the driver is
5988 * loaded. All it does is register with the PCI subsystem.
5989 **/
5990 static int __init ixgbe_init_module(void)
5991 {
5992 int ret;
5993 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5994 ixgbe_driver_string, ixgbe_driver_version);
5995
5996 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5997
5998 #ifdef CONFIG_IXGBE_DCA
5999 dca_register_notify(&dca_notifier);
6000 #endif
6001
6002 ret = pci_register_driver(&ixgbe_driver);
6003 return ret;
6004 }
6005
6006 module_init(ixgbe_init_module);
6007
6008 /**
6009 * ixgbe_exit_module - Driver Exit Cleanup Routine
6010 *
6011 * ixgbe_exit_module is called just before the driver is removed
6012 * from memory.
6013 **/
6014 static void __exit ixgbe_exit_module(void)
6015 {
6016 #ifdef CONFIG_IXGBE_DCA
6017 dca_unregister_notify(&dca_notifier);
6018 #endif
6019 pci_unregister_driver(&ixgbe_driver);
6020 }
6021
6022 #ifdef CONFIG_IXGBE_DCA
6023 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6024 void *p)
6025 {
6026 int ret_val;
6027
6028 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6029 __ixgbe_notify_dca);
6030
6031 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6032 }
6033
6034 #endif /* CONFIG_IXGBE_DCA */
6035 #ifdef DEBUG
6036 /**
6037 * ixgbe_get_hw_dev_name - return device name string
6038 * used by hardware layer to print debugging information
6039 **/
6040 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6041 {
6042 struct ixgbe_adapter *adapter = hw->back;
6043 return adapter->netdev->name;
6044 }
6045
6046 #endif
6047 module_exit(ixgbe_exit_module);
6048
6049 /* ixgbe_main.c */
kernel-based virtual machine