?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[SKY2]: ethtool register reserved area blackout
[linux-2.6/kvm.git] / drivers / net / sky2.c
blob4832f64037214b2b8f60808839e0d0c71df4bd76
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/aer.h>
35 #include <linux/ip.h>
36 #include <net/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/debugfs.h>
44 #include <linux/mii.h>
45
46 #include <asm/irq.h>
47
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define SKY2_VLAN_TAG_USED 1
50 #endif
51
52 #include "sky2.h"
53
54 #define DRV_NAME "sky2"
55 #define DRV_VERSION "1.18"
56 #define PFX DRV_NAME " "
57
58 /*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
61 * similar to Tigon3.
62 */
63
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
80
81 #define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
84 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95 static int copybreak __read_mostly = 128;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 { 0 }
138 };
139
140 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
145 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
154 "FE+", /* 0xb8 */
155 };
156
157 static void sky2_set_multicast(struct net_device *dev);
158
159 /* Access to external PHY */
160 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 {
162 int i;
163
164 gma_write16(hw, port, GM_SMI_DATA, val);
165 gma_write16(hw, port, GM_SMI_CTRL,
166 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167
168 for (i = 0; i < PHY_RETRIES; i++) {
169 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
170 return 0;
171 udelay(1);
172 }
173
174 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
175 return -ETIMEDOUT;
176 }
177
178 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
179 {
180 int i;
181
182 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
183 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184
185 for (i = 0; i < PHY_RETRIES; i++) {
186 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
187 *val = gma_read16(hw, port, GM_SMI_DATA);
188 return 0;
189 }
190
191 udelay(1);
192 }
193
194 return -ETIMEDOUT;
195 }
196
197 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
198 {
199 u16 v;
200
201 if (__gm_phy_read(hw, port, reg, &v) != 0)
202 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
203 return v;
204 }
205
206
207 static void sky2_power_on(struct sky2_hw *hw)
208 {
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
226 struct pci_dev *pdev = hw->pdev;
227 u32 reg;
228
229 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
230
231 pci_read_config_dword(pdev, PCI_DEV_REG4, &reg);
232 /* set all bits to 0 except bits 15..12 and 8 */
233 reg &= P_ASPM_CONTROL_MSK;
234 pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
235
236 pci_read_config_dword(pdev, PCI_DEV_REG5, &reg);
237 /* set all bits to 0 except bits 28 & 27 */
238 reg &= P_CTL_TIM_VMAIN_AV_MSK;
239 pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
240
241 pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
242
243 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
244 reg = sky2_read32(hw, B2_GP_IO);
245 reg |= GLB_GPIO_STAT_RACE_DIS;
246 sky2_write32(hw, B2_GP_IO, reg);
247
248 sky2_read32(hw, B2_GP_IO);
249 }
250 }
251
252 static void sky2_power_aux(struct sky2_hw *hw)
253 {
254 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
256 else
257 /* enable bits are inverted */
258 sky2_write8(hw, B2_Y2_CLK_GATE,
259 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
260 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
261 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
262
263 /* switch power to VAUX */
264 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
265 sky2_write8(hw, B0_POWER_CTRL,
266 (PC_VAUX_ENA | PC_VCC_ENA |
267 PC_VAUX_ON | PC_VCC_OFF));
268 }
269
270 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
271 {
272 u16 reg;
273
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
278
279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
287 }
288
289 /* flow control to advertise bits */
290 static const u16 copper_fc_adv[] = {
291 [FC_NONE] = 0,
292 [FC_TX] = PHY_M_AN_ASP,
293 [FC_RX] = PHY_M_AN_PC,
294 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
295 };
296
297 /* flow control to advertise bits when using 1000BaseX */
298 static const u16 fiber_fc_adv[] = {
299 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
300 [FC_TX] = PHY_M_P_ASYM_MD_X,
301 [FC_RX] = PHY_M_P_SYM_MD_X,
302 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
303 };
304
305 /* flow control to GMA disable bits */
306 static const u16 gm_fc_disable[] = {
307 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
308 [FC_TX] = GM_GPCR_FC_RX_DIS,
309 [FC_RX] = GM_GPCR_FC_TX_DIS,
310 [FC_BOTH] = 0,
311 };
312
313
314 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
315 {
316 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
317 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
318
319 if (sky2->autoneg == AUTONEG_ENABLE &&
320 !(hw->flags & SKY2_HW_NEWER_PHY)) {
321 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
322
323 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
324 PHY_M_EC_MAC_S_MSK);
325 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
326
327 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
328 if (hw->chip_id == CHIP_ID_YUKON_EC)
329 /* set downshift counter to 3x and enable downshift */
330 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
331 else
332 /* set master & slave downshift counter to 1x */
333 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
334
335 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
336 }
337
338 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
339 if (sky2_is_copper(hw)) {
340 if (!(hw->flags & SKY2_HW_GIGABIT)) {
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
343
344 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
345 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
346 u16 spec;
347
348 /* Enable Class A driver for FE+ A0 */
349 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
350 spec |= PHY_M_FESC_SEL_CL_A;
351 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
352 }
353 } else {
354 /* disable energy detect */
355 ctrl &= ~PHY_M_PC_EN_DET_MSK;
356
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
359
360 /* downshift on PHY 88E1112 and 88E1149 is changed */
361 if (sky2->autoneg == AUTONEG_ENABLE
362 && (hw->flags & SKY2_HW_NEWER_PHY)) {
363 /* set downshift counter to 3x and enable downshift */
364 ctrl &= ~PHY_M_PC_DSC_MSK;
365 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
366 }
367 }
368 } else {
369 /* workaround for deviation #4.88 (CRC errors) */
370 /* disable Automatic Crossover */
371
372 ctrl &= ~PHY_M_PC_MDIX_MSK;
373 }
374
375 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
376
377 /* special setup for PHY 88E1112 Fiber */
378 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
379 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
380
381 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
383 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
384 ctrl &= ~PHY_M_MAC_MD_MSK;
385 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
386 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
387
388 if (hw->pmd_type == 'P') {
389 /* select page 1 to access Fiber registers */
390 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
391
392 /* for SFP-module set SIGDET polarity to low */
393 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
394 ctrl |= PHY_M_FIB_SIGD_POL;
395 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
396 }
397
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
399 }
400
401 ctrl = PHY_CT_RESET;
402 ct1000 = 0;
403 adv = PHY_AN_CSMA;
404 reg = 0;
405
406 if (sky2->autoneg == AUTONEG_ENABLE) {
407 if (sky2_is_copper(hw)) {
408 if (sky2->advertising & ADVERTISED_1000baseT_Full)
409 ct1000 |= PHY_M_1000C_AFD;
410 if (sky2->advertising & ADVERTISED_1000baseT_Half)
411 ct1000 |= PHY_M_1000C_AHD;
412 if (sky2->advertising & ADVERTISED_100baseT_Full)
413 adv |= PHY_M_AN_100_FD;
414 if (sky2->advertising & ADVERTISED_100baseT_Half)
415 adv |= PHY_M_AN_100_HD;
416 if (sky2->advertising & ADVERTISED_10baseT_Full)
417 adv |= PHY_M_AN_10_FD;
418 if (sky2->advertising & ADVERTISED_10baseT_Half)
419 adv |= PHY_M_AN_10_HD;
420
421 adv |= copper_fc_adv[sky2->flow_mode];
422 } else { /* special defines for FIBER (88E1040S only) */
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 adv |= PHY_M_AN_1000X_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 adv |= PHY_M_AN_1000X_AHD;
427
428 adv |= fiber_fc_adv[sky2->flow_mode];
429 }
430
431 /* Restart Auto-negotiation */
432 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
433 } else {
434 /* forced speed/duplex settings */
435 ct1000 = PHY_M_1000C_MSE;
436
437 /* Disable auto update for duplex flow control and speed */
438 reg |= GM_GPCR_AU_ALL_DIS;
439
440 switch (sky2->speed) {
441 case SPEED_1000:
442 ctrl |= PHY_CT_SP1000;
443 reg |= GM_GPCR_SPEED_1000;
444 break;
445 case SPEED_100:
446 ctrl |= PHY_CT_SP100;
447 reg |= GM_GPCR_SPEED_100;
448 break;
449 }
450
451 if (sky2->duplex == DUPLEX_FULL) {
452 reg |= GM_GPCR_DUP_FULL;
453 ctrl |= PHY_CT_DUP_MD;
454 } else if (sky2->speed < SPEED_1000)
455 sky2->flow_mode = FC_NONE;
456
457
458 reg |= gm_fc_disable[sky2->flow_mode];
459
460 /* Forward pause packets to GMAC? */
461 if (sky2->flow_mode & FC_RX)
462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
463 else
464 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
465 }
466
467 gma_write16(hw, port, GM_GP_CTRL, reg);
468
469 if (hw->flags & SKY2_HW_GIGABIT)
470 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
471
472 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
473 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
474
475 /* Setup Phy LED's */
476 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
477 ledover = 0;
478
479 switch (hw->chip_id) {
480 case CHIP_ID_YUKON_FE:
481 /* on 88E3082 these bits are at 11..9 (shifted left) */
482 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
483
484 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
485
486 /* delete ACT LED control bits */
487 ctrl &= ~PHY_M_FELP_LED1_MSK;
488 /* change ACT LED control to blink mode */
489 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
490 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
491 break;
492
493 case CHIP_ID_YUKON_FE_P:
494 /* Enable Link Partner Next Page */
495 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
496 ctrl |= PHY_M_PC_ENA_LIP_NP;
497
498 /* disable Energy Detect and enable scrambler */
499 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
500 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
501
502 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
503 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
504 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
505 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
506
507 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 break;
509
510 case CHIP_ID_YUKON_XL:
511 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
512
513 /* select page 3 to access LED control register */
514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
515
516 /* set LED Function Control register */
517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
518 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
519 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
520 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
521 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
522
523 /* set Polarity Control register */
524 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
525 (PHY_M_POLC_LS1_P_MIX(4) |
526 PHY_M_POLC_IS0_P_MIX(4) |
527 PHY_M_POLC_LOS_CTRL(2) |
528 PHY_M_POLC_INIT_CTRL(2) |
529 PHY_M_POLC_STA1_CTRL(2) |
530 PHY_M_POLC_STA0_CTRL(2)));
531
532 /* restore page register */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
534 break;
535
536 case CHIP_ID_YUKON_EC_U:
537 case CHIP_ID_YUKON_EX:
538 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
539
540 /* select page 3 to access LED control register */
541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
542
543 /* set LED Function Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
545 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
546 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
547 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
548 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
549
550 /* set Blink Rate in LED Timer Control Register */
551 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
552 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
553 /* restore page register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
555 break;
556
557 default:
558 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
559 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
560 /* turn off the Rx LED (LED_RX) */
561 ledover &= ~PHY_M_LED_MO_RX;
562 }
563
564 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
565 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
566 /* apply fixes in PHY AFE */
567 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
568
569 /* increase differential signal amplitude in 10BASE-T */
570 gm_phy_write(hw, port, 0x18, 0xaa99);
571 gm_phy_write(hw, port, 0x17, 0x2011);
572
573 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
574 gm_phy_write(hw, port, 0x18, 0xa204);
575 gm_phy_write(hw, port, 0x17, 0x2002);
576
577 /* set page register to 0 */
578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
579 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
580 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
581 /* apply workaround for integrated resistors calibration */
582 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
583 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
584 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
585 /* no effect on Yukon-XL */
586 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
587
588 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
589 /* turn on 100 Mbps LED (LED_LINK100) */
590 ledover |= PHY_M_LED_MO_100;
591 }
592
593 if (ledover)
594 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
595
596 }
597
598 /* Enable phy interrupt on auto-negotiation complete (or link up) */
599 if (sky2->autoneg == AUTONEG_ENABLE)
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
601 else
602 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
603 }
604
605 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
606 {
607 struct pci_dev *pdev = hw->pdev;
608 u32 reg1;
609 static const u32 phy_power[]
610 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
611
612 /* looks like this XL is back asswards .. */
613 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
614 onoff = !onoff;
615
616 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
617 if (onoff)
618 /* Turn off phy power saving */
619 reg1 &= ~phy_power[port];
620 else
621 reg1 |= phy_power[port];
622
623 pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
624 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
625
626 udelay(100);
627 }
628
629 /* Force a renegotiation */
630 static void sky2_phy_reinit(struct sky2_port *sky2)
631 {
632 spin_lock_bh(&sky2->phy_lock);
633 sky2_phy_init(sky2->hw, sky2->port);
634 spin_unlock_bh(&sky2->phy_lock);
635 }
636
637 /* Put device in state to listen for Wake On Lan */
638 static void sky2_wol_init(struct sky2_port *sky2)
639 {
640 struct sky2_hw *hw = sky2->hw;
641 unsigned port = sky2->port;
642 enum flow_control save_mode;
643 u16 ctrl;
644 u32 reg1;
645
646 /* Bring hardware out of reset */
647 sky2_write16(hw, B0_CTST, CS_RST_CLR);
648 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
649
650 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
651 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
652
653 /* Force to 10/100
654 * sky2_reset will re-enable on resume
655 */
656 save_mode = sky2->flow_mode;
657 ctrl = sky2->advertising;
658
659 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
660 sky2->flow_mode = FC_NONE;
661 sky2_phy_power(hw, port, 1);
662 sky2_phy_reinit(sky2);
663
664 sky2->flow_mode = save_mode;
665 sky2->advertising = ctrl;
666
667 /* Set GMAC to no flow control and auto update for speed/duplex */
668 gma_write16(hw, port, GM_GP_CTRL,
669 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
670 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
671
672 /* Set WOL address */
673 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
674 sky2->netdev->dev_addr, ETH_ALEN);
675
676 /* Turn on appropriate WOL control bits */
677 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
678 ctrl = 0;
679 if (sky2->wol & WAKE_PHY)
680 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
681 else
682 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
683
684 if (sky2->wol & WAKE_MAGIC)
685 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
686 else
687 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
688
689 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
690 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
691
692 /* Turn on legacy PCI-Express PME mode */
693 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
694 reg1 |= PCI_Y2_PME_LEGACY;
695 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
696
697 /* block receiver */
698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
699
700 }
701
702 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
703 {
704 struct net_device *dev = hw->dev[port];
705
706 if (dev->mtu <= ETH_DATA_LEN)
707 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
708 TX_JUMBO_DIS | TX_STFW_ENA);
709
710 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
711 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
712 TX_STFW_ENA | TX_JUMBO_ENA);
713 else {
714 /* set Tx GMAC FIFO Almost Empty Threshold */
715 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
716 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
717
718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
719 TX_JUMBO_ENA | TX_STFW_DIS);
720
721 /* Can't do offload because of lack of store/forward */
722 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
723 }
724 }
725
726 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
727 {
728 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
729 u16 reg;
730 u32 rx_reg;
731 int i;
732 const u8 *addr = hw->dev[port]->dev_addr;
733
734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
735 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
736
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738
739 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
740 /* WA DEV_472 -- looks like crossed wires on port 2 */
741 /* clear GMAC 1 Control reset */
742 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
743 do {
744 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
745 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
746 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
747 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
748 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
749 }
750
751 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
752
753 /* Enable Transmit FIFO Underrun */
754 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
755
756 spin_lock_bh(&sky2->phy_lock);
757 sky2_phy_init(hw, port);
758 spin_unlock_bh(&sky2->phy_lock);
759
760 /* MIB clear */
761 reg = gma_read16(hw, port, GM_PHY_ADDR);
762 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
763
764 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
765 gma_read16(hw, port, i);
766 gma_write16(hw, port, GM_PHY_ADDR, reg);
767
768 /* transmit control */
769 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
770
771 /* receive control reg: unicast + multicast + no FCS */
772 gma_write16(hw, port, GM_RX_CTRL,
773 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
774
775 /* transmit flow control */
776 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
777
778 /* transmit parameter */
779 gma_write16(hw, port, GM_TX_PARAM,
780 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
781 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
782 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
783 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
784
785 /* serial mode register */
786 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
787 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
788
789 if (hw->dev[port]->mtu > ETH_DATA_LEN)
790 reg |= GM_SMOD_JUMBO_ENA;
791
792 gma_write16(hw, port, GM_SERIAL_MODE, reg);
793
794 /* virtual address for data */
795 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
796
797 /* physical address: used for pause frames */
798 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
799
800 /* ignore counter overflows */
801 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
802 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
803 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
804
805 /* Configure Rx MAC FIFO */
806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
807 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
808 if (hw->chip_id == CHIP_ID_YUKON_EX ||
809 hw->chip_id == CHIP_ID_YUKON_FE_P)
810 rx_reg |= GMF_RX_OVER_ON;
811
812 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
813
814 /* Flush Rx MAC FIFO on any flow control or error */
815 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
816
817 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
818 reg = RX_GMF_FL_THR_DEF + 1;
819 /* Another magic mystery workaround from sk98lin */
820 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
821 hw->chip_rev == CHIP_REV_YU_FE2_A0)
822 reg = 0x178;
823 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
824
825 /* Configure Tx MAC FIFO */
826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
827 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
828
829 /* On chips without ram buffer, pause is controled by MAC level */
830 if (sky2_read8(hw, B2_E_0) == 0) {
831 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
832 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
833
834 sky2_set_tx_stfwd(hw, port);
835 }
836
837 }
838
839 /* Assign Ram Buffer allocation to queue */
840 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
841 {
842 u32 end;
843
844 /* convert from K bytes to qwords used for hw register */
845 start *= 1024/8;
846 space *= 1024/8;
847 end = start + space - 1;
848
849 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
850 sky2_write32(hw, RB_ADDR(q, RB_START), start);
851 sky2_write32(hw, RB_ADDR(q, RB_END), end);
852 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
853 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
854
855 if (q == Q_R1 || q == Q_R2) {
856 u32 tp = space - space/4;
857
858 /* On receive queue's set the thresholds
859 * give receiver priority when > 3/4 full
860 * send pause when down to 2K
861 */
862 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
863 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
864
865 tp = space - 2048/8;
866 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
867 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
868 } else {
869 /* Enable store & forward on Tx queue's because
870 * Tx FIFO is only 1K on Yukon
871 */
872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
873 }
874
875 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
876 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
877 }
878
879 /* Setup Bus Memory Interface */
880 static void sky2_qset(struct sky2_hw *hw, u16 q)
881 {
882 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
883 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
885 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
886 }
887
888 /* Setup prefetch unit registers. This is the interface between
889 * hardware and driver list elements
890 */
891 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
892 u64 addr, u32 last)
893 {
894 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
896 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
897 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
898 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
899 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
900
901 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
902 }
903
904 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
905 {
906 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
907
908 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
909 le->ctrl = 0;
910 return le;
911 }
912
913 static void tx_init(struct sky2_port *sky2)
914 {
915 struct sky2_tx_le *le;
916
917 sky2->tx_prod = sky2->tx_cons = 0;
918 sky2->tx_tcpsum = 0;
919 sky2->tx_last_mss = 0;
920
921 le = get_tx_le(sky2);
922 le->addr = 0;
923 le->opcode = OP_ADDR64 | HW_OWNER;
924 sky2->tx_addr64 = 0;
925 }
926
927 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
928 struct sky2_tx_le *le)
929 {
930 return sky2->tx_ring + (le - sky2->tx_le);
931 }
932
933 /* Update chip's next pointer */
934 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
935 {
936 /* Make sure write' to descriptors are complete before we tell hardware */
937 wmb();
938 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
939
940 /* Synchronize I/O on since next processor may write to tail */
941 mmiowb();
942 }
943
944
945 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
946 {
947 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
948 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
949 le->ctrl = 0;
950 return le;
951 }
952
953 /* Build description to hardware for one receive segment */
954 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
955 dma_addr_t map, unsigned len)
956 {
957 struct sky2_rx_le *le;
958 u32 hi = upper_32_bits(map);
959
960 if (sky2->rx_addr64 != hi) {
961 le = sky2_next_rx(sky2);
962 le->addr = cpu_to_le32(hi);
963 le->opcode = OP_ADDR64 | HW_OWNER;
964 sky2->rx_addr64 = upper_32_bits(map + len);
965 }
966
967 le = sky2_next_rx(sky2);
968 le->addr = cpu_to_le32((u32) map);
969 le->length = cpu_to_le16(len);
970 le->opcode = op | HW_OWNER;
971 }
972
973 /* Build description to hardware for one possibly fragmented skb */
974 static void sky2_rx_submit(struct sky2_port *sky2,
975 const struct rx_ring_info *re)
976 {
977 int i;
978
979 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
980
981 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
982 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
983 }
984
985
986 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
987 unsigned size)
988 {
989 struct sk_buff *skb = re->skb;
990 int i;
991
992 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
993 pci_unmap_len_set(re, data_size, size);
994
995 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
996 re->frag_addr[i] = pci_map_page(pdev,
997 skb_shinfo(skb)->frags[i].page,
998 skb_shinfo(skb)->frags[i].page_offset,
999 skb_shinfo(skb)->frags[i].size,
1000 PCI_DMA_FROMDEVICE);
1001 }
1002
1003 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1004 {
1005 struct sk_buff *skb = re->skb;
1006 int i;
1007
1008 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1009 PCI_DMA_FROMDEVICE);
1010
1011 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1012 pci_unmap_page(pdev, re->frag_addr[i],
1013 skb_shinfo(skb)->frags[i].size,
1014 PCI_DMA_FROMDEVICE);
1015 }
1016
1017 /* Tell chip where to start receive checksum.
1018 * Actually has two checksums, but set both same to avoid possible byte
1019 * order problems.
1020 */
1021 static void rx_set_checksum(struct sky2_port *sky2)
1022 {
1023 struct sky2_rx_le *le = sky2_next_rx(sky2);
1024
1025 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1026 le->ctrl = 0;
1027 le->opcode = OP_TCPSTART | HW_OWNER;
1028
1029 sky2_write32(sky2->hw,
1030 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1031 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1032 }
1033
1034 /*
1035 * The RX Stop command will not work for Yukon-2 if the BMU does not
1036 * reach the end of packet and since we can't make sure that we have
1037 * incoming data, we must reset the BMU while it is not doing a DMA
1038 * transfer. Since it is possible that the RX path is still active,
1039 * the RX RAM buffer will be stopped first, so any possible incoming
1040 * data will not trigger a DMA. After the RAM buffer is stopped, the
1041 * BMU is polled until any DMA in progress is ended and only then it
1042 * will be reset.
1043 */
1044 static void sky2_rx_stop(struct sky2_port *sky2)
1045 {
1046 struct sky2_hw *hw = sky2->hw;
1047 unsigned rxq = rxqaddr[sky2->port];
1048 int i;
1049
1050 /* disable the RAM Buffer receive queue */
1051 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1052
1053 for (i = 0; i < 0xffff; i++)
1054 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1055 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1056 goto stopped;
1057
1058 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1059 sky2->netdev->name);
1060 stopped:
1061 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1062
1063 /* reset the Rx prefetch unit */
1064 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1065 mmiowb();
1066 }
1067
1068 /* Clean out receive buffer area, assumes receiver hardware stopped */
1069 static void sky2_rx_clean(struct sky2_port *sky2)
1070 {
1071 unsigned i;
1072
1073 memset(sky2->rx_le, 0, RX_LE_BYTES);
1074 for (i = 0; i < sky2->rx_pending; i++) {
1075 struct rx_ring_info *re = sky2->rx_ring + i;
1076
1077 if (re->skb) {
1078 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1079 kfree_skb(re->skb);
1080 re->skb = NULL;
1081 }
1082 }
1083 }
1084
1085 /* Basic MII support */
1086 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1087 {
1088 struct mii_ioctl_data *data = if_mii(ifr);
1089 struct sky2_port *sky2 = netdev_priv(dev);
1090 struct sky2_hw *hw = sky2->hw;
1091 int err = -EOPNOTSUPP;
1092
1093 if (!netif_running(dev))
1094 return -ENODEV; /* Phy still in reset */
1095
1096 switch (cmd) {
1097 case SIOCGMIIPHY:
1098 data->phy_id = PHY_ADDR_MARV;
1099
1100 /* fallthru */
1101 case SIOCGMIIREG: {
1102 u16 val = 0;
1103
1104 spin_lock_bh(&sky2->phy_lock);
1105 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1106 spin_unlock_bh(&sky2->phy_lock);
1107
1108 data->val_out = val;
1109 break;
1110 }
1111
1112 case SIOCSMIIREG:
1113 if (!capable(CAP_NET_ADMIN))
1114 return -EPERM;
1115
1116 spin_lock_bh(&sky2->phy_lock);
1117 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1118 data->val_in);
1119 spin_unlock_bh(&sky2->phy_lock);
1120 break;
1121 }
1122 return err;
1123 }
1124
1125 #ifdef SKY2_VLAN_TAG_USED
1126 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1127 {
1128 struct sky2_port *sky2 = netdev_priv(dev);
1129 struct sky2_hw *hw = sky2->hw;
1130 u16 port = sky2->port;
1131
1132 netif_tx_lock_bh(dev);
1133 napi_disable(&hw->napi);
1134
1135 sky2->vlgrp = grp;
1136 if (grp) {
1137 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1138 RX_VLAN_STRIP_ON);
1139 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1140 TX_VLAN_TAG_ON);
1141 } else {
1142 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1143 RX_VLAN_STRIP_OFF);
1144 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1145 TX_VLAN_TAG_OFF);
1146 }
1147
1148 napi_enable(&hw->napi);
1149 netif_tx_unlock_bh(dev);
1150 }
1151 #endif
1152
1153 /*
1154 * Allocate an skb for receiving. If the MTU is large enough
1155 * make the skb non-linear with a fragment list of pages.
1156 *
1157 * It appears the hardware has a bug in the FIFO logic that
1158 * cause it to hang if the FIFO gets overrun and the receive buffer
1159 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1160 * aligned except if slab debugging is enabled.
1161 */
1162 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1163 {
1164 struct sk_buff *skb;
1165 unsigned long p;
1166 int i;
1167
1168 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1169 if (!skb)
1170 goto nomem;
1171
1172 p = (unsigned long) skb->data;
1173 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1174
1175 for (i = 0; i < sky2->rx_nfrags; i++) {
1176 struct page *page = alloc_page(GFP_ATOMIC);
1177
1178 if (!page)
1179 goto free_partial;
1180 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1181 }
1182
1183 return skb;
1184 free_partial:
1185 kfree_skb(skb);
1186 nomem:
1187 return NULL;
1188 }
1189
1190 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1191 {
1192 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1193 }
1194
1195 /*
1196 * Allocate and setup receiver buffer pool.
1197 * Normal case this ends up creating one list element for skb
1198 * in the receive ring. Worst case if using large MTU and each
1199 * allocation falls on a different 64 bit region, that results
1200 * in 6 list elements per ring entry.
1201 * One element is used for checksum enable/disable, and one
1202 * extra to avoid wrap.
1203 */
1204 static int sky2_rx_start(struct sky2_port *sky2)
1205 {
1206 struct sky2_hw *hw = sky2->hw;
1207 struct rx_ring_info *re;
1208 unsigned rxq = rxqaddr[sky2->port];
1209 unsigned i, size, space, thresh;
1210
1211 sky2->rx_put = sky2->rx_next = 0;
1212 sky2_qset(hw, rxq);
1213
1214 /* On PCI express lowering the watermark gives better performance */
1215 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1216 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1217
1218 /* These chips have no ram buffer?
1219 * MAC Rx RAM Read is controlled by hardware */
1220 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1221 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1222 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1223 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1224
1225 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1226
1227 if (!(hw->flags & SKY2_HW_NEW_LE))
1228 rx_set_checksum(sky2);
1229
1230 /* Space needed for frame data + headers rounded up */
1231 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1232
1233 /* Stopping point for hardware truncation */
1234 thresh = (size - 8) / sizeof(u32);
1235
1236 /* Account for overhead of skb - to avoid order > 0 allocation */
1237 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1238 + sizeof(struct skb_shared_info);
1239
1240 sky2->rx_nfrags = space >> PAGE_SHIFT;
1241 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1242
1243 if (sky2->rx_nfrags != 0) {
1244 /* Compute residue after pages */
1245 space = sky2->rx_nfrags << PAGE_SHIFT;
1246
1247 if (space < size)
1248 size -= space;
1249 else
1250 size = 0;
1251
1252 /* Optimize to handle small packets and headers */
1253 if (size < copybreak)
1254 size = copybreak;
1255 if (size < ETH_HLEN)
1256 size = ETH_HLEN;
1257 }
1258 sky2->rx_data_size = size;
1259
1260 /* Fill Rx ring */
1261 for (i = 0; i < sky2->rx_pending; i++) {
1262 re = sky2->rx_ring + i;
1263
1264 re->skb = sky2_rx_alloc(sky2);
1265 if (!re->skb)
1266 goto nomem;
1267
1268 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1269 sky2_rx_submit(sky2, re);
1270 }
1271
1272 /*
1273 * The receiver hangs if it receives frames larger than the
1274 * packet buffer. As a workaround, truncate oversize frames, but
1275 * the register is limited to 9 bits, so if you do frames > 2052
1276 * you better get the MTU right!
1277 */
1278 if (thresh > 0x1ff)
1279 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1280 else {
1281 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1282 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1283 }
1284
1285 /* Tell chip about available buffers */
1286 sky2_rx_update(sky2, rxq);
1287 return 0;
1288 nomem:
1289 sky2_rx_clean(sky2);
1290 return -ENOMEM;
1291 }
1292
1293 /* Bring up network interface. */
1294 static int sky2_up(struct net_device *dev)
1295 {
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
1298 unsigned port = sky2->port;
1299 u32 imask, ramsize;
1300 int cap, err = -ENOMEM;
1301 struct net_device *otherdev = hw->dev[sky2->port^1];
1302
1303 /*
1304 * On dual port PCI-X card, there is an problem where status
1305 * can be received out of order due to split transactions
1306 */
1307 if (otherdev && netif_running(otherdev) &&
1308 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1309 struct sky2_port *osky2 = netdev_priv(otherdev);
1310 u16 cmd;
1311
1312 pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd);
1313 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1314 pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd);
1315
1316 sky2->rx_csum = 0;
1317 osky2->rx_csum = 0;
1318 }
1319
1320 if (netif_msg_ifup(sky2))
1321 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1322
1323 netif_carrier_off(dev);
1324
1325 /* must be power of 2 */
1326 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1327 TX_RING_SIZE *
1328 sizeof(struct sky2_tx_le),
1329 &sky2->tx_le_map);
1330 if (!sky2->tx_le)
1331 goto err_out;
1332
1333 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1334 GFP_KERNEL);
1335 if (!sky2->tx_ring)
1336 goto err_out;
1337
1338 tx_init(sky2);
1339
1340 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1341 &sky2->rx_le_map);
1342 if (!sky2->rx_le)
1343 goto err_out;
1344 memset(sky2->rx_le, 0, RX_LE_BYTES);
1345
1346 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1347 GFP_KERNEL);
1348 if (!sky2->rx_ring)
1349 goto err_out;
1350
1351 sky2_phy_power(hw, port, 1);
1352
1353 sky2_mac_init(hw, port);
1354
1355 /* Register is number of 4K blocks on internal RAM buffer. */
1356 ramsize = sky2_read8(hw, B2_E_0) * 4;
1357 if (ramsize > 0) {
1358 u32 rxspace;
1359
1360 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1361 if (ramsize < 16)
1362 rxspace = ramsize / 2;
1363 else
1364 rxspace = 8 + (2*(ramsize - 16))/3;
1365
1366 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1367 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1368
1369 /* Make sure SyncQ is disabled */
1370 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1371 RB_RST_SET);
1372 }
1373
1374 sky2_qset(hw, txqaddr[port]);
1375
1376 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1377 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1378 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1379
1380 /* Set almost empty threshold */
1381 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1382 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1383 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1384
1385 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1386 TX_RING_SIZE - 1);
1387
1388 napi_enable(&hw->napi);
1389
1390 err = sky2_rx_start(sky2);
1391 if (err) {
1392 napi_disable(&hw->napi);
1393 goto err_out;
1394 }
1395
1396 /* Enable interrupts from phy/mac for port */
1397 imask = sky2_read32(hw, B0_IMSK);
1398 imask |= portirq_msk[port];
1399 sky2_write32(hw, B0_IMSK, imask);
1400
1401 return 0;
1402
1403 err_out:
1404 if (sky2->rx_le) {
1405 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1406 sky2->rx_le, sky2->rx_le_map);
1407 sky2->rx_le = NULL;
1408 }
1409 if (sky2->tx_le) {
1410 pci_free_consistent(hw->pdev,
1411 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1412 sky2->tx_le, sky2->tx_le_map);
1413 sky2->tx_le = NULL;
1414 }
1415 kfree(sky2->tx_ring);
1416 kfree(sky2->rx_ring);
1417
1418 sky2->tx_ring = NULL;
1419 sky2->rx_ring = NULL;
1420 return err;
1421 }
1422
1423 /* Modular subtraction in ring */
1424 static inline int tx_dist(unsigned tail, unsigned head)
1425 {
1426 return (head - tail) & (TX_RING_SIZE - 1);
1427 }
1428
1429 /* Number of list elements available for next tx */
1430 static inline int tx_avail(const struct sky2_port *sky2)
1431 {
1432 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1433 }
1434
1435 /* Estimate of number of transmit list elements required */
1436 static unsigned tx_le_req(const struct sk_buff *skb)
1437 {
1438 unsigned count;
1439
1440 count = sizeof(dma_addr_t) / sizeof(u32);
1441 count += skb_shinfo(skb)->nr_frags * count;
1442
1443 if (skb_is_gso(skb))
1444 ++count;
1445
1446 if (skb->ip_summed == CHECKSUM_PARTIAL)
1447 ++count;
1448
1449 return count;
1450 }
1451
1452 /*
1453 * Put one packet in ring for transmit.
1454 * A single packet can generate multiple list elements, and
1455 * the number of ring elements will probably be less than the number
1456 * of list elements used.
1457 */
1458 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1459 {
1460 struct sky2_port *sky2 = netdev_priv(dev);
1461 struct sky2_hw *hw = sky2->hw;
1462 struct sky2_tx_le *le = NULL;
1463 struct tx_ring_info *re;
1464 unsigned i, len;
1465 dma_addr_t mapping;
1466 u32 addr64;
1467 u16 mss;
1468 u8 ctrl;
1469
1470 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1471 return NETDEV_TX_BUSY;
1472
1473 if (unlikely(netif_msg_tx_queued(sky2)))
1474 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1475 dev->name, sky2->tx_prod, skb->len);
1476
1477 len = skb_headlen(skb);
1478 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1479 addr64 = upper_32_bits(mapping);
1480
1481 /* Send high bits if changed or crosses boundary */
1482 if (addr64 != sky2->tx_addr64 ||
1483 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1484 le = get_tx_le(sky2);
1485 le->addr = cpu_to_le32(addr64);
1486 le->opcode = OP_ADDR64 | HW_OWNER;
1487 sky2->tx_addr64 = upper_32_bits(mapping + len);
1488 }
1489
1490 /* Check for TCP Segmentation Offload */
1491 mss = skb_shinfo(skb)->gso_size;
1492 if (mss != 0) {
1493
1494 if (!(hw->flags & SKY2_HW_NEW_LE))
1495 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1496
1497 if (mss != sky2->tx_last_mss) {
1498 le = get_tx_le(sky2);
1499 le->addr = cpu_to_le32(mss);
1500
1501 if (hw->flags & SKY2_HW_NEW_LE)
1502 le->opcode = OP_MSS | HW_OWNER;
1503 else
1504 le->opcode = OP_LRGLEN | HW_OWNER;
1505 sky2->tx_last_mss = mss;
1506 }
1507 }
1508
1509 ctrl = 0;
1510 #ifdef SKY2_VLAN_TAG_USED
1511 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1512 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1513 if (!le) {
1514 le = get_tx_le(sky2);
1515 le->addr = 0;
1516 le->opcode = OP_VLAN|HW_OWNER;
1517 } else
1518 le->opcode |= OP_VLAN;
1519 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1520 ctrl |= INS_VLAN;
1521 }
1522 #endif
1523
1524 /* Handle TCP checksum offload */
1525 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1526 /* On Yukon EX (some versions) encoding change. */
1527 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1528 ctrl |= CALSUM; /* auto checksum */
1529 else {
1530 const unsigned offset = skb_transport_offset(skb);
1531 u32 tcpsum;
1532
1533 tcpsum = offset << 16; /* sum start */
1534 tcpsum |= offset + skb->csum_offset; /* sum write */
1535
1536 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1537 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1538 ctrl |= UDPTCP;
1539
1540 if (tcpsum != sky2->tx_tcpsum) {
1541 sky2->tx_tcpsum = tcpsum;
1542
1543 le = get_tx_le(sky2);
1544 le->addr = cpu_to_le32(tcpsum);
1545 le->length = 0; /* initial checksum value */
1546 le->ctrl = 1; /* one packet */
1547 le->opcode = OP_TCPLISW | HW_OWNER;
1548 }
1549 }
1550 }
1551
1552 le = get_tx_le(sky2);
1553 le->addr = cpu_to_le32((u32) mapping);
1554 le->length = cpu_to_le16(len);
1555 le->ctrl = ctrl;
1556 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1557
1558 re = tx_le_re(sky2, le);
1559 re->skb = skb;
1560 pci_unmap_addr_set(re, mapaddr, mapping);
1561 pci_unmap_len_set(re, maplen, len);
1562
1563 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1564 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1565
1566 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1567 frag->size, PCI_DMA_TODEVICE);
1568 addr64 = upper_32_bits(mapping);
1569 if (addr64 != sky2->tx_addr64) {
1570 le = get_tx_le(sky2);
1571 le->addr = cpu_to_le32(addr64);
1572 le->ctrl = 0;
1573 le->opcode = OP_ADDR64 | HW_OWNER;
1574 sky2->tx_addr64 = addr64;
1575 }
1576
1577 le = get_tx_le(sky2);
1578 le->addr = cpu_to_le32((u32) mapping);
1579 le->length = cpu_to_le16(frag->size);
1580 le->ctrl = ctrl;
1581 le->opcode = OP_BUFFER | HW_OWNER;
1582
1583 re = tx_le_re(sky2, le);
1584 re->skb = skb;
1585 pci_unmap_addr_set(re, mapaddr, mapping);
1586 pci_unmap_len_set(re, maplen, frag->size);
1587 }
1588
1589 le->ctrl |= EOP;
1590
1591 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1592 netif_stop_queue(dev);
1593
1594 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1595
1596 dev->trans_start = jiffies;
1597 return NETDEV_TX_OK;
1598 }
1599
1600 /*
1601 * Free ring elements from starting at tx_cons until "done"
1602 *
1603 * NB: the hardware will tell us about partial completion of multi-part
1604 * buffers so make sure not to free skb to early.
1605 */
1606 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1607 {
1608 struct net_device *dev = sky2->netdev;
1609 struct pci_dev *pdev = sky2->hw->pdev;
1610 unsigned idx;
1611
1612 BUG_ON(done >= TX_RING_SIZE);
1613
1614 for (idx = sky2->tx_cons; idx != done;
1615 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1616 struct sky2_tx_le *le = sky2->tx_le + idx;
1617 struct tx_ring_info *re = sky2->tx_ring + idx;
1618
1619 switch(le->opcode & ~HW_OWNER) {
1620 case OP_LARGESEND:
1621 case OP_PACKET:
1622 pci_unmap_single(pdev,
1623 pci_unmap_addr(re, mapaddr),
1624 pci_unmap_len(re, maplen),
1625 PCI_DMA_TODEVICE);
1626 break;
1627 case OP_BUFFER:
1628 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1629 pci_unmap_len(re, maplen),
1630 PCI_DMA_TODEVICE);
1631 break;
1632 }
1633
1634 if (le->ctrl & EOP) {
1635 if (unlikely(netif_msg_tx_done(sky2)))
1636 printk(KERN_DEBUG "%s: tx done %u\n",
1637 dev->name, idx);
1638
1639 sky2->net_stats.tx_packets++;
1640 sky2->net_stats.tx_bytes += re->skb->len;
1641
1642 dev_kfree_skb_any(re->skb);
1643 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1644 }
1645 }
1646
1647 sky2->tx_cons = idx;
1648 smp_mb();
1649
1650 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1651 netif_wake_queue(dev);
1652 }
1653
1654 /* Cleanup all untransmitted buffers, assume transmitter not running */
1655 static void sky2_tx_clean(struct net_device *dev)
1656 {
1657 struct sky2_port *sky2 = netdev_priv(dev);
1658
1659 netif_tx_lock_bh(dev);
1660 sky2_tx_complete(sky2, sky2->tx_prod);
1661 netif_tx_unlock_bh(dev);
1662 }
1663
1664 /* Network shutdown */
1665 static int sky2_down(struct net_device *dev)
1666 {
1667 struct sky2_port *sky2 = netdev_priv(dev);
1668 struct sky2_hw *hw = sky2->hw;
1669 unsigned port = sky2->port;
1670 u16 ctrl;
1671 u32 imask;
1672
1673 /* Never really got started! */
1674 if (!sky2->tx_le)
1675 return 0;
1676
1677 if (netif_msg_ifdown(sky2))
1678 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1679
1680 /* Stop more packets from being queued */
1681 netif_stop_queue(dev);
1682
1683 napi_disable(&hw->napi);
1684
1685 /* Disable port IRQ */
1686 imask = sky2_read32(hw, B0_IMSK);
1687 imask &= ~portirq_msk[port];
1688 sky2_write32(hw, B0_IMSK, imask);
1689
1690 sky2_gmac_reset(hw, port);
1691
1692 /* Stop transmitter */
1693 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1694 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1695
1696 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1697 RB_RST_SET | RB_DIS_OP_MD);
1698
1699 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1700 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1701 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1702
1703 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1704
1705 /* Workaround shared GMAC reset */
1706 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1707 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1708 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1709
1710 /* Disable Force Sync bit and Enable Alloc bit */
1711 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1712 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1713
1714 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1715 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1716 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1717
1718 /* Reset the PCI FIFO of the async Tx queue */
1719 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1720 BMU_RST_SET | BMU_FIFO_RST);
1721
1722 /* Reset the Tx prefetch units */
1723 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1724 PREF_UNIT_RST_SET);
1725
1726 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1727
1728 sky2_rx_stop(sky2);
1729
1730 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1731 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1732
1733 sky2_phy_power(hw, port, 0);
1734
1735 netif_carrier_off(dev);
1736
1737 /* turn off LED's */
1738 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1739
1740 synchronize_irq(hw->pdev->irq);
1741
1742 sky2_tx_clean(dev);
1743 sky2_rx_clean(sky2);
1744
1745 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1746 sky2->rx_le, sky2->rx_le_map);
1747 kfree(sky2->rx_ring);
1748
1749 pci_free_consistent(hw->pdev,
1750 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1751 sky2->tx_le, sky2->tx_le_map);
1752 kfree(sky2->tx_ring);
1753
1754 sky2->tx_le = NULL;
1755 sky2->rx_le = NULL;
1756
1757 sky2->rx_ring = NULL;
1758 sky2->tx_ring = NULL;
1759
1760 return 0;
1761 }
1762
1763 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1764 {
1765 if (hw->flags & SKY2_HW_FIBRE_PHY)
1766 return SPEED_1000;
1767
1768 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1769 if (aux & PHY_M_PS_SPEED_100)
1770 return SPEED_100;
1771 else
1772 return SPEED_10;
1773 }
1774
1775 switch (aux & PHY_M_PS_SPEED_MSK) {
1776 case PHY_M_PS_SPEED_1000:
1777 return SPEED_1000;
1778 case PHY_M_PS_SPEED_100:
1779 return SPEED_100;
1780 default:
1781 return SPEED_10;
1782 }
1783 }
1784
1785 static void sky2_link_up(struct sky2_port *sky2)
1786 {
1787 struct sky2_hw *hw = sky2->hw;
1788 unsigned port = sky2->port;
1789 u16 reg;
1790 static const char *fc_name[] = {
1791 [FC_NONE] = "none",
1792 [FC_TX] = "tx",
1793 [FC_RX] = "rx",
1794 [FC_BOTH] = "both",
1795 };
1796
1797 /* enable Rx/Tx */
1798 reg = gma_read16(hw, port, GM_GP_CTRL);
1799 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1800 gma_write16(hw, port, GM_GP_CTRL, reg);
1801
1802 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1803
1804 netif_carrier_on(sky2->netdev);
1805
1806 mod_timer(&hw->watchdog_timer, jiffies + 1);
1807
1808 /* Turn on link LED */
1809 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1810 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1811
1812 if (hw->flags & SKY2_HW_NEWER_PHY) {
1813 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1814 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1815
1816 switch(sky2->speed) {
1817 case SPEED_10:
1818 led |= PHY_M_LEDC_INIT_CTRL(7);
1819 break;
1820
1821 case SPEED_100:
1822 led |= PHY_M_LEDC_STA1_CTRL(7);
1823 break;
1824
1825 case SPEED_1000:
1826 led |= PHY_M_LEDC_STA0_CTRL(7);
1827 break;
1828 }
1829
1830 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1831 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1832 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1833 }
1834
1835 if (netif_msg_link(sky2))
1836 printk(KERN_INFO PFX
1837 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1838 sky2->netdev->name, sky2->speed,
1839 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1840 fc_name[sky2->flow_status]);
1841 }
1842
1843 static void sky2_link_down(struct sky2_port *sky2)
1844 {
1845 struct sky2_hw *hw = sky2->hw;
1846 unsigned port = sky2->port;
1847 u16 reg;
1848
1849 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1850
1851 reg = gma_read16(hw, port, GM_GP_CTRL);
1852 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1853 gma_write16(hw, port, GM_GP_CTRL, reg);
1854
1855 netif_carrier_off(sky2->netdev);
1856
1857 /* Turn on link LED */
1858 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1859
1860 if (netif_msg_link(sky2))
1861 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1862
1863 sky2_phy_init(hw, port);
1864 }
1865
1866 static enum flow_control sky2_flow(int rx, int tx)
1867 {
1868 if (rx)
1869 return tx ? FC_BOTH : FC_RX;
1870 else
1871 return tx ? FC_TX : FC_NONE;
1872 }
1873
1874 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1875 {
1876 struct sky2_hw *hw = sky2->hw;
1877 unsigned port = sky2->port;
1878 u16 advert, lpa;
1879
1880 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1881 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1882 if (lpa & PHY_M_AN_RF) {
1883 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1884 return -1;
1885 }
1886
1887 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1888 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1889 sky2->netdev->name);
1890 return -1;
1891 }
1892
1893 sky2->speed = sky2_phy_speed(hw, aux);
1894 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1895
1896 /* Since the pause result bits seem to in different positions on
1897 * different chips. look at registers.
1898 */
1899 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1900 /* Shift for bits in fiber PHY */
1901 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1902 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1903
1904 if (advert & ADVERTISE_1000XPAUSE)
1905 advert |= ADVERTISE_PAUSE_CAP;
1906 if (advert & ADVERTISE_1000XPSE_ASYM)
1907 advert |= ADVERTISE_PAUSE_ASYM;
1908 if (lpa & LPA_1000XPAUSE)
1909 lpa |= LPA_PAUSE_CAP;
1910 if (lpa & LPA_1000XPAUSE_ASYM)
1911 lpa |= LPA_PAUSE_ASYM;
1912 }
1913
1914 sky2->flow_status = FC_NONE;
1915 if (advert & ADVERTISE_PAUSE_CAP) {
1916 if (lpa & LPA_PAUSE_CAP)
1917 sky2->flow_status = FC_BOTH;
1918 else if (advert & ADVERTISE_PAUSE_ASYM)
1919 sky2->flow_status = FC_RX;
1920 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1921 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1922 sky2->flow_status = FC_TX;
1923 }
1924
1925 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1926 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1927 sky2->flow_status = FC_NONE;
1928
1929 if (sky2->flow_status & FC_TX)
1930 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1931 else
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1933
1934 return 0;
1935 }
1936
1937 /* Interrupt from PHY */
1938 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1939 {
1940 struct net_device *dev = hw->dev[port];
1941 struct sky2_port *sky2 = netdev_priv(dev);
1942 u16 istatus, phystat;
1943
1944 if (!netif_running(dev))
1945 return;
1946
1947 spin_lock(&sky2->phy_lock);
1948 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1949 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1950
1951 if (netif_msg_intr(sky2))
1952 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1953 sky2->netdev->name, istatus, phystat);
1954
1955 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1956 if (sky2_autoneg_done(sky2, phystat) == 0)
1957 sky2_link_up(sky2);
1958 goto out;
1959 }
1960
1961 if (istatus & PHY_M_IS_LSP_CHANGE)
1962 sky2->speed = sky2_phy_speed(hw, phystat);
1963
1964 if (istatus & PHY_M_IS_DUP_CHANGE)
1965 sky2->duplex =
1966 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1967
1968 if (istatus & PHY_M_IS_LST_CHANGE) {
1969 if (phystat & PHY_M_PS_LINK_UP)
1970 sky2_link_up(sky2);
1971 else
1972 sky2_link_down(sky2);
1973 }
1974 out:
1975 spin_unlock(&sky2->phy_lock);
1976 }
1977
1978 /* Transmit timeout is only called if we are running, carrier is up
1979 * and tx queue is full (stopped).
1980 */
1981 static void sky2_tx_timeout(struct net_device *dev)
1982 {
1983 struct sky2_port *sky2 = netdev_priv(dev);
1984 struct sky2_hw *hw = sky2->hw;
1985
1986 if (netif_msg_timer(sky2))
1987 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1988
1989 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1990 dev->name, sky2->tx_cons, sky2->tx_prod,
1991 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1992 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1993
1994 /* can't restart safely under softirq */
1995 schedule_work(&hw->restart_work);
1996 }
1997
1998 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1999 {
2000 struct sky2_port *sky2 = netdev_priv(dev);
2001 struct sky2_hw *hw = sky2->hw;
2002 unsigned port = sky2->port;
2003 int err;
2004 u16 ctl, mode;
2005 u32 imask;
2006
2007 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2008 return -EINVAL;
2009
2010 if (new_mtu > ETH_DATA_LEN &&
2011 (hw->chip_id == CHIP_ID_YUKON_FE ||
2012 hw->chip_id == CHIP_ID_YUKON_FE_P))
2013 return -EINVAL;
2014
2015 if (!netif_running(dev)) {
2016 dev->mtu = new_mtu;
2017 return 0;
2018 }
2019
2020 imask = sky2_read32(hw, B0_IMSK);
2021 sky2_write32(hw, B0_IMSK, 0);
2022
2023 dev->trans_start = jiffies; /* prevent tx timeout */
2024 netif_stop_queue(dev);
2025 napi_disable(&hw->napi);
2026
2027 synchronize_irq(hw->pdev->irq);
2028
2029 if (sky2_read8(hw, B2_E_0) == 0)
2030 sky2_set_tx_stfwd(hw, port);
2031
2032 ctl = gma_read16(hw, port, GM_GP_CTRL);
2033 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2034 sky2_rx_stop(sky2);
2035 sky2_rx_clean(sky2);
2036
2037 dev->mtu = new_mtu;
2038
2039 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2040 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2041
2042 if (dev->mtu > ETH_DATA_LEN)
2043 mode |= GM_SMOD_JUMBO_ENA;
2044
2045 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2046
2047 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2048
2049 err = sky2_rx_start(sky2);
2050 sky2_write32(hw, B0_IMSK, imask);
2051
2052 /* Unconditionally re-enable NAPI because even if we
2053 * call dev_close() that will do a napi_disable().
2054 */
2055 napi_enable(&hw->napi);
2056
2057 if (err)
2058 dev_close(dev);
2059 else {
2060 gma_write16(hw, port, GM_GP_CTRL, ctl);
2061
2062 netif_wake_queue(dev);
2063 }
2064
2065 return err;
2066 }
2067
2068 /* For small just reuse existing skb for next receive */
2069 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2070 const struct rx_ring_info *re,
2071 unsigned length)
2072 {
2073 struct sk_buff *skb;
2074
2075 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2076 if (likely(skb)) {
2077 skb_reserve(skb, 2);
2078 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2079 length, PCI_DMA_FROMDEVICE);
2080 skb_copy_from_linear_data(re->skb, skb->data, length);
2081 skb->ip_summed = re->skb->ip_summed;
2082 skb->csum = re->skb->csum;
2083 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2084 length, PCI_DMA_FROMDEVICE);
2085 re->skb->ip_summed = CHECKSUM_NONE;
2086 skb_put(skb, length);
2087 }
2088 return skb;
2089 }
2090
2091 /* Adjust length of skb with fragments to match received data */
2092 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2093 unsigned int length)
2094 {
2095 int i, num_frags;
2096 unsigned int size;
2097
2098 /* put header into skb */
2099 size = min(length, hdr_space);
2100 skb->tail += size;
2101 skb->len += size;
2102 length -= size;
2103
2104 num_frags = skb_shinfo(skb)->nr_frags;
2105 for (i = 0; i < num_frags; i++) {
2106 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2107
2108 if (length == 0) {
2109 /* don't need this page */
2110 __free_page(frag->page);
2111 --skb_shinfo(skb)->nr_frags;
2112 } else {
2113 size = min(length, (unsigned) PAGE_SIZE);
2114
2115 frag->size = size;
2116 skb->data_len += size;
2117 skb->truesize += size;
2118 skb->len += size;
2119 length -= size;
2120 }
2121 }
2122 }
2123
2124 /* Normal packet - take skb from ring element and put in a new one */
2125 static struct sk_buff *receive_new(struct sky2_port *sky2,
2126 struct rx_ring_info *re,
2127 unsigned int length)
2128 {
2129 struct sk_buff *skb, *nskb;
2130 unsigned hdr_space = sky2->rx_data_size;
2131
2132 /* Don't be tricky about reusing pages (yet) */
2133 nskb = sky2_rx_alloc(sky2);
2134 if (unlikely(!nskb))
2135 return NULL;
2136
2137 skb = re->skb;
2138 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2139
2140 prefetch(skb->data);
2141 re->skb = nskb;
2142 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2143
2144 if (skb_shinfo(skb)->nr_frags)
2145 skb_put_frags(skb, hdr_space, length);
2146 else
2147 skb_put(skb, length);
2148 return skb;
2149 }
2150
2151 /*
2152 * Receive one packet.
2153 * For larger packets, get new buffer.
2154 */
2155 static struct sk_buff *sky2_receive(struct net_device *dev,
2156 u16 length, u32 status)
2157 {
2158 struct sky2_port *sky2 = netdev_priv(dev);
2159 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2160 struct sk_buff *skb = NULL;
2161 u16 count = (status & GMR_FS_LEN) >> 16;
2162
2163 #ifdef SKY2_VLAN_TAG_USED
2164 /* Account for vlan tag */
2165 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2166 count -= VLAN_HLEN;
2167 #endif
2168
2169 if (unlikely(netif_msg_rx_status(sky2)))
2170 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2171 dev->name, sky2->rx_next, status, length);
2172
2173 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2174 prefetch(sky2->rx_ring + sky2->rx_next);
2175
2176 /* This chip has hardware problems that generates bogus status.
2177 * So do only marginal checking and expect higher level protocols
2178 * to handle crap frames.
2179 */
2180 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2181 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2182 length != count)
2183 goto okay;
2184
2185 if (status & GMR_FS_ANY_ERR)
2186 goto error;
2187
2188 if (!(status & GMR_FS_RX_OK))
2189 goto resubmit;
2190
2191 /* if length reported by DMA does not match PHY, packet was truncated */
2192 if (length != count)
2193 goto len_error;
2194
2195 okay:
2196 if (length < copybreak)
2197 skb = receive_copy(sky2, re, length);
2198 else
2199 skb = receive_new(sky2, re, length);
2200 resubmit:
2201 sky2_rx_submit(sky2, re);
2202
2203 return skb;
2204
2205 len_error:
2206 /* Truncation of overlength packets
2207 causes PHY length to not match MAC length */
2208 ++sky2->net_stats.rx_length_errors;
2209 if (netif_msg_rx_err(sky2) && net_ratelimit())
2210 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2211 dev->name, status, length);
2212 goto resubmit;
2213
2214 error:
2215 ++sky2->net_stats.rx_errors;
2216 if (status & GMR_FS_RX_FF_OV) {
2217 sky2->net_stats.rx_over_errors++;
2218 goto resubmit;
2219 }
2220
2221 if (netif_msg_rx_err(sky2) && net_ratelimit())
2222 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2223 dev->name, status, length);
2224
2225 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2226 sky2->net_stats.rx_length_errors++;
2227 if (status & GMR_FS_FRAGMENT)
2228 sky2->net_stats.rx_frame_errors++;
2229 if (status & GMR_FS_CRC_ERR)
2230 sky2->net_stats.rx_crc_errors++;
2231
2232 goto resubmit;
2233 }
2234
2235 /* Transmit complete */
2236 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2237 {
2238 struct sky2_port *sky2 = netdev_priv(dev);
2239
2240 if (netif_running(dev)) {
2241 netif_tx_lock(dev);
2242 sky2_tx_complete(sky2, last);
2243 netif_tx_unlock(dev);
2244 }
2245 }
2246
2247 /* Process status response ring */
2248 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2249 {
2250 int work_done = 0;
2251 unsigned rx[2] = { 0, 0 };
2252
2253 rmb();
2254 do {
2255 struct sky2_port *sky2;
2256 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2257 unsigned port = le->css & CSS_LINK_BIT;
2258 struct net_device *dev;
2259 struct sk_buff *skb;
2260 u32 status;
2261 u16 length;
2262
2263 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2264
2265 dev = hw->dev[port];
2266 sky2 = netdev_priv(dev);
2267 length = le16_to_cpu(le->length);
2268 status = le32_to_cpu(le->status);
2269
2270 switch (le->opcode & ~HW_OWNER) {
2271 case OP_RXSTAT:
2272 ++rx[port];
2273 skb = sky2_receive(dev, length, status);
2274 if (unlikely(!skb)) {
2275 sky2->net_stats.rx_dropped++;
2276 break;
2277 }
2278
2279 /* This chip reports checksum status differently */
2280 if (hw->flags & SKY2_HW_NEW_LE) {
2281 if (sky2->rx_csum &&
2282 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2283 (le->css & CSS_TCPUDPCSOK))
2284 skb->ip_summed = CHECKSUM_UNNECESSARY;
2285 else
2286 skb->ip_summed = CHECKSUM_NONE;
2287 }
2288
2289 skb->protocol = eth_type_trans(skb, dev);
2290 sky2->net_stats.rx_packets++;
2291 sky2->net_stats.rx_bytes += skb->len;
2292 dev->last_rx = jiffies;
2293
2294 #ifdef SKY2_VLAN_TAG_USED
2295 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2296 vlan_hwaccel_receive_skb(skb,
2297 sky2->vlgrp,
2298 be16_to_cpu(sky2->rx_tag));
2299 } else
2300 #endif
2301 netif_receive_skb(skb);
2302
2303 /* Stop after net poll weight */
2304 if (++work_done >= to_do)
2305 goto exit_loop;
2306 break;
2307
2308 #ifdef SKY2_VLAN_TAG_USED
2309 case OP_RXVLAN:
2310 sky2->rx_tag = length;
2311 break;
2312
2313 case OP_RXCHKSVLAN:
2314 sky2->rx_tag = length;
2315 /* fall through */
2316 #endif
2317 case OP_RXCHKS:
2318 if (!sky2->rx_csum)
2319 break;
2320
2321 /* If this happens then driver assuming wrong format */
2322 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2323 if (net_ratelimit())
2324 printk(KERN_NOTICE "%s: unexpected"
2325 " checksum status\n",
2326 dev->name);
2327 break;
2328 }
2329
2330 /* Both checksum counters are programmed to start at
2331 * the same offset, so unless there is a problem they
2332 * should match. This failure is an early indication that
2333 * hardware receive checksumming won't work.
2334 */
2335 if (likely(status >> 16 == (status & 0xffff))) {
2336 skb = sky2->rx_ring[sky2->rx_next].skb;
2337 skb->ip_summed = CHECKSUM_COMPLETE;
2338 skb->csum = status & 0xffff;
2339 } else {
2340 printk(KERN_NOTICE PFX "%s: hardware receive "
2341 "checksum problem (status = %#x)\n",
2342 dev->name, status);
2343 sky2->rx_csum = 0;
2344 sky2_write32(sky2->hw,
2345 Q_ADDR(rxqaddr[port], Q_CSR),
2346 BMU_DIS_RX_CHKSUM);
2347 }
2348 break;
2349
2350 case OP_TXINDEXLE:
2351 /* TX index reports status for both ports */
2352 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2353 sky2_tx_done(hw->dev[0], status & 0xfff);
2354 if (hw->dev[1])
2355 sky2_tx_done(hw->dev[1],
2356 ((status >> 24) & 0xff)
2357 | (u16)(length & 0xf) << 8);
2358 break;
2359
2360 default:
2361 if (net_ratelimit())
2362 printk(KERN_WARNING PFX
2363 "unknown status opcode 0x%x\n", le->opcode);
2364 }
2365 } while (hw->st_idx != idx);
2366
2367 /* Fully processed status ring so clear irq */
2368 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2369
2370 exit_loop:
2371 if (rx[0])
2372 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2373
2374 if (rx[1])
2375 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2376
2377 return work_done;
2378 }
2379
2380 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2381 {
2382 struct net_device *dev = hw->dev[port];
2383
2384 if (net_ratelimit())
2385 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2386 dev->name, status);
2387
2388 if (status & Y2_IS_PAR_RD1) {
2389 if (net_ratelimit())
2390 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2391 dev->name);
2392 /* Clear IRQ */
2393 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2394 }
2395
2396 if (status & Y2_IS_PAR_WR1) {
2397 if (net_ratelimit())
2398 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2399 dev->name);
2400
2401 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2402 }
2403
2404 if (status & Y2_IS_PAR_MAC1) {
2405 if (net_ratelimit())
2406 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2407 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2408 }
2409
2410 if (status & Y2_IS_PAR_RX1) {
2411 if (net_ratelimit())
2412 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2413 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2414 }
2415
2416 if (status & Y2_IS_TCP_TXA1) {
2417 if (net_ratelimit())
2418 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2419 dev->name);
2420 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2421 }
2422 }
2423
2424 static void sky2_hw_intr(struct sky2_hw *hw)
2425 {
2426 struct pci_dev *pdev = hw->pdev;
2427 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2428 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2429
2430 status &= hwmsk;
2431
2432 if (status & Y2_IS_TIST_OV)
2433 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2434
2435 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2436 u16 pci_err;
2437
2438 pci_read_config_word(pdev, PCI_STATUS, &pci_err);
2439 if (net_ratelimit())
2440 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2441 pci_err);
2442
2443 pci_write_config_word(pdev, PCI_STATUS,
2444 pci_err | PCI_STATUS_ERROR_BITS);
2445 }
2446
2447 if (status & Y2_IS_PCI_EXP) {
2448 /* PCI-Express uncorrectable Error occurred */
2449 int pos = pci_find_aer_capability(hw->pdev);
2450 u32 err;
2451
2452 pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_STATUS, &err);
2453 if (net_ratelimit())
2454 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2455 pci_cleanup_aer_uncorrect_error_status(pdev);
2456 }
2457
2458 if (status & Y2_HWE_L1_MASK)
2459 sky2_hw_error(hw, 0, status);
2460 status >>= 8;
2461 if (status & Y2_HWE_L1_MASK)
2462 sky2_hw_error(hw, 1, status);
2463 }
2464
2465 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2466 {
2467 struct net_device *dev = hw->dev[port];
2468 struct sky2_port *sky2 = netdev_priv(dev);
2469 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2470
2471 if (netif_msg_intr(sky2))
2472 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2473 dev->name, status);
2474
2475 if (status & GM_IS_RX_CO_OV)
2476 gma_read16(hw, port, GM_RX_IRQ_SRC);
2477
2478 if (status & GM_IS_TX_CO_OV)
2479 gma_read16(hw, port, GM_TX_IRQ_SRC);
2480
2481 if (status & GM_IS_RX_FF_OR) {
2482 ++sky2->net_stats.rx_fifo_errors;
2483 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2484 }
2485
2486 if (status & GM_IS_TX_FF_UR) {
2487 ++sky2->net_stats.tx_fifo_errors;
2488 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2489 }
2490 }
2491
2492 /* This should never happen it is a bug. */
2493 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2494 u16 q, unsigned ring_size)
2495 {
2496 struct net_device *dev = hw->dev[port];
2497 struct sky2_port *sky2 = netdev_priv(dev);
2498 unsigned idx;
2499 const u64 *le = (q == Q_R1 || q == Q_R2)
2500 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2501
2502 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2503 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2504 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2505 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2506
2507 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2508 }
2509
2510 static int sky2_rx_hung(struct net_device *dev)
2511 {
2512 struct sky2_port *sky2 = netdev_priv(dev);
2513 struct sky2_hw *hw = sky2->hw;
2514 unsigned port = sky2->port;
2515 unsigned rxq = rxqaddr[port];
2516 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2517 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2518 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2519 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2520
2521 /* If idle and MAC or PCI is stuck */
2522 if (sky2->check.last == dev->last_rx &&
2523 ((mac_rp == sky2->check.mac_rp &&
2524 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2525 /* Check if the PCI RX hang */
2526 (fifo_rp == sky2->check.fifo_rp &&
2527 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2528 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2529 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2530 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2531 return 1;
2532 } else {
2533 sky2->check.last = dev->last_rx;
2534 sky2->check.mac_rp = mac_rp;
2535 sky2->check.mac_lev = mac_lev;
2536 sky2->check.fifo_rp = fifo_rp;
2537 sky2->check.fifo_lev = fifo_lev;
2538 return 0;
2539 }
2540 }
2541
2542 static void sky2_watchdog(unsigned long arg)
2543 {
2544 struct sky2_hw *hw = (struct sky2_hw *) arg;
2545
2546 /* Check for lost IRQ once a second */
2547 if (sky2_read32(hw, B0_ISRC)) {
2548 napi_schedule(&hw->napi);
2549 } else {
2550 int i, active = 0;
2551
2552 for (i = 0; i < hw->ports; i++) {
2553 struct net_device *dev = hw->dev[i];
2554 if (!netif_running(dev))
2555 continue;
2556 ++active;
2557
2558 /* For chips with Rx FIFO, check if stuck */
2559 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2560 sky2_rx_hung(dev)) {
2561 pr_info(PFX "%s: receiver hang detected\n",
2562 dev->name);
2563 schedule_work(&hw->restart_work);
2564 return;
2565 }
2566 }
2567
2568 if (active == 0)
2569 return;
2570 }
2571
2572 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2573 }
2574
2575 /* Hardware/software error handling */
2576 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2577 {
2578 if (net_ratelimit())
2579 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2580
2581 if (status & Y2_IS_HW_ERR)
2582 sky2_hw_intr(hw);
2583
2584 if (status & Y2_IS_IRQ_MAC1)
2585 sky2_mac_intr(hw, 0);
2586
2587 if (status & Y2_IS_IRQ_MAC2)
2588 sky2_mac_intr(hw, 1);
2589
2590 if (status & Y2_IS_CHK_RX1)
2591 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2592
2593 if (status & Y2_IS_CHK_RX2)
2594 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2595
2596 if (status & Y2_IS_CHK_TXA1)
2597 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2598
2599 if (status & Y2_IS_CHK_TXA2)
2600 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2601 }
2602
2603 static int sky2_poll(struct napi_struct *napi, int work_limit)
2604 {
2605 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2606 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2607 int work_done = 0;
2608 u16 idx;
2609
2610 if (unlikely(status & Y2_IS_ERROR))
2611 sky2_err_intr(hw, status);
2612
2613 if (status & Y2_IS_IRQ_PHY1)
2614 sky2_phy_intr(hw, 0);
2615
2616 if (status & Y2_IS_IRQ_PHY2)
2617 sky2_phy_intr(hw, 1);
2618
2619 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2620 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2621
2622 if (work_done >= work_limit)
2623 goto done;
2624 }
2625
2626 /* Bug/Errata workaround?
2627 * Need to kick the TX irq moderation timer.
2628 */
2629 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2630 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2631 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2632 }
2633 napi_complete(napi);
2634 sky2_read32(hw, B0_Y2_SP_LISR);
2635 done:
2636
2637 return work_done;
2638 }
2639
2640 static irqreturn_t sky2_intr(int irq, void *dev_id)
2641 {
2642 struct sky2_hw *hw = dev_id;
2643 u32 status;
2644
2645 /* Reading this mask interrupts as side effect */
2646 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2647 if (status == 0 || status == ~0)
2648 return IRQ_NONE;
2649
2650 prefetch(&hw->st_le[hw->st_idx]);
2651
2652 napi_schedule(&hw->napi);
2653
2654 return IRQ_HANDLED;
2655 }
2656
2657 #ifdef CONFIG_NET_POLL_CONTROLLER
2658 static void sky2_netpoll(struct net_device *dev)
2659 {
2660 struct sky2_port *sky2 = netdev_priv(dev);
2661
2662 napi_schedule(&sky2->hw->napi);
2663 }
2664 #endif
2665
2666 /* Chip internal frequency for clock calculations */
2667 static u32 sky2_mhz(const struct sky2_hw *hw)
2668 {
2669 switch (hw->chip_id) {
2670 case CHIP_ID_YUKON_EC:
2671 case CHIP_ID_YUKON_EC_U:
2672 case CHIP_ID_YUKON_EX:
2673 return 125;
2674
2675 case CHIP_ID_YUKON_FE:
2676 return 100;
2677
2678 case CHIP_ID_YUKON_FE_P:
2679 return 50;
2680
2681 case CHIP_ID_YUKON_XL:
2682 return 156;
2683
2684 default:
2685 BUG();
2686 }
2687 }
2688
2689 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2690 {
2691 return sky2_mhz(hw) * us;
2692 }
2693
2694 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2695 {
2696 return clk / sky2_mhz(hw);
2697 }
2698
2699
2700 static int __devinit sky2_init(struct sky2_hw *hw)
2701 {
2702 int rc;
2703 u8 t8;
2704
2705 /* Enable all clocks and check for bad PCI access */
2706 rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
2707 if (rc)
2708 return rc;
2709
2710 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2711
2712 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2713 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2714
2715 switch(hw->chip_id) {
2716 case CHIP_ID_YUKON_XL:
2717 hw->flags = SKY2_HW_GIGABIT
2718 | SKY2_HW_NEWER_PHY;
2719 if (hw->chip_rev < 3)
2720 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2721
2722 break;
2723
2724 case CHIP_ID_YUKON_EC_U:
2725 hw->flags = SKY2_HW_GIGABIT
2726 | SKY2_HW_NEWER_PHY
2727 | SKY2_HW_ADV_POWER_CTL;
2728 break;
2729
2730 case CHIP_ID_YUKON_EX:
2731 hw->flags = SKY2_HW_GIGABIT
2732 | SKY2_HW_NEWER_PHY
2733 | SKY2_HW_NEW_LE
2734 | SKY2_HW_ADV_POWER_CTL;
2735
2736 /* New transmit checksum */
2737 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2738 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2739 break;
2740
2741 case CHIP_ID_YUKON_EC:
2742 /* This rev is really old, and requires untested workarounds */
2743 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2744 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2745 return -EOPNOTSUPP;
2746 }
2747 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2748 break;
2749
2750 case CHIP_ID_YUKON_FE:
2751 break;
2752
2753 case CHIP_ID_YUKON_FE_P:
2754 hw->flags = SKY2_HW_NEWER_PHY
2755 | SKY2_HW_NEW_LE
2756 | SKY2_HW_AUTO_TX_SUM
2757 | SKY2_HW_ADV_POWER_CTL;
2758 break;
2759 default:
2760 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2761 hw->chip_id);
2762 return -EOPNOTSUPP;
2763 }
2764
2765 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2766 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2767 hw->flags |= SKY2_HW_FIBRE_PHY;
2768
2769
2770 hw->ports = 1;
2771 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2772 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2773 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2774 ++hw->ports;
2775 }
2776
2777 return 0;
2778 }
2779
2780 static void sky2_reset(struct sky2_hw *hw)
2781 {
2782 struct pci_dev *pdev = hw->pdev;
2783 u16 status;
2784 int i, cap;
2785 u32 hwe_mask = Y2_HWE_ALL_MASK;
2786
2787 /* disable ASF */
2788 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2789 status = sky2_read16(hw, HCU_CCSR);
2790 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2791 HCU_CCSR_UC_STATE_MSK);
2792 sky2_write16(hw, HCU_CCSR, status);
2793 } else
2794 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2795 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2796
2797 /* do a SW reset */
2798 sky2_write8(hw, B0_CTST, CS_RST_SET);
2799 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2800
2801 /* clear PCI errors, if any */
2802 pci_read_config_word(pdev, PCI_STATUS, &status);
2803 status |= PCI_STATUS_ERROR_BITS;
2804 pci_write_config_word(pdev, PCI_STATUS, status);
2805
2806 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2807
2808 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2809 if (cap) {
2810 /* Check for advanced error reporting */
2811 pci_cleanup_aer_uncorrect_error_status(pdev);
2812 pci_cleanup_aer_correct_error_status(pdev);
2813
2814 /* If error bit is stuck on ignore it */
2815 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2816 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2817
2818 else if (pci_enable_pcie_error_reporting(pdev))
2819 hwe_mask |= Y2_IS_PCI_EXP;
2820 }
2821
2822 sky2_power_on(hw);
2823
2824 for (i = 0; i < hw->ports; i++) {
2825 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2826 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2827
2828 if (hw->chip_id == CHIP_ID_YUKON_EX)
2829 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2830 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2831 | GMC_BYP_RETR_ON);
2832 }
2833
2834 /* Clear I2C IRQ noise */
2835 sky2_write32(hw, B2_I2C_IRQ, 1);
2836
2837 /* turn off hardware timer (unused) */
2838 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2839 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2840
2841 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2842
2843 /* Turn off descriptor polling */
2844 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2845
2846 /* Turn off receive timestamp */
2847 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2848 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2849
2850 /* enable the Tx Arbiters */
2851 for (i = 0; i < hw->ports; i++)
2852 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2853
2854 /* Initialize ram interface */
2855 for (i = 0; i < hw->ports; i++) {
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2857
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2867 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2868 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2869 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2870 }
2871
2872 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2873
2874 for (i = 0; i < hw->ports; i++)
2875 sky2_gmac_reset(hw, i);
2876
2877 memset(hw->st_le, 0, STATUS_LE_BYTES);
2878 hw->st_idx = 0;
2879
2880 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2881 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2882
2883 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2884 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2885
2886 /* Set the list last index */
2887 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2888
2889 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2890 sky2_write8(hw, STAT_FIFO_WM, 16);
2891
2892 /* set Status-FIFO ISR watermark */
2893 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2894 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2895 else
2896 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2897
2898 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2899 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2900 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2901
2902 /* enable status unit */
2903 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2904
2905 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2906 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2907 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2908 }
2909
2910 static void sky2_restart(struct work_struct *work)
2911 {
2912 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2913 struct net_device *dev;
2914 int i, err;
2915
2916 rtnl_lock();
2917 sky2_write32(hw, B0_IMSK, 0);
2918 sky2_read32(hw, B0_IMSK);
2919
2920 for (i = 0; i < hw->ports; i++) {
2921 dev = hw->dev[i];
2922 if (netif_running(dev))
2923 sky2_down(dev);
2924 }
2925
2926 sky2_reset(hw);
2927 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2928
2929 for (i = 0; i < hw->ports; i++) {
2930 dev = hw->dev[i];
2931 if (netif_running(dev)) {
2932 err = sky2_up(dev);
2933 if (err) {
2934 printk(KERN_INFO PFX "%s: could not restart %d\n",
2935 dev->name, err);
2936 dev_close(dev);
2937 }
2938 }
2939 }
2940
2941 rtnl_unlock();
2942 }
2943
2944 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2945 {
2946 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2947 }
2948
2949 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2950 {
2951 const struct sky2_port *sky2 = netdev_priv(dev);
2952
2953 wol->supported = sky2_wol_supported(sky2->hw);
2954 wol->wolopts = sky2->wol;
2955 }
2956
2957 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2958 {
2959 struct sky2_port *sky2 = netdev_priv(dev);
2960 struct sky2_hw *hw = sky2->hw;
2961
2962 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2963 return -EOPNOTSUPP;
2964
2965 sky2->wol = wol->wolopts;
2966
2967 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2968 hw->chip_id == CHIP_ID_YUKON_EX ||
2969 hw->chip_id == CHIP_ID_YUKON_FE_P)
2970 sky2_write32(hw, B0_CTST, sky2->wol
2971 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2972
2973 if (!netif_running(dev))
2974 sky2_wol_init(sky2);
2975 return 0;
2976 }
2977
2978 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2979 {
2980 if (sky2_is_copper(hw)) {
2981 u32 modes = SUPPORTED_10baseT_Half
2982 | SUPPORTED_10baseT_Full
2983 | SUPPORTED_100baseT_Half
2984 | SUPPORTED_100baseT_Full
2985 | SUPPORTED_Autoneg | SUPPORTED_TP;
2986
2987 if (hw->flags & SKY2_HW_GIGABIT)
2988 modes |= SUPPORTED_1000baseT_Half
2989 | SUPPORTED_1000baseT_Full;
2990 return modes;
2991 } else
2992 return SUPPORTED_1000baseT_Half
2993 | SUPPORTED_1000baseT_Full
2994 | SUPPORTED_Autoneg
2995 | SUPPORTED_FIBRE;
2996 }
2997
2998 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2999 {
3000 struct sky2_port *sky2 = netdev_priv(dev);
3001 struct sky2_hw *hw = sky2->hw;
3002
3003 ecmd->transceiver = XCVR_INTERNAL;
3004 ecmd->supported = sky2_supported_modes(hw);
3005 ecmd->phy_address = PHY_ADDR_MARV;
3006 if (sky2_is_copper(hw)) {
3007 ecmd->port = PORT_TP;
3008 ecmd->speed = sky2->speed;
3009 } else {
3010 ecmd->speed = SPEED_1000;
3011 ecmd->port = PORT_FIBRE;
3012 }
3013
3014 ecmd->advertising = sky2->advertising;
3015 ecmd->autoneg = sky2->autoneg;
3016 ecmd->duplex = sky2->duplex;
3017 return 0;
3018 }
3019
3020 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3021 {
3022 struct sky2_port *sky2 = netdev_priv(dev);
3023 const struct sky2_hw *hw = sky2->hw;
3024 u32 supported = sky2_supported_modes(hw);
3025
3026 if (ecmd->autoneg == AUTONEG_ENABLE) {
3027 ecmd->advertising = supported;
3028 sky2->duplex = -1;
3029 sky2->speed = -1;
3030 } else {
3031 u32 setting;
3032
3033 switch (ecmd->speed) {
3034 case SPEED_1000:
3035 if (ecmd->duplex == DUPLEX_FULL)
3036 setting = SUPPORTED_1000baseT_Full;
3037 else if (ecmd->duplex == DUPLEX_HALF)
3038 setting = SUPPORTED_1000baseT_Half;
3039 else
3040 return -EINVAL;
3041 break;
3042 case SPEED_100:
3043 if (ecmd->duplex == DUPLEX_FULL)
3044 setting = SUPPORTED_100baseT_Full;
3045 else if (ecmd->duplex == DUPLEX_HALF)
3046 setting = SUPPORTED_100baseT_Half;
3047 else
3048 return -EINVAL;
3049 break;
3050
3051 case SPEED_10:
3052 if (ecmd->duplex == DUPLEX_FULL)
3053 setting = SUPPORTED_10baseT_Full;
3054 else if (ecmd->duplex == DUPLEX_HALF)
3055 setting = SUPPORTED_10baseT_Half;
3056 else
3057 return -EINVAL;
3058 break;
3059 default:
3060 return -EINVAL;
3061 }
3062
3063 if ((setting & supported) == 0)
3064 return -EINVAL;
3065
3066 sky2->speed = ecmd->speed;
3067 sky2->duplex = ecmd->duplex;
3068 }
3069
3070 sky2->autoneg = ecmd->autoneg;
3071 sky2->advertising = ecmd->advertising;
3072
3073 if (netif_running(dev)) {
3074 sky2_phy_reinit(sky2);
3075 sky2_set_multicast(dev);
3076 }
3077
3078 return 0;
3079 }
3080
3081 static void sky2_get_drvinfo(struct net_device *dev,
3082 struct ethtool_drvinfo *info)
3083 {
3084 struct sky2_port *sky2 = netdev_priv(dev);
3085
3086 strcpy(info->driver, DRV_NAME);
3087 strcpy(info->version, DRV_VERSION);
3088 strcpy(info->fw_version, "N/A");
3089 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3090 }
3091
3092 static const struct sky2_stat {
3093 char name[ETH_GSTRING_LEN];
3094 u16 offset;
3095 } sky2_stats[] = {
3096 { "tx_bytes", GM_TXO_OK_HI },
3097 { "rx_bytes", GM_RXO_OK_HI },
3098 { "tx_broadcast", GM_TXF_BC_OK },
3099 { "rx_broadcast", GM_RXF_BC_OK },
3100 { "tx_multicast", GM_TXF_MC_OK },
3101 { "rx_multicast", GM_RXF_MC_OK },
3102 { "tx_unicast", GM_TXF_UC_OK },
3103 { "rx_unicast", GM_RXF_UC_OK },
3104 { "tx_mac_pause", GM_TXF_MPAUSE },
3105 { "rx_mac_pause", GM_RXF_MPAUSE },
3106 { "collisions", GM_TXF_COL },
3107 { "late_collision",GM_TXF_LAT_COL },
3108 { "aborted", GM_TXF_ABO_COL },
3109 { "single_collisions", GM_TXF_SNG_COL },
3110 { "multi_collisions", GM_TXF_MUL_COL },
3111
3112 { "rx_short", GM_RXF_SHT },
3113 { "rx_runt", GM_RXE_FRAG },
3114 { "rx_64_byte_packets", GM_RXF_64B },
3115 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3116 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3117 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3118 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3119 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3120 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3121 { "rx_too_long", GM_RXF_LNG_ERR },
3122 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3123 { "rx_jabber", GM_RXF_JAB_PKT },
3124 { "rx_fcs_error", GM_RXF_FCS_ERR },
3125
3126 { "tx_64_byte_packets", GM_TXF_64B },
3127 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3128 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3129 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3130 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3131 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3132 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3133 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3134 };
3135
3136 static u32 sky2_get_rx_csum(struct net_device *dev)
3137 {
3138 struct sky2_port *sky2 = netdev_priv(dev);
3139
3140 return sky2->rx_csum;
3141 }
3142
3143 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3144 {
3145 struct sky2_port *sky2 = netdev_priv(dev);
3146
3147 sky2->rx_csum = data;
3148
3149 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3150 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3151
3152 return 0;
3153 }
3154
3155 static u32 sky2_get_msglevel(struct net_device *netdev)
3156 {
3157 struct sky2_port *sky2 = netdev_priv(netdev);
3158 return sky2->msg_enable;
3159 }
3160
3161 static int sky2_nway_reset(struct net_device *dev)
3162 {
3163 struct sky2_port *sky2 = netdev_priv(dev);
3164
3165 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3166 return -EINVAL;
3167
3168 sky2_phy_reinit(sky2);
3169 sky2_set_multicast(dev);
3170
3171 return 0;
3172 }
3173
3174 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3175 {
3176 struct sky2_hw *hw = sky2->hw;
3177 unsigned port = sky2->port;
3178 int i;
3179
3180 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3181 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3182 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3183 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3184
3185 for (i = 2; i < count; i++)
3186 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3187 }
3188
3189 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3190 {
3191 struct sky2_port *sky2 = netdev_priv(netdev);
3192 sky2->msg_enable = value;
3193 }
3194
3195 static int sky2_get_sset_count(struct net_device *dev, int sset)
3196 {
3197 switch (sset) {
3198 case ETH_SS_STATS:
3199 return ARRAY_SIZE(sky2_stats);
3200 default:
3201 return -EOPNOTSUPP;
3202 }
3203 }
3204
3205 static void sky2_get_ethtool_stats(struct net_device *dev,
3206 struct ethtool_stats *stats, u64 * data)
3207 {
3208 struct sky2_port *sky2 = netdev_priv(dev);
3209
3210 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3211 }
3212
3213 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3214 {
3215 int i;
3216
3217 switch (stringset) {
3218 case ETH_SS_STATS:
3219 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3220 memcpy(data + i * ETH_GSTRING_LEN,
3221 sky2_stats[i].name, ETH_GSTRING_LEN);
3222 break;
3223 }
3224 }
3225
3226 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3227 {
3228 struct sky2_port *sky2 = netdev_priv(dev);
3229 return &sky2->net_stats;
3230 }
3231
3232 static int sky2_set_mac_address(struct net_device *dev, void *p)
3233 {
3234 struct sky2_port *sky2 = netdev_priv(dev);
3235 struct sky2_hw *hw = sky2->hw;
3236 unsigned port = sky2->port;
3237 const struct sockaddr *addr = p;
3238
3239 if (!is_valid_ether_addr(addr->sa_data))
3240 return -EADDRNOTAVAIL;
3241
3242 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3243 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3244 dev->dev_addr, ETH_ALEN);
3245 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3246 dev->dev_addr, ETH_ALEN);
3247
3248 /* virtual address for data */
3249 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3250
3251 /* physical address: used for pause frames */
3252 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3253
3254 return 0;
3255 }
3256
3257 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3258 {
3259 u32 bit;
3260
3261 bit = ether_crc(ETH_ALEN, addr) & 63;
3262 filter[bit >> 3] |= 1 << (bit & 7);
3263 }
3264
3265 static void sky2_set_multicast(struct net_device *dev)
3266 {
3267 struct sky2_port *sky2 = netdev_priv(dev);
3268 struct sky2_hw *hw = sky2->hw;
3269 unsigned port = sky2->port;
3270 struct dev_mc_list *list = dev->mc_list;
3271 u16 reg;
3272 u8 filter[8];
3273 int rx_pause;
3274 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3275
3276 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3277 memset(filter, 0, sizeof(filter));
3278
3279 reg = gma_read16(hw, port, GM_RX_CTRL);
3280 reg |= GM_RXCR_UCF_ENA;
3281
3282 if (dev->flags & IFF_PROMISC) /* promiscuous */
3283 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3284 else if (dev->flags & IFF_ALLMULTI)
3285 memset(filter, 0xff, sizeof(filter));
3286 else if (dev->mc_count == 0 && !rx_pause)
3287 reg &= ~GM_RXCR_MCF_ENA;
3288 else {
3289 int i;
3290 reg |= GM_RXCR_MCF_ENA;
3291
3292 if (rx_pause)
3293 sky2_add_filter(filter, pause_mc_addr);
3294
3295 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3296 sky2_add_filter(filter, list->dmi_addr);
3297 }
3298
3299 gma_write16(hw, port, GM_MC_ADDR_H1,
3300 (u16) filter[0] | ((u16) filter[1] << 8));
3301 gma_write16(hw, port, GM_MC_ADDR_H2,
3302 (u16) filter[2] | ((u16) filter[3] << 8));
3303 gma_write16(hw, port, GM_MC_ADDR_H3,
3304 (u16) filter[4] | ((u16) filter[5] << 8));
3305 gma_write16(hw, port, GM_MC_ADDR_H4,
3306 (u16) filter[6] | ((u16) filter[7] << 8));
3307
3308 gma_write16(hw, port, GM_RX_CTRL, reg);
3309 }
3310
3311 /* Can have one global because blinking is controlled by
3312 * ethtool and that is always under RTNL mutex
3313 */
3314 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3315 {
3316 u16 pg;
3317
3318 switch (hw->chip_id) {
3319 case CHIP_ID_YUKON_XL:
3320 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3321 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3322 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3323 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3324 PHY_M_LEDC_INIT_CTRL(7) |
3325 PHY_M_LEDC_STA1_CTRL(7) |
3326 PHY_M_LEDC_STA0_CTRL(7))
3327 : 0);
3328
3329 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3330 break;
3331
3332 default:
3333 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3334 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3335 on ? PHY_M_LED_ALL : 0);
3336 }
3337 }
3338
3339 /* blink LED's for finding board */
3340 static int sky2_phys_id(struct net_device *dev, u32 data)
3341 {
3342 struct sky2_port *sky2 = netdev_priv(dev);
3343 struct sky2_hw *hw = sky2->hw;
3344 unsigned port = sky2->port;
3345 u16 ledctrl, ledover = 0;
3346 long ms;
3347 int interrupted;
3348 int onoff = 1;
3349
3350 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3351 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3352 else
3353 ms = data * 1000;
3354
3355 /* save initial values */
3356 spin_lock_bh(&sky2->phy_lock);
3357 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3358 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3360 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3361 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3362 } else {
3363 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3364 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3365 }
3366
3367 interrupted = 0;
3368 while (!interrupted && ms > 0) {
3369 sky2_led(hw, port, onoff);
3370 onoff = !onoff;
3371
3372 spin_unlock_bh(&sky2->phy_lock);
3373 interrupted = msleep_interruptible(250);
3374 spin_lock_bh(&sky2->phy_lock);
3375
3376 ms -= 250;
3377 }
3378
3379 /* resume regularly scheduled programming */
3380 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3381 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3383 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3384 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3385 } else {
3386 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3387 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3388 }
3389 spin_unlock_bh(&sky2->phy_lock);
3390
3391 return 0;
3392 }
3393
3394 static void sky2_get_pauseparam(struct net_device *dev,
3395 struct ethtool_pauseparam *ecmd)
3396 {
3397 struct sky2_port *sky2 = netdev_priv(dev);
3398
3399 switch (sky2->flow_mode) {
3400 case FC_NONE:
3401 ecmd->tx_pause = ecmd->rx_pause = 0;
3402 break;
3403 case FC_TX:
3404 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3405 break;
3406 case FC_RX:
3407 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3408 break;
3409 case FC_BOTH:
3410 ecmd->tx_pause = ecmd->rx_pause = 1;
3411 }
3412
3413 ecmd->autoneg = sky2->autoneg;
3414 }
3415
3416 static int sky2_set_pauseparam(struct net_device *dev,
3417 struct ethtool_pauseparam *ecmd)
3418 {
3419 struct sky2_port *sky2 = netdev_priv(dev);
3420
3421 sky2->autoneg = ecmd->autoneg;
3422 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3423
3424 if (netif_running(dev))
3425 sky2_phy_reinit(sky2);
3426
3427 return 0;
3428 }
3429
3430 static int sky2_get_coalesce(struct net_device *dev,
3431 struct ethtool_coalesce *ecmd)
3432 {
3433 struct sky2_port *sky2 = netdev_priv(dev);
3434 struct sky2_hw *hw = sky2->hw;
3435
3436 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3437 ecmd->tx_coalesce_usecs = 0;
3438 else {
3439 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3440 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3441 }
3442 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3443
3444 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3445 ecmd->rx_coalesce_usecs = 0;
3446 else {
3447 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3448 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3449 }
3450 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3451
3452 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3453 ecmd->rx_coalesce_usecs_irq = 0;
3454 else {
3455 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3456 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3457 }
3458
3459 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3460
3461 return 0;
3462 }
3463
3464 /* Note: this affect both ports */
3465 static int sky2_set_coalesce(struct net_device *dev,
3466 struct ethtool_coalesce *ecmd)
3467 {
3468 struct sky2_port *sky2 = netdev_priv(dev);
3469 struct sky2_hw *hw = sky2->hw;
3470 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3471
3472 if (ecmd->tx_coalesce_usecs > tmax ||
3473 ecmd->rx_coalesce_usecs > tmax ||
3474 ecmd->rx_coalesce_usecs_irq > tmax)
3475 return -EINVAL;
3476
3477 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3478 return -EINVAL;
3479 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3480 return -EINVAL;
3481 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3482 return -EINVAL;
3483
3484 if (ecmd->tx_coalesce_usecs == 0)
3485 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3486 else {
3487 sky2_write32(hw, STAT_TX_TIMER_INI,
3488 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3489 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3490 }
3491 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3492
3493 if (ecmd->rx_coalesce_usecs == 0)
3494 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3495 else {
3496 sky2_write32(hw, STAT_LEV_TIMER_INI,
3497 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3498 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3499 }
3500 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3501
3502 if (ecmd->rx_coalesce_usecs_irq == 0)
3503 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3504 else {
3505 sky2_write32(hw, STAT_ISR_TIMER_INI,
3506 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3507 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3508 }
3509 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3510 return 0;
3511 }
3512
3513 static void sky2_get_ringparam(struct net_device *dev,
3514 struct ethtool_ringparam *ering)
3515 {
3516 struct sky2_port *sky2 = netdev_priv(dev);
3517
3518 ering->rx_max_pending = RX_MAX_PENDING;
3519 ering->rx_mini_max_pending = 0;
3520 ering->rx_jumbo_max_pending = 0;
3521 ering->tx_max_pending = TX_RING_SIZE - 1;
3522
3523 ering->rx_pending = sky2->rx_pending;
3524 ering->rx_mini_pending = 0;
3525 ering->rx_jumbo_pending = 0;
3526 ering->tx_pending = sky2->tx_pending;
3527 }
3528
3529 static int sky2_set_ringparam(struct net_device *dev,
3530 struct ethtool_ringparam *ering)
3531 {
3532 struct sky2_port *sky2 = netdev_priv(dev);
3533 int err = 0;
3534
3535 if (ering->rx_pending > RX_MAX_PENDING ||
3536 ering->rx_pending < 8 ||
3537 ering->tx_pending < MAX_SKB_TX_LE ||
3538 ering->tx_pending > TX_RING_SIZE - 1)
3539 return -EINVAL;
3540
3541 if (netif_running(dev))
3542 sky2_down(dev);
3543
3544 sky2->rx_pending = ering->rx_pending;
3545 sky2->tx_pending = ering->tx_pending;
3546
3547 if (netif_running(dev)) {
3548 err = sky2_up(dev);
3549 if (err)
3550 dev_close(dev);
3551 else
3552 sky2_set_multicast(dev);
3553 }
3554
3555 return err;
3556 }
3557
3558 static int sky2_get_regs_len(struct net_device *dev)
3559 {
3560 return 0x4000;
3561 }
3562
3563 /*
3564 * Returns copy of control register region
3565 * Note: ethtool_get_regs always provides full size (16k) buffer
3566 */
3567 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3568 void *p)
3569 {
3570 const struct sky2_port *sky2 = netdev_priv(dev);
3571 const void __iomem *io = sky2->hw->regs;
3572 unsigned int b;
3573
3574 regs->version = 1;
3575
3576 for (b = 0; b < 128; b++) {
3577 /* This complicated switch statement is to make sure and
3578 * only access regions that are unreserved.
3579 * Some blocks are only valid on dual port cards.
3580 * and block 3 has some special diagnostic registers that
3581 * are poison.
3582 */
3583 switch (b) {
3584 case 3:
3585 /* skip diagnostic ram region */
3586 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3587 break;
3588
3589 /* dual port cards only */
3590 case 5: /* Tx Arbiter 2 */
3591 case 9: /* RX2 */
3592 case 14 ... 15: /* TX2 */
3593 case 17: case 19: /* Ram Buffer 2 */
3594 case 22 ... 23: /* Tx Ram Buffer 2 */
3595 case 25: /* Rx MAC Fifo 1 */
3596 case 27: /* Tx MAC Fifo 2 */
3597 case 31: /* GPHY 2 */
3598 case 40 ... 47: /* Pattern Ram 2 */
3599 case 52: case 54: /* TCP Segmentation 2 */
3600 case 112 ... 116: /* GMAC 2 */
3601 if (sky2->hw->ports == 1)
3602 goto reserved;
3603 /* fall through */
3604 case 0: /* Control */
3605 case 2: /* Mac address */
3606 case 4: /* Tx Arbiter 1 */
3607 case 7: /* PCI express reg */
3608 case 8: /* RX1 */
3609 case 12 ... 13: /* TX1 */
3610 case 16: case 18:/* Rx Ram Buffer 1 */
3611 case 20 ... 21: /* Tx Ram Buffer 1 */
3612 case 24: /* Rx MAC Fifo 1 */
3613 case 26: /* Tx MAC Fifo 1 */
3614 case 28 ... 29: /* Descriptor and status unit */
3615 case 30: /* GPHY 1*/
3616 case 32 ... 39: /* Pattern Ram 1 */
3617 case 48: case 50: /* TCP Segmentation 1 */
3618 case 56 ... 60: /* PCI space */
3619 case 80 ... 84: /* GMAC 1 */
3620 memcpy_fromio(p, io, 128);
3621 break;
3622 default:
3623 reserved:
3624 memset(p, 0, 128);
3625 }
3626
3627 p += 128;
3628 io += 128;
3629 }
3630 }
3631
3632 /* In order to do Jumbo packets on these chips, need to turn off the
3633 * transmit store/forward. Therefore checksum offload won't work.
3634 */
3635 static int no_tx_offload(struct net_device *dev)
3636 {
3637 const struct sky2_port *sky2 = netdev_priv(dev);
3638 const struct sky2_hw *hw = sky2->hw;
3639
3640 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3641 }
3642
3643 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3644 {
3645 if (data && no_tx_offload(dev))
3646 return -EINVAL;
3647
3648 return ethtool_op_set_tx_csum(dev, data);
3649 }
3650
3651
3652 static int sky2_set_tso(struct net_device *dev, u32 data)
3653 {
3654 if (data && no_tx_offload(dev))
3655 return -EINVAL;
3656
3657 return ethtool_op_set_tso(dev, data);
3658 }
3659
3660 static int sky2_get_eeprom_len(struct net_device *dev)
3661 {
3662 struct sky2_port *sky2 = netdev_priv(dev);
3663 u16 reg2;
3664
3665 pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, &reg2);
3666 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3667 }
3668
3669 static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
3670 {
3671 u32 val;
3672
3673 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
3674
3675 do {
3676 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3677 } while (!(offset & PCI_VPD_ADDR_F));
3678
3679 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
3680 return val;
3681 }
3682
3683 static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
3684 {
3685 pci_write_config_word(pdev, cap + PCI_VPD_DATA, val);
3686 pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3687 do {
3688 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3689 } while (offset & PCI_VPD_ADDR_F);
3690 }
3691
3692 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3693 u8 *data)
3694 {
3695 struct sky2_port *sky2 = netdev_priv(dev);
3696 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3697 int length = eeprom->len;
3698 u16 offset = eeprom->offset;
3699
3700 if (!cap)
3701 return -EINVAL;
3702
3703 eeprom->magic = SKY2_EEPROM_MAGIC;
3704
3705 while (length > 0) {
3706 u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3707 int n = min_t(int, length, sizeof(val));
3708
3709 memcpy(data, &val, n);
3710 length -= n;
3711 data += n;
3712 offset += n;
3713 }
3714 return 0;
3715 }
3716
3717 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3718 u8 *data)
3719 {
3720 struct sky2_port *sky2 = netdev_priv(dev);
3721 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3722 int length = eeprom->len;
3723 u16 offset = eeprom->offset;
3724
3725 if (!cap)
3726 return -EINVAL;
3727
3728 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3729 return -EINVAL;
3730
3731 while (length > 0) {
3732 u32 val;
3733 int n = min_t(int, length, sizeof(val));
3734
3735 if (n < sizeof(val))
3736 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3737 memcpy(&val, data, n);
3738
3739 sky2_vpd_write(sky2->hw->pdev, cap, offset, val);
3740
3741 length -= n;
3742 data += n;
3743 offset += n;
3744 }
3745 return 0;
3746 }
3747
3748
3749 static const struct ethtool_ops sky2_ethtool_ops = {
3750 .get_settings = sky2_get_settings,
3751 .set_settings = sky2_set_settings,
3752 .get_drvinfo = sky2_get_drvinfo,
3753 .get_wol = sky2_get_wol,
3754 .set_wol = sky2_set_wol,
3755 .get_msglevel = sky2_get_msglevel,
3756 .set_msglevel = sky2_set_msglevel,
3757 .nway_reset = sky2_nway_reset,
3758 .get_regs_len = sky2_get_regs_len,
3759 .get_regs = sky2_get_regs,
3760 .get_link = ethtool_op_get_link,
3761 .get_eeprom_len = sky2_get_eeprom_len,
3762 .get_eeprom = sky2_get_eeprom,
3763 .set_eeprom = sky2_set_eeprom,
3764 .set_sg = ethtool_op_set_sg,
3765 .set_tx_csum = sky2_set_tx_csum,
3766 .set_tso = sky2_set_tso,
3767 .get_rx_csum = sky2_get_rx_csum,
3768 .set_rx_csum = sky2_set_rx_csum,
3769 .get_strings = sky2_get_strings,
3770 .get_coalesce = sky2_get_coalesce,
3771 .set_coalesce = sky2_set_coalesce,
3772 .get_ringparam = sky2_get_ringparam,
3773 .set_ringparam = sky2_set_ringparam,
3774 .get_pauseparam = sky2_get_pauseparam,
3775 .set_pauseparam = sky2_set_pauseparam,
3776 .phys_id = sky2_phys_id,
3777 .get_sset_count = sky2_get_sset_count,
3778 .get_ethtool_stats = sky2_get_ethtool_stats,
3779 };
3780
3781 #ifdef CONFIG_SKY2_DEBUG
3782
3783 static struct dentry *sky2_debug;
3784
3785 static int sky2_debug_show(struct seq_file *seq, void *v)
3786 {
3787 struct net_device *dev = seq->private;
3788 const struct sky2_port *sky2 = netdev_priv(dev);
3789 struct sky2_hw *hw = sky2->hw;
3790 unsigned port = sky2->port;
3791 unsigned idx, last;
3792 int sop;
3793
3794 if (!netif_running(dev))
3795 return -ENETDOWN;
3796
3797 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3798 sky2_read32(hw, B0_ISRC),
3799 sky2_read32(hw, B0_IMSK),
3800 sky2_read32(hw, B0_Y2_SP_ICR));
3801
3802 napi_disable(&hw->napi);
3803 last = sky2_read16(hw, STAT_PUT_IDX);
3804
3805 if (hw->st_idx == last)
3806 seq_puts(seq, "Status ring (empty)\n");
3807 else {
3808 seq_puts(seq, "Status ring\n");
3809 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3810 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3811 const struct sky2_status_le *le = hw->st_le + idx;
3812 seq_printf(seq, "[%d] %#x %d %#x\n",
3813 idx, le->opcode, le->length, le->status);
3814 }
3815 seq_puts(seq, "\n");
3816 }
3817
3818 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3819 sky2->tx_cons, sky2->tx_prod,
3820 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3821 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3822
3823 /* Dump contents of tx ring */
3824 sop = 1;
3825 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3826 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3827 const struct sky2_tx_le *le = sky2->tx_le + idx;
3828 u32 a = le32_to_cpu(le->addr);
3829
3830 if (sop)
3831 seq_printf(seq, "%u:", idx);
3832 sop = 0;
3833
3834 switch(le->opcode & ~HW_OWNER) {
3835 case OP_ADDR64:
3836 seq_printf(seq, " %#x:", a);
3837 break;
3838 case OP_LRGLEN:
3839 seq_printf(seq, " mtu=%d", a);
3840 break;
3841 case OP_VLAN:
3842 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3843 break;
3844 case OP_TCPLISW:
3845 seq_printf(seq, " csum=%#x", a);
3846 break;
3847 case OP_LARGESEND:
3848 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3849 break;
3850 case OP_PACKET:
3851 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3852 break;
3853 case OP_BUFFER:
3854 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3855 break;
3856 default:
3857 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3858 a, le16_to_cpu(le->length));
3859 }
3860
3861 if (le->ctrl & EOP) {
3862 seq_putc(seq, '\n');
3863 sop = 1;
3864 }
3865 }
3866
3867 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3868 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3869 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3870 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3871
3872 napi_enable(&hw->napi);
3873 return 0;
3874 }
3875
3876 static int sky2_debug_open(struct inode *inode, struct file *file)
3877 {
3878 return single_open(file, sky2_debug_show, inode->i_private);
3879 }
3880
3881 static const struct file_operations sky2_debug_fops = {
3882 .owner = THIS_MODULE,
3883 .open = sky2_debug_open,
3884 .read = seq_read,
3885 .llseek = seq_lseek,
3886 .release = single_release,
3887 };
3888
3889 /*
3890 * Use network device events to create/remove/rename
3891 * debugfs file entries
3892 */
3893 static int sky2_device_event(struct notifier_block *unused,
3894 unsigned long event, void *ptr)
3895 {
3896 struct net_device *dev = ptr;
3897 struct sky2_port *sky2 = netdev_priv(dev);
3898
3899 if (dev->open != sky2_up || !sky2_debug)
3900 return NOTIFY_DONE;
3901
3902 switch(event) {
3903 case NETDEV_CHANGENAME:
3904 if (sky2->debugfs) {
3905 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3906 sky2_debug, dev->name);
3907 }
3908 break;
3909
3910 case NETDEV_GOING_DOWN:
3911 if (sky2->debugfs) {
3912 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3913 dev->name);
3914 debugfs_remove(sky2->debugfs);
3915 sky2->debugfs = NULL;
3916 }
3917 break;
3918
3919 case NETDEV_UP:
3920 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3921 sky2_debug, dev,
3922 &sky2_debug_fops);
3923 if (IS_ERR(sky2->debugfs))
3924 sky2->debugfs = NULL;
3925 }
3926
3927 return NOTIFY_DONE;
3928 }
3929
3930 static struct notifier_block sky2_notifier = {
3931 .notifier_call = sky2_device_event,
3932 };
3933
3934
3935 static __init void sky2_debug_init(void)
3936 {
3937 struct dentry *ent;
3938
3939 ent = debugfs_create_dir("sky2", NULL);
3940 if (!ent || IS_ERR(ent))
3941 return;
3942
3943 sky2_debug = ent;
3944 register_netdevice_notifier(&sky2_notifier);
3945 }
3946
3947 static __exit void sky2_debug_cleanup(void)
3948 {
3949 if (sky2_debug) {
3950 unregister_netdevice_notifier(&sky2_notifier);
3951 debugfs_remove(sky2_debug);
3952 sky2_debug = NULL;
3953 }
3954 }
3955
3956 #else
3957 #define sky2_debug_init()
3958 #define sky2_debug_cleanup()
3959 #endif
3960
3961
3962 /* Initialize network device */
3963 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3964 unsigned port,
3965 int highmem, int wol)
3966 {
3967 struct sky2_port *sky2;
3968 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3969
3970 if (!dev) {
3971 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3972 return NULL;
3973 }
3974
3975 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3976 dev->irq = hw->pdev->irq;
3977 dev->open = sky2_up;
3978 dev->stop = sky2_down;
3979 dev->do_ioctl = sky2_ioctl;
3980 dev->hard_start_xmit = sky2_xmit_frame;
3981 dev->get_stats = sky2_get_stats;
3982 dev->set_multicast_list = sky2_set_multicast;
3983 dev->set_mac_address = sky2_set_mac_address;
3984 dev->change_mtu = sky2_change_mtu;
3985 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3986 dev->tx_timeout = sky2_tx_timeout;
3987 dev->watchdog_timeo = TX_WATCHDOG;
3988 #ifdef CONFIG_NET_POLL_CONTROLLER
3989 dev->poll_controller = sky2_netpoll;
3990 #endif
3991
3992 sky2 = netdev_priv(dev);
3993 sky2->netdev = dev;
3994 sky2->hw = hw;
3995 sky2->msg_enable = netif_msg_init(debug, default_msg);
3996
3997 /* Auto speed and flow control */
3998 sky2->autoneg = AUTONEG_ENABLE;
3999 sky2->flow_mode = FC_BOTH;
4000
4001 sky2->duplex = -1;
4002 sky2->speed = -1;
4003 sky2->advertising = sky2_supported_modes(hw);
4004 sky2->rx_csum = 1;
4005 sky2->wol = wol;
4006
4007 spin_lock_init(&sky2->phy_lock);
4008 sky2->tx_pending = TX_DEF_PENDING;
4009 sky2->rx_pending = RX_DEF_PENDING;
4010
4011 hw->dev[port] = dev;
4012
4013 sky2->port = port;
4014
4015 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4016 if (highmem)
4017 dev->features |= NETIF_F_HIGHDMA;
4018
4019 #ifdef SKY2_VLAN_TAG_USED
4020 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4021 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4022 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4023 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4024 dev->vlan_rx_register = sky2_vlan_rx_register;
4025 }
4026 #endif
4027
4028 /* read the mac address */
4029 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4030 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4031
4032 return dev;
4033 }
4034
4035 static void __devinit sky2_show_addr(struct net_device *dev)
4036 {
4037 const struct sky2_port *sky2 = netdev_priv(dev);
4038 DECLARE_MAC_BUF(mac);
4039
4040 if (netif_msg_probe(sky2))
4041 printk(KERN_INFO PFX "%s: addr %s\n",
4042 dev->name, print_mac(mac, dev->dev_addr));
4043 }
4044
4045 /* Handle software interrupt used during MSI test */
4046 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4047 {
4048 struct sky2_hw *hw = dev_id;
4049 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4050
4051 if (status == 0)
4052 return IRQ_NONE;
4053
4054 if (status & Y2_IS_IRQ_SW) {
4055 hw->flags |= SKY2_HW_USE_MSI;
4056 wake_up(&hw->msi_wait);
4057 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4058 }
4059 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4060
4061 return IRQ_HANDLED;
4062 }
4063
4064 /* Test interrupt path by forcing a a software IRQ */
4065 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4066 {
4067 struct pci_dev *pdev = hw->pdev;
4068 int err;
4069
4070 init_waitqueue_head (&hw->msi_wait);
4071
4072 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4073
4074 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4075 if (err) {
4076 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4077 return err;
4078 }
4079
4080 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4081 sky2_read8(hw, B0_CTST);
4082
4083 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4084
4085 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4086 /* MSI test failed, go back to INTx mode */
4087 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4088 "switching to INTx mode.\n");
4089
4090 err = -EOPNOTSUPP;
4091 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4092 }
4093
4094 sky2_write32(hw, B0_IMSK, 0);
4095 sky2_read32(hw, B0_IMSK);
4096
4097 free_irq(pdev->irq, hw);
4098
4099 return err;
4100 }
4101
4102 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4103 {
4104 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4105 u16 value;
4106
4107 if (!pm)
4108 return 0;
4109 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4110 return 0;
4111 return value & PCI_PM_CTRL_PME_ENABLE;
4112 }
4113
4114 static int __devinit sky2_probe(struct pci_dev *pdev,
4115 const struct pci_device_id *ent)
4116 {
4117 struct net_device *dev;
4118 struct sky2_hw *hw;
4119 int err, using_dac = 0, wol_default;
4120
4121 err = pci_enable_device(pdev);
4122 if (err) {
4123 dev_err(&pdev->dev, "cannot enable PCI device\n");
4124 goto err_out;
4125 }
4126
4127 err = pci_request_regions(pdev, DRV_NAME);
4128 if (err) {
4129 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4130 goto err_out_disable;
4131 }
4132
4133 pci_set_master(pdev);
4134
4135 if (sizeof(dma_addr_t) > sizeof(u32) &&
4136 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4137 using_dac = 1;
4138 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4139 if (err < 0) {
4140 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4141 "for consistent allocations\n");
4142 goto err_out_free_regions;
4143 }
4144 } else {
4145 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4146 if (err) {
4147 dev_err(&pdev->dev, "no usable DMA configuration\n");
4148 goto err_out_free_regions;
4149 }
4150 }
4151
4152 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4153
4154 err = -ENOMEM;
4155 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4156 if (!hw) {
4157 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4158 goto err_out_free_regions;
4159 }
4160
4161 hw->pdev = pdev;
4162
4163 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4164 if (!hw->regs) {
4165 dev_err(&pdev->dev, "cannot map device registers\n");
4166 goto err_out_free_hw;
4167 }
4168
4169 #ifdef __BIG_ENDIAN
4170 /* The sk98lin vendor driver uses hardware byte swapping but
4171 * this driver uses software swapping.
4172 */
4173 {
4174 u32 reg;
4175 pci_read_config_dword(pdev,PCI_DEV_REG2, &reg);
4176 reg &= ~PCI_REV_DESC;
4177 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4178 }
4179 #endif
4180
4181 /* ring for status responses */
4182 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4183 if (!hw->st_le)
4184 goto err_out_iounmap;
4185
4186 err = sky2_init(hw);
4187 if (err)
4188 goto err_out_iounmap;
4189
4190 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4191 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4192 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4193 hw->chip_id, hw->chip_rev);
4194
4195 sky2_reset(hw);
4196
4197 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4198 if (!dev) {
4199 err = -ENOMEM;
4200 goto err_out_free_pci;
4201 }
4202 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4203
4204 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4205 err = sky2_test_msi(hw);
4206 if (err == -EOPNOTSUPP)
4207 pci_disable_msi(pdev);
4208 else if (err)
4209 goto err_out_free_netdev;
4210 }
4211
4212 err = register_netdev(dev);
4213 if (err) {
4214 dev_err(&pdev->dev, "cannot register net device\n");
4215 goto err_out_free_netdev;
4216 }
4217
4218 err = request_irq(pdev->irq, sky2_intr,
4219 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4220 dev->name, hw);
4221 if (err) {
4222 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4223 goto err_out_unregister;
4224 }
4225 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4226
4227 sky2_show_addr(dev);
4228
4229 if (hw->ports > 1) {
4230 struct net_device *dev1;
4231
4232 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4233 if (!dev1)
4234 dev_warn(&pdev->dev, "allocation for second device failed\n");
4235 else if ((err = register_netdev(dev1))) {
4236 dev_warn(&pdev->dev,
4237 "register of second port failed (%d)\n", err);
4238 hw->dev[1] = NULL;
4239 free_netdev(dev1);
4240 } else
4241 sky2_show_addr(dev1);
4242 }
4243
4244 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4245 INIT_WORK(&hw->restart_work, sky2_restart);
4246
4247 pci_set_drvdata(pdev, hw);
4248
4249 return 0;
4250
4251 err_out_unregister:
4252 if (hw->flags & SKY2_HW_USE_MSI)
4253 pci_disable_msi(pdev);
4254 unregister_netdev(dev);
4255 err_out_free_netdev:
4256 free_netdev(dev);
4257 err_out_free_pci:
4258 sky2_write8(hw, B0_CTST, CS_RST_SET);
4259 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4260 err_out_iounmap:
4261 iounmap(hw->regs);
4262 err_out_free_hw:
4263 kfree(hw);
4264 err_out_free_regions:
4265 pci_release_regions(pdev);
4266 err_out_disable:
4267 pci_disable_device(pdev);
4268 err_out:
4269 pci_set_drvdata(pdev, NULL);
4270 return err;
4271 }
4272
4273 static void __devexit sky2_remove(struct pci_dev *pdev)
4274 {
4275 struct sky2_hw *hw = pci_get_drvdata(pdev);
4276 struct net_device *dev0, *dev1;
4277
4278 if (!hw)
4279 return;
4280
4281 del_timer_sync(&hw->watchdog_timer);
4282
4283 flush_scheduled_work();
4284
4285 sky2_write32(hw, B0_IMSK, 0);
4286 synchronize_irq(hw->pdev->irq);
4287
4288 dev0 = hw->dev[0];
4289 dev1 = hw->dev[1];
4290 if (dev1)
4291 unregister_netdev(dev1);
4292 unregister_netdev(dev0);
4293
4294 sky2_power_aux(hw);
4295
4296 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4297 sky2_write8(hw, B0_CTST, CS_RST_SET);
4298 sky2_read8(hw, B0_CTST);
4299
4300 free_irq(pdev->irq, hw);
4301 if (hw->flags & SKY2_HW_USE_MSI)
4302 pci_disable_msi(pdev);
4303 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4304 pci_release_regions(pdev);
4305 pci_disable_device(pdev);
4306
4307 if (dev1)
4308 free_netdev(dev1);
4309 free_netdev(dev0);
4310 iounmap(hw->regs);
4311 kfree(hw);
4312
4313 pci_set_drvdata(pdev, NULL);
4314 }
4315
4316 #ifdef CONFIG_PM
4317 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4318 {
4319 struct sky2_hw *hw = pci_get_drvdata(pdev);
4320 int i, wol = 0;
4321
4322 if (!hw)
4323 return 0;
4324
4325 for (i = 0; i < hw->ports; i++) {
4326 struct net_device *dev = hw->dev[i];
4327 struct sky2_port *sky2 = netdev_priv(dev);
4328
4329 if (netif_running(dev))
4330 sky2_down(dev);
4331
4332 if (sky2->wol)
4333 sky2_wol_init(sky2);
4334
4335 wol |= sky2->wol;
4336 }
4337
4338 sky2_write32(hw, B0_IMSK, 0);
4339 sky2_power_aux(hw);
4340
4341 pci_save_state(pdev);
4342 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4343 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4344
4345 return 0;
4346 }
4347
4348 static int sky2_resume(struct pci_dev *pdev)
4349 {
4350 struct sky2_hw *hw = pci_get_drvdata(pdev);
4351 int i, err;
4352
4353 if (!hw)
4354 return 0;
4355
4356 err = pci_set_power_state(pdev, PCI_D0);
4357 if (err)
4358 goto out;
4359
4360 err = pci_restore_state(pdev);
4361 if (err)
4362 goto out;
4363
4364 pci_enable_wake(pdev, PCI_D0, 0);
4365
4366 /* Re-enable all clocks */
4367 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4368 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4369 hw->chip_id == CHIP_ID_YUKON_FE_P)
4370 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4371
4372 sky2_reset(hw);
4373
4374 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4375
4376 for (i = 0; i < hw->ports; i++) {
4377 struct net_device *dev = hw->dev[i];
4378 if (netif_running(dev)) {
4379 err = sky2_up(dev);
4380 if (err) {
4381 printk(KERN_ERR PFX "%s: could not up: %d\n",
4382 dev->name, err);
4383 dev_close(dev);
4384 goto out;
4385 }
4386
4387 sky2_set_multicast(dev);
4388 }
4389 }
4390
4391 return 0;
4392 out:
4393 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4394 pci_disable_device(pdev);
4395 return err;
4396 }
4397 #endif
4398
4399 static void sky2_shutdown(struct pci_dev *pdev)
4400 {
4401 struct sky2_hw *hw = pci_get_drvdata(pdev);
4402 int i, wol = 0;
4403
4404 if (!hw)
4405 return;
4406
4407 napi_disable(&hw->napi);
4408
4409 for (i = 0; i < hw->ports; i++) {
4410 struct net_device *dev = hw->dev[i];
4411 struct sky2_port *sky2 = netdev_priv(dev);
4412
4413 if (sky2->wol) {
4414 wol = 1;
4415 sky2_wol_init(sky2);
4416 }
4417 }
4418
4419 if (wol)
4420 sky2_power_aux(hw);
4421
4422 pci_enable_wake(pdev, PCI_D3hot, wol);
4423 pci_enable_wake(pdev, PCI_D3cold, wol);
4424
4425 pci_disable_device(pdev);
4426 pci_set_power_state(pdev, PCI_D3hot);
4427
4428 }
4429
4430 static struct pci_driver sky2_driver = {
4431 .name = DRV_NAME,
4432 .id_table = sky2_id_table,
4433 .probe = sky2_probe,
4434 .remove = __devexit_p(sky2_remove),
4435 #ifdef CONFIG_PM
4436 .suspend = sky2_suspend,
4437 .resume = sky2_resume,
4438 #endif
4439 .shutdown = sky2_shutdown,
4440 };
4441
4442 static int __init sky2_init_module(void)
4443 {
4444 sky2_debug_init();
4445 return pci_register_driver(&sky2_driver);
4446 }
4447
4448 static void __exit sky2_cleanup_module(void)
4449 {
4450 pci_unregister_driver(&sky2_driver);
4451 sky2_debug_cleanup();
4452 }
4453
4454 module_init(sky2_init_module);
4455 module_exit(sky2_cleanup_module);
4456
4457 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4458 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4459 MODULE_LICENSE("GPL");
4460 MODULE_VERSION(DRV_VERSION);
kernel-based virtual machine