?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6/kvm.git] / drivers / net / gianfar.c
blobea7d5ddb7760641d7134cbc4a0d7a86df9657eaa
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 *
13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
28 *
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
78 #include <linux/mm.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
81 #include <linux/ip.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
84 #include <linux/in.h>
85 #include <linux/net_tstamp.h>
86
87 #include <asm/io.h>
88 #include <asm/irq.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
95 #include <linux/phy_fixed.h>
96 #include <linux/of.h>
97
98 #include "gianfar.h"
99 #include "fsl_pq_mdio.h"
100
101 #define TX_TIMEOUT (1*HZ)
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
104
105 const char gfar_driver_name[] = "Gianfar Ethernet";
106 const char gfar_driver_version[] = "1.3";
107
108 static int gfar_enet_open(struct net_device *dev);
109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void gfar_reset_task(struct work_struct *work);
111 static void gfar_timeout(struct net_device *dev);
112 static int gfar_close(struct net_device *dev);
113 struct sk_buff *gfar_new_skb(struct net_device *dev);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 struct sk_buff *skb);
116 static int gfar_set_mac_address(struct net_device *dev);
117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
118 static irqreturn_t gfar_error(int irq, void *dev_id);
119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
121 static void adjust_link(struct net_device *dev);
122 static void init_registers(struct net_device *dev);
123 static int init_phy(struct net_device *dev);
124 static int gfar_probe(struct of_device *ofdev,
125 const struct of_device_id *match);
126 static int gfar_remove(struct of_device *ofdev);
127 static void free_skb_resources(struct gfar_private *priv);
128 static void gfar_set_multi(struct net_device *dev);
129 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
130 static void gfar_configure_serdes(struct net_device *dev);
131 static int gfar_poll(struct napi_struct *napi, int budget);
132 #ifdef CONFIG_NET_POLL_CONTROLLER
133 static void gfar_netpoll(struct net_device *dev);
134 #endif
135 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
136 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
137 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
138 int amount_pull);
139 static void gfar_vlan_rx_register(struct net_device *netdev,
140 struct vlan_group *grp);
141 void gfar_halt(struct net_device *dev);
142 static void gfar_halt_nodisable(struct net_device *dev);
143 void gfar_start(struct net_device *dev);
144 static void gfar_clear_exact_match(struct net_device *dev);
145 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
147
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
151
152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
153 dma_addr_t buf)
154 {
155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166 }
167
168 static int gfar_init_bds(struct net_device *ndev)
169 {
170 struct gfar_private *priv = netdev_priv(ndev);
171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
175 int i, j;
176
177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
193
194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
197 }
198
199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
204
205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
207
208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
214 pr_err("%s: Can't allocate RX buffers\n",
215 ndev->name);
216 goto err_rxalloc_fail;
217 }
218 rx_queue->rx_skbuff[j] = skb;
219
220 gfar_new_rxbdp(rx_queue, rxbdp, skb);
221 }
222
223 rxbdp++;
224 }
225
226 }
227
228 return 0;
229
230 err_rxalloc_fail:
231 free_skb_resources(priv);
232 return -ENOMEM;
233 }
234
235 static int gfar_alloc_skb_resources(struct net_device *ndev)
236 {
237 void *vaddr;
238 dma_addr_t addr;
239 int i, j, k;
240 struct gfar_private *priv = netdev_priv(ndev);
241 struct device *dev = &priv->ofdev->dev;
242 struct gfar_priv_tx_q *tx_queue = NULL;
243 struct gfar_priv_rx_q *rx_queue = NULL;
244
245 priv->total_tx_ring_size = 0;
246 for (i = 0; i < priv->num_tx_queues; i++)
247 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
248
249 priv->total_rx_ring_size = 0;
250 for (i = 0; i < priv->num_rx_queues; i++)
251 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
252
253 /* Allocate memory for the buffer descriptors */
254 vaddr = dma_alloc_coherent(dev,
255 sizeof(struct txbd8) * priv->total_tx_ring_size +
256 sizeof(struct rxbd8) * priv->total_rx_ring_size,
257 &addr, GFP_KERNEL);
258 if (!vaddr) {
259 if (netif_msg_ifup(priv))
260 pr_err("%s: Could not allocate buffer descriptors!\n",
261 ndev->name);
262 return -ENOMEM;
263 }
264
265 for (i = 0; i < priv->num_tx_queues; i++) {
266 tx_queue = priv->tx_queue[i];
267 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
268 tx_queue->tx_bd_dma_base = addr;
269 tx_queue->dev = ndev;
270 /* enet DMA only understands physical addresses */
271 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
272 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 }
274
275 /* Start the rx descriptor ring where the tx ring leaves off */
276 for (i = 0; i < priv->num_rx_queues; i++) {
277 rx_queue = priv->rx_queue[i];
278 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
279 rx_queue->rx_bd_dma_base = addr;
280 rx_queue->dev = ndev;
281 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
282 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 }
284
285 /* Setup the skbuff rings */
286 for (i = 0; i < priv->num_tx_queues; i++) {
287 tx_queue = priv->tx_queue[i];
288 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
289 tx_queue->tx_ring_size, GFP_KERNEL);
290 if (!tx_queue->tx_skbuff) {
291 if (netif_msg_ifup(priv))
292 pr_err("%s: Could not allocate tx_skbuff\n",
293 ndev->name);
294 goto cleanup;
295 }
296
297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
299 }
300
301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
303 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
304 rx_queue->rx_ring_size, GFP_KERNEL);
305
306 if (!rx_queue->rx_skbuff) {
307 if (netif_msg_ifup(priv))
308 pr_err("%s: Could not allocate rx_skbuff\n",
309 ndev->name);
310 goto cleanup;
311 }
312
313 for (j = 0; j < rx_queue->rx_ring_size; j++)
314 rx_queue->rx_skbuff[j] = NULL;
315 }
316
317 if (gfar_init_bds(ndev))
318 goto cleanup;
319
320 return 0;
321
322 cleanup:
323 free_skb_resources(priv);
324 return -ENOMEM;
325 }
326
327 static void gfar_init_tx_rx_base(struct gfar_private *priv)
328 {
329 struct gfar __iomem *regs = priv->gfargrp[0].regs;
330 u32 __iomem *baddr;
331 int i;
332
333 baddr = &regs->tbase0;
334 for(i = 0; i < priv->num_tx_queues; i++) {
335 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
336 baddr += 2;
337 }
338
339 baddr = &regs->rbase0;
340 for(i = 0; i < priv->num_rx_queues; i++) {
341 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342 baddr += 2;
343 }
344 }
345
346 static void gfar_init_mac(struct net_device *ndev)
347 {
348 struct gfar_private *priv = netdev_priv(ndev);
349 struct gfar __iomem *regs = priv->gfargrp[0].regs;
350 u32 rctrl = 0;
351 u32 tctrl = 0;
352 u32 attrs = 0;
353
354 /* write the tx/rx base registers */
355 gfar_init_tx_rx_base(priv);
356
357 /* Configure the coalescing support */
358 gfar_configure_coalescing(priv, 0xFF, 0xFF);
359
360 if (priv->rx_filer_enable) {
361 rctrl |= RCTRL_FILREN;
362 /* Program the RIR0 reg with the required distribution */
363 gfar_write(&regs->rir0, DEFAULT_RIR0);
364 }
365
366 if (priv->rx_csum_enable)
367 rctrl |= RCTRL_CHECKSUMMING;
368
369 if (priv->extended_hash) {
370 rctrl |= RCTRL_EXTHASH;
371
372 gfar_clear_exact_match(ndev);
373 rctrl |= RCTRL_EMEN;
374 }
375
376 if (priv->padding) {
377 rctrl &= ~RCTRL_PAL_MASK;
378 rctrl |= RCTRL_PADDING(priv->padding);
379 }
380
381 /* Insert receive time stamps into padding alignment bytes */
382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
383 rctrl &= ~RCTRL_PAL_MASK;
384 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE | RCTRL_PADDING(8);
385 priv->padding = 8;
386 }
387
388 /* keep vlan related bits if it's enabled */
389 if (priv->vlgrp) {
390 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
391 tctrl |= TCTRL_VLINS;
392 }
393
394 /* Init rctrl based on our settings */
395 gfar_write(&regs->rctrl, rctrl);
396
397 if (ndev->features & NETIF_F_IP_CSUM)
398 tctrl |= TCTRL_INIT_CSUM;
399
400 tctrl |= TCTRL_TXSCHED_PRIO;
401
402 gfar_write(&regs->tctrl, tctrl);
403
404 /* Set the extraction length and index */
405 attrs = ATTRELI_EL(priv->rx_stash_size) |
406 ATTRELI_EI(priv->rx_stash_index);
407
408 gfar_write(&regs->attreli, attrs);
409
410 /* Start with defaults, and add stashing or locking
411 * depending on the approprate variables */
412 attrs = ATTR_INIT_SETTINGS;
413
414 if (priv->bd_stash_en)
415 attrs |= ATTR_BDSTASH;
416
417 if (priv->rx_stash_size != 0)
418 attrs |= ATTR_BUFSTASH;
419
420 gfar_write(&regs->attr, attrs);
421
422 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
423 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
424 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
425 }
426
427 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
428 {
429 struct gfar_private *priv = netdev_priv(dev);
430 struct netdev_queue *txq;
431 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
432 unsigned long tx_packets = 0, tx_bytes = 0;
433 int i = 0;
434
435 for (i = 0; i < priv->num_rx_queues; i++) {
436 rx_packets += priv->rx_queue[i]->stats.rx_packets;
437 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
438 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
439 }
440
441 dev->stats.rx_packets = rx_packets;
442 dev->stats.rx_bytes = rx_bytes;
443 dev->stats.rx_dropped = rx_dropped;
444
445 for (i = 0; i < priv->num_tx_queues; i++) {
446 txq = netdev_get_tx_queue(dev, i);
447 tx_bytes += txq->tx_bytes;
448 tx_packets += txq->tx_packets;
449 }
450
451 dev->stats.tx_bytes = tx_bytes;
452 dev->stats.tx_packets = tx_packets;
453
454 return &dev->stats;
455 }
456
457 static const struct net_device_ops gfar_netdev_ops = {
458 .ndo_open = gfar_enet_open,
459 .ndo_start_xmit = gfar_start_xmit,
460 .ndo_stop = gfar_close,
461 .ndo_change_mtu = gfar_change_mtu,
462 .ndo_set_multicast_list = gfar_set_multi,
463 .ndo_tx_timeout = gfar_timeout,
464 .ndo_do_ioctl = gfar_ioctl,
465 .ndo_get_stats = gfar_get_stats,
466 .ndo_vlan_rx_register = gfar_vlan_rx_register,
467 .ndo_set_mac_address = eth_mac_addr,
468 .ndo_validate_addr = eth_validate_addr,
469 #ifdef CONFIG_NET_POLL_CONTROLLER
470 .ndo_poll_controller = gfar_netpoll,
471 #endif
472 };
473
474 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
475 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
476
477 void lock_rx_qs(struct gfar_private *priv)
478 {
479 int i = 0x0;
480
481 for (i = 0; i < priv->num_rx_queues; i++)
482 spin_lock(&priv->rx_queue[i]->rxlock);
483 }
484
485 void lock_tx_qs(struct gfar_private *priv)
486 {
487 int i = 0x0;
488
489 for (i = 0; i < priv->num_tx_queues; i++)
490 spin_lock(&priv->tx_queue[i]->txlock);
491 }
492
493 void unlock_rx_qs(struct gfar_private *priv)
494 {
495 int i = 0x0;
496
497 for (i = 0; i < priv->num_rx_queues; i++)
498 spin_unlock(&priv->rx_queue[i]->rxlock);
499 }
500
501 void unlock_tx_qs(struct gfar_private *priv)
502 {
503 int i = 0x0;
504
505 for (i = 0; i < priv->num_tx_queues; i++)
506 spin_unlock(&priv->tx_queue[i]->txlock);
507 }
508
509 /* Returns 1 if incoming frames use an FCB */
510 static inline int gfar_uses_fcb(struct gfar_private *priv)
511 {
512 return priv->vlgrp || priv->rx_csum_enable ||
513 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
514 }
515
516 static void free_tx_pointers(struct gfar_private *priv)
517 {
518 int i = 0;
519
520 for (i = 0; i < priv->num_tx_queues; i++)
521 kfree(priv->tx_queue[i]);
522 }
523
524 static void free_rx_pointers(struct gfar_private *priv)
525 {
526 int i = 0;
527
528 for (i = 0; i < priv->num_rx_queues; i++)
529 kfree(priv->rx_queue[i]);
530 }
531
532 static void unmap_group_regs(struct gfar_private *priv)
533 {
534 int i = 0;
535
536 for (i = 0; i < MAXGROUPS; i++)
537 if (priv->gfargrp[i].regs)
538 iounmap(priv->gfargrp[i].regs);
539 }
540
541 static void disable_napi(struct gfar_private *priv)
542 {
543 int i = 0;
544
545 for (i = 0; i < priv->num_grps; i++)
546 napi_disable(&priv->gfargrp[i].napi);
547 }
548
549 static void enable_napi(struct gfar_private *priv)
550 {
551 int i = 0;
552
553 for (i = 0; i < priv->num_grps; i++)
554 napi_enable(&priv->gfargrp[i].napi);
555 }
556
557 static int gfar_parse_group(struct device_node *np,
558 struct gfar_private *priv, const char *model)
559 {
560 u32 *queue_mask;
561
562 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
563 if (!priv->gfargrp[priv->num_grps].regs)
564 return -ENOMEM;
565
566 priv->gfargrp[priv->num_grps].interruptTransmit =
567 irq_of_parse_and_map(np, 0);
568
569 /* If we aren't the FEC we have multiple interrupts */
570 if (model && strcasecmp(model, "FEC")) {
571 priv->gfargrp[priv->num_grps].interruptReceive =
572 irq_of_parse_and_map(np, 1);
573 priv->gfargrp[priv->num_grps].interruptError =
574 irq_of_parse_and_map(np,2);
575 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
576 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
577 priv->gfargrp[priv->num_grps].interruptError < 0) {
578 return -EINVAL;
579 }
580 }
581
582 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
583 priv->gfargrp[priv->num_grps].priv = priv;
584 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
585 if(priv->mode == MQ_MG_MODE) {
586 queue_mask = (u32 *)of_get_property(np,
587 "fsl,rx-bit-map", NULL);
588 priv->gfargrp[priv->num_grps].rx_bit_map =
589 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
590 queue_mask = (u32 *)of_get_property(np,
591 "fsl,tx-bit-map", NULL);
592 priv->gfargrp[priv->num_grps].tx_bit_map =
593 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
594 } else {
595 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
596 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
597 }
598 priv->num_grps++;
599
600 return 0;
601 }
602
603 static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
604 {
605 const char *model;
606 const char *ctype;
607 const void *mac_addr;
608 int err = 0, i;
609 struct net_device *dev = NULL;
610 struct gfar_private *priv = NULL;
611 struct device_node *np = ofdev->node;
612 struct device_node *child = NULL;
613 const u32 *stash;
614 const u32 *stash_len;
615 const u32 *stash_idx;
616 unsigned int num_tx_qs, num_rx_qs;
617 u32 *tx_queues, *rx_queues;
618
619 if (!np || !of_device_is_available(np))
620 return -ENODEV;
621
622 /* parse the num of tx and rx queues */
623 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
624 num_tx_qs = tx_queues ? *tx_queues : 1;
625
626 if (num_tx_qs > MAX_TX_QS) {
627 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
628 num_tx_qs, MAX_TX_QS);
629 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
630 return -EINVAL;
631 }
632
633 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
634 num_rx_qs = rx_queues ? *rx_queues : 1;
635
636 if (num_rx_qs > MAX_RX_QS) {
637 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
638 num_tx_qs, MAX_TX_QS);
639 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
640 return -EINVAL;
641 }
642
643 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
644 dev = *pdev;
645 if (NULL == dev)
646 return -ENOMEM;
647
648 priv = netdev_priv(dev);
649 priv->node = ofdev->node;
650 priv->ndev = dev;
651
652 dev->num_tx_queues = num_tx_qs;
653 dev->real_num_tx_queues = num_tx_qs;
654 priv->num_tx_queues = num_tx_qs;
655 priv->num_rx_queues = num_rx_qs;
656 priv->num_grps = 0x0;
657
658 model = of_get_property(np, "model", NULL);
659
660 for (i = 0; i < MAXGROUPS; i++)
661 priv->gfargrp[i].regs = NULL;
662
663 /* Parse and initialize group specific information */
664 if (of_device_is_compatible(np, "fsl,etsec2")) {
665 priv->mode = MQ_MG_MODE;
666 for_each_child_of_node(np, child) {
667 err = gfar_parse_group(child, priv, model);
668 if (err)
669 goto err_grp_init;
670 }
671 } else {
672 priv->mode = SQ_SG_MODE;
673 err = gfar_parse_group(np, priv, model);
674 if(err)
675 goto err_grp_init;
676 }
677
678 for (i = 0; i < priv->num_tx_queues; i++)
679 priv->tx_queue[i] = NULL;
680 for (i = 0; i < priv->num_rx_queues; i++)
681 priv->rx_queue[i] = NULL;
682
683 for (i = 0; i < priv->num_tx_queues; i++) {
684 priv->tx_queue[i] = (struct gfar_priv_tx_q *)kzalloc(
685 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
686 if (!priv->tx_queue[i]) {
687 err = -ENOMEM;
688 goto tx_alloc_failed;
689 }
690 priv->tx_queue[i]->tx_skbuff = NULL;
691 priv->tx_queue[i]->qindex = i;
692 priv->tx_queue[i]->dev = dev;
693 spin_lock_init(&(priv->tx_queue[i]->txlock));
694 }
695
696 for (i = 0; i < priv->num_rx_queues; i++) {
697 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc(
698 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
699 if (!priv->rx_queue[i]) {
700 err = -ENOMEM;
701 goto rx_alloc_failed;
702 }
703 priv->rx_queue[i]->rx_skbuff = NULL;
704 priv->rx_queue[i]->qindex = i;
705 priv->rx_queue[i]->dev = dev;
706 spin_lock_init(&(priv->rx_queue[i]->rxlock));
707 }
708
709
710 stash = of_get_property(np, "bd-stash", NULL);
711
712 if (stash) {
713 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
714 priv->bd_stash_en = 1;
715 }
716
717 stash_len = of_get_property(np, "rx-stash-len", NULL);
718
719 if (stash_len)
720 priv->rx_stash_size = *stash_len;
721
722 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
723
724 if (stash_idx)
725 priv->rx_stash_index = *stash_idx;
726
727 if (stash_len || stash_idx)
728 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
729
730 mac_addr = of_get_mac_address(np);
731 if (mac_addr)
732 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
733
734 if (model && !strcasecmp(model, "TSEC"))
735 priv->device_flags =
736 FSL_GIANFAR_DEV_HAS_GIGABIT |
737 FSL_GIANFAR_DEV_HAS_COALESCE |
738 FSL_GIANFAR_DEV_HAS_RMON |
739 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
740 if (model && !strcasecmp(model, "eTSEC"))
741 priv->device_flags =
742 FSL_GIANFAR_DEV_HAS_GIGABIT |
743 FSL_GIANFAR_DEV_HAS_COALESCE |
744 FSL_GIANFAR_DEV_HAS_RMON |
745 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
746 FSL_GIANFAR_DEV_HAS_PADDING |
747 FSL_GIANFAR_DEV_HAS_CSUM |
748 FSL_GIANFAR_DEV_HAS_VLAN |
749 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
750 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
751 FSL_GIANFAR_DEV_HAS_TIMER;
752
753 ctype = of_get_property(np, "phy-connection-type", NULL);
754
755 /* We only care about rgmii-id. The rest are autodetected */
756 if (ctype && !strcmp(ctype, "rgmii-id"))
757 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
758 else
759 priv->interface = PHY_INTERFACE_MODE_MII;
760
761 if (of_get_property(np, "fsl,magic-packet", NULL))
762 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
763
764 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
765
766 /* Find the TBI PHY. If it's not there, we don't support SGMII */
767 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
768
769 return 0;
770
771 rx_alloc_failed:
772 free_rx_pointers(priv);
773 tx_alloc_failed:
774 free_tx_pointers(priv);
775 err_grp_init:
776 unmap_group_regs(priv);
777 free_netdev(dev);
778 return err;
779 }
780
781 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
782 struct ifreq *ifr, int cmd)
783 {
784 struct hwtstamp_config config;
785 struct gfar_private *priv = netdev_priv(netdev);
786
787 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
788 return -EFAULT;
789
790 /* reserved for future extensions */
791 if (config.flags)
792 return -EINVAL;
793
794 switch (config.tx_type) {
795 case HWTSTAMP_TX_OFF:
796 priv->hwts_tx_en = 0;
797 break;
798 case HWTSTAMP_TX_ON:
799 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
800 return -ERANGE;
801 priv->hwts_tx_en = 1;
802 break;
803 default:
804 return -ERANGE;
805 }
806
807 switch (config.rx_filter) {
808 case HWTSTAMP_FILTER_NONE:
809 priv->hwts_rx_en = 0;
810 break;
811 default:
812 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
813 return -ERANGE;
814 priv->hwts_rx_en = 1;
815 config.rx_filter = HWTSTAMP_FILTER_ALL;
816 break;
817 }
818
819 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
820 -EFAULT : 0;
821 }
822
823 /* Ioctl MII Interface */
824 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
825 {
826 struct gfar_private *priv = netdev_priv(dev);
827
828 if (!netif_running(dev))
829 return -EINVAL;
830
831 if (cmd == SIOCSHWTSTAMP)
832 return gfar_hwtstamp_ioctl(dev, rq, cmd);
833
834 if (!priv->phydev)
835 return -ENODEV;
836
837 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
838 }
839
840 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
841 {
842 unsigned int new_bit_map = 0x0;
843 int mask = 0x1 << (max_qs - 1), i;
844 for (i = 0; i < max_qs; i++) {
845 if (bit_map & mask)
846 new_bit_map = new_bit_map + (1 << i);
847 mask = mask >> 0x1;
848 }
849 return new_bit_map;
850 }
851
852 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
853 u32 class)
854 {
855 u32 rqfpr = FPR_FILER_MASK;
856 u32 rqfcr = 0x0;
857
858 rqfar--;
859 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
860 ftp_rqfpr[rqfar] = rqfpr;
861 ftp_rqfcr[rqfar] = rqfcr;
862 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
863
864 rqfar--;
865 rqfcr = RQFCR_CMP_NOMATCH;
866 ftp_rqfpr[rqfar] = rqfpr;
867 ftp_rqfcr[rqfar] = rqfcr;
868 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
869
870 rqfar--;
871 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
872 rqfpr = class;
873 ftp_rqfcr[rqfar] = rqfcr;
874 ftp_rqfpr[rqfar] = rqfpr;
875 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
876
877 rqfar--;
878 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
879 rqfpr = class;
880 ftp_rqfcr[rqfar] = rqfcr;
881 ftp_rqfpr[rqfar] = rqfpr;
882 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
883
884 return rqfar;
885 }
886
887 static void gfar_init_filer_table(struct gfar_private *priv)
888 {
889 int i = 0x0;
890 u32 rqfar = MAX_FILER_IDX;
891 u32 rqfcr = 0x0;
892 u32 rqfpr = FPR_FILER_MASK;
893
894 /* Default rule */
895 rqfcr = RQFCR_CMP_MATCH;
896 ftp_rqfcr[rqfar] = rqfcr;
897 ftp_rqfpr[rqfar] = rqfpr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899
900 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
902 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
903 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
904 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
905 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
906
907 /* cur_filer_idx indicated the fisrt non-masked rule */
908 priv->cur_filer_idx = rqfar;
909
910 /* Rest are masked rules */
911 rqfcr = RQFCR_CMP_NOMATCH;
912 for (i = 0; i < rqfar; i++) {
913 ftp_rqfcr[i] = rqfcr;
914 ftp_rqfpr[i] = rqfpr;
915 gfar_write_filer(priv, i, rqfcr, rqfpr);
916 }
917 }
918
919 /* Set up the ethernet device structure, private data,
920 * and anything else we need before we start */
921 static int gfar_probe(struct of_device *ofdev,
922 const struct of_device_id *match)
923 {
924 u32 tempval;
925 struct net_device *dev = NULL;
926 struct gfar_private *priv = NULL;
927 struct gfar __iomem *regs = NULL;
928 int err = 0, i, grp_idx = 0;
929 int len_devname;
930 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
931 u32 isrg = 0;
932 u32 __iomem *baddr;
933
934 err = gfar_of_init(ofdev, &dev);
935
936 if (err)
937 return err;
938
939 priv = netdev_priv(dev);
940 priv->ndev = dev;
941 priv->ofdev = ofdev;
942 priv->node = ofdev->node;
943 SET_NETDEV_DEV(dev, &ofdev->dev);
944
945 spin_lock_init(&priv->bflock);
946 INIT_WORK(&priv->reset_task, gfar_reset_task);
947
948 dev_set_drvdata(&ofdev->dev, priv);
949 regs = priv->gfargrp[0].regs;
950
951 /* Stop the DMA engine now, in case it was running before */
952 /* (The firmware could have used it, and left it running). */
953 gfar_halt(dev);
954
955 /* Reset MAC layer */
956 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
957
958 /* We need to delay at least 3 TX clocks */
959 udelay(2);
960
961 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
962 gfar_write(&regs->maccfg1, tempval);
963
964 /* Initialize MACCFG2. */
965 gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
966
967 /* Initialize ECNTRL */
968 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
969
970 /* Set the dev->base_addr to the gfar reg region */
971 dev->base_addr = (unsigned long) regs;
972
973 SET_NETDEV_DEV(dev, &ofdev->dev);
974
975 /* Fill in the dev structure */
976 dev->watchdog_timeo = TX_TIMEOUT;
977 dev->mtu = 1500;
978 dev->netdev_ops = &gfar_netdev_ops;
979 dev->ethtool_ops = &gfar_ethtool_ops;
980
981 /* Register for napi ...We are registering NAPI for each grp */
982 for (i = 0; i < priv->num_grps; i++)
983 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
984
985 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
986 priv->rx_csum_enable = 1;
987 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
988 } else
989 priv->rx_csum_enable = 0;
990
991 priv->vlgrp = NULL;
992
993 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
994 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
995
996 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
997 priv->extended_hash = 1;
998 priv->hash_width = 9;
999
1000 priv->hash_regs[0] = &regs->igaddr0;
1001 priv->hash_regs[1] = &regs->igaddr1;
1002 priv->hash_regs[2] = &regs->igaddr2;
1003 priv->hash_regs[3] = &regs->igaddr3;
1004 priv->hash_regs[4] = &regs->igaddr4;
1005 priv->hash_regs[5] = &regs->igaddr5;
1006 priv->hash_regs[6] = &regs->igaddr6;
1007 priv->hash_regs[7] = &regs->igaddr7;
1008 priv->hash_regs[8] = &regs->gaddr0;
1009 priv->hash_regs[9] = &regs->gaddr1;
1010 priv->hash_regs[10] = &regs->gaddr2;
1011 priv->hash_regs[11] = &regs->gaddr3;
1012 priv->hash_regs[12] = &regs->gaddr4;
1013 priv->hash_regs[13] = &regs->gaddr5;
1014 priv->hash_regs[14] = &regs->gaddr6;
1015 priv->hash_regs[15] = &regs->gaddr7;
1016
1017 } else {
1018 priv->extended_hash = 0;
1019 priv->hash_width = 8;
1020
1021 priv->hash_regs[0] = &regs->gaddr0;
1022 priv->hash_regs[1] = &regs->gaddr1;
1023 priv->hash_regs[2] = &regs->gaddr2;
1024 priv->hash_regs[3] = &regs->gaddr3;
1025 priv->hash_regs[4] = &regs->gaddr4;
1026 priv->hash_regs[5] = &regs->gaddr5;
1027 priv->hash_regs[6] = &regs->gaddr6;
1028 priv->hash_regs[7] = &regs->gaddr7;
1029 }
1030
1031 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1032 priv->padding = DEFAULT_PADDING;
1033 else
1034 priv->padding = 0;
1035
1036 if (dev->features & NETIF_F_IP_CSUM ||
1037 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1038 dev->hard_header_len += GMAC_FCB_LEN;
1039
1040 /* Program the isrg regs only if number of grps > 1 */
1041 if (priv->num_grps > 1) {
1042 baddr = &regs->isrg0;
1043 for (i = 0; i < priv->num_grps; i++) {
1044 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1045 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1046 gfar_write(baddr, isrg);
1047 baddr++;
1048 isrg = 0x0;
1049 }
1050 }
1051
1052 /* Need to reverse the bit maps as bit_map's MSB is q0
1053 * but, for_each_set_bit parses from right to left, which
1054 * basically reverses the queue numbers */
1055 for (i = 0; i< priv->num_grps; i++) {
1056 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1057 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1058 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1059 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1060 }
1061
1062 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1063 * also assign queues to groups */
1064 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1065 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1066 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1067 priv->num_rx_queues) {
1068 priv->gfargrp[grp_idx].num_rx_queues++;
1069 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1070 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1071 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1072 }
1073 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1074 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1075 priv->num_tx_queues) {
1076 priv->gfargrp[grp_idx].num_tx_queues++;
1077 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1078 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1079 tqueue = tqueue | (TQUEUE_EN0 >> i);
1080 }
1081 priv->gfargrp[grp_idx].rstat = rstat;
1082 priv->gfargrp[grp_idx].tstat = tstat;
1083 rstat = tstat =0;
1084 }
1085
1086 gfar_write(&regs->rqueue, rqueue);
1087 gfar_write(&regs->tqueue, tqueue);
1088
1089 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1090
1091 /* Initializing some of the rx/tx queue level parameters */
1092 for (i = 0; i < priv->num_tx_queues; i++) {
1093 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1094 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1095 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1096 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1097 }
1098
1099 for (i = 0; i < priv->num_rx_queues; i++) {
1100 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1101 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1102 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1103 }
1104
1105 /* enable filer if using multiple RX queues*/
1106 if(priv->num_rx_queues > 1)
1107 priv->rx_filer_enable = 1;
1108 /* Enable most messages by default */
1109 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1110
1111 /* Carrier starts down, phylib will bring it up */
1112 netif_carrier_off(dev);
1113
1114 err = register_netdev(dev);
1115
1116 if (err) {
1117 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1118 dev->name);
1119 goto register_fail;
1120 }
1121
1122 device_init_wakeup(&dev->dev,
1123 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1124
1125 /* fill out IRQ number and name fields */
1126 len_devname = strlen(dev->name);
1127 for (i = 0; i < priv->num_grps; i++) {
1128 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1129 len_devname);
1130 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1131 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1132 "_g", sizeof("_g"));
1133 priv->gfargrp[i].int_name_tx[
1134 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1135 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1136 priv->gfargrp[i].int_name_tx)],
1137 "_tx", sizeof("_tx") + 1);
1138
1139 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1140 len_devname);
1141 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1142 "_g", sizeof("_g"));
1143 priv->gfargrp[i].int_name_rx[
1144 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1145 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1146 priv->gfargrp[i].int_name_rx)],
1147 "_rx", sizeof("_rx") + 1);
1148
1149 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1150 len_devname);
1151 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1152 "_g", sizeof("_g"));
1153 priv->gfargrp[i].int_name_er[strlen(
1154 priv->gfargrp[i].int_name_er)] = i+48;
1155 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1156 priv->gfargrp[i].int_name_er)],
1157 "_er", sizeof("_er") + 1);
1158 } else
1159 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1160 }
1161
1162 /* Initialize the filer table */
1163 gfar_init_filer_table(priv);
1164
1165 /* Create all the sysfs files */
1166 gfar_init_sysfs(dev);
1167
1168 /* Print out the device info */
1169 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1170
1171 /* Even more device info helps when determining which kernel */
1172 /* provided which set of benchmarks. */
1173 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1174 for (i = 0; i < priv->num_rx_queues; i++)
1175 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1176 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1177 for(i = 0; i < priv->num_tx_queues; i++)
1178 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1179 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1180
1181 return 0;
1182
1183 register_fail:
1184 unmap_group_regs(priv);
1185 free_tx_pointers(priv);
1186 free_rx_pointers(priv);
1187 if (priv->phy_node)
1188 of_node_put(priv->phy_node);
1189 if (priv->tbi_node)
1190 of_node_put(priv->tbi_node);
1191 free_netdev(dev);
1192 return err;
1193 }
1194
1195 static int gfar_remove(struct of_device *ofdev)
1196 {
1197 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1198
1199 if (priv->phy_node)
1200 of_node_put(priv->phy_node);
1201 if (priv->tbi_node)
1202 of_node_put(priv->tbi_node);
1203
1204 dev_set_drvdata(&ofdev->dev, NULL);
1205
1206 unregister_netdev(priv->ndev);
1207 unmap_group_regs(priv);
1208 free_netdev(priv->ndev);
1209
1210 return 0;
1211 }
1212
1213 #ifdef CONFIG_PM
1214
1215 static int gfar_suspend(struct device *dev)
1216 {
1217 struct gfar_private *priv = dev_get_drvdata(dev);
1218 struct net_device *ndev = priv->ndev;
1219 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1220 unsigned long flags;
1221 u32 tempval;
1222
1223 int magic_packet = priv->wol_en &&
1224 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1225
1226 netif_device_detach(ndev);
1227
1228 if (netif_running(ndev)) {
1229
1230 local_irq_save(flags);
1231 lock_tx_qs(priv);
1232 lock_rx_qs(priv);
1233
1234 gfar_halt_nodisable(ndev);
1235
1236 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1237 tempval = gfar_read(&regs->maccfg1);
1238
1239 tempval &= ~MACCFG1_TX_EN;
1240
1241 if (!magic_packet)
1242 tempval &= ~MACCFG1_RX_EN;
1243
1244 gfar_write(&regs->maccfg1, tempval);
1245
1246 unlock_rx_qs(priv);
1247 unlock_tx_qs(priv);
1248 local_irq_restore(flags);
1249
1250 disable_napi(priv);
1251
1252 if (magic_packet) {
1253 /* Enable interrupt on Magic Packet */
1254 gfar_write(&regs->imask, IMASK_MAG);
1255
1256 /* Enable Magic Packet mode */
1257 tempval = gfar_read(&regs->maccfg2);
1258 tempval |= MACCFG2_MPEN;
1259 gfar_write(&regs->maccfg2, tempval);
1260 } else {
1261 phy_stop(priv->phydev);
1262 }
1263 }
1264
1265 return 0;
1266 }
1267
1268 static int gfar_resume(struct device *dev)
1269 {
1270 struct gfar_private *priv = dev_get_drvdata(dev);
1271 struct net_device *ndev = priv->ndev;
1272 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273 unsigned long flags;
1274 u32 tempval;
1275 int magic_packet = priv->wol_en &&
1276 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1277
1278 if (!netif_running(ndev)) {
1279 netif_device_attach(ndev);
1280 return 0;
1281 }
1282
1283 if (!magic_packet && priv->phydev)
1284 phy_start(priv->phydev);
1285
1286 /* Disable Magic Packet mode, in case something
1287 * else woke us up.
1288 */
1289 local_irq_save(flags);
1290 lock_tx_qs(priv);
1291 lock_rx_qs(priv);
1292
1293 tempval = gfar_read(&regs->maccfg2);
1294 tempval &= ~MACCFG2_MPEN;
1295 gfar_write(&regs->maccfg2, tempval);
1296
1297 gfar_start(ndev);
1298
1299 unlock_rx_qs(priv);
1300 unlock_tx_qs(priv);
1301 local_irq_restore(flags);
1302
1303 netif_device_attach(ndev);
1304
1305 enable_napi(priv);
1306
1307 return 0;
1308 }
1309
1310 static int gfar_restore(struct device *dev)
1311 {
1312 struct gfar_private *priv = dev_get_drvdata(dev);
1313 struct net_device *ndev = priv->ndev;
1314
1315 if (!netif_running(ndev))
1316 return 0;
1317
1318 gfar_init_bds(ndev);
1319 init_registers(ndev);
1320 gfar_set_mac_address(ndev);
1321 gfar_init_mac(ndev);
1322 gfar_start(ndev);
1323
1324 priv->oldlink = 0;
1325 priv->oldspeed = 0;
1326 priv->oldduplex = -1;
1327
1328 if (priv->phydev)
1329 phy_start(priv->phydev);
1330
1331 netif_device_attach(ndev);
1332 enable_napi(priv);
1333
1334 return 0;
1335 }
1336
1337 static struct dev_pm_ops gfar_pm_ops = {
1338 .suspend = gfar_suspend,
1339 .resume = gfar_resume,
1340 .freeze = gfar_suspend,
1341 .thaw = gfar_resume,
1342 .restore = gfar_restore,
1343 };
1344
1345 #define GFAR_PM_OPS (&gfar_pm_ops)
1346
1347 static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
1348 {
1349 return gfar_suspend(&ofdev->dev);
1350 }
1351
1352 static int gfar_legacy_resume(struct of_device *ofdev)
1353 {
1354 return gfar_resume(&ofdev->dev);
1355 }
1356
1357 #else
1358
1359 #define GFAR_PM_OPS NULL
1360 #define gfar_legacy_suspend NULL
1361 #define gfar_legacy_resume NULL
1362
1363 #endif
1364
1365 /* Reads the controller's registers to determine what interface
1366 * connects it to the PHY.
1367 */
1368 static phy_interface_t gfar_get_interface(struct net_device *dev)
1369 {
1370 struct gfar_private *priv = netdev_priv(dev);
1371 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1372 u32 ecntrl;
1373
1374 ecntrl = gfar_read(&regs->ecntrl);
1375
1376 if (ecntrl & ECNTRL_SGMII_MODE)
1377 return PHY_INTERFACE_MODE_SGMII;
1378
1379 if (ecntrl & ECNTRL_TBI_MODE) {
1380 if (ecntrl & ECNTRL_REDUCED_MODE)
1381 return PHY_INTERFACE_MODE_RTBI;
1382 else
1383 return PHY_INTERFACE_MODE_TBI;
1384 }
1385
1386 if (ecntrl & ECNTRL_REDUCED_MODE) {
1387 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1388 return PHY_INTERFACE_MODE_RMII;
1389 else {
1390 phy_interface_t interface = priv->interface;
1391
1392 /*
1393 * This isn't autodetected right now, so it must
1394 * be set by the device tree or platform code.
1395 */
1396 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1397 return PHY_INTERFACE_MODE_RGMII_ID;
1398
1399 return PHY_INTERFACE_MODE_RGMII;
1400 }
1401 }
1402
1403 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1404 return PHY_INTERFACE_MODE_GMII;
1405
1406 return PHY_INTERFACE_MODE_MII;
1407 }
1408
1409
1410 /* Initializes driver's PHY state, and attaches to the PHY.
1411 * Returns 0 on success.
1412 */
1413 static int init_phy(struct net_device *dev)
1414 {
1415 struct gfar_private *priv = netdev_priv(dev);
1416 uint gigabit_support =
1417 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1418 SUPPORTED_1000baseT_Full : 0;
1419 phy_interface_t interface;
1420
1421 priv->oldlink = 0;
1422 priv->oldspeed = 0;
1423 priv->oldduplex = -1;
1424
1425 interface = gfar_get_interface(dev);
1426
1427 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1428 interface);
1429 if (!priv->phydev)
1430 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1431 interface);
1432 if (!priv->phydev) {
1433 dev_err(&dev->dev, "could not attach to PHY\n");
1434 return -ENODEV;
1435 }
1436
1437 if (interface == PHY_INTERFACE_MODE_SGMII)
1438 gfar_configure_serdes(dev);
1439
1440 /* Remove any features not supported by the controller */
1441 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1442 priv->phydev->advertising = priv->phydev->supported;
1443
1444 return 0;
1445 }
1446
1447 /*
1448 * Initialize TBI PHY interface for communicating with the
1449 * SERDES lynx PHY on the chip. We communicate with this PHY
1450 * through the MDIO bus on each controller, treating it as a
1451 * "normal" PHY at the address found in the TBIPA register. We assume
1452 * that the TBIPA register is valid. Either the MDIO bus code will set
1453 * it to a value that doesn't conflict with other PHYs on the bus, or the
1454 * value doesn't matter, as there are no other PHYs on the bus.
1455 */
1456 static void gfar_configure_serdes(struct net_device *dev)
1457 {
1458 struct gfar_private *priv = netdev_priv(dev);
1459 struct phy_device *tbiphy;
1460
1461 if (!priv->tbi_node) {
1462 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1463 "device tree specify a tbi-handle\n");
1464 return;
1465 }
1466
1467 tbiphy = of_phy_find_device(priv->tbi_node);
1468 if (!tbiphy) {
1469 dev_err(&dev->dev, "error: Could not get TBI device\n");
1470 return;
1471 }
1472
1473 /*
1474 * If the link is already up, we must already be ok, and don't need to
1475 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1476 * everything for us? Resetting it takes the link down and requires
1477 * several seconds for it to come back.
1478 */
1479 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1480 return;
1481
1482 /* Single clk mode, mii mode off(for serdes communication) */
1483 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1484
1485 phy_write(tbiphy, MII_ADVERTISE,
1486 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1487 ADVERTISE_1000XPSE_ASYM);
1488
1489 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1490 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1491 }
1492
1493 static void init_registers(struct net_device *dev)
1494 {
1495 struct gfar_private *priv = netdev_priv(dev);
1496 struct gfar __iomem *regs = NULL;
1497 int i = 0;
1498
1499 for (i = 0; i < priv->num_grps; i++) {
1500 regs = priv->gfargrp[i].regs;
1501 /* Clear IEVENT */
1502 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1503
1504 /* Initialize IMASK */
1505 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1506 }
1507
1508 regs = priv->gfargrp[0].regs;
1509 /* Init hash registers to zero */
1510 gfar_write(&regs->igaddr0, 0);
1511 gfar_write(&regs->igaddr1, 0);
1512 gfar_write(&regs->igaddr2, 0);
1513 gfar_write(&regs->igaddr3, 0);
1514 gfar_write(&regs->igaddr4, 0);
1515 gfar_write(&regs->igaddr5, 0);
1516 gfar_write(&regs->igaddr6, 0);
1517 gfar_write(&regs->igaddr7, 0);
1518
1519 gfar_write(&regs->gaddr0, 0);
1520 gfar_write(&regs->gaddr1, 0);
1521 gfar_write(&regs->gaddr2, 0);
1522 gfar_write(&regs->gaddr3, 0);
1523 gfar_write(&regs->gaddr4, 0);
1524 gfar_write(&regs->gaddr5, 0);
1525 gfar_write(&regs->gaddr6, 0);
1526 gfar_write(&regs->gaddr7, 0);
1527
1528 /* Zero out the rmon mib registers if it has them */
1529 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1530 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1531
1532 /* Mask off the CAM interrupts */
1533 gfar_write(&regs->rmon.cam1, 0xffffffff);
1534 gfar_write(&regs->rmon.cam2, 0xffffffff);
1535 }
1536
1537 /* Initialize the max receive buffer length */
1538 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1539
1540 /* Initialize the Minimum Frame Length Register */
1541 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1542 }
1543
1544
1545 /* Halt the receive and transmit queues */
1546 static void gfar_halt_nodisable(struct net_device *dev)
1547 {
1548 struct gfar_private *priv = netdev_priv(dev);
1549 struct gfar __iomem *regs = NULL;
1550 u32 tempval;
1551 int i = 0;
1552
1553 for (i = 0; i < priv->num_grps; i++) {
1554 regs = priv->gfargrp[i].regs;
1555 /* Mask all interrupts */
1556 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1557
1558 /* Clear all interrupts */
1559 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1560 }
1561
1562 regs = priv->gfargrp[0].regs;
1563 /* Stop the DMA, and wait for it to stop */
1564 tempval = gfar_read(&regs->dmactrl);
1565 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1566 != (DMACTRL_GRS | DMACTRL_GTS)) {
1567 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1568 gfar_write(&regs->dmactrl, tempval);
1569
1570 spin_event_timeout(((gfar_read(&regs->ievent) &
1571 (IEVENT_GRSC | IEVENT_GTSC)) ==
1572 (IEVENT_GRSC | IEVENT_GTSC)), -1, 0);
1573 }
1574 }
1575
1576 /* Halt the receive and transmit queues */
1577 void gfar_halt(struct net_device *dev)
1578 {
1579 struct gfar_private *priv = netdev_priv(dev);
1580 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1581 u32 tempval;
1582
1583 gfar_halt_nodisable(dev);
1584
1585 /* Disable Rx and Tx */
1586 tempval = gfar_read(&regs->maccfg1);
1587 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1588 gfar_write(&regs->maccfg1, tempval);
1589 }
1590
1591 static void free_grp_irqs(struct gfar_priv_grp *grp)
1592 {
1593 free_irq(grp->interruptError, grp);
1594 free_irq(grp->interruptTransmit, grp);
1595 free_irq(grp->interruptReceive, grp);
1596 }
1597
1598 void stop_gfar(struct net_device *dev)
1599 {
1600 struct gfar_private *priv = netdev_priv(dev);
1601 unsigned long flags;
1602 int i;
1603
1604 phy_stop(priv->phydev);
1605
1606
1607 /* Lock it down */
1608 local_irq_save(flags);
1609 lock_tx_qs(priv);
1610 lock_rx_qs(priv);
1611
1612 gfar_halt(dev);
1613
1614 unlock_rx_qs(priv);
1615 unlock_tx_qs(priv);
1616 local_irq_restore(flags);
1617
1618 /* Free the IRQs */
1619 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1620 for (i = 0; i < priv->num_grps; i++)
1621 free_grp_irqs(&priv->gfargrp[i]);
1622 } else {
1623 for (i = 0; i < priv->num_grps; i++)
1624 free_irq(priv->gfargrp[i].interruptTransmit,
1625 &priv->gfargrp[i]);
1626 }
1627
1628 free_skb_resources(priv);
1629 }
1630
1631 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1632 {
1633 struct txbd8 *txbdp;
1634 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1635 int i, j;
1636
1637 txbdp = tx_queue->tx_bd_base;
1638
1639 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1640 if (!tx_queue->tx_skbuff[i])
1641 continue;
1642
1643 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1644 txbdp->length, DMA_TO_DEVICE);
1645 txbdp->lstatus = 0;
1646 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1647 j++) {
1648 txbdp++;
1649 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1650 txbdp->length, DMA_TO_DEVICE);
1651 }
1652 txbdp++;
1653 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1654 tx_queue->tx_skbuff[i] = NULL;
1655 }
1656 kfree(tx_queue->tx_skbuff);
1657 }
1658
1659 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1660 {
1661 struct rxbd8 *rxbdp;
1662 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1663 int i;
1664
1665 rxbdp = rx_queue->rx_bd_base;
1666
1667 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1668 if (rx_queue->rx_skbuff[i]) {
1669 dma_unmap_single(&priv->ofdev->dev,
1670 rxbdp->bufPtr, priv->rx_buffer_size,
1671 DMA_FROM_DEVICE);
1672 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1673 rx_queue->rx_skbuff[i] = NULL;
1674 }
1675 rxbdp->lstatus = 0;
1676 rxbdp->bufPtr = 0;
1677 rxbdp++;
1678 }
1679 kfree(rx_queue->rx_skbuff);
1680 }
1681
1682 /* If there are any tx skbs or rx skbs still around, free them.
1683 * Then free tx_skbuff and rx_skbuff */
1684 static void free_skb_resources(struct gfar_private *priv)
1685 {
1686 struct gfar_priv_tx_q *tx_queue = NULL;
1687 struct gfar_priv_rx_q *rx_queue = NULL;
1688 int i;
1689
1690 /* Go through all the buffer descriptors and free their data buffers */
1691 for (i = 0; i < priv->num_tx_queues; i++) {
1692 tx_queue = priv->tx_queue[i];
1693 if(tx_queue->tx_skbuff)
1694 free_skb_tx_queue(tx_queue);
1695 }
1696
1697 for (i = 0; i < priv->num_rx_queues; i++) {
1698 rx_queue = priv->rx_queue[i];
1699 if(rx_queue->rx_skbuff)
1700 free_skb_rx_queue(rx_queue);
1701 }
1702
1703 dma_free_coherent(&priv->ofdev->dev,
1704 sizeof(struct txbd8) * priv->total_tx_ring_size +
1705 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1706 priv->tx_queue[0]->tx_bd_base,
1707 priv->tx_queue[0]->tx_bd_dma_base);
1708 skb_queue_purge(&priv->rx_recycle);
1709 }
1710
1711 void gfar_start(struct net_device *dev)
1712 {
1713 struct gfar_private *priv = netdev_priv(dev);
1714 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1715 u32 tempval;
1716 int i = 0;
1717
1718 /* Enable Rx and Tx in MACCFG1 */
1719 tempval = gfar_read(&regs->maccfg1);
1720 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1721 gfar_write(&regs->maccfg1, tempval);
1722
1723 /* Initialize DMACTRL to have WWR and WOP */
1724 tempval = gfar_read(&regs->dmactrl);
1725 tempval |= DMACTRL_INIT_SETTINGS;
1726 gfar_write(&regs->dmactrl, tempval);
1727
1728 /* Make sure we aren't stopped */
1729 tempval = gfar_read(&regs->dmactrl);
1730 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1731 gfar_write(&regs->dmactrl, tempval);
1732
1733 for (i = 0; i < priv->num_grps; i++) {
1734 regs = priv->gfargrp[i].regs;
1735 /* Clear THLT/RHLT, so that the DMA starts polling now */
1736 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1737 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1738 /* Unmask the interrupts we look for */
1739 gfar_write(&regs->imask, IMASK_DEFAULT);
1740 }
1741
1742 dev->trans_start = jiffies; /* prevent tx timeout */
1743 }
1744
1745 void gfar_configure_coalescing(struct gfar_private *priv,
1746 unsigned long tx_mask, unsigned long rx_mask)
1747 {
1748 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1749 u32 __iomem *baddr;
1750 int i = 0;
1751
1752 /* Backward compatible case ---- even if we enable
1753 * multiple queues, there's only single reg to program
1754 */
1755 gfar_write(&regs->txic, 0);
1756 if(likely(priv->tx_queue[0]->txcoalescing))
1757 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1758
1759 gfar_write(&regs->rxic, 0);
1760 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1761 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1762
1763 if (priv->mode == MQ_MG_MODE) {
1764 baddr = &regs->txic0;
1765 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1766 if (likely(priv->tx_queue[i]->txcoalescing)) {
1767 gfar_write(baddr + i, 0);
1768 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1769 }
1770 }
1771
1772 baddr = &regs->rxic0;
1773 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1774 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1775 gfar_write(baddr + i, 0);
1776 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1777 }
1778 }
1779 }
1780 }
1781
1782 static int register_grp_irqs(struct gfar_priv_grp *grp)
1783 {
1784 struct gfar_private *priv = grp->priv;
1785 struct net_device *dev = priv->ndev;
1786 int err;
1787
1788 /* If the device has multiple interrupts, register for
1789 * them. Otherwise, only register for the one */
1790 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1791 /* Install our interrupt handlers for Error,
1792 * Transmit, and Receive */
1793 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1794 grp->int_name_er,grp)) < 0) {
1795 if (netif_msg_intr(priv))
1796 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1797 dev->name, grp->interruptError);
1798
1799 goto err_irq_fail;
1800 }
1801
1802 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1803 0, grp->int_name_tx, grp)) < 0) {
1804 if (netif_msg_intr(priv))
1805 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1806 dev->name, grp->interruptTransmit);
1807 goto tx_irq_fail;
1808 }
1809
1810 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1811 grp->int_name_rx, grp)) < 0) {
1812 if (netif_msg_intr(priv))
1813 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1814 dev->name, grp->interruptReceive);
1815 goto rx_irq_fail;
1816 }
1817 } else {
1818 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1819 grp->int_name_tx, grp)) < 0) {
1820 if (netif_msg_intr(priv))
1821 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1822 dev->name, grp->interruptTransmit);
1823 goto err_irq_fail;
1824 }
1825 }
1826
1827 return 0;
1828
1829 rx_irq_fail:
1830 free_irq(grp->interruptTransmit, grp);
1831 tx_irq_fail:
1832 free_irq(grp->interruptError, grp);
1833 err_irq_fail:
1834 return err;
1835
1836 }
1837
1838 /* Bring the controller up and running */
1839 int startup_gfar(struct net_device *ndev)
1840 {
1841 struct gfar_private *priv = netdev_priv(ndev);
1842 struct gfar __iomem *regs = NULL;
1843 int err, i, j;
1844
1845 for (i = 0; i < priv->num_grps; i++) {
1846 regs= priv->gfargrp[i].regs;
1847 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1848 }
1849
1850 regs= priv->gfargrp[0].regs;
1851 err = gfar_alloc_skb_resources(ndev);
1852 if (err)
1853 return err;
1854
1855 gfar_init_mac(ndev);
1856
1857 for (i = 0; i < priv->num_grps; i++) {
1858 err = register_grp_irqs(&priv->gfargrp[i]);
1859 if (err) {
1860 for (j = 0; j < i; j++)
1861 free_grp_irqs(&priv->gfargrp[j]);
1862 goto irq_fail;
1863 }
1864 }
1865
1866 /* Start the controller */
1867 gfar_start(ndev);
1868
1869 phy_start(priv->phydev);
1870
1871 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1872
1873 return 0;
1874
1875 irq_fail:
1876 free_skb_resources(priv);
1877 return err;
1878 }
1879
1880 /* Called when something needs to use the ethernet device */
1881 /* Returns 0 for success. */
1882 static int gfar_enet_open(struct net_device *dev)
1883 {
1884 struct gfar_private *priv = netdev_priv(dev);
1885 int err;
1886
1887 enable_napi(priv);
1888
1889 skb_queue_head_init(&priv->rx_recycle);
1890
1891 /* Initialize a bunch of registers */
1892 init_registers(dev);
1893
1894 gfar_set_mac_address(dev);
1895
1896 err = init_phy(dev);
1897
1898 if (err) {
1899 disable_napi(priv);
1900 return err;
1901 }
1902
1903 err = startup_gfar(dev);
1904 if (err) {
1905 disable_napi(priv);
1906 return err;
1907 }
1908
1909 netif_tx_start_all_queues(dev);
1910
1911 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1912
1913 return err;
1914 }
1915
1916 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1917 {
1918 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1919
1920 memset(fcb, 0, GMAC_FCB_LEN);
1921
1922 return fcb;
1923 }
1924
1925 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1926 {
1927 u8 flags = 0;
1928
1929 /* If we're here, it's a IP packet with a TCP or UDP
1930 * payload. We set it to checksum, using a pseudo-header
1931 * we provide
1932 */
1933 flags = TXFCB_DEFAULT;
1934
1935 /* Tell the controller what the protocol is */
1936 /* And provide the already calculated phcs */
1937 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1938 flags |= TXFCB_UDP;
1939 fcb->phcs = udp_hdr(skb)->check;
1940 } else
1941 fcb->phcs = tcp_hdr(skb)->check;
1942
1943 /* l3os is the distance between the start of the
1944 * frame (skb->data) and the start of the IP hdr.
1945 * l4os is the distance between the start of the
1946 * l3 hdr and the l4 hdr */
1947 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1948 fcb->l4os = skb_network_header_len(skb);
1949
1950 fcb->flags = flags;
1951 }
1952
1953 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1954 {
1955 fcb->flags |= TXFCB_VLN;
1956 fcb->vlctl = vlan_tx_tag_get(skb);
1957 }
1958
1959 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1960 struct txbd8 *base, int ring_size)
1961 {
1962 struct txbd8 *new_bd = bdp + stride;
1963
1964 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1965 }
1966
1967 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1968 int ring_size)
1969 {
1970 return skip_txbd(bdp, 1, base, ring_size);
1971 }
1972
1973 /* This is called by the kernel when a frame is ready for transmission. */
1974 /* It is pointed to by the dev->hard_start_xmit function pointer */
1975 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1976 {
1977 struct gfar_private *priv = netdev_priv(dev);
1978 struct gfar_priv_tx_q *tx_queue = NULL;
1979 struct netdev_queue *txq;
1980 struct gfar __iomem *regs = NULL;
1981 struct txfcb *fcb = NULL;
1982 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1983 u32 lstatus;
1984 int i, rq = 0, do_tstamp = 0;
1985 u32 bufaddr;
1986 unsigned long flags;
1987 unsigned int nr_frags, nr_txbds, length;
1988 union skb_shared_tx *shtx;
1989
1990 rq = skb->queue_mapping;
1991 tx_queue = priv->tx_queue[rq];
1992 txq = netdev_get_tx_queue(dev, rq);
1993 base = tx_queue->tx_bd_base;
1994 regs = tx_queue->grp->regs;
1995 shtx = skb_tx(skb);
1996
1997 /* check if time stamp should be generated */
1998 if (unlikely(shtx->hardware && priv->hwts_tx_en))
1999 do_tstamp = 1;
2000
2001 /* make space for additional header when fcb is needed */
2002 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2003 (priv->vlgrp && vlan_tx_tag_present(skb)) ||
2004 unlikely(do_tstamp)) &&
2005 (skb_headroom(skb) < GMAC_FCB_LEN)) {
2006 struct sk_buff *skb_new;
2007
2008 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2009 if (!skb_new) {
2010 dev->stats.tx_errors++;
2011 kfree_skb(skb);
2012 return NETDEV_TX_OK;
2013 }
2014 kfree_skb(skb);
2015 skb = skb_new;
2016 }
2017
2018 /* total number of fragments in the SKB */
2019 nr_frags = skb_shinfo(skb)->nr_frags;
2020
2021 /* calculate the required number of TxBDs for this skb */
2022 if (unlikely(do_tstamp))
2023 nr_txbds = nr_frags + 2;
2024 else
2025 nr_txbds = nr_frags + 1;
2026
2027 /* check if there is space to queue this packet */
2028 if (nr_txbds > tx_queue->num_txbdfree) {
2029 /* no space, stop the queue */
2030 netif_tx_stop_queue(txq);
2031 dev->stats.tx_fifo_errors++;
2032 return NETDEV_TX_BUSY;
2033 }
2034
2035 /* Update transmit stats */
2036 txq->tx_bytes += skb->len;
2037 txq->tx_packets ++;
2038
2039 txbdp = txbdp_start = tx_queue->cur_tx;
2040 lstatus = txbdp->lstatus;
2041
2042 /* Time stamp insertion requires one additional TxBD */
2043 if (unlikely(do_tstamp))
2044 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2045 tx_queue->tx_ring_size);
2046
2047 if (nr_frags == 0) {
2048 if (unlikely(do_tstamp))
2049 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2050 TXBD_INTERRUPT);
2051 else
2052 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2053 } else {
2054 /* Place the fragment addresses and lengths into the TxBDs */
2055 for (i = 0; i < nr_frags; i++) {
2056 /* Point at the next BD, wrapping as needed */
2057 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2058
2059 length = skb_shinfo(skb)->frags[i].size;
2060
2061 lstatus = txbdp->lstatus | length |
2062 BD_LFLAG(TXBD_READY);
2063
2064 /* Handle the last BD specially */
2065 if (i == nr_frags - 1)
2066 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2067
2068 bufaddr = dma_map_page(&priv->ofdev->dev,
2069 skb_shinfo(skb)->frags[i].page,
2070 skb_shinfo(skb)->frags[i].page_offset,
2071 length,
2072 DMA_TO_DEVICE);
2073
2074 /* set the TxBD length and buffer pointer */
2075 txbdp->bufPtr = bufaddr;
2076 txbdp->lstatus = lstatus;
2077 }
2078
2079 lstatus = txbdp_start->lstatus;
2080 }
2081
2082 /* Set up checksumming */
2083 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2084 fcb = gfar_add_fcb(skb);
2085 lstatus |= BD_LFLAG(TXBD_TOE);
2086 gfar_tx_checksum(skb, fcb);
2087 }
2088
2089 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
2090 if (unlikely(NULL == fcb)) {
2091 fcb = gfar_add_fcb(skb);
2092 lstatus |= BD_LFLAG(TXBD_TOE);
2093 }
2094
2095 gfar_tx_vlan(skb, fcb);
2096 }
2097
2098 /* Setup tx hardware time stamping if requested */
2099 if (unlikely(do_tstamp)) {
2100 shtx->in_progress = 1;
2101 if (fcb == NULL)
2102 fcb = gfar_add_fcb(skb);
2103 fcb->ptp = 1;
2104 lstatus |= BD_LFLAG(TXBD_TOE);
2105 }
2106
2107 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2108 skb_headlen(skb), DMA_TO_DEVICE);
2109
2110 /*
2111 * If time stamping is requested one additional TxBD must be set up. The
2112 * first TxBD points to the FCB and must have a data length of
2113 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2114 * the full frame length.
2115 */
2116 if (unlikely(do_tstamp)) {
2117 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2118 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2119 (skb_headlen(skb) - GMAC_FCB_LEN);
2120 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2121 } else {
2122 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2123 }
2124
2125 /*
2126 * We can work in parallel with gfar_clean_tx_ring(), except
2127 * when modifying num_txbdfree. Note that we didn't grab the lock
2128 * when we were reading the num_txbdfree and checking for available
2129 * space, that's because outside of this function it can only grow,
2130 * and once we've got needed space, it cannot suddenly disappear.
2131 *
2132 * The lock also protects us from gfar_error(), which can modify
2133 * regs->tstat and thus retrigger the transfers, which is why we
2134 * also must grab the lock before setting ready bit for the first
2135 * to be transmitted BD.
2136 */
2137 spin_lock_irqsave(&tx_queue->txlock, flags);
2138
2139 /*
2140 * The powerpc-specific eieio() is used, as wmb() has too strong
2141 * semantics (it requires synchronization between cacheable and
2142 * uncacheable mappings, which eieio doesn't provide and which we
2143 * don't need), thus requiring a more expensive sync instruction. At
2144 * some point, the set of architecture-independent barrier functions
2145 * should be expanded to include weaker barriers.
2146 */
2147 eieio();
2148
2149 txbdp_start->lstatus = lstatus;
2150
2151 eieio(); /* force lstatus write before tx_skbuff */
2152
2153 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2154
2155 /* Update the current skb pointer to the next entry we will use
2156 * (wrapping if necessary) */
2157 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2158 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2159
2160 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2161
2162 /* reduce TxBD free count */
2163 tx_queue->num_txbdfree -= (nr_txbds);
2164
2165 /* If the next BD still needs to be cleaned up, then the bds
2166 are full. We need to tell the kernel to stop sending us stuff. */
2167 if (!tx_queue->num_txbdfree) {
2168 netif_tx_stop_queue(txq);
2169
2170 dev->stats.tx_fifo_errors++;
2171 }
2172
2173 /* Tell the DMA to go go go */
2174 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2175
2176 /* Unlock priv */
2177 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2178
2179 return NETDEV_TX_OK;
2180 }
2181
2182 /* Stops the kernel queue, and halts the controller */
2183 static int gfar_close(struct net_device *dev)
2184 {
2185 struct gfar_private *priv = netdev_priv(dev);
2186
2187 disable_napi(priv);
2188
2189 cancel_work_sync(&priv->reset_task);
2190 stop_gfar(dev);
2191
2192 /* Disconnect from the PHY */
2193 phy_disconnect(priv->phydev);
2194 priv->phydev = NULL;
2195
2196 netif_tx_stop_all_queues(dev);
2197
2198 return 0;
2199 }
2200
2201 /* Changes the mac address if the controller is not running. */
2202 static int gfar_set_mac_address(struct net_device *dev)
2203 {
2204 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2205
2206 return 0;
2207 }
2208
2209
2210 /* Enables and disables VLAN insertion/extraction */
2211 static void gfar_vlan_rx_register(struct net_device *dev,
2212 struct vlan_group *grp)
2213 {
2214 struct gfar_private *priv = netdev_priv(dev);
2215 struct gfar __iomem *regs = NULL;
2216 unsigned long flags;
2217 u32 tempval;
2218
2219 regs = priv->gfargrp[0].regs;
2220 local_irq_save(flags);
2221 lock_rx_qs(priv);
2222
2223 priv->vlgrp = grp;
2224
2225 if (grp) {
2226 /* Enable VLAN tag insertion */
2227 tempval = gfar_read(&regs->tctrl);
2228 tempval |= TCTRL_VLINS;
2229
2230 gfar_write(&regs->tctrl, tempval);
2231
2232 /* Enable VLAN tag extraction */
2233 tempval = gfar_read(&regs->rctrl);
2234 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2235 gfar_write(&regs->rctrl, tempval);
2236 } else {
2237 /* Disable VLAN tag insertion */
2238 tempval = gfar_read(&regs->tctrl);
2239 tempval &= ~TCTRL_VLINS;
2240 gfar_write(&regs->tctrl, tempval);
2241
2242 /* Disable VLAN tag extraction */
2243 tempval = gfar_read(&regs->rctrl);
2244 tempval &= ~RCTRL_VLEX;
2245 /* If parse is no longer required, then disable parser */
2246 if (tempval & RCTRL_REQ_PARSER)
2247 tempval |= RCTRL_PRSDEP_INIT;
2248 else
2249 tempval &= ~RCTRL_PRSDEP_INIT;
2250 gfar_write(&regs->rctrl, tempval);
2251 }
2252
2253 gfar_change_mtu(dev, dev->mtu);
2254
2255 unlock_rx_qs(priv);
2256 local_irq_restore(flags);
2257 }
2258
2259 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2260 {
2261 int tempsize, tempval;
2262 struct gfar_private *priv = netdev_priv(dev);
2263 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2264 int oldsize = priv->rx_buffer_size;
2265 int frame_size = new_mtu + ETH_HLEN;
2266
2267 if (priv->vlgrp)
2268 frame_size += VLAN_HLEN;
2269
2270 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2271 if (netif_msg_drv(priv))
2272 printk(KERN_ERR "%s: Invalid MTU setting\n",
2273 dev->name);
2274 return -EINVAL;
2275 }
2276
2277 if (gfar_uses_fcb(priv))
2278 frame_size += GMAC_FCB_LEN;
2279
2280 frame_size += priv->padding;
2281
2282 tempsize =
2283 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2284 INCREMENTAL_BUFFER_SIZE;
2285
2286 /* Only stop and start the controller if it isn't already
2287 * stopped, and we changed something */
2288 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2289 stop_gfar(dev);
2290
2291 priv->rx_buffer_size = tempsize;
2292
2293 dev->mtu = new_mtu;
2294
2295 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2296 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2297
2298 /* If the mtu is larger than the max size for standard
2299 * ethernet frames (ie, a jumbo frame), then set maccfg2
2300 * to allow huge frames, and to check the length */
2301 tempval = gfar_read(&regs->maccfg2);
2302
2303 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2304 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2305 else
2306 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2307
2308 gfar_write(&regs->maccfg2, tempval);
2309
2310 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2311 startup_gfar(dev);
2312
2313 return 0;
2314 }
2315
2316 /* gfar_reset_task gets scheduled when a packet has not been
2317 * transmitted after a set amount of time.
2318 * For now, assume that clearing out all the structures, and
2319 * starting over will fix the problem.
2320 */
2321 static void gfar_reset_task(struct work_struct *work)
2322 {
2323 struct gfar_private *priv = container_of(work, struct gfar_private,
2324 reset_task);
2325 struct net_device *dev = priv->ndev;
2326
2327 if (dev->flags & IFF_UP) {
2328 netif_tx_stop_all_queues(dev);
2329 stop_gfar(dev);
2330 startup_gfar(dev);
2331 netif_tx_start_all_queues(dev);
2332 }
2333
2334 netif_tx_schedule_all(dev);
2335 }
2336
2337 static void gfar_timeout(struct net_device *dev)
2338 {
2339 struct gfar_private *priv = netdev_priv(dev);
2340
2341 dev->stats.tx_errors++;
2342 schedule_work(&priv->reset_task);
2343 }
2344
2345 /* Interrupt Handler for Transmit complete */
2346 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2347 {
2348 struct net_device *dev = tx_queue->dev;
2349 struct gfar_private *priv = netdev_priv(dev);
2350 struct gfar_priv_rx_q *rx_queue = NULL;
2351 struct txbd8 *bdp, *next = NULL;
2352 struct txbd8 *lbdp = NULL;
2353 struct txbd8 *base = tx_queue->tx_bd_base;
2354 struct sk_buff *skb;
2355 int skb_dirtytx;
2356 int tx_ring_size = tx_queue->tx_ring_size;
2357 int frags = 0, nr_txbds = 0;
2358 int i;
2359 int howmany = 0;
2360 u32 lstatus;
2361 size_t buflen;
2362 union skb_shared_tx *shtx;
2363
2364 rx_queue = priv->rx_queue[tx_queue->qindex];
2365 bdp = tx_queue->dirty_tx;
2366 skb_dirtytx = tx_queue->skb_dirtytx;
2367
2368 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2369 unsigned long flags;
2370
2371 frags = skb_shinfo(skb)->nr_frags;
2372
2373 /*
2374 * When time stamping, one additional TxBD must be freed.
2375 * Also, we need to dma_unmap_single() the TxPAL.
2376 */
2377 shtx = skb_tx(skb);
2378 if (unlikely(shtx->in_progress))
2379 nr_txbds = frags + 2;
2380 else
2381 nr_txbds = frags + 1;
2382
2383 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2384
2385 lstatus = lbdp->lstatus;
2386
2387 /* Only clean completed frames */
2388 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2389 (lstatus & BD_LENGTH_MASK))
2390 break;
2391
2392 if (unlikely(shtx->in_progress)) {
2393 next = next_txbd(bdp, base, tx_ring_size);
2394 buflen = next->length + GMAC_FCB_LEN;
2395 } else
2396 buflen = bdp->length;
2397
2398 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2399 buflen, DMA_TO_DEVICE);
2400
2401 if (unlikely(shtx->in_progress)) {
2402 struct skb_shared_hwtstamps shhwtstamps;
2403 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2404 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2405 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2406 skb_tstamp_tx(skb, &shhwtstamps);
2407 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2408 bdp = next;
2409 }
2410
2411 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2412 bdp = next_txbd(bdp, base, tx_ring_size);
2413
2414 for (i = 0; i < frags; i++) {
2415 dma_unmap_page(&priv->ofdev->dev,
2416 bdp->bufPtr,
2417 bdp->length,
2418 DMA_TO_DEVICE);
2419 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2420 bdp = next_txbd(bdp, base, tx_ring_size);
2421 }
2422
2423 /*
2424 * If there's room in the queue (limit it to rx_buffer_size)
2425 * we add this skb back into the pool, if it's the right size
2426 */
2427 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2428 skb_recycle_check(skb, priv->rx_buffer_size +
2429 RXBUF_ALIGNMENT))
2430 __skb_queue_head(&priv->rx_recycle, skb);
2431 else
2432 dev_kfree_skb_any(skb);
2433
2434 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2435
2436 skb_dirtytx = (skb_dirtytx + 1) &
2437 TX_RING_MOD_MASK(tx_ring_size);
2438
2439 howmany++;
2440 spin_lock_irqsave(&tx_queue->txlock, flags);
2441 tx_queue->num_txbdfree += nr_txbds;
2442 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2443 }
2444
2445 /* If we freed a buffer, we can restart transmission, if necessary */
2446 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2447 netif_wake_subqueue(dev, tx_queue->qindex);
2448
2449 /* Update dirty indicators */
2450 tx_queue->skb_dirtytx = skb_dirtytx;
2451 tx_queue->dirty_tx = bdp;
2452
2453 return howmany;
2454 }
2455
2456 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2457 {
2458 unsigned long flags;
2459
2460 spin_lock_irqsave(&gfargrp->grplock, flags);
2461 if (napi_schedule_prep(&gfargrp->napi)) {
2462 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2463 __napi_schedule(&gfargrp->napi);
2464 } else {
2465 /*
2466 * Clear IEVENT, so interrupts aren't called again
2467 * because of the packets that have already arrived.
2468 */
2469 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2470 }
2471 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2472
2473 }
2474
2475 /* Interrupt Handler for Transmit complete */
2476 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2477 {
2478 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2479 return IRQ_HANDLED;
2480 }
2481
2482 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2483 struct sk_buff *skb)
2484 {
2485 struct net_device *dev = rx_queue->dev;
2486 struct gfar_private *priv = netdev_priv(dev);
2487 dma_addr_t buf;
2488
2489 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2490 priv->rx_buffer_size, DMA_FROM_DEVICE);
2491 gfar_init_rxbdp(rx_queue, bdp, buf);
2492 }
2493
2494
2495 struct sk_buff * gfar_new_skb(struct net_device *dev)
2496 {
2497 unsigned int alignamount;
2498 struct gfar_private *priv = netdev_priv(dev);
2499 struct sk_buff *skb = NULL;
2500
2501 skb = __skb_dequeue(&priv->rx_recycle);
2502 if (!skb)
2503 skb = netdev_alloc_skb(dev,
2504 priv->rx_buffer_size + RXBUF_ALIGNMENT);
2505
2506 if (!skb)
2507 return NULL;
2508
2509 alignamount = RXBUF_ALIGNMENT -
2510 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
2511
2512 /* We need the data buffer to be aligned properly. We will reserve
2513 * as many bytes as needed to align the data properly
2514 */
2515 skb_reserve(skb, alignamount);
2516 GFAR_CB(skb)->alignamount = alignamount;
2517
2518 return skb;
2519 }
2520
2521 static inline void count_errors(unsigned short status, struct net_device *dev)
2522 {
2523 struct gfar_private *priv = netdev_priv(dev);
2524 struct net_device_stats *stats = &dev->stats;
2525 struct gfar_extra_stats *estats = &priv->extra_stats;
2526
2527 /* If the packet was truncated, none of the other errors
2528 * matter */
2529 if (status & RXBD_TRUNCATED) {
2530 stats->rx_length_errors++;
2531
2532 estats->rx_trunc++;
2533
2534 return;
2535 }
2536 /* Count the errors, if there were any */
2537 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2538 stats->rx_length_errors++;
2539
2540 if (status & RXBD_LARGE)
2541 estats->rx_large++;
2542 else
2543 estats->rx_short++;
2544 }
2545 if (status & RXBD_NONOCTET) {
2546 stats->rx_frame_errors++;
2547 estats->rx_nonoctet++;
2548 }
2549 if (status & RXBD_CRCERR) {
2550 estats->rx_crcerr++;
2551 stats->rx_crc_errors++;
2552 }
2553 if (status & RXBD_OVERRUN) {
2554 estats->rx_overrun++;
2555 stats->rx_crc_errors++;
2556 }
2557 }
2558
2559 irqreturn_t gfar_receive(int irq, void *grp_id)
2560 {
2561 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2562 return IRQ_HANDLED;
2563 }
2564
2565 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2566 {
2567 /* If valid headers were found, and valid sums
2568 * were verified, then we tell the kernel that no
2569 * checksumming is necessary. Otherwise, it is */
2570 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2571 skb->ip_summed = CHECKSUM_UNNECESSARY;
2572 else
2573 skb->ip_summed = CHECKSUM_NONE;
2574 }
2575
2576
2577 /* gfar_process_frame() -- handle one incoming packet if skb
2578 * isn't NULL. */
2579 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2580 int amount_pull)
2581 {
2582 struct gfar_private *priv = netdev_priv(dev);
2583 struct rxfcb *fcb = NULL;
2584
2585 int ret;
2586
2587 /* fcb is at the beginning if exists */
2588 fcb = (struct rxfcb *)skb->data;
2589
2590 /* Remove the FCB from the skb */
2591 /* Remove the padded bytes, if there are any */
2592 if (amount_pull) {
2593 skb_record_rx_queue(skb, fcb->rq);
2594 skb_pull(skb, amount_pull);
2595 }
2596
2597 /* Get receive timestamp from the skb */
2598 if (priv->hwts_rx_en) {
2599 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2600 u64 *ns = (u64 *) skb->data;
2601 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2602 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2603 }
2604
2605 if (priv->padding)
2606 skb_pull(skb, priv->padding);
2607
2608 if (priv->rx_csum_enable)
2609 gfar_rx_checksum(skb, fcb);
2610
2611 /* Tell the skb what kind of packet this is */
2612 skb->protocol = eth_type_trans(skb, dev);
2613
2614 /* Send the packet up the stack */
2615 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2616 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2617 else
2618 ret = netif_receive_skb(skb);
2619
2620 if (NET_RX_DROP == ret)
2621 priv->extra_stats.kernel_dropped++;
2622
2623 return 0;
2624 }
2625
2626 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2627 * until the budget/quota has been reached. Returns the number
2628 * of frames handled
2629 */
2630 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2631 {
2632 struct net_device *dev = rx_queue->dev;
2633 struct rxbd8 *bdp, *base;
2634 struct sk_buff *skb;
2635 int pkt_len;
2636 int amount_pull;
2637 int howmany = 0;
2638 struct gfar_private *priv = netdev_priv(dev);
2639
2640 /* Get the first full descriptor */
2641 bdp = rx_queue->cur_rx;
2642 base = rx_queue->rx_bd_base;
2643
2644 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2645
2646 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2647 struct sk_buff *newskb;
2648 rmb();
2649
2650 /* Add another skb for the future */
2651 newskb = gfar_new_skb(dev);
2652
2653 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2654
2655 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2656 priv->rx_buffer_size, DMA_FROM_DEVICE);
2657
2658 /* We drop the frame if we failed to allocate a new buffer */
2659 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2660 bdp->status & RXBD_ERR)) {
2661 count_errors(bdp->status, dev);
2662
2663 if (unlikely(!newskb))
2664 newskb = skb;
2665 else if (skb) {
2666 /*
2667 * We need to un-reserve() the skb to what it
2668 * was before gfar_new_skb() re-aligned
2669 * it to an RXBUF_ALIGNMENT boundary
2670 * before we put the skb back on the
2671 * recycle list.
2672 */
2673 skb_reserve(skb, -GFAR_CB(skb)->alignamount);
2674 __skb_queue_head(&priv->rx_recycle, skb);
2675 }
2676 } else {
2677 /* Increment the number of packets */
2678 rx_queue->stats.rx_packets++;
2679 howmany++;
2680
2681 if (likely(skb)) {
2682 pkt_len = bdp->length - ETH_FCS_LEN;
2683 /* Remove the FCS from the packet length */
2684 skb_put(skb, pkt_len);
2685 rx_queue->stats.rx_bytes += pkt_len;
2686 skb_record_rx_queue(skb, rx_queue->qindex);
2687 gfar_process_frame(dev, skb, amount_pull);
2688
2689 } else {
2690 if (netif_msg_rx_err(priv))
2691 printk(KERN_WARNING
2692 "%s: Missing skb!\n", dev->name);
2693 rx_queue->stats.rx_dropped++;
2694 priv->extra_stats.rx_skbmissing++;
2695 }
2696
2697 }
2698
2699 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2700
2701 /* Setup the new bdp */
2702 gfar_new_rxbdp(rx_queue, bdp, newskb);
2703
2704 /* Update to the next pointer */
2705 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2706
2707 /* update to point at the next skb */
2708 rx_queue->skb_currx =
2709 (rx_queue->skb_currx + 1) &
2710 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2711 }
2712
2713 /* Update the current rxbd pointer to be the next one */
2714 rx_queue->cur_rx = bdp;
2715
2716 return howmany;
2717 }
2718
2719 static int gfar_poll(struct napi_struct *napi, int budget)
2720 {
2721 struct gfar_priv_grp *gfargrp = container_of(napi,
2722 struct gfar_priv_grp, napi);
2723 struct gfar_private *priv = gfargrp->priv;
2724 struct gfar __iomem *regs = gfargrp->regs;
2725 struct gfar_priv_tx_q *tx_queue = NULL;
2726 struct gfar_priv_rx_q *rx_queue = NULL;
2727 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2728 int tx_cleaned = 0, i, left_over_budget = budget;
2729 unsigned long serviced_queues = 0;
2730 int num_queues = 0;
2731
2732 num_queues = gfargrp->num_rx_queues;
2733 budget_per_queue = budget/num_queues;
2734
2735 /* Clear IEVENT, so interrupts aren't called again
2736 * because of the packets that have already arrived */
2737 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2738
2739 while (num_queues && left_over_budget) {
2740
2741 budget_per_queue = left_over_budget/num_queues;
2742 left_over_budget = 0;
2743
2744 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2745 if (test_bit(i, &serviced_queues))
2746 continue;
2747 rx_queue = priv->rx_queue[i];
2748 tx_queue = priv->tx_queue[rx_queue->qindex];
2749
2750 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2751 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2752 budget_per_queue);
2753 rx_cleaned += rx_cleaned_per_queue;
2754 if(rx_cleaned_per_queue < budget_per_queue) {
2755 left_over_budget = left_over_budget +
2756 (budget_per_queue - rx_cleaned_per_queue);
2757 set_bit(i, &serviced_queues);
2758 num_queues--;
2759 }
2760 }
2761 }
2762
2763 if (tx_cleaned)
2764 return budget;
2765
2766 if (rx_cleaned < budget) {
2767 napi_complete(napi);
2768
2769 /* Clear the halt bit in RSTAT */
2770 gfar_write(&regs->rstat, gfargrp->rstat);
2771
2772 gfar_write(&regs->imask, IMASK_DEFAULT);
2773
2774 /* If we are coalescing interrupts, update the timer */
2775 /* Otherwise, clear it */
2776 gfar_configure_coalescing(priv,
2777 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2778 }
2779
2780 return rx_cleaned;
2781 }
2782
2783 #ifdef CONFIG_NET_POLL_CONTROLLER
2784 /*
2785 * Polling 'interrupt' - used by things like netconsole to send skbs
2786 * without having to re-enable interrupts. It's not called while
2787 * the interrupt routine is executing.
2788 */
2789 static void gfar_netpoll(struct net_device *dev)
2790 {
2791 struct gfar_private *priv = netdev_priv(dev);
2792 int i = 0;
2793
2794 /* If the device has multiple interrupts, run tx/rx */
2795 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2796 for (i = 0; i < priv->num_grps; i++) {
2797 disable_irq(priv->gfargrp[i].interruptTransmit);
2798 disable_irq(priv->gfargrp[i].interruptReceive);
2799 disable_irq(priv->gfargrp[i].interruptError);
2800 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2801 &priv->gfargrp[i]);
2802 enable_irq(priv->gfargrp[i].interruptError);
2803 enable_irq(priv->gfargrp[i].interruptReceive);
2804 enable_irq(priv->gfargrp[i].interruptTransmit);
2805 }
2806 } else {
2807 for (i = 0; i < priv->num_grps; i++) {
2808 disable_irq(priv->gfargrp[i].interruptTransmit);
2809 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2810 &priv->gfargrp[i]);
2811 enable_irq(priv->gfargrp[i].interruptTransmit);
2812 }
2813 }
2814 }
2815 #endif
2816
2817 /* The interrupt handler for devices with one interrupt */
2818 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2819 {
2820 struct gfar_priv_grp *gfargrp = grp_id;
2821
2822 /* Save ievent for future reference */
2823 u32 events = gfar_read(&gfargrp->regs->ievent);
2824
2825 /* Check for reception */
2826 if (events & IEVENT_RX_MASK)
2827 gfar_receive(irq, grp_id);
2828
2829 /* Check for transmit completion */
2830 if (events & IEVENT_TX_MASK)
2831 gfar_transmit(irq, grp_id);
2832
2833 /* Check for errors */
2834 if (events & IEVENT_ERR_MASK)
2835 gfar_error(irq, grp_id);
2836
2837 return IRQ_HANDLED;
2838 }
2839
2840 /* Called every time the controller might need to be made
2841 * aware of new link state. The PHY code conveys this
2842 * information through variables in the phydev structure, and this
2843 * function converts those variables into the appropriate
2844 * register values, and can bring down the device if needed.
2845 */
2846 static void adjust_link(struct net_device *dev)
2847 {
2848 struct gfar_private *priv = netdev_priv(dev);
2849 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2850 unsigned long flags;
2851 struct phy_device *phydev = priv->phydev;
2852 int new_state = 0;
2853
2854 local_irq_save(flags);
2855 lock_tx_qs(priv);
2856
2857 if (phydev->link) {
2858 u32 tempval = gfar_read(&regs->maccfg2);
2859 u32 ecntrl = gfar_read(&regs->ecntrl);
2860
2861 /* Now we make sure that we can be in full duplex mode.
2862 * If not, we operate in half-duplex mode. */
2863 if (phydev->duplex != priv->oldduplex) {
2864 new_state = 1;
2865 if (!(phydev->duplex))
2866 tempval &= ~(MACCFG2_FULL_DUPLEX);
2867 else
2868 tempval |= MACCFG2_FULL_DUPLEX;
2869
2870 priv->oldduplex = phydev->duplex;
2871 }
2872
2873 if (phydev->speed != priv->oldspeed) {
2874 new_state = 1;
2875 switch (phydev->speed) {
2876 case 1000:
2877 tempval =
2878 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2879
2880 ecntrl &= ~(ECNTRL_R100);
2881 break;
2882 case 100:
2883 case 10:
2884 tempval =
2885 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2886
2887 /* Reduced mode distinguishes
2888 * between 10 and 100 */
2889 if (phydev->speed == SPEED_100)
2890 ecntrl |= ECNTRL_R100;
2891 else
2892 ecntrl &= ~(ECNTRL_R100);
2893 break;
2894 default:
2895 if (netif_msg_link(priv))
2896 printk(KERN_WARNING
2897 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2898 dev->name, phydev->speed);
2899 break;
2900 }
2901
2902 priv->oldspeed = phydev->speed;
2903 }
2904
2905 gfar_write(&regs->maccfg2, tempval);
2906 gfar_write(&regs->ecntrl, ecntrl);
2907
2908 if (!priv->oldlink) {
2909 new_state = 1;
2910 priv->oldlink = 1;
2911 }
2912 } else if (priv->oldlink) {
2913 new_state = 1;
2914 priv->oldlink = 0;
2915 priv->oldspeed = 0;
2916 priv->oldduplex = -1;
2917 }
2918
2919 if (new_state && netif_msg_link(priv))
2920 phy_print_status(phydev);
2921 unlock_tx_qs(priv);
2922 local_irq_restore(flags);
2923 }
2924
2925 /* Update the hash table based on the current list of multicast
2926 * addresses we subscribe to. Also, change the promiscuity of
2927 * the device based on the flags (this function is called
2928 * whenever dev->flags is changed */
2929 static void gfar_set_multi(struct net_device *dev)
2930 {
2931 struct netdev_hw_addr *ha;
2932 struct gfar_private *priv = netdev_priv(dev);
2933 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2934 u32 tempval;
2935
2936 if (dev->flags & IFF_PROMISC) {
2937 /* Set RCTRL to PROM */
2938 tempval = gfar_read(&regs->rctrl);
2939 tempval |= RCTRL_PROM;
2940 gfar_write(&regs->rctrl, tempval);
2941 } else {
2942 /* Set RCTRL to not PROM */
2943 tempval = gfar_read(&regs->rctrl);
2944 tempval &= ~(RCTRL_PROM);
2945 gfar_write(&regs->rctrl, tempval);
2946 }
2947
2948 if (dev->flags & IFF_ALLMULTI) {
2949 /* Set the hash to rx all multicast frames */
2950 gfar_write(&regs->igaddr0, 0xffffffff);
2951 gfar_write(&regs->igaddr1, 0xffffffff);
2952 gfar_write(&regs->igaddr2, 0xffffffff);
2953 gfar_write(&regs->igaddr3, 0xffffffff);
2954 gfar_write(&regs->igaddr4, 0xffffffff);
2955 gfar_write(&regs->igaddr5, 0xffffffff);
2956 gfar_write(&regs->igaddr6, 0xffffffff);
2957 gfar_write(&regs->igaddr7, 0xffffffff);
2958 gfar_write(&regs->gaddr0, 0xffffffff);
2959 gfar_write(&regs->gaddr1, 0xffffffff);
2960 gfar_write(&regs->gaddr2, 0xffffffff);
2961 gfar_write(&regs->gaddr3, 0xffffffff);
2962 gfar_write(&regs->gaddr4, 0xffffffff);
2963 gfar_write(&regs->gaddr5, 0xffffffff);
2964 gfar_write(&regs->gaddr6, 0xffffffff);
2965 gfar_write(&regs->gaddr7, 0xffffffff);
2966 } else {
2967 int em_num;
2968 int idx;
2969
2970 /* zero out the hash */
2971 gfar_write(&regs->igaddr0, 0x0);
2972 gfar_write(&regs->igaddr1, 0x0);
2973 gfar_write(&regs->igaddr2, 0x0);
2974 gfar_write(&regs->igaddr3, 0x0);
2975 gfar_write(&regs->igaddr4, 0x0);
2976 gfar_write(&regs->igaddr5, 0x0);
2977 gfar_write(&regs->igaddr6, 0x0);
2978 gfar_write(&regs->igaddr7, 0x0);
2979 gfar_write(&regs->gaddr0, 0x0);
2980 gfar_write(&regs->gaddr1, 0x0);
2981 gfar_write(&regs->gaddr2, 0x0);
2982 gfar_write(&regs->gaddr3, 0x0);
2983 gfar_write(&regs->gaddr4, 0x0);
2984 gfar_write(&regs->gaddr5, 0x0);
2985 gfar_write(&regs->gaddr6, 0x0);
2986 gfar_write(&regs->gaddr7, 0x0);
2987
2988 /* If we have extended hash tables, we need to
2989 * clear the exact match registers to prepare for
2990 * setting them */
2991 if (priv->extended_hash) {
2992 em_num = GFAR_EM_NUM + 1;
2993 gfar_clear_exact_match(dev);
2994 idx = 1;
2995 } else {
2996 idx = 0;
2997 em_num = 0;
2998 }
2999
3000 if (netdev_mc_empty(dev))
3001 return;
3002
3003 /* Parse the list, and set the appropriate bits */
3004 netdev_for_each_mc_addr(ha, dev) {
3005 if (idx < em_num) {
3006 gfar_set_mac_for_addr(dev, idx, ha->addr);
3007 idx++;
3008 } else
3009 gfar_set_hash_for_addr(dev, ha->addr);
3010 }
3011 }
3012
3013 return;
3014 }
3015
3016
3017 /* Clears each of the exact match registers to zero, so they
3018 * don't interfere with normal reception */
3019 static void gfar_clear_exact_match(struct net_device *dev)
3020 {
3021 int idx;
3022 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3023
3024 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3025 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3026 }
3027
3028 /* Set the appropriate hash bit for the given addr */
3029 /* The algorithm works like so:
3030 * 1) Take the Destination Address (ie the multicast address), and
3031 * do a CRC on it (little endian), and reverse the bits of the
3032 * result.
3033 * 2) Use the 8 most significant bits as a hash into a 256-entry
3034 * table. The table is controlled through 8 32-bit registers:
3035 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3036 * gaddr7. This means that the 3 most significant bits in the
3037 * hash index which gaddr register to use, and the 5 other bits
3038 * indicate which bit (assuming an IBM numbering scheme, which
3039 * for PowerPC (tm) is usually the case) in the register holds
3040 * the entry. */
3041 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3042 {
3043 u32 tempval;
3044 struct gfar_private *priv = netdev_priv(dev);
3045 u32 result = ether_crc(MAC_ADDR_LEN, addr);
3046 int width = priv->hash_width;
3047 u8 whichbit = (result >> (32 - width)) & 0x1f;
3048 u8 whichreg = result >> (32 - width + 5);
3049 u32 value = (1 << (31-whichbit));
3050
3051 tempval = gfar_read(priv->hash_regs[whichreg]);
3052 tempval |= value;
3053 gfar_write(priv->hash_regs[whichreg], tempval);
3054
3055 return;
3056 }
3057
3058
3059 /* There are multiple MAC Address register pairs on some controllers
3060 * This function sets the numth pair to a given address
3061 */
3062 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3063 {
3064 struct gfar_private *priv = netdev_priv(dev);
3065 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3066 int idx;
3067 char tmpbuf[MAC_ADDR_LEN];
3068 u32 tempval;
3069 u32 __iomem *macptr = &regs->macstnaddr1;
3070
3071 macptr += num*2;
3072
3073 /* Now copy it into the mac registers backwards, cuz */
3074 /* little endian is silly */
3075 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3076 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3077
3078 gfar_write(macptr, *((u32 *) (tmpbuf)));
3079
3080 tempval = *((u32 *) (tmpbuf + 4));
3081
3082 gfar_write(macptr+1, tempval);
3083 }
3084
3085 /* GFAR error interrupt handler */
3086 static irqreturn_t gfar_error(int irq, void *grp_id)
3087 {
3088 struct gfar_priv_grp *gfargrp = grp_id;
3089 struct gfar __iomem *regs = gfargrp->regs;
3090 struct gfar_private *priv= gfargrp->priv;
3091 struct net_device *dev = priv->ndev;
3092
3093 /* Save ievent for future reference */
3094 u32 events = gfar_read(&regs->ievent);
3095
3096 /* Clear IEVENT */
3097 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3098
3099 /* Magic Packet is not an error. */
3100 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3101 (events & IEVENT_MAG))
3102 events &= ~IEVENT_MAG;
3103
3104 /* Hmm... */
3105 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3106 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3107 dev->name, events, gfar_read(&regs->imask));
3108
3109 /* Update the error counters */
3110 if (events & IEVENT_TXE) {
3111 dev->stats.tx_errors++;
3112
3113 if (events & IEVENT_LC)
3114 dev->stats.tx_window_errors++;
3115 if (events & IEVENT_CRL)
3116 dev->stats.tx_aborted_errors++;
3117 if (events & IEVENT_XFUN) {
3118 unsigned long flags;
3119
3120 if (netif_msg_tx_err(priv))
3121 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3122 "packet dropped.\n", dev->name);
3123 dev->stats.tx_dropped++;
3124 priv->extra_stats.tx_underrun++;
3125
3126 local_irq_save(flags);
3127 lock_tx_qs(priv);
3128
3129 /* Reactivate the Tx Queues */
3130 gfar_write(&regs->tstat, gfargrp->tstat);
3131
3132 unlock_tx_qs(priv);
3133 local_irq_restore(flags);
3134 }
3135 if (netif_msg_tx_err(priv))
3136 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3137 }
3138 if (events & IEVENT_BSY) {
3139 dev->stats.rx_errors++;
3140 priv->extra_stats.rx_bsy++;
3141
3142 gfar_receive(irq, grp_id);
3143
3144 if (netif_msg_rx_err(priv))
3145 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3146 dev->name, gfar_read(&regs->rstat));
3147 }
3148 if (events & IEVENT_BABR) {
3149 dev->stats.rx_errors++;
3150 priv->extra_stats.rx_babr++;
3151
3152 if (netif_msg_rx_err(priv))
3153 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3154 }
3155 if (events & IEVENT_EBERR) {
3156 priv->extra_stats.eberr++;
3157 if (netif_msg_rx_err(priv))
3158 printk(KERN_DEBUG "%s: bus error\n", dev->name);
3159 }
3160 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3161 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3162
3163 if (events & IEVENT_BABT) {
3164 priv->extra_stats.tx_babt++;
3165 if (netif_msg_tx_err(priv))
3166 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3167 }
3168 return IRQ_HANDLED;
3169 }
3170
3171 static struct of_device_id gfar_match[] =
3172 {
3173 {
3174 .type = "network",
3175 .compatible = "gianfar",
3176 },
3177 {
3178 .compatible = "fsl,etsec2",
3179 },
3180 {},
3181 };
3182 MODULE_DEVICE_TABLE(of, gfar_match);
3183
3184 /* Structure for a device driver */
3185 static struct of_platform_driver gfar_driver = {
3186 .name = "fsl-gianfar",
3187 .match_table = gfar_match,
3188
3189 .probe = gfar_probe,
3190 .remove = gfar_remove,
3191 .suspend = gfar_legacy_suspend,
3192 .resume = gfar_legacy_resume,
3193 .driver.pm = GFAR_PM_OPS,
3194 };
3195
3196 static int __init gfar_init(void)
3197 {
3198 return of_register_platform_driver(&gfar_driver);
3199 }
3200
3201 static void __exit gfar_exit(void)
3202 {
3203 of_unregister_platform_driver(&gfar_driver);
3204 }
3205
3206 module_init(gfar_init);
3207 module_exit(gfar_exit);
3208
kernel-based virtual machine