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igb: Fix erroneous display of stats by ethtool -S
[linux-2.6/kvm.git] / drivers / net / igb / igb_ethtool.c
bloba6da32f25a834646d3b9b27e23ccb4fe934a0282
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37
38 #include "igb.h"
39
40 enum {NETDEV_STATS, IGB_STATS};
41
42 struct igb_stats {
43 char stat_string[ETH_GSTRING_LEN];
44 int type;
45 int sizeof_stat;
46 int stat_offset;
47 };
48
49 #define IGB_STAT(m) IGB_STATS, \
50 FIELD_SIZEOF(struct igb_adapter, m), \
51 offsetof(struct igb_adapter, m)
52 #define IGB_NETDEV_STAT(m) NETDEV_STATS, \
53 FIELD_SIZEOF(struct net_device, m), \
54 offsetof(struct net_device, m)
55
56 static const struct igb_stats igb_gstrings_stats[] = {
57 { "rx_packets", IGB_STAT(stats.gprc) },
58 { "tx_packets", IGB_STAT(stats.gptc) },
59 { "rx_bytes", IGB_STAT(stats.gorc) },
60 { "tx_bytes", IGB_STAT(stats.gotc) },
61 { "rx_broadcast", IGB_STAT(stats.bprc) },
62 { "tx_broadcast", IGB_STAT(stats.bptc) },
63 { "rx_multicast", IGB_STAT(stats.mprc) },
64 { "tx_multicast", IGB_STAT(stats.mptc) },
65 { "rx_errors", IGB_NETDEV_STAT(stats.rx_errors) },
66 { "tx_errors", IGB_NETDEV_STAT(stats.tx_errors) },
67 { "tx_dropped", IGB_NETDEV_STAT(stats.tx_dropped) },
68 { "multicast", IGB_STAT(stats.mprc) },
69 { "collisions", IGB_STAT(stats.colc) },
70 { "rx_length_errors", IGB_NETDEV_STAT(stats.rx_length_errors) },
71 { "rx_over_errors", IGB_NETDEV_STAT(stats.rx_over_errors) },
72 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
73 { "rx_frame_errors", IGB_NETDEV_STAT(stats.rx_frame_errors) },
74 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
75 { "rx_queue_drop_packet_count", IGB_NETDEV_STAT(stats.rx_fifo_errors) },
76 { "rx_missed_errors", IGB_STAT(stats.mpc) },
77 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
78 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
79 { "tx_fifo_errors", IGB_NETDEV_STAT(stats.tx_fifo_errors) },
80 { "tx_heartbeat_errors", IGB_NETDEV_STAT(stats.tx_heartbeat_errors) },
81 { "tx_window_errors", IGB_STAT(stats.latecol) },
82 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
83 { "tx_deferred_ok", IGB_STAT(stats.dc) },
84 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
85 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
86 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
87 { "tx_restart_queue", IGB_STAT(restart_queue) },
88 { "rx_long_length_errors", IGB_STAT(stats.roc) },
89 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
90 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
91 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
92 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
93 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
94 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
95 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
96 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
97 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
98 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
99 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
100 { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
101 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
102 { "tx_smbus", IGB_STAT(stats.mgptc) },
103 { "rx_smbus", IGB_STAT(stats.mgprc) },
104 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
105 };
106
107 #define IGB_QUEUE_STATS_LEN \
108 (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
109 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
110 ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
111 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
112 #define IGB_GLOBAL_STATS_LEN \
113 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
114 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
115 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
116 "Register test (offline)", "Eeprom test (offline)",
117 "Interrupt test (offline)", "Loopback test (offline)",
118 "Link test (on/offline)"
119 };
120 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
121
122 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
123 {
124 struct igb_adapter *adapter = netdev_priv(netdev);
125 struct e1000_hw *hw = &adapter->hw;
126
127 if (hw->phy.media_type == e1000_media_type_copper) {
128
129 ecmd->supported = (SUPPORTED_10baseT_Half |
130 SUPPORTED_10baseT_Full |
131 SUPPORTED_100baseT_Half |
132 SUPPORTED_100baseT_Full |
133 SUPPORTED_1000baseT_Full|
134 SUPPORTED_Autoneg |
135 SUPPORTED_TP);
136 ecmd->advertising = ADVERTISED_TP;
137
138 if (hw->mac.autoneg == 1) {
139 ecmd->advertising |= ADVERTISED_Autoneg;
140 /* the e1000 autoneg seems to match ethtool nicely */
141 ecmd->advertising |= hw->phy.autoneg_advertised;
142 }
143
144 ecmd->port = PORT_TP;
145 ecmd->phy_address = hw->phy.addr;
146 } else {
147 ecmd->supported = (SUPPORTED_1000baseT_Full |
148 SUPPORTED_FIBRE |
149 SUPPORTED_Autoneg);
150
151 ecmd->advertising = (ADVERTISED_1000baseT_Full |
152 ADVERTISED_FIBRE |
153 ADVERTISED_Autoneg);
154
155 ecmd->port = PORT_FIBRE;
156 }
157
158 ecmd->transceiver = XCVR_INTERNAL;
159
160 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
161
162 adapter->hw.mac.ops.get_speed_and_duplex(hw,
163 &adapter->link_speed,
164 &adapter->link_duplex);
165 ecmd->speed = adapter->link_speed;
166
167 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
168 * and HALF_DUPLEX != DUPLEX_HALF */
169
170 if (adapter->link_duplex == FULL_DUPLEX)
171 ecmd->duplex = DUPLEX_FULL;
172 else
173 ecmd->duplex = DUPLEX_HALF;
174 } else {
175 ecmd->speed = -1;
176 ecmd->duplex = -1;
177 }
178
179 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
180 return 0;
181 }
182
183 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
184 {
185 struct igb_adapter *adapter = netdev_priv(netdev);
186 struct e1000_hw *hw = &adapter->hw;
187
188 /* When SoL/IDER sessions are active, autoneg/speed/duplex
189 * cannot be changed */
190 if (igb_check_reset_block(hw)) {
191 dev_err(&adapter->pdev->dev, "Cannot change link "
192 "characteristics when SoL/IDER is active.\n");
193 return -EINVAL;
194 }
195
196 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
197 msleep(1);
198
199 if (ecmd->autoneg == AUTONEG_ENABLE) {
200 hw->mac.autoneg = 1;
201 hw->phy.autoneg_advertised = ecmd->advertising |
202 ADVERTISED_TP |
203 ADVERTISED_Autoneg;
204 ecmd->advertising = hw->phy.autoneg_advertised;
205 if (adapter->fc_autoneg)
206 hw->fc.requested_mode = e1000_fc_default;
207 } else {
208 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
209 clear_bit(__IGB_RESETTING, &adapter->state);
210 return -EINVAL;
211 }
212 }
213
214 /* reset the link */
215 if (netif_running(adapter->netdev)) {
216 igb_down(adapter);
217 igb_up(adapter);
218 } else
219 igb_reset(adapter);
220
221 clear_bit(__IGB_RESETTING, &adapter->state);
222 return 0;
223 }
224
225 static void igb_get_pauseparam(struct net_device *netdev,
226 struct ethtool_pauseparam *pause)
227 {
228 struct igb_adapter *adapter = netdev_priv(netdev);
229 struct e1000_hw *hw = &adapter->hw;
230
231 pause->autoneg =
232 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
233
234 if (hw->fc.current_mode == e1000_fc_rx_pause)
235 pause->rx_pause = 1;
236 else if (hw->fc.current_mode == e1000_fc_tx_pause)
237 pause->tx_pause = 1;
238 else if (hw->fc.current_mode == e1000_fc_full) {
239 pause->rx_pause = 1;
240 pause->tx_pause = 1;
241 }
242 }
243
244 static int igb_set_pauseparam(struct net_device *netdev,
245 struct ethtool_pauseparam *pause)
246 {
247 struct igb_adapter *adapter = netdev_priv(netdev);
248 struct e1000_hw *hw = &adapter->hw;
249 int retval = 0;
250
251 adapter->fc_autoneg = pause->autoneg;
252
253 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
254 msleep(1);
255
256 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
257 hw->fc.requested_mode = e1000_fc_default;
258 if (netif_running(adapter->netdev)) {
259 igb_down(adapter);
260 igb_up(adapter);
261 } else
262 igb_reset(adapter);
263 } else {
264 if (pause->rx_pause && pause->tx_pause)
265 hw->fc.requested_mode = e1000_fc_full;
266 else if (pause->rx_pause && !pause->tx_pause)
267 hw->fc.requested_mode = e1000_fc_rx_pause;
268 else if (!pause->rx_pause && pause->tx_pause)
269 hw->fc.requested_mode = e1000_fc_tx_pause;
270 else if (!pause->rx_pause && !pause->tx_pause)
271 hw->fc.requested_mode = e1000_fc_none;
272
273 hw->fc.current_mode = hw->fc.requested_mode;
274
275 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
276 igb_force_mac_fc(hw) : igb_setup_link(hw));
277 }
278
279 clear_bit(__IGB_RESETTING, &adapter->state);
280 return retval;
281 }
282
283 static u32 igb_get_rx_csum(struct net_device *netdev)
284 {
285 struct igb_adapter *adapter = netdev_priv(netdev);
286 return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
287 }
288
289 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
290 {
291 struct igb_adapter *adapter = netdev_priv(netdev);
292
293 if (data)
294 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
295 else
296 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
297
298 return 0;
299 }
300
301 static u32 igb_get_tx_csum(struct net_device *netdev)
302 {
303 return (netdev->features & NETIF_F_IP_CSUM) != 0;
304 }
305
306 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
307 {
308 struct igb_adapter *adapter = netdev_priv(netdev);
309
310 if (data) {
311 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
312 if (adapter->hw.mac.type == e1000_82576)
313 netdev->features |= NETIF_F_SCTP_CSUM;
314 } else {
315 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
316 NETIF_F_SCTP_CSUM);
317 }
318
319 return 0;
320 }
321
322 static int igb_set_tso(struct net_device *netdev, u32 data)
323 {
324 struct igb_adapter *adapter = netdev_priv(netdev);
325
326 if (data) {
327 netdev->features |= NETIF_F_TSO;
328 netdev->features |= NETIF_F_TSO6;
329 } else {
330 netdev->features &= ~NETIF_F_TSO;
331 netdev->features &= ~NETIF_F_TSO6;
332 }
333
334 dev_info(&adapter->pdev->dev, "TSO is %s\n",
335 data ? "Enabled" : "Disabled");
336 return 0;
337 }
338
339 static u32 igb_get_msglevel(struct net_device *netdev)
340 {
341 struct igb_adapter *adapter = netdev_priv(netdev);
342 return adapter->msg_enable;
343 }
344
345 static void igb_set_msglevel(struct net_device *netdev, u32 data)
346 {
347 struct igb_adapter *adapter = netdev_priv(netdev);
348 adapter->msg_enable = data;
349 }
350
351 static int igb_get_regs_len(struct net_device *netdev)
352 {
353 #define IGB_REGS_LEN 551
354 return IGB_REGS_LEN * sizeof(u32);
355 }
356
357 static void igb_get_regs(struct net_device *netdev,
358 struct ethtool_regs *regs, void *p)
359 {
360 struct igb_adapter *adapter = netdev_priv(netdev);
361 struct e1000_hw *hw = &adapter->hw;
362 u32 *regs_buff = p;
363 u8 i;
364
365 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
366
367 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
368
369 /* General Registers */
370 regs_buff[0] = rd32(E1000_CTRL);
371 regs_buff[1] = rd32(E1000_STATUS);
372 regs_buff[2] = rd32(E1000_CTRL_EXT);
373 regs_buff[3] = rd32(E1000_MDIC);
374 regs_buff[4] = rd32(E1000_SCTL);
375 regs_buff[5] = rd32(E1000_CONNSW);
376 regs_buff[6] = rd32(E1000_VET);
377 regs_buff[7] = rd32(E1000_LEDCTL);
378 regs_buff[8] = rd32(E1000_PBA);
379 regs_buff[9] = rd32(E1000_PBS);
380 regs_buff[10] = rd32(E1000_FRTIMER);
381 regs_buff[11] = rd32(E1000_TCPTIMER);
382
383 /* NVM Register */
384 regs_buff[12] = rd32(E1000_EECD);
385
386 /* Interrupt */
387 /* Reading EICS for EICR because they read the
388 * same but EICS does not clear on read */
389 regs_buff[13] = rd32(E1000_EICS);
390 regs_buff[14] = rd32(E1000_EICS);
391 regs_buff[15] = rd32(E1000_EIMS);
392 regs_buff[16] = rd32(E1000_EIMC);
393 regs_buff[17] = rd32(E1000_EIAC);
394 regs_buff[18] = rd32(E1000_EIAM);
395 /* Reading ICS for ICR because they read the
396 * same but ICS does not clear on read */
397 regs_buff[19] = rd32(E1000_ICS);
398 regs_buff[20] = rd32(E1000_ICS);
399 regs_buff[21] = rd32(E1000_IMS);
400 regs_buff[22] = rd32(E1000_IMC);
401 regs_buff[23] = rd32(E1000_IAC);
402 regs_buff[24] = rd32(E1000_IAM);
403 regs_buff[25] = rd32(E1000_IMIRVP);
404
405 /* Flow Control */
406 regs_buff[26] = rd32(E1000_FCAL);
407 regs_buff[27] = rd32(E1000_FCAH);
408 regs_buff[28] = rd32(E1000_FCTTV);
409 regs_buff[29] = rd32(E1000_FCRTL);
410 regs_buff[30] = rd32(E1000_FCRTH);
411 regs_buff[31] = rd32(E1000_FCRTV);
412
413 /* Receive */
414 regs_buff[32] = rd32(E1000_RCTL);
415 regs_buff[33] = rd32(E1000_RXCSUM);
416 regs_buff[34] = rd32(E1000_RLPML);
417 regs_buff[35] = rd32(E1000_RFCTL);
418 regs_buff[36] = rd32(E1000_MRQC);
419 regs_buff[37] = rd32(E1000_VT_CTL);
420
421 /* Transmit */
422 regs_buff[38] = rd32(E1000_TCTL);
423 regs_buff[39] = rd32(E1000_TCTL_EXT);
424 regs_buff[40] = rd32(E1000_TIPG);
425 regs_buff[41] = rd32(E1000_DTXCTL);
426
427 /* Wake Up */
428 regs_buff[42] = rd32(E1000_WUC);
429 regs_buff[43] = rd32(E1000_WUFC);
430 regs_buff[44] = rd32(E1000_WUS);
431 regs_buff[45] = rd32(E1000_IPAV);
432 regs_buff[46] = rd32(E1000_WUPL);
433
434 /* MAC */
435 regs_buff[47] = rd32(E1000_PCS_CFG0);
436 regs_buff[48] = rd32(E1000_PCS_LCTL);
437 regs_buff[49] = rd32(E1000_PCS_LSTAT);
438 regs_buff[50] = rd32(E1000_PCS_ANADV);
439 regs_buff[51] = rd32(E1000_PCS_LPAB);
440 regs_buff[52] = rd32(E1000_PCS_NPTX);
441 regs_buff[53] = rd32(E1000_PCS_LPABNP);
442
443 /* Statistics */
444 regs_buff[54] = adapter->stats.crcerrs;
445 regs_buff[55] = adapter->stats.algnerrc;
446 regs_buff[56] = adapter->stats.symerrs;
447 regs_buff[57] = adapter->stats.rxerrc;
448 regs_buff[58] = adapter->stats.mpc;
449 regs_buff[59] = adapter->stats.scc;
450 regs_buff[60] = adapter->stats.ecol;
451 regs_buff[61] = adapter->stats.mcc;
452 regs_buff[62] = adapter->stats.latecol;
453 regs_buff[63] = adapter->stats.colc;
454 regs_buff[64] = adapter->stats.dc;
455 regs_buff[65] = adapter->stats.tncrs;
456 regs_buff[66] = adapter->stats.sec;
457 regs_buff[67] = adapter->stats.htdpmc;
458 regs_buff[68] = adapter->stats.rlec;
459 regs_buff[69] = adapter->stats.xonrxc;
460 regs_buff[70] = adapter->stats.xontxc;
461 regs_buff[71] = adapter->stats.xoffrxc;
462 regs_buff[72] = adapter->stats.xofftxc;
463 regs_buff[73] = adapter->stats.fcruc;
464 regs_buff[74] = adapter->stats.prc64;
465 regs_buff[75] = adapter->stats.prc127;
466 regs_buff[76] = adapter->stats.prc255;
467 regs_buff[77] = adapter->stats.prc511;
468 regs_buff[78] = adapter->stats.prc1023;
469 regs_buff[79] = adapter->stats.prc1522;
470 regs_buff[80] = adapter->stats.gprc;
471 regs_buff[81] = adapter->stats.bprc;
472 regs_buff[82] = adapter->stats.mprc;
473 regs_buff[83] = adapter->stats.gptc;
474 regs_buff[84] = adapter->stats.gorc;
475 regs_buff[86] = adapter->stats.gotc;
476 regs_buff[88] = adapter->stats.rnbc;
477 regs_buff[89] = adapter->stats.ruc;
478 regs_buff[90] = adapter->stats.rfc;
479 regs_buff[91] = adapter->stats.roc;
480 regs_buff[92] = adapter->stats.rjc;
481 regs_buff[93] = adapter->stats.mgprc;
482 regs_buff[94] = adapter->stats.mgpdc;
483 regs_buff[95] = adapter->stats.mgptc;
484 regs_buff[96] = adapter->stats.tor;
485 regs_buff[98] = adapter->stats.tot;
486 regs_buff[100] = adapter->stats.tpr;
487 regs_buff[101] = adapter->stats.tpt;
488 regs_buff[102] = adapter->stats.ptc64;
489 regs_buff[103] = adapter->stats.ptc127;
490 regs_buff[104] = adapter->stats.ptc255;
491 regs_buff[105] = adapter->stats.ptc511;
492 regs_buff[106] = adapter->stats.ptc1023;
493 regs_buff[107] = adapter->stats.ptc1522;
494 regs_buff[108] = adapter->stats.mptc;
495 regs_buff[109] = adapter->stats.bptc;
496 regs_buff[110] = adapter->stats.tsctc;
497 regs_buff[111] = adapter->stats.iac;
498 regs_buff[112] = adapter->stats.rpthc;
499 regs_buff[113] = adapter->stats.hgptc;
500 regs_buff[114] = adapter->stats.hgorc;
501 regs_buff[116] = adapter->stats.hgotc;
502 regs_buff[118] = adapter->stats.lenerrs;
503 regs_buff[119] = adapter->stats.scvpc;
504 regs_buff[120] = adapter->stats.hrmpc;
505
506 /* These should probably be added to e1000_regs.h instead */
507 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
508 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
509 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
510 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
511 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
512 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
513 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
514
515 for (i = 0; i < 4; i++)
516 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
517 for (i = 0; i < 4; i++)
518 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
519 for (i = 0; i < 4; i++)
520 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
521 for (i = 0; i < 4; i++)
522 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
523 for (i = 0; i < 4; i++)
524 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
525 for (i = 0; i < 4; i++)
526 regs_buff[141 + i] = rd32(E1000_RDH(i));
527 for (i = 0; i < 4; i++)
528 regs_buff[145 + i] = rd32(E1000_RDT(i));
529 for (i = 0; i < 4; i++)
530 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
531
532 for (i = 0; i < 10; i++)
533 regs_buff[153 + i] = rd32(E1000_EITR(i));
534 for (i = 0; i < 8; i++)
535 regs_buff[163 + i] = rd32(E1000_IMIR(i));
536 for (i = 0; i < 8; i++)
537 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
538 for (i = 0; i < 16; i++)
539 regs_buff[179 + i] = rd32(E1000_RAL(i));
540 for (i = 0; i < 16; i++)
541 regs_buff[195 + i] = rd32(E1000_RAH(i));
542
543 for (i = 0; i < 4; i++)
544 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
545 for (i = 0; i < 4; i++)
546 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
547 for (i = 0; i < 4; i++)
548 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
549 for (i = 0; i < 4; i++)
550 regs_buff[223 + i] = rd32(E1000_TDH(i));
551 for (i = 0; i < 4; i++)
552 regs_buff[227 + i] = rd32(E1000_TDT(i));
553 for (i = 0; i < 4; i++)
554 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
555 for (i = 0; i < 4; i++)
556 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
557 for (i = 0; i < 4; i++)
558 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
559 for (i = 0; i < 4; i++)
560 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
561
562 for (i = 0; i < 4; i++)
563 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
564 for (i = 0; i < 4; i++)
565 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
566 for (i = 0; i < 32; i++)
567 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
568 for (i = 0; i < 128; i++)
569 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
570 for (i = 0; i < 128; i++)
571 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
572 for (i = 0; i < 4; i++)
573 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
574
575 regs_buff[547] = rd32(E1000_TDFH);
576 regs_buff[548] = rd32(E1000_TDFT);
577 regs_buff[549] = rd32(E1000_TDFHS);
578 regs_buff[550] = rd32(E1000_TDFPC);
579
580 }
581
582 static int igb_get_eeprom_len(struct net_device *netdev)
583 {
584 struct igb_adapter *adapter = netdev_priv(netdev);
585 return adapter->hw.nvm.word_size * 2;
586 }
587
588 static int igb_get_eeprom(struct net_device *netdev,
589 struct ethtool_eeprom *eeprom, u8 *bytes)
590 {
591 struct igb_adapter *adapter = netdev_priv(netdev);
592 struct e1000_hw *hw = &adapter->hw;
593 u16 *eeprom_buff;
594 int first_word, last_word;
595 int ret_val = 0;
596 u16 i;
597
598 if (eeprom->len == 0)
599 return -EINVAL;
600
601 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
602
603 first_word = eeprom->offset >> 1;
604 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
605
606 eeprom_buff = kmalloc(sizeof(u16) *
607 (last_word - first_word + 1), GFP_KERNEL);
608 if (!eeprom_buff)
609 return -ENOMEM;
610
611 if (hw->nvm.type == e1000_nvm_eeprom_spi)
612 ret_val = hw->nvm.ops.read(hw, first_word,
613 last_word - first_word + 1,
614 eeprom_buff);
615 else {
616 for (i = 0; i < last_word - first_word + 1; i++) {
617 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
618 &eeprom_buff[i]);
619 if (ret_val)
620 break;
621 }
622 }
623
624 /* Device's eeprom is always little-endian, word addressable */
625 for (i = 0; i < last_word - first_word + 1; i++)
626 le16_to_cpus(&eeprom_buff[i]);
627
628 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
629 eeprom->len);
630 kfree(eeprom_buff);
631
632 return ret_val;
633 }
634
635 static int igb_set_eeprom(struct net_device *netdev,
636 struct ethtool_eeprom *eeprom, u8 *bytes)
637 {
638 struct igb_adapter *adapter = netdev_priv(netdev);
639 struct e1000_hw *hw = &adapter->hw;
640 u16 *eeprom_buff;
641 void *ptr;
642 int max_len, first_word, last_word, ret_val = 0;
643 u16 i;
644
645 if (eeprom->len == 0)
646 return -EOPNOTSUPP;
647
648 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
649 return -EFAULT;
650
651 max_len = hw->nvm.word_size * 2;
652
653 first_word = eeprom->offset >> 1;
654 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
655 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
656 if (!eeprom_buff)
657 return -ENOMEM;
658
659 ptr = (void *)eeprom_buff;
660
661 if (eeprom->offset & 1) {
662 /* need read/modify/write of first changed EEPROM word */
663 /* only the second byte of the word is being modified */
664 ret_val = hw->nvm.ops.read(hw, first_word, 1,
665 &eeprom_buff[0]);
666 ptr++;
667 }
668 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
669 /* need read/modify/write of last changed EEPROM word */
670 /* only the first byte of the word is being modified */
671 ret_val = hw->nvm.ops.read(hw, last_word, 1,
672 &eeprom_buff[last_word - first_word]);
673 }
674
675 /* Device's eeprom is always little-endian, word addressable */
676 for (i = 0; i < last_word - first_word + 1; i++)
677 le16_to_cpus(&eeprom_buff[i]);
678
679 memcpy(ptr, bytes, eeprom->len);
680
681 for (i = 0; i < last_word - first_word + 1; i++)
682 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
683
684 ret_val = hw->nvm.ops.write(hw, first_word,
685 last_word - first_word + 1, eeprom_buff);
686
687 /* Update the checksum over the first part of the EEPROM if needed
688 * and flush shadow RAM for 82573 controllers */
689 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
690 igb_update_nvm_checksum(hw);
691
692 kfree(eeprom_buff);
693 return ret_val;
694 }
695
696 static void igb_get_drvinfo(struct net_device *netdev,
697 struct ethtool_drvinfo *drvinfo)
698 {
699 struct igb_adapter *adapter = netdev_priv(netdev);
700 char firmware_version[32];
701 u16 eeprom_data;
702
703 strncpy(drvinfo->driver, igb_driver_name, 32);
704 strncpy(drvinfo->version, igb_driver_version, 32);
705
706 /* EEPROM image version # is reported as firmware version # for
707 * 82575 controllers */
708 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
709 sprintf(firmware_version, "%d.%d-%d",
710 (eeprom_data & 0xF000) >> 12,
711 (eeprom_data & 0x0FF0) >> 4,
712 eeprom_data & 0x000F);
713
714 strncpy(drvinfo->fw_version, firmware_version, 32);
715 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
716 drvinfo->n_stats = IGB_STATS_LEN;
717 drvinfo->testinfo_len = IGB_TEST_LEN;
718 drvinfo->regdump_len = igb_get_regs_len(netdev);
719 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
720 }
721
722 static void igb_get_ringparam(struct net_device *netdev,
723 struct ethtool_ringparam *ring)
724 {
725 struct igb_adapter *adapter = netdev_priv(netdev);
726
727 ring->rx_max_pending = IGB_MAX_RXD;
728 ring->tx_max_pending = IGB_MAX_TXD;
729 ring->rx_mini_max_pending = 0;
730 ring->rx_jumbo_max_pending = 0;
731 ring->rx_pending = adapter->rx_ring_count;
732 ring->tx_pending = adapter->tx_ring_count;
733 ring->rx_mini_pending = 0;
734 ring->rx_jumbo_pending = 0;
735 }
736
737 static int igb_set_ringparam(struct net_device *netdev,
738 struct ethtool_ringparam *ring)
739 {
740 struct igb_adapter *adapter = netdev_priv(netdev);
741 struct igb_ring *temp_ring;
742 int i, err;
743 u32 new_rx_count, new_tx_count;
744
745 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
746 return -EINVAL;
747
748 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
749 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
750 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
751
752 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
753 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
754 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
755
756 if ((new_tx_count == adapter->tx_ring_count) &&
757 (new_rx_count == adapter->rx_ring_count)) {
758 /* nothing to do */
759 return 0;
760 }
761
762 if (adapter->num_tx_queues > adapter->num_rx_queues)
763 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
764 else
765 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
766 if (!temp_ring)
767 return -ENOMEM;
768
769 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
770 msleep(1);
771
772 if (netif_running(adapter->netdev))
773 igb_down(adapter);
774
775 /*
776 * We can't just free everything and then setup again,
777 * because the ISRs in MSI-X mode get passed pointers
778 * to the tx and rx ring structs.
779 */
780 if (new_tx_count != adapter->tx_ring_count) {
781 memcpy(temp_ring, adapter->tx_ring,
782 adapter->num_tx_queues * sizeof(struct igb_ring));
783
784 for (i = 0; i < adapter->num_tx_queues; i++) {
785 temp_ring[i].count = new_tx_count;
786 err = igb_setup_tx_resources(adapter, &temp_ring[i]);
787 if (err) {
788 while (i) {
789 i--;
790 igb_free_tx_resources(&temp_ring[i]);
791 }
792 goto err_setup;
793 }
794 }
795
796 for (i = 0; i < adapter->num_tx_queues; i++)
797 igb_free_tx_resources(&adapter->tx_ring[i]);
798
799 memcpy(adapter->tx_ring, temp_ring,
800 adapter->num_tx_queues * sizeof(struct igb_ring));
801
802 adapter->tx_ring_count = new_tx_count;
803 }
804
805 if (new_rx_count != adapter->rx_ring->count) {
806 memcpy(temp_ring, adapter->rx_ring,
807 adapter->num_rx_queues * sizeof(struct igb_ring));
808
809 for (i = 0; i < adapter->num_rx_queues; i++) {
810 temp_ring[i].count = new_rx_count;
811 err = igb_setup_rx_resources(adapter, &temp_ring[i]);
812 if (err) {
813 while (i) {
814 i--;
815 igb_free_rx_resources(&temp_ring[i]);
816 }
817 goto err_setup;
818 }
819
820 }
821
822 for (i = 0; i < adapter->num_rx_queues; i++)
823 igb_free_rx_resources(&adapter->rx_ring[i]);
824
825 memcpy(adapter->rx_ring, temp_ring,
826 adapter->num_rx_queues * sizeof(struct igb_ring));
827
828 adapter->rx_ring_count = new_rx_count;
829 }
830
831 err = 0;
832 err_setup:
833 if (netif_running(adapter->netdev))
834 igb_up(adapter);
835
836 clear_bit(__IGB_RESETTING, &adapter->state);
837 vfree(temp_ring);
838 return err;
839 }
840
841 /* ethtool register test data */
842 struct igb_reg_test {
843 u16 reg;
844 u16 reg_offset;
845 u16 array_len;
846 u16 test_type;
847 u32 mask;
848 u32 write;
849 };
850
851 /* In the hardware, registers are laid out either singly, in arrays
852 * spaced 0x100 bytes apart, or in contiguous tables. We assume
853 * most tests take place on arrays or single registers (handled
854 * as a single-element array) and special-case the tables.
855 * Table tests are always pattern tests.
856 *
857 * We also make provision for some required setup steps by specifying
858 * registers to be written without any read-back testing.
859 */
860
861 #define PATTERN_TEST 1
862 #define SET_READ_TEST 2
863 #define WRITE_NO_TEST 3
864 #define TABLE32_TEST 4
865 #define TABLE64_TEST_LO 5
866 #define TABLE64_TEST_HI 6
867
868 /* 82576 reg test */
869 static struct igb_reg_test reg_test_82576[] = {
870 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
871 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
872 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
873 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
874 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
875 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
876 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
877 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
878 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
879 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
880 /* Enable all RX queues before testing. */
881 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
882 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
883 /* RDH is read-only for 82576, only test RDT. */
884 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
885 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
886 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
887 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
888 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
889 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
890 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
891 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
892 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
893 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
894 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
895 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
896 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
897 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
898 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
899 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
900 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
901 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
902 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
903 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
904 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
905 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
906 { 0, 0, 0, 0 }
907 };
908
909 /* 82575 register test */
910 static struct igb_reg_test reg_test_82575[] = {
911 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
912 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
913 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
914 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
915 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
916 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
917 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
918 /* Enable all four RX queues before testing. */
919 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
920 /* RDH is read-only for 82575, only test RDT. */
921 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
922 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
923 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
924 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
925 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
926 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
927 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
928 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
929 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
930 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
931 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
932 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
933 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
934 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
935 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
936 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
937 { 0, 0, 0, 0 }
938 };
939
940 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
941 int reg, u32 mask, u32 write)
942 {
943 struct e1000_hw *hw = &adapter->hw;
944 u32 pat, val;
945 u32 _test[] =
946 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
947 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
948 wr32(reg, (_test[pat] & write));
949 val = rd32(reg);
950 if (val != (_test[pat] & write & mask)) {
951 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
952 "failed: got 0x%08X expected 0x%08X\n",
953 reg, val, (_test[pat] & write & mask));
954 *data = reg;
955 return 1;
956 }
957 }
958 return 0;
959 }
960
961 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
962 int reg, u32 mask, u32 write)
963 {
964 struct e1000_hw *hw = &adapter->hw;
965 u32 val;
966 wr32(reg, write & mask);
967 val = rd32(reg);
968 if ((write & mask) != (val & mask)) {
969 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
970 " got 0x%08X expected 0x%08X\n", reg,
971 (val & mask), (write & mask));
972 *data = reg;
973 return 1;
974 }
975 return 0;
976 }
977
978 #define REG_PATTERN_TEST(reg, mask, write) \
979 do { \
980 if (reg_pattern_test(adapter, data, reg, mask, write)) \
981 return 1; \
982 } while (0)
983
984 #define REG_SET_AND_CHECK(reg, mask, write) \
985 do { \
986 if (reg_set_and_check(adapter, data, reg, mask, write)) \
987 return 1; \
988 } while (0)
989
990 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
991 {
992 struct e1000_hw *hw = &adapter->hw;
993 struct igb_reg_test *test;
994 u32 value, before, after;
995 u32 i, toggle;
996
997 toggle = 0x7FFFF3FF;
998
999 switch (adapter->hw.mac.type) {
1000 case e1000_82576:
1001 test = reg_test_82576;
1002 break;
1003 default:
1004 test = reg_test_82575;
1005 break;
1006 }
1007
1008 /* Because the status register is such a special case,
1009 * we handle it separately from the rest of the register
1010 * tests. Some bits are read-only, some toggle, and some
1011 * are writable on newer MACs.
1012 */
1013 before = rd32(E1000_STATUS);
1014 value = (rd32(E1000_STATUS) & toggle);
1015 wr32(E1000_STATUS, toggle);
1016 after = rd32(E1000_STATUS) & toggle;
1017 if (value != after) {
1018 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1019 "got: 0x%08X expected: 0x%08X\n", after, value);
1020 *data = 1;
1021 return 1;
1022 }
1023 /* restore previous status */
1024 wr32(E1000_STATUS, before);
1025
1026 /* Perform the remainder of the register test, looping through
1027 * the test table until we either fail or reach the null entry.
1028 */
1029 while (test->reg) {
1030 for (i = 0; i < test->array_len; i++) {
1031 switch (test->test_type) {
1032 case PATTERN_TEST:
1033 REG_PATTERN_TEST(test->reg +
1034 (i * test->reg_offset),
1035 test->mask,
1036 test->write);
1037 break;
1038 case SET_READ_TEST:
1039 REG_SET_AND_CHECK(test->reg +
1040 (i * test->reg_offset),
1041 test->mask,
1042 test->write);
1043 break;
1044 case WRITE_NO_TEST:
1045 writel(test->write,
1046 (adapter->hw.hw_addr + test->reg)
1047 + (i * test->reg_offset));
1048 break;
1049 case TABLE32_TEST:
1050 REG_PATTERN_TEST(test->reg + (i * 4),
1051 test->mask,
1052 test->write);
1053 break;
1054 case TABLE64_TEST_LO:
1055 REG_PATTERN_TEST(test->reg + (i * 8),
1056 test->mask,
1057 test->write);
1058 break;
1059 case TABLE64_TEST_HI:
1060 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1061 test->mask,
1062 test->write);
1063 break;
1064 }
1065 }
1066 test++;
1067 }
1068
1069 *data = 0;
1070 return 0;
1071 }
1072
1073 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1074 {
1075 u16 temp;
1076 u16 checksum = 0;
1077 u16 i;
1078
1079 *data = 0;
1080 /* Read and add up the contents of the EEPROM */
1081 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1082 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1083 < 0) {
1084 *data = 1;
1085 break;
1086 }
1087 checksum += temp;
1088 }
1089
1090 /* If Checksum is not Correct return error else test passed */
1091 if ((checksum != (u16) NVM_SUM) && !(*data))
1092 *data = 2;
1093
1094 return *data;
1095 }
1096
1097 static irqreturn_t igb_test_intr(int irq, void *data)
1098 {
1099 struct net_device *netdev = (struct net_device *) data;
1100 struct igb_adapter *adapter = netdev_priv(netdev);
1101 struct e1000_hw *hw = &adapter->hw;
1102
1103 adapter->test_icr |= rd32(E1000_ICR);
1104
1105 return IRQ_HANDLED;
1106 }
1107
1108 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1109 {
1110 struct e1000_hw *hw = &adapter->hw;
1111 struct net_device *netdev = adapter->netdev;
1112 u32 mask, ics_mask, i = 0, shared_int = true;
1113 u32 irq = adapter->pdev->irq;
1114
1115 *data = 0;
1116
1117 /* Hook up test interrupt handler just for this test */
1118 if (adapter->msix_entries)
1119 /* NOTE: we don't test MSI-X interrupts here, yet */
1120 return 0;
1121
1122 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1123 shared_int = false;
1124 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1125 *data = 1;
1126 return -1;
1127 }
1128 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1129 netdev->name, netdev)) {
1130 shared_int = false;
1131 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1132 netdev->name, netdev)) {
1133 *data = 1;
1134 return -1;
1135 }
1136 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1137 (shared_int ? "shared" : "unshared"));
1138 /* Disable all the interrupts */
1139 wr32(E1000_IMC, 0xFFFFFFFF);
1140 msleep(10);
1141
1142 /* Define all writable bits for ICS */
1143 switch(hw->mac.type) {
1144 case e1000_82575:
1145 ics_mask = 0x37F47EDD;
1146 break;
1147 case e1000_82576:
1148 ics_mask = 0x77D4FBFD;
1149 break;
1150 default:
1151 ics_mask = 0x7FFFFFFF;
1152 break;
1153 }
1154
1155 /* Test each interrupt */
1156 for (; i < 31; i++) {
1157 /* Interrupt to test */
1158 mask = 1 << i;
1159
1160 if (!(mask & ics_mask))
1161 continue;
1162
1163 if (!shared_int) {
1164 /* Disable the interrupt to be reported in
1165 * the cause register and then force the same
1166 * interrupt and see if one gets posted. If
1167 * an interrupt was posted to the bus, the
1168 * test failed.
1169 */
1170 adapter->test_icr = 0;
1171
1172 /* Flush any pending interrupts */
1173 wr32(E1000_ICR, ~0);
1174
1175 wr32(E1000_IMC, mask);
1176 wr32(E1000_ICS, mask);
1177 msleep(10);
1178
1179 if (adapter->test_icr & mask) {
1180 *data = 3;
1181 break;
1182 }
1183 }
1184
1185 /* Enable the interrupt to be reported in
1186 * the cause register and then force the same
1187 * interrupt and see if one gets posted. If
1188 * an interrupt was not posted to the bus, the
1189 * test failed.
1190 */
1191 adapter->test_icr = 0;
1192
1193 /* Flush any pending interrupts */
1194 wr32(E1000_ICR, ~0);
1195
1196 wr32(E1000_IMS, mask);
1197 wr32(E1000_ICS, mask);
1198 msleep(10);
1199
1200 if (!(adapter->test_icr & mask)) {
1201 *data = 4;
1202 break;
1203 }
1204
1205 if (!shared_int) {
1206 /* Disable the other interrupts to be reported in
1207 * the cause register and then force the other
1208 * interrupts and see if any get posted. If
1209 * an interrupt was posted to the bus, the
1210 * test failed.
1211 */
1212 adapter->test_icr = 0;
1213
1214 /* Flush any pending interrupts */
1215 wr32(E1000_ICR, ~0);
1216
1217 wr32(E1000_IMC, ~mask);
1218 wr32(E1000_ICS, ~mask);
1219 msleep(10);
1220
1221 if (adapter->test_icr & mask) {
1222 *data = 5;
1223 break;
1224 }
1225 }
1226 }
1227
1228 /* Disable all the interrupts */
1229 wr32(E1000_IMC, ~0);
1230 msleep(10);
1231
1232 /* Unhook test interrupt handler */
1233 free_irq(irq, netdev);
1234
1235 return *data;
1236 }
1237
1238 static void igb_free_desc_rings(struct igb_adapter *adapter)
1239 {
1240 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1241 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1242 struct pci_dev *pdev = adapter->pdev;
1243 int i;
1244
1245 if (tx_ring->desc && tx_ring->buffer_info) {
1246 for (i = 0; i < tx_ring->count; i++) {
1247 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1248 if (buf->dma)
1249 pci_unmap_single(pdev, buf->dma, buf->length,
1250 PCI_DMA_TODEVICE);
1251 if (buf->skb)
1252 dev_kfree_skb(buf->skb);
1253 }
1254 }
1255
1256 if (rx_ring->desc && rx_ring->buffer_info) {
1257 for (i = 0; i < rx_ring->count; i++) {
1258 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1259 if (buf->dma)
1260 pci_unmap_single(pdev, buf->dma,
1261 IGB_RXBUFFER_2048,
1262 PCI_DMA_FROMDEVICE);
1263 if (buf->skb)
1264 dev_kfree_skb(buf->skb);
1265 }
1266 }
1267
1268 if (tx_ring->desc) {
1269 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1270 tx_ring->dma);
1271 tx_ring->desc = NULL;
1272 }
1273 if (rx_ring->desc) {
1274 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1275 rx_ring->dma);
1276 rx_ring->desc = NULL;
1277 }
1278
1279 kfree(tx_ring->buffer_info);
1280 tx_ring->buffer_info = NULL;
1281 kfree(rx_ring->buffer_info);
1282 rx_ring->buffer_info = NULL;
1283
1284 return;
1285 }
1286
1287 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1288 {
1289 struct e1000_hw *hw = &adapter->hw;
1290 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1291 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1292 struct pci_dev *pdev = adapter->pdev;
1293 struct igb_buffer *buffer_info;
1294 u32 rctl;
1295 int i, ret_val;
1296
1297 /* Setup Tx descriptor ring and Tx buffers */
1298
1299 if (!tx_ring->count)
1300 tx_ring->count = IGB_DEFAULT_TXD;
1301
1302 tx_ring->buffer_info = kcalloc(tx_ring->count,
1303 sizeof(struct igb_buffer),
1304 GFP_KERNEL);
1305 if (!tx_ring->buffer_info) {
1306 ret_val = 1;
1307 goto err_nomem;
1308 }
1309
1310 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1311 tx_ring->size = ALIGN(tx_ring->size, 4096);
1312 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1313 &tx_ring->dma);
1314 if (!tx_ring->desc) {
1315 ret_val = 2;
1316 goto err_nomem;
1317 }
1318 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1319
1320 wr32(E1000_TDBAL(0),
1321 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1322 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1323 wr32(E1000_TDLEN(0),
1324 tx_ring->count * sizeof(union e1000_adv_tx_desc));
1325 wr32(E1000_TDH(0), 0);
1326 wr32(E1000_TDT(0), 0);
1327 wr32(E1000_TCTL,
1328 E1000_TCTL_PSP | E1000_TCTL_EN |
1329 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1330 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1331
1332 for (i = 0; i < tx_ring->count; i++) {
1333 union e1000_adv_tx_desc *tx_desc;
1334 struct sk_buff *skb;
1335 unsigned int size = 1024;
1336
1337 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1338 skb = alloc_skb(size, GFP_KERNEL);
1339 if (!skb) {
1340 ret_val = 3;
1341 goto err_nomem;
1342 }
1343 skb_put(skb, size);
1344 buffer_info = &tx_ring->buffer_info[i];
1345 buffer_info->skb = skb;
1346 buffer_info->length = skb->len;
1347 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1348 PCI_DMA_TODEVICE);
1349 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1350 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1351 E1000_ADVTXD_PAYLEN_SHIFT;
1352 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1353 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1354 E1000_TXD_CMD_IFCS |
1355 E1000_TXD_CMD_RS |
1356 E1000_ADVTXD_DTYP_DATA |
1357 E1000_ADVTXD_DCMD_DEXT);
1358 }
1359
1360 /* Setup Rx descriptor ring and Rx buffers */
1361
1362 if (!rx_ring->count)
1363 rx_ring->count = IGB_DEFAULT_RXD;
1364
1365 rx_ring->buffer_info = kcalloc(rx_ring->count,
1366 sizeof(struct igb_buffer),
1367 GFP_KERNEL);
1368 if (!rx_ring->buffer_info) {
1369 ret_val = 4;
1370 goto err_nomem;
1371 }
1372
1373 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1374 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1375 &rx_ring->dma);
1376 if (!rx_ring->desc) {
1377 ret_val = 5;
1378 goto err_nomem;
1379 }
1380 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1381
1382 rctl = rd32(E1000_RCTL);
1383 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1384 wr32(E1000_RDBAL(0),
1385 ((u64) rx_ring->dma & 0xFFFFFFFF));
1386 wr32(E1000_RDBAH(0),
1387 ((u64) rx_ring->dma >> 32));
1388 wr32(E1000_RDLEN(0), rx_ring->size);
1389 wr32(E1000_RDH(0), 0);
1390 wr32(E1000_RDT(0), 0);
1391 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1392 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1393 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1394 wr32(E1000_RCTL, rctl);
1395 wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1396
1397 for (i = 0; i < rx_ring->count; i++) {
1398 union e1000_adv_rx_desc *rx_desc;
1399 struct sk_buff *skb;
1400
1401 buffer_info = &rx_ring->buffer_info[i];
1402 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1403 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1404 GFP_KERNEL);
1405 if (!skb) {
1406 ret_val = 6;
1407 goto err_nomem;
1408 }
1409 skb_reserve(skb, NET_IP_ALIGN);
1410 buffer_info->skb = skb;
1411 buffer_info->dma = pci_map_single(pdev, skb->data,
1412 IGB_RXBUFFER_2048,
1413 PCI_DMA_FROMDEVICE);
1414 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1415 memset(skb->data, 0x00, skb->len);
1416 }
1417
1418 return 0;
1419
1420 err_nomem:
1421 igb_free_desc_rings(adapter);
1422 return ret_val;
1423 }
1424
1425 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1426 {
1427 struct e1000_hw *hw = &adapter->hw;
1428
1429 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1430 igb_write_phy_reg(hw, 29, 0x001F);
1431 igb_write_phy_reg(hw, 30, 0x8FFC);
1432 igb_write_phy_reg(hw, 29, 0x001A);
1433 igb_write_phy_reg(hw, 30, 0x8FF0);
1434 }
1435
1436 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1437 {
1438 struct e1000_hw *hw = &adapter->hw;
1439 u32 ctrl_reg = 0;
1440
1441 hw->mac.autoneg = false;
1442
1443 if (hw->phy.type == e1000_phy_m88) {
1444 /* Auto-MDI/MDIX Off */
1445 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1446 /* reset to update Auto-MDI/MDIX */
1447 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1448 /* autoneg off */
1449 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1450 }
1451
1452 ctrl_reg = rd32(E1000_CTRL);
1453
1454 /* force 1000, set loopback */
1455 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1456
1457 /* Now set up the MAC to the same speed/duplex as the PHY. */
1458 ctrl_reg = rd32(E1000_CTRL);
1459 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1460 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1461 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1462 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1463 E1000_CTRL_FD | /* Force Duplex to FULL */
1464 E1000_CTRL_SLU); /* Set link up enable bit */
1465
1466 if (hw->phy.type == e1000_phy_m88)
1467 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1468
1469 wr32(E1000_CTRL, ctrl_reg);
1470
1471 /* Disable the receiver on the PHY so when a cable is plugged in, the
1472 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1473 */
1474 if (hw->phy.type == e1000_phy_m88)
1475 igb_phy_disable_receiver(adapter);
1476
1477 udelay(500);
1478
1479 return 0;
1480 }
1481
1482 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1483 {
1484 return igb_integrated_phy_loopback(adapter);
1485 }
1486
1487 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1488 {
1489 struct e1000_hw *hw = &adapter->hw;
1490 u32 reg;
1491
1492 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1493 reg = rd32(E1000_RCTL);
1494 reg |= E1000_RCTL_LBM_TCVR;
1495 wr32(E1000_RCTL, reg);
1496
1497 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1498
1499 reg = rd32(E1000_CTRL);
1500 reg &= ~(E1000_CTRL_RFCE |
1501 E1000_CTRL_TFCE |
1502 E1000_CTRL_LRST);
1503 reg |= E1000_CTRL_SLU |
1504 E1000_CTRL_FD;
1505 wr32(E1000_CTRL, reg);
1506
1507 /* Unset switch control to serdes energy detect */
1508 reg = rd32(E1000_CONNSW);
1509 reg &= ~E1000_CONNSW_ENRGSRC;
1510 wr32(E1000_CONNSW, reg);
1511
1512 /* Set PCS register for forced speed */
1513 reg = rd32(E1000_PCS_LCTL);
1514 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1515 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1516 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1517 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1518 E1000_PCS_LCTL_FSD | /* Force Speed */
1519 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1520 wr32(E1000_PCS_LCTL, reg);
1521
1522 return 0;
1523 } else if (hw->phy.media_type == e1000_media_type_copper) {
1524 return igb_set_phy_loopback(adapter);
1525 }
1526
1527 return 7;
1528 }
1529
1530 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1531 {
1532 struct e1000_hw *hw = &adapter->hw;
1533 u32 rctl;
1534 u16 phy_reg;
1535
1536 rctl = rd32(E1000_RCTL);
1537 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1538 wr32(E1000_RCTL, rctl);
1539
1540 hw->mac.autoneg = true;
1541 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1542 if (phy_reg & MII_CR_LOOPBACK) {
1543 phy_reg &= ~MII_CR_LOOPBACK;
1544 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1545 igb_phy_sw_reset(hw);
1546 }
1547 }
1548
1549 static void igb_create_lbtest_frame(struct sk_buff *skb,
1550 unsigned int frame_size)
1551 {
1552 memset(skb->data, 0xFF, frame_size);
1553 frame_size &= ~1;
1554 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1555 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1556 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1557 }
1558
1559 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1560 {
1561 frame_size &= ~1;
1562 if (*(skb->data + 3) == 0xFF)
1563 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1564 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1565 return 0;
1566 return 13;
1567 }
1568
1569 static int igb_run_loopback_test(struct igb_adapter *adapter)
1570 {
1571 struct e1000_hw *hw = &adapter->hw;
1572 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1573 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1574 struct pci_dev *pdev = adapter->pdev;
1575 int i, j, k, l, lc, good_cnt;
1576 int ret_val = 0;
1577 unsigned long time;
1578
1579 wr32(E1000_RDT(0), rx_ring->count - 1);
1580
1581 /* Calculate the loop count based on the largest descriptor ring
1582 * The idea is to wrap the largest ring a number of times using 64
1583 * send/receive pairs during each loop
1584 */
1585
1586 if (rx_ring->count <= tx_ring->count)
1587 lc = ((tx_ring->count / 64) * 2) + 1;
1588 else
1589 lc = ((rx_ring->count / 64) * 2) + 1;
1590
1591 k = l = 0;
1592 for (j = 0; j <= lc; j++) { /* loop count loop */
1593 for (i = 0; i < 64; i++) { /* send the packets */
1594 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1595 1024);
1596 pci_dma_sync_single_for_device(pdev,
1597 tx_ring->buffer_info[k].dma,
1598 tx_ring->buffer_info[k].length,
1599 PCI_DMA_TODEVICE);
1600 k++;
1601 if (k == tx_ring->count)
1602 k = 0;
1603 }
1604 wr32(E1000_TDT(0), k);
1605 msleep(200);
1606 time = jiffies; /* set the start time for the receive */
1607 good_cnt = 0;
1608 do { /* receive the sent packets */
1609 pci_dma_sync_single_for_cpu(pdev,
1610 rx_ring->buffer_info[l].dma,
1611 IGB_RXBUFFER_2048,
1612 PCI_DMA_FROMDEVICE);
1613
1614 ret_val = igb_check_lbtest_frame(
1615 rx_ring->buffer_info[l].skb, 1024);
1616 if (!ret_val)
1617 good_cnt++;
1618 l++;
1619 if (l == rx_ring->count)
1620 l = 0;
1621 /* time + 20 msecs (200 msecs on 2.4) is more than
1622 * enough time to complete the receives, if it's
1623 * exceeded, break and error off
1624 */
1625 } while (good_cnt < 64 && jiffies < (time + 20));
1626 if (good_cnt != 64) {
1627 ret_val = 13; /* ret_val is the same as mis-compare */
1628 break;
1629 }
1630 if (jiffies >= (time + 20)) {
1631 ret_val = 14; /* error code for time out error */
1632 break;
1633 }
1634 } /* end loop count loop */
1635 return ret_val;
1636 }
1637
1638 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1639 {
1640 /* PHY loopback cannot be performed if SoL/IDER
1641 * sessions are active */
1642 if (igb_check_reset_block(&adapter->hw)) {
1643 dev_err(&adapter->pdev->dev,
1644 "Cannot do PHY loopback test "
1645 "when SoL/IDER is active.\n");
1646 *data = 0;
1647 goto out;
1648 }
1649 *data = igb_setup_desc_rings(adapter);
1650 if (*data)
1651 goto out;
1652 *data = igb_setup_loopback_test(adapter);
1653 if (*data)
1654 goto err_loopback;
1655 *data = igb_run_loopback_test(adapter);
1656 igb_loopback_cleanup(adapter);
1657
1658 err_loopback:
1659 igb_free_desc_rings(adapter);
1660 out:
1661 return *data;
1662 }
1663
1664 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1665 {
1666 struct e1000_hw *hw = &adapter->hw;
1667 *data = 0;
1668 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1669 int i = 0;
1670 hw->mac.serdes_has_link = false;
1671
1672 /* On some blade server designs, link establishment
1673 * could take as long as 2-3 minutes */
1674 do {
1675 hw->mac.ops.check_for_link(&adapter->hw);
1676 if (hw->mac.serdes_has_link)
1677 return *data;
1678 msleep(20);
1679 } while (i++ < 3750);
1680
1681 *data = 1;
1682 } else {
1683 hw->mac.ops.check_for_link(&adapter->hw);
1684 if (hw->mac.autoneg)
1685 msleep(4000);
1686
1687 if (!(rd32(E1000_STATUS) &
1688 E1000_STATUS_LU))
1689 *data = 1;
1690 }
1691 return *data;
1692 }
1693
1694 static void igb_diag_test(struct net_device *netdev,
1695 struct ethtool_test *eth_test, u64 *data)
1696 {
1697 struct igb_adapter *adapter = netdev_priv(netdev);
1698 u16 autoneg_advertised;
1699 u8 forced_speed_duplex, autoneg;
1700 bool if_running = netif_running(netdev);
1701
1702 set_bit(__IGB_TESTING, &adapter->state);
1703 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1704 /* Offline tests */
1705
1706 /* save speed, duplex, autoneg settings */
1707 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1708 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1709 autoneg = adapter->hw.mac.autoneg;
1710
1711 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1712
1713 /* Link test performed before hardware reset so autoneg doesn't
1714 * interfere with test result */
1715 if (igb_link_test(adapter, &data[4]))
1716 eth_test->flags |= ETH_TEST_FL_FAILED;
1717
1718 if (if_running)
1719 /* indicate we're in test mode */
1720 dev_close(netdev);
1721 else
1722 igb_reset(adapter);
1723
1724 if (igb_reg_test(adapter, &data[0]))
1725 eth_test->flags |= ETH_TEST_FL_FAILED;
1726
1727 igb_reset(adapter);
1728 if (igb_eeprom_test(adapter, &data[1]))
1729 eth_test->flags |= ETH_TEST_FL_FAILED;
1730
1731 igb_reset(adapter);
1732 if (igb_intr_test(adapter, &data[2]))
1733 eth_test->flags |= ETH_TEST_FL_FAILED;
1734
1735 igb_reset(adapter);
1736 if (igb_loopback_test(adapter, &data[3]))
1737 eth_test->flags |= ETH_TEST_FL_FAILED;
1738
1739 /* restore speed, duplex, autoneg settings */
1740 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1741 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1742 adapter->hw.mac.autoneg = autoneg;
1743
1744 /* force this routine to wait until autoneg complete/timeout */
1745 adapter->hw.phy.autoneg_wait_to_complete = true;
1746 igb_reset(adapter);
1747 adapter->hw.phy.autoneg_wait_to_complete = false;
1748
1749 clear_bit(__IGB_TESTING, &adapter->state);
1750 if (if_running)
1751 dev_open(netdev);
1752 } else {
1753 dev_info(&adapter->pdev->dev, "online testing starting\n");
1754 /* Online tests */
1755 if (igb_link_test(adapter, &data[4]))
1756 eth_test->flags |= ETH_TEST_FL_FAILED;
1757
1758 /* Online tests aren't run; pass by default */
1759 data[0] = 0;
1760 data[1] = 0;
1761 data[2] = 0;
1762 data[3] = 0;
1763
1764 clear_bit(__IGB_TESTING, &adapter->state);
1765 }
1766 msleep_interruptible(4 * 1000);
1767 }
1768
1769 static int igb_wol_exclusion(struct igb_adapter *adapter,
1770 struct ethtool_wolinfo *wol)
1771 {
1772 struct e1000_hw *hw = &adapter->hw;
1773 int retval = 1; /* fail by default */
1774
1775 switch (hw->device_id) {
1776 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1777 /* WoL not supported */
1778 wol->supported = 0;
1779 break;
1780 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1781 case E1000_DEV_ID_82576_FIBER:
1782 case E1000_DEV_ID_82576_SERDES:
1783 /* Wake events not supported on port B */
1784 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1785 wol->supported = 0;
1786 break;
1787 }
1788 /* return success for non excluded adapter ports */
1789 retval = 0;
1790 break;
1791 case E1000_DEV_ID_82576_QUAD_COPPER:
1792 /* quad port adapters only support WoL on port A */
1793 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1794 wol->supported = 0;
1795 break;
1796 }
1797 /* return success for non excluded adapter ports */
1798 retval = 0;
1799 break;
1800 default:
1801 /* dual port cards only support WoL on port A from now on
1802 * unless it was enabled in the eeprom for port B
1803 * so exclude FUNC_1 ports from having WoL enabled */
1804 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1805 !adapter->eeprom_wol) {
1806 wol->supported = 0;
1807 break;
1808 }
1809
1810 retval = 0;
1811 }
1812
1813 return retval;
1814 }
1815
1816 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1817 {
1818 struct igb_adapter *adapter = netdev_priv(netdev);
1819
1820 wol->supported = WAKE_UCAST | WAKE_MCAST |
1821 WAKE_BCAST | WAKE_MAGIC;
1822 wol->wolopts = 0;
1823
1824 /* this function will set ->supported = 0 and return 1 if wol is not
1825 * supported by this hardware */
1826 if (igb_wol_exclusion(adapter, wol) ||
1827 !device_can_wakeup(&adapter->pdev->dev))
1828 return;
1829
1830 /* apply any specific unsupported masks here */
1831 switch (adapter->hw.device_id) {
1832 default:
1833 break;
1834 }
1835
1836 if (adapter->wol & E1000_WUFC_EX)
1837 wol->wolopts |= WAKE_UCAST;
1838 if (adapter->wol & E1000_WUFC_MC)
1839 wol->wolopts |= WAKE_MCAST;
1840 if (adapter->wol & E1000_WUFC_BC)
1841 wol->wolopts |= WAKE_BCAST;
1842 if (adapter->wol & E1000_WUFC_MAG)
1843 wol->wolopts |= WAKE_MAGIC;
1844
1845 return;
1846 }
1847
1848 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1849 {
1850 struct igb_adapter *adapter = netdev_priv(netdev);
1851
1852 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1853 return -EOPNOTSUPP;
1854
1855 if (igb_wol_exclusion(adapter, wol) ||
1856 !device_can_wakeup(&adapter->pdev->dev))
1857 return wol->wolopts ? -EOPNOTSUPP : 0;
1858
1859 /* these settings will always override what we currently have */
1860 adapter->wol = 0;
1861
1862 if (wol->wolopts & WAKE_UCAST)
1863 adapter->wol |= E1000_WUFC_EX;
1864 if (wol->wolopts & WAKE_MCAST)
1865 adapter->wol |= E1000_WUFC_MC;
1866 if (wol->wolopts & WAKE_BCAST)
1867 adapter->wol |= E1000_WUFC_BC;
1868 if (wol->wolopts & WAKE_MAGIC)
1869 adapter->wol |= E1000_WUFC_MAG;
1870
1871 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1872
1873 return 0;
1874 }
1875
1876 /* bit defines for adapter->led_status */
1877 #define IGB_LED_ON 0
1878
1879 static int igb_phys_id(struct net_device *netdev, u32 data)
1880 {
1881 struct igb_adapter *adapter = netdev_priv(netdev);
1882 struct e1000_hw *hw = &adapter->hw;
1883
1884 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1885 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1886
1887 igb_blink_led(hw);
1888 msleep_interruptible(data * 1000);
1889
1890 igb_led_off(hw);
1891 clear_bit(IGB_LED_ON, &adapter->led_status);
1892 igb_cleanup_led(hw);
1893
1894 return 0;
1895 }
1896
1897 static int igb_set_coalesce(struct net_device *netdev,
1898 struct ethtool_coalesce *ec)
1899 {
1900 struct igb_adapter *adapter = netdev_priv(netdev);
1901 struct e1000_hw *hw = &adapter->hw;
1902 int i;
1903
1904 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1905 ((ec->rx_coalesce_usecs > 3) &&
1906 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1907 (ec->rx_coalesce_usecs == 2))
1908 return -EINVAL;
1909
1910 /* convert to rate of irq's per second */
1911 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1912 adapter->itr_setting = ec->rx_coalesce_usecs;
1913 adapter->itr = IGB_START_ITR;
1914 } else {
1915 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1916 adapter->itr = adapter->itr_setting;
1917 }
1918
1919 for (i = 0; i < adapter->num_rx_queues; i++)
1920 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1921
1922 return 0;
1923 }
1924
1925 static int igb_get_coalesce(struct net_device *netdev,
1926 struct ethtool_coalesce *ec)
1927 {
1928 struct igb_adapter *adapter = netdev_priv(netdev);
1929
1930 if (adapter->itr_setting <= 3)
1931 ec->rx_coalesce_usecs = adapter->itr_setting;
1932 else
1933 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1934
1935 return 0;
1936 }
1937
1938
1939 static int igb_nway_reset(struct net_device *netdev)
1940 {
1941 struct igb_adapter *adapter = netdev_priv(netdev);
1942 if (netif_running(netdev))
1943 igb_reinit_locked(adapter);
1944 return 0;
1945 }
1946
1947 static int igb_get_sset_count(struct net_device *netdev, int sset)
1948 {
1949 switch (sset) {
1950 case ETH_SS_STATS:
1951 return IGB_STATS_LEN;
1952 case ETH_SS_TEST:
1953 return IGB_TEST_LEN;
1954 default:
1955 return -ENOTSUPP;
1956 }
1957 }
1958
1959 static void igb_get_ethtool_stats(struct net_device *netdev,
1960 struct ethtool_stats *stats, u64 *data)
1961 {
1962 struct igb_adapter *adapter = netdev_priv(netdev);
1963 u64 *queue_stat;
1964 int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1965 int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
1966 int j;
1967 int i;
1968 char *p = NULL;
1969
1970 igb_update_stats(adapter);
1971 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1972 switch (igb_gstrings_stats[i].type) {
1973 case NETDEV_STATS:
1974 p = (char *) netdev +
1975 igb_gstrings_stats[i].stat_offset;
1976 break;
1977 case IGB_STATS:
1978 p = (char *) adapter +
1979 igb_gstrings_stats[i].stat_offset;
1980 break;
1981 }
1982
1983 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1984 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1985 }
1986 for (j = 0; j < adapter->num_tx_queues; j++) {
1987 int k;
1988 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1989 for (k = 0; k < stat_count_tx; k++)
1990 data[i + k] = queue_stat[k];
1991 i += k;
1992 }
1993 for (j = 0; j < adapter->num_rx_queues; j++) {
1994 int k;
1995 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1996 for (k = 0; k < stat_count_rx; k++)
1997 data[i + k] = queue_stat[k];
1998 i += k;
1999 }
2000 }
2001
2002 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2003 {
2004 struct igb_adapter *adapter = netdev_priv(netdev);
2005 u8 *p = data;
2006 int i;
2007
2008 switch (stringset) {
2009 case ETH_SS_TEST:
2010 memcpy(data, *igb_gstrings_test,
2011 IGB_TEST_LEN*ETH_GSTRING_LEN);
2012 break;
2013 case ETH_SS_STATS:
2014 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2015 memcpy(p, igb_gstrings_stats[i].stat_string,
2016 ETH_GSTRING_LEN);
2017 p += ETH_GSTRING_LEN;
2018 }
2019 for (i = 0; i < adapter->num_tx_queues; i++) {
2020 sprintf(p, "tx_queue_%u_packets", i);
2021 p += ETH_GSTRING_LEN;
2022 sprintf(p, "tx_queue_%u_bytes", i);
2023 p += ETH_GSTRING_LEN;
2024 }
2025 for (i = 0; i < adapter->num_rx_queues; i++) {
2026 sprintf(p, "rx_queue_%u_packets", i);
2027 p += ETH_GSTRING_LEN;
2028 sprintf(p, "rx_queue_%u_bytes", i);
2029 p += ETH_GSTRING_LEN;
2030 sprintf(p, "rx_queue_%u_drops", i);
2031 p += ETH_GSTRING_LEN;
2032 }
2033 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2034 break;
2035 }
2036 }
2037
2038 static const struct ethtool_ops igb_ethtool_ops = {
2039 .get_settings = igb_get_settings,
2040 .set_settings = igb_set_settings,
2041 .get_drvinfo = igb_get_drvinfo,
2042 .get_regs_len = igb_get_regs_len,
2043 .get_regs = igb_get_regs,
2044 .get_wol = igb_get_wol,
2045 .set_wol = igb_set_wol,
2046 .get_msglevel = igb_get_msglevel,
2047 .set_msglevel = igb_set_msglevel,
2048 .nway_reset = igb_nway_reset,
2049 .get_link = ethtool_op_get_link,
2050 .get_eeprom_len = igb_get_eeprom_len,
2051 .get_eeprom = igb_get_eeprom,
2052 .set_eeprom = igb_set_eeprom,
2053 .get_ringparam = igb_get_ringparam,
2054 .set_ringparam = igb_set_ringparam,
2055 .get_pauseparam = igb_get_pauseparam,
2056 .set_pauseparam = igb_set_pauseparam,
2057 .get_rx_csum = igb_get_rx_csum,
2058 .set_rx_csum = igb_set_rx_csum,
2059 .get_tx_csum = igb_get_tx_csum,
2060 .set_tx_csum = igb_set_tx_csum,
2061 .get_sg = ethtool_op_get_sg,
2062 .set_sg = ethtool_op_set_sg,
2063 .get_tso = ethtool_op_get_tso,
2064 .set_tso = igb_set_tso,
2065 .self_test = igb_diag_test,
2066 .get_strings = igb_get_strings,
2067 .phys_id = igb_phys_id,
2068 .get_sset_count = igb_get_sset_count,
2069 .get_ethtool_stats = igb_get_ethtool_stats,
2070 .get_coalesce = igb_get_coalesce,
2071 .set_coalesce = igb_set_coalesce,
2072 };
2073
2074 void igb_set_ethtool_ops(struct net_device *netdev)
2075 {
2076 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2077 }
kernel-based virtual machine