?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mv643xx_eth: get rid of receive-side locking
[linux-2.6/kvm.git] / drivers / net / mv643xx_eth.c
blob3831a8bffbd6e576141d02a31856c94c76f7dd5e
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
53 #include <asm/io.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
56
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
59
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_TX_FAST_REFILL
62
63 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
64 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
65 #else
66 #define MAX_DESCS_PER_SKB 1
67 #endif
68
69 /*
70 * Registers shared between all ports.
71 */
72 #define PHY_ADDR 0x0000
73 #define SMI_REG 0x0004
74 #define SMI_BUSY 0x10000000
75 #define SMI_READ_VALID 0x08000000
76 #define SMI_OPCODE_READ 0x04000000
77 #define SMI_OPCODE_WRITE 0x00000000
78 #define ERR_INT_CAUSE 0x0080
79 #define ERR_INT_SMI_DONE 0x00000010
80 #define ERR_INT_MASK 0x0084
81 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
82 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
83 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
84 #define WINDOW_BAR_ENABLE 0x0290
85 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
86
87 /*
88 * Per-port registers.
89 */
90 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
91 #define UNICAST_PROMISCUOUS_MODE 0x00000001
92 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
93 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
94 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
95 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
96 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
97 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
98 #define TX_FIFO_EMPTY 0x00000400
99 #define TX_IN_PROGRESS 0x00000080
100 #define PORT_SPEED_MASK 0x00000030
101 #define PORT_SPEED_1000 0x00000010
102 #define PORT_SPEED_100 0x00000020
103 #define PORT_SPEED_10 0x00000000
104 #define FLOW_CONTROL_ENABLED 0x00000008
105 #define FULL_DUPLEX 0x00000004
106 #define LINK_UP 0x00000002
107 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
108 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
109 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
110 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
111 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
112 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
113 #define INT_TX_END_0 0x00080000
114 #define INT_TX_END 0x07f80000
115 #define INT_RX 0x0007fbfc
116 #define INT_EXT 0x00000002
117 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
118 #define INT_EXT_LINK 0x00100000
119 #define INT_EXT_PHY 0x00010000
120 #define INT_EXT_TX_ERROR_0 0x00000100
121 #define INT_EXT_TX_0 0x00000001
122 #define INT_EXT_TX 0x0000ffff
123 #define INT_MASK(p) (0x0468 + ((p) << 10))
124 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
125 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
126 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
127 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
128 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
129 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
130 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
131 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
132 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
133 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
134 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
135 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
136 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
137 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
138 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
139 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
140
141
142 /*
143 * SDMA configuration register.
144 */
145 #define RX_BURST_SIZE_16_64BIT (4 << 1)
146 #define BLM_RX_NO_SWAP (1 << 4)
147 #define BLM_TX_NO_SWAP (1 << 5)
148 #define TX_BURST_SIZE_16_64BIT (4 << 22)
149
150 #if defined(__BIG_ENDIAN)
151 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
152 RX_BURST_SIZE_16_64BIT | \
153 TX_BURST_SIZE_16_64BIT
154 #elif defined(__LITTLE_ENDIAN)
155 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
156 RX_BURST_SIZE_16_64BIT | \
157 BLM_RX_NO_SWAP | \
158 BLM_TX_NO_SWAP | \
159 TX_BURST_SIZE_16_64BIT
160 #else
161 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
162 #endif
163
164
165 /*
166 * Port serial control register.
167 */
168 #define SET_MII_SPEED_TO_100 (1 << 24)
169 #define SET_GMII_SPEED_TO_1000 (1 << 23)
170 #define SET_FULL_DUPLEX_MODE (1 << 21)
171 #define MAX_RX_PACKET_9700BYTE (5 << 17)
172 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
173 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
174 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
175 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
176 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
177 #define FORCE_LINK_PASS (1 << 1)
178 #define SERIAL_PORT_ENABLE (1 << 0)
179
180 #define DEFAULT_RX_QUEUE_SIZE 400
181 #define DEFAULT_TX_QUEUE_SIZE 800
182
183
184 /*
185 * RX/TX descriptors.
186 */
187 #if defined(__BIG_ENDIAN)
188 struct rx_desc {
189 u16 byte_cnt; /* Descriptor buffer byte count */
190 u16 buf_size; /* Buffer size */
191 u32 cmd_sts; /* Descriptor command status */
192 u32 next_desc_ptr; /* Next descriptor pointer */
193 u32 buf_ptr; /* Descriptor buffer pointer */
194 };
195
196 struct tx_desc {
197 u16 byte_cnt; /* buffer byte count */
198 u16 l4i_chk; /* CPU provided TCP checksum */
199 u32 cmd_sts; /* Command/status field */
200 u32 next_desc_ptr; /* Pointer to next descriptor */
201 u32 buf_ptr; /* pointer to buffer for this descriptor*/
202 };
203 #elif defined(__LITTLE_ENDIAN)
204 struct rx_desc {
205 u32 cmd_sts; /* Descriptor command status */
206 u16 buf_size; /* Buffer size */
207 u16 byte_cnt; /* Descriptor buffer byte count */
208 u32 buf_ptr; /* Descriptor buffer pointer */
209 u32 next_desc_ptr; /* Next descriptor pointer */
210 };
211
212 struct tx_desc {
213 u32 cmd_sts; /* Command/status field */
214 u16 l4i_chk; /* CPU provided TCP checksum */
215 u16 byte_cnt; /* buffer byte count */
216 u32 buf_ptr; /* pointer to buffer for this descriptor*/
217 u32 next_desc_ptr; /* Pointer to next descriptor */
218 };
219 #else
220 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
221 #endif
222
223 /* RX & TX descriptor command */
224 #define BUFFER_OWNED_BY_DMA 0x80000000
225
226 /* RX & TX descriptor status */
227 #define ERROR_SUMMARY 0x00000001
228
229 /* RX descriptor status */
230 #define LAYER_4_CHECKSUM_OK 0x40000000
231 #define RX_ENABLE_INTERRUPT 0x20000000
232 #define RX_FIRST_DESC 0x08000000
233 #define RX_LAST_DESC 0x04000000
234
235 /* TX descriptor command */
236 #define TX_ENABLE_INTERRUPT 0x00800000
237 #define GEN_CRC 0x00400000
238 #define TX_FIRST_DESC 0x00200000
239 #define TX_LAST_DESC 0x00100000
240 #define ZERO_PADDING 0x00080000
241 #define GEN_IP_V4_CHECKSUM 0x00040000
242 #define GEN_TCP_UDP_CHECKSUM 0x00020000
243 #define UDP_FRAME 0x00010000
244 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
245 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
246
247 #define TX_IHL_SHIFT 11
248
249
250 /* global *******************************************************************/
251 struct mv643xx_eth_shared_private {
252 /*
253 * Ethernet controller base address.
254 */
255 void __iomem *base;
256
257 /*
258 * Protects access to SMI_REG, which is shared between ports.
259 */
260 struct mutex phy_lock;
261
262 /*
263 * If we have access to the error interrupt pin (which is
264 * somewhat misnamed as it not only reflects internal errors
265 * but also reflects SMI completion), use that to wait for
266 * SMI access completion instead of polling the SMI busy bit.
267 */
268 int err_interrupt;
269 wait_queue_head_t smi_busy_wait;
270
271 /*
272 * Per-port MBUS window access register value.
273 */
274 u32 win_protect;
275
276 /*
277 * Hardware-specific parameters.
278 */
279 unsigned int t_clk;
280 int extended_rx_coal_limit;
281 int tx_bw_control_moved;
282 };
283
284
285 /* per-port *****************************************************************/
286 struct mib_counters {
287 u64 good_octets_received;
288 u32 bad_octets_received;
289 u32 internal_mac_transmit_err;
290 u32 good_frames_received;
291 u32 bad_frames_received;
292 u32 broadcast_frames_received;
293 u32 multicast_frames_received;
294 u32 frames_64_octets;
295 u32 frames_65_to_127_octets;
296 u32 frames_128_to_255_octets;
297 u32 frames_256_to_511_octets;
298 u32 frames_512_to_1023_octets;
299 u32 frames_1024_to_max_octets;
300 u64 good_octets_sent;
301 u32 good_frames_sent;
302 u32 excessive_collision;
303 u32 multicast_frames_sent;
304 u32 broadcast_frames_sent;
305 u32 unrec_mac_control_received;
306 u32 fc_sent;
307 u32 good_fc_received;
308 u32 bad_fc_received;
309 u32 undersize_received;
310 u32 fragments_received;
311 u32 oversize_received;
312 u32 jabber_received;
313 u32 mac_receive_error;
314 u32 bad_crc_event;
315 u32 collision;
316 u32 late_collision;
317 };
318
319 struct rx_queue {
320 int index;
321
322 int rx_ring_size;
323
324 int rx_desc_count;
325 int rx_curr_desc;
326 int rx_used_desc;
327
328 struct rx_desc *rx_desc_area;
329 dma_addr_t rx_desc_dma;
330 int rx_desc_area_size;
331 struct sk_buff **rx_skb;
332 };
333
334 struct tx_queue {
335 int index;
336
337 int tx_ring_size;
338
339 int tx_desc_count;
340 int tx_curr_desc;
341 int tx_used_desc;
342
343 struct tx_desc *tx_desc_area;
344 dma_addr_t tx_desc_dma;
345 int tx_desc_area_size;
346 struct sk_buff **tx_skb;
347 };
348
349 struct mv643xx_eth_private {
350 struct mv643xx_eth_shared_private *shared;
351 int port_num;
352
353 struct net_device *dev;
354
355 struct mv643xx_eth_shared_private *shared_smi;
356 int phy_addr;
357
358 spinlock_t lock;
359
360 struct mib_counters mib_counters;
361 struct work_struct tx_timeout_task;
362 struct mii_if_info mii;
363
364 /*
365 * RX state.
366 */
367 int default_rx_ring_size;
368 unsigned long rx_desc_sram_addr;
369 int rx_desc_sram_size;
370 u8 rxq_mask;
371 int rxq_primary;
372 struct napi_struct napi;
373 struct timer_list rx_oom;
374 struct rx_queue rxq[8];
375
376 /*
377 * TX state.
378 */
379 int default_tx_ring_size;
380 unsigned long tx_desc_sram_addr;
381 int tx_desc_sram_size;
382 u8 txq_mask;
383 int txq_primary;
384 struct tx_queue txq[8];
385 #ifdef MV643XX_ETH_TX_FAST_REFILL
386 int tx_clean_threshold;
387 #endif
388 };
389
390
391 /* port register accessors **************************************************/
392 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
393 {
394 return readl(mp->shared->base + offset);
395 }
396
397 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
398 {
399 writel(data, mp->shared->base + offset);
400 }
401
402
403 /* rxq/txq helper functions *************************************************/
404 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
405 {
406 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
407 }
408
409 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
410 {
411 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
412 }
413
414 static void rxq_enable(struct rx_queue *rxq)
415 {
416 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
417 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
418 }
419
420 static void rxq_disable(struct rx_queue *rxq)
421 {
422 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
423 u8 mask = 1 << rxq->index;
424
425 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
426 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
427 udelay(10);
428 }
429
430 static void txq_reset_hw_ptr(struct tx_queue *txq)
431 {
432 struct mv643xx_eth_private *mp = txq_to_mp(txq);
433 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
434 u32 addr;
435
436 addr = (u32)txq->tx_desc_dma;
437 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
438 wrl(mp, off, addr);
439 }
440
441 static void txq_enable(struct tx_queue *txq)
442 {
443 struct mv643xx_eth_private *mp = txq_to_mp(txq);
444 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
445 }
446
447 static void txq_disable(struct tx_queue *txq)
448 {
449 struct mv643xx_eth_private *mp = txq_to_mp(txq);
450 u8 mask = 1 << txq->index;
451
452 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
453 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
454 udelay(10);
455 }
456
457 static void __txq_maybe_wake(struct tx_queue *txq)
458 {
459 struct mv643xx_eth_private *mp = txq_to_mp(txq);
460
461 /*
462 * netif_{stop,wake}_queue() flow control only applies to
463 * the primary queue.
464 */
465 BUG_ON(txq->index != mp->txq_primary);
466
467 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
468 netif_wake_queue(mp->dev);
469 }
470
471
472 /* rx ***********************************************************************/
473 static void txq_reclaim(struct tx_queue *txq, int force);
474
475 static int rxq_refill(struct rx_queue *rxq, int budget, int *oom)
476 {
477 int skb_size;
478 int refilled;
479
480 /*
481 * Reserve 2+14 bytes for an ethernet header (the hardware
482 * automatically prepends 2 bytes of dummy data to each
483 * received packet), 16 bytes for up to four VLAN tags, and
484 * 4 bytes for the trailing FCS -- 36 bytes total.
485 */
486 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
487
488 /*
489 * Make sure that the skb size is a multiple of 8 bytes, as
490 * the lower three bits of the receive descriptor's buffer
491 * size field are ignored by the hardware.
492 */
493 skb_size = (skb_size + 7) & ~7;
494
495 refilled = 0;
496 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
497 struct sk_buff *skb;
498 int unaligned;
499 int rx;
500
501 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
502 if (skb == NULL) {
503 *oom = 1;
504 break;
505 }
506
507 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
508 if (unaligned)
509 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
510
511 refilled++;
512 rxq->rx_desc_count++;
513
514 rx = rxq->rx_used_desc++;
515 if (rxq->rx_used_desc == rxq->rx_ring_size)
516 rxq->rx_used_desc = 0;
517
518 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
519 skb_size, DMA_FROM_DEVICE);
520 rxq->rx_desc_area[rx].buf_size = skb_size;
521 rxq->rx_skb[rx] = skb;
522 wmb();
523 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
524 RX_ENABLE_INTERRUPT;
525 wmb();
526
527 /*
528 * The hardware automatically prepends 2 bytes of
529 * dummy data to each received packet, so that the
530 * IP header ends up 16-byte aligned.
531 */
532 skb_reserve(skb, 2);
533 }
534
535 return refilled;
536 }
537
538 static int rxq_process(struct rx_queue *rxq, int budget)
539 {
540 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
541 struct net_device_stats *stats = &mp->dev->stats;
542 int rx;
543
544 rx = 0;
545 while (rx < budget && rxq->rx_desc_count) {
546 struct rx_desc *rx_desc;
547 unsigned int cmd_sts;
548 struct sk_buff *skb;
549
550 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
551
552 cmd_sts = rx_desc->cmd_sts;
553 if (cmd_sts & BUFFER_OWNED_BY_DMA)
554 break;
555 rmb();
556
557 skb = rxq->rx_skb[rxq->rx_curr_desc];
558 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
559
560 rxq->rx_curr_desc++;
561 if (rxq->rx_curr_desc == rxq->rx_ring_size)
562 rxq->rx_curr_desc = 0;
563
564 dma_unmap_single(NULL, rx_desc->buf_ptr,
565 rx_desc->buf_size, DMA_FROM_DEVICE);
566 rxq->rx_desc_count--;
567 rx++;
568
569 /*
570 * Update statistics.
571 *
572 * Note that the descriptor byte count includes 2 dummy
573 * bytes automatically inserted by the hardware at the
574 * start of the packet (which we don't count), and a 4
575 * byte CRC at the end of the packet (which we do count).
576 */
577 stats->rx_packets++;
578 stats->rx_bytes += rx_desc->byte_cnt - 2;
579
580 /*
581 * In case we received a packet without first / last bits
582 * on, or the error summary bit is set, the packet needs
583 * to be dropped.
584 */
585 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
586 (RX_FIRST_DESC | RX_LAST_DESC))
587 || (cmd_sts & ERROR_SUMMARY)) {
588 stats->rx_dropped++;
589
590 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
591 (RX_FIRST_DESC | RX_LAST_DESC)) {
592 if (net_ratelimit())
593 dev_printk(KERN_ERR, &mp->dev->dev,
594 "received packet spanning "
595 "multiple descriptors\n");
596 }
597
598 if (cmd_sts & ERROR_SUMMARY)
599 stats->rx_errors++;
600
601 dev_kfree_skb(skb);
602 } else {
603 /*
604 * The -4 is for the CRC in the trailer of the
605 * received packet
606 */
607 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
608
609 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
610 skb->ip_summed = CHECKSUM_UNNECESSARY;
611 skb->csum = htons(
612 (cmd_sts & 0x0007fff8) >> 3);
613 }
614 skb->protocol = eth_type_trans(skb, mp->dev);
615 netif_receive_skb(skb);
616 }
617
618 mp->dev->last_rx = jiffies;
619 }
620
621 return rx;
622 }
623
624 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
625 {
626 struct mv643xx_eth_private *mp;
627 int work_done;
628 int oom;
629 int i;
630
631 mp = container_of(napi, struct mv643xx_eth_private, napi);
632
633 #ifdef MV643XX_ETH_TX_FAST_REFILL
634 if (++mp->tx_clean_threshold > 5) {
635 mp->tx_clean_threshold = 0;
636 for (i = 0; i < 8; i++)
637 if (mp->txq_mask & (1 << i))
638 txq_reclaim(mp->txq + i, 0);
639
640 if (netif_carrier_ok(mp->dev)) {
641 spin_lock_irq(&mp->lock);
642 __txq_maybe_wake(mp->txq + mp->txq_primary);
643 spin_unlock_irq(&mp->lock);
644 }
645 }
646 #endif
647
648 work_done = 0;
649 oom = 0;
650 for (i = 7; work_done < budget && i >= 0; i--) {
651 if (mp->rxq_mask & (1 << i)) {
652 struct rx_queue *rxq = mp->rxq + i;
653
654 work_done += rxq_process(rxq, budget - work_done);
655 work_done += rxq_refill(rxq, budget - work_done, &oom);
656 }
657 }
658
659 if (work_done < budget) {
660 if (oom)
661 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
662 netif_rx_complete(mp->dev, napi);
663 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
664 }
665
666 return work_done;
667 }
668
669 static inline void oom_timer_wrapper(unsigned long data)
670 {
671 struct mv643xx_eth_private *mp = (void *)data;
672
673 napi_schedule(&mp->napi);
674 }
675
676
677 /* tx ***********************************************************************/
678 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
679 {
680 int frag;
681
682 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
683 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
684 if (fragp->size <= 8 && fragp->page_offset & 7)
685 return 1;
686 }
687
688 return 0;
689 }
690
691 static int txq_alloc_desc_index(struct tx_queue *txq)
692 {
693 int tx_desc_curr;
694
695 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
696
697 tx_desc_curr = txq->tx_curr_desc++;
698 if (txq->tx_curr_desc == txq->tx_ring_size)
699 txq->tx_curr_desc = 0;
700
701 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
702
703 return tx_desc_curr;
704 }
705
706 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
707 {
708 int nr_frags = skb_shinfo(skb)->nr_frags;
709 int frag;
710
711 for (frag = 0; frag < nr_frags; frag++) {
712 skb_frag_t *this_frag;
713 int tx_index;
714 struct tx_desc *desc;
715
716 this_frag = &skb_shinfo(skb)->frags[frag];
717 tx_index = txq_alloc_desc_index(txq);
718 desc = &txq->tx_desc_area[tx_index];
719
720 /*
721 * The last fragment will generate an interrupt
722 * which will free the skb on TX completion.
723 */
724 if (frag == nr_frags - 1) {
725 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
726 ZERO_PADDING | TX_LAST_DESC |
727 TX_ENABLE_INTERRUPT;
728 txq->tx_skb[tx_index] = skb;
729 } else {
730 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
731 txq->tx_skb[tx_index] = NULL;
732 }
733
734 desc->l4i_chk = 0;
735 desc->byte_cnt = this_frag->size;
736 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
737 this_frag->page_offset,
738 this_frag->size,
739 DMA_TO_DEVICE);
740 }
741 }
742
743 static inline __be16 sum16_as_be(__sum16 sum)
744 {
745 return (__force __be16)sum;
746 }
747
748 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
749 {
750 struct mv643xx_eth_private *mp = txq_to_mp(txq);
751 int nr_frags = skb_shinfo(skb)->nr_frags;
752 int tx_index;
753 struct tx_desc *desc;
754 u32 cmd_sts;
755 int length;
756
757 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
758
759 tx_index = txq_alloc_desc_index(txq);
760 desc = &txq->tx_desc_area[tx_index];
761
762 if (nr_frags) {
763 txq_submit_frag_skb(txq, skb);
764
765 length = skb_headlen(skb);
766 txq->tx_skb[tx_index] = NULL;
767 } else {
768 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
769 length = skb->len;
770 txq->tx_skb[tx_index] = skb;
771 }
772
773 desc->byte_cnt = length;
774 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
775
776 if (skb->ip_summed == CHECKSUM_PARTIAL) {
777 int mac_hdr_len;
778
779 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
780 skb->protocol != htons(ETH_P_8021Q));
781
782 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
783 GEN_IP_V4_CHECKSUM |
784 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
785
786 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
787 switch (mac_hdr_len - ETH_HLEN) {
788 case 0:
789 break;
790 case 4:
791 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
792 break;
793 case 8:
794 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
795 break;
796 case 12:
797 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
798 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
799 break;
800 default:
801 if (net_ratelimit())
802 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
803 "mac header length is %d?!\n", mac_hdr_len);
804 break;
805 }
806
807 switch (ip_hdr(skb)->protocol) {
808 case IPPROTO_UDP:
809 cmd_sts |= UDP_FRAME;
810 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
811 break;
812 case IPPROTO_TCP:
813 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
814 break;
815 default:
816 BUG();
817 }
818 } else {
819 /* Errata BTS #50, IHL must be 5 if no HW checksum */
820 cmd_sts |= 5 << TX_IHL_SHIFT;
821 desc->l4i_chk = 0;
822 }
823
824 /* ensure all other descriptors are written before first cmd_sts */
825 wmb();
826 desc->cmd_sts = cmd_sts;
827
828 /* clear TX_END interrupt status */
829 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
830 rdl(mp, INT_CAUSE(mp->port_num));
831
832 /* ensure all descriptors are written before poking hardware */
833 wmb();
834 txq_enable(txq);
835
836 txq->tx_desc_count += nr_frags + 1;
837 }
838
839 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
840 {
841 struct mv643xx_eth_private *mp = netdev_priv(dev);
842 struct net_device_stats *stats = &dev->stats;
843 struct tx_queue *txq;
844 unsigned long flags;
845
846 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
847 stats->tx_dropped++;
848 dev_printk(KERN_DEBUG, &dev->dev,
849 "failed to linearize skb with tiny "
850 "unaligned fragment\n");
851 return NETDEV_TX_BUSY;
852 }
853
854 spin_lock_irqsave(&mp->lock, flags);
855
856 txq = mp->txq + mp->txq_primary;
857
858 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
859 spin_unlock_irqrestore(&mp->lock, flags);
860 if (txq->index == mp->txq_primary && net_ratelimit())
861 dev_printk(KERN_ERR, &dev->dev,
862 "primary tx queue full?!\n");
863 kfree_skb(skb);
864 return NETDEV_TX_OK;
865 }
866
867 txq_submit_skb(txq, skb);
868 stats->tx_bytes += skb->len;
869 stats->tx_packets++;
870 dev->trans_start = jiffies;
871
872 if (txq->index == mp->txq_primary) {
873 int entries_left;
874
875 entries_left = txq->tx_ring_size - txq->tx_desc_count;
876 if (entries_left < MAX_DESCS_PER_SKB)
877 netif_stop_queue(dev);
878 }
879
880 spin_unlock_irqrestore(&mp->lock, flags);
881
882 return NETDEV_TX_OK;
883 }
884
885
886 /* tx rate control **********************************************************/
887 /*
888 * Set total maximum TX rate (shared by all TX queues for this port)
889 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
890 */
891 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
892 {
893 int token_rate;
894 int mtu;
895 int bucket_size;
896
897 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
898 if (token_rate > 1023)
899 token_rate = 1023;
900
901 mtu = (mp->dev->mtu + 255) >> 8;
902 if (mtu > 63)
903 mtu = 63;
904
905 bucket_size = (burst + 255) >> 8;
906 if (bucket_size > 65535)
907 bucket_size = 65535;
908
909 if (mp->shared->tx_bw_control_moved) {
910 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
911 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
912 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
913 } else {
914 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
915 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
916 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
917 }
918 }
919
920 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
921 {
922 struct mv643xx_eth_private *mp = txq_to_mp(txq);
923 int token_rate;
924 int bucket_size;
925
926 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
927 if (token_rate > 1023)
928 token_rate = 1023;
929
930 bucket_size = (burst + 255) >> 8;
931 if (bucket_size > 65535)
932 bucket_size = 65535;
933
934 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
935 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
936 (bucket_size << 10) | token_rate);
937 }
938
939 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
940 {
941 struct mv643xx_eth_private *mp = txq_to_mp(txq);
942 int off;
943 u32 val;
944
945 /*
946 * Turn on fixed priority mode.
947 */
948 if (mp->shared->tx_bw_control_moved)
949 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
950 else
951 off = TXQ_FIX_PRIO_CONF(mp->port_num);
952
953 val = rdl(mp, off);
954 val |= 1 << txq->index;
955 wrl(mp, off, val);
956 }
957
958 static void txq_set_wrr(struct tx_queue *txq, int weight)
959 {
960 struct mv643xx_eth_private *mp = txq_to_mp(txq);
961 int off;
962 u32 val;
963
964 /*
965 * Turn off fixed priority mode.
966 */
967 if (mp->shared->tx_bw_control_moved)
968 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
969 else
970 off = TXQ_FIX_PRIO_CONF(mp->port_num);
971
972 val = rdl(mp, off);
973 val &= ~(1 << txq->index);
974 wrl(mp, off, val);
975
976 /*
977 * Configure WRR weight for this queue.
978 */
979 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
980
981 val = rdl(mp, off);
982 val = (val & ~0xff) | (weight & 0xff);
983 wrl(mp, off, val);
984 }
985
986
987 /* mii management interface *************************************************/
988 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
989 {
990 struct mv643xx_eth_shared_private *msp = dev_id;
991
992 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
993 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
994 wake_up(&msp->smi_busy_wait);
995 return IRQ_HANDLED;
996 }
997
998 return IRQ_NONE;
999 }
1000
1001 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1002 {
1003 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1004 }
1005
1006 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1007 {
1008 if (msp->err_interrupt == NO_IRQ) {
1009 int i;
1010
1011 for (i = 0; !smi_is_done(msp); i++) {
1012 if (i == 10)
1013 return -ETIMEDOUT;
1014 msleep(10);
1015 }
1016
1017 return 0;
1018 }
1019
1020 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1021 msecs_to_jiffies(100)))
1022 return -ETIMEDOUT;
1023
1024 return 0;
1025 }
1026
1027 static int smi_reg_read(struct mv643xx_eth_private *mp,
1028 unsigned int addr, unsigned int reg)
1029 {
1030 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1031 void __iomem *smi_reg = msp->base + SMI_REG;
1032 int ret;
1033
1034 mutex_lock(&msp->phy_lock);
1035
1036 if (smi_wait_ready(msp)) {
1037 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1038 ret = -ETIMEDOUT;
1039 goto out;
1040 }
1041
1042 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1043
1044 if (smi_wait_ready(msp)) {
1045 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1046 ret = -ETIMEDOUT;
1047 goto out;
1048 }
1049
1050 ret = readl(smi_reg);
1051 if (!(ret & SMI_READ_VALID)) {
1052 printk("%s: SMI bus read not valid\n", mp->dev->name);
1053 ret = -ENODEV;
1054 goto out;
1055 }
1056
1057 ret &= 0xffff;
1058
1059 out:
1060 mutex_unlock(&msp->phy_lock);
1061
1062 return ret;
1063 }
1064
1065 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1066 unsigned int reg, unsigned int value)
1067 {
1068 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1069 void __iomem *smi_reg = msp->base + SMI_REG;
1070
1071 mutex_lock(&msp->phy_lock);
1072
1073 if (smi_wait_ready(msp)) {
1074 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1075 mutex_unlock(&msp->phy_lock);
1076 return -ETIMEDOUT;
1077 }
1078
1079 writel(SMI_OPCODE_WRITE | (reg << 21) |
1080 (addr << 16) | (value & 0xffff), smi_reg);
1081
1082 mutex_unlock(&msp->phy_lock);
1083
1084 return 0;
1085 }
1086
1087
1088 /* mib counters *************************************************************/
1089 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1090 {
1091 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1092 }
1093
1094 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1095 {
1096 int i;
1097
1098 for (i = 0; i < 0x80; i += 4)
1099 mib_read(mp, i);
1100 }
1101
1102 static void mib_counters_update(struct mv643xx_eth_private *mp)
1103 {
1104 struct mib_counters *p = &mp->mib_counters;
1105
1106 p->good_octets_received += mib_read(mp, 0x00);
1107 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1108 p->bad_octets_received += mib_read(mp, 0x08);
1109 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1110 p->good_frames_received += mib_read(mp, 0x10);
1111 p->bad_frames_received += mib_read(mp, 0x14);
1112 p->broadcast_frames_received += mib_read(mp, 0x18);
1113 p->multicast_frames_received += mib_read(mp, 0x1c);
1114 p->frames_64_octets += mib_read(mp, 0x20);
1115 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1116 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1117 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1118 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1119 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1120 p->good_octets_sent += mib_read(mp, 0x38);
1121 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1122 p->good_frames_sent += mib_read(mp, 0x40);
1123 p->excessive_collision += mib_read(mp, 0x44);
1124 p->multicast_frames_sent += mib_read(mp, 0x48);
1125 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1126 p->unrec_mac_control_received += mib_read(mp, 0x50);
1127 p->fc_sent += mib_read(mp, 0x54);
1128 p->good_fc_received += mib_read(mp, 0x58);
1129 p->bad_fc_received += mib_read(mp, 0x5c);
1130 p->undersize_received += mib_read(mp, 0x60);
1131 p->fragments_received += mib_read(mp, 0x64);
1132 p->oversize_received += mib_read(mp, 0x68);
1133 p->jabber_received += mib_read(mp, 0x6c);
1134 p->mac_receive_error += mib_read(mp, 0x70);
1135 p->bad_crc_event += mib_read(mp, 0x74);
1136 p->collision += mib_read(mp, 0x78);
1137 p->late_collision += mib_read(mp, 0x7c);
1138 }
1139
1140
1141 /* ethtool ******************************************************************/
1142 struct mv643xx_eth_stats {
1143 char stat_string[ETH_GSTRING_LEN];
1144 int sizeof_stat;
1145 int netdev_off;
1146 int mp_off;
1147 };
1148
1149 #define SSTAT(m) \
1150 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1151 offsetof(struct net_device, stats.m), -1 }
1152
1153 #define MIBSTAT(m) \
1154 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1155 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1156
1157 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1158 SSTAT(rx_packets),
1159 SSTAT(tx_packets),
1160 SSTAT(rx_bytes),
1161 SSTAT(tx_bytes),
1162 SSTAT(rx_errors),
1163 SSTAT(tx_errors),
1164 SSTAT(rx_dropped),
1165 SSTAT(tx_dropped),
1166 MIBSTAT(good_octets_received),
1167 MIBSTAT(bad_octets_received),
1168 MIBSTAT(internal_mac_transmit_err),
1169 MIBSTAT(good_frames_received),
1170 MIBSTAT(bad_frames_received),
1171 MIBSTAT(broadcast_frames_received),
1172 MIBSTAT(multicast_frames_received),
1173 MIBSTAT(frames_64_octets),
1174 MIBSTAT(frames_65_to_127_octets),
1175 MIBSTAT(frames_128_to_255_octets),
1176 MIBSTAT(frames_256_to_511_octets),
1177 MIBSTAT(frames_512_to_1023_octets),
1178 MIBSTAT(frames_1024_to_max_octets),
1179 MIBSTAT(good_octets_sent),
1180 MIBSTAT(good_frames_sent),
1181 MIBSTAT(excessive_collision),
1182 MIBSTAT(multicast_frames_sent),
1183 MIBSTAT(broadcast_frames_sent),
1184 MIBSTAT(unrec_mac_control_received),
1185 MIBSTAT(fc_sent),
1186 MIBSTAT(good_fc_received),
1187 MIBSTAT(bad_fc_received),
1188 MIBSTAT(undersize_received),
1189 MIBSTAT(fragments_received),
1190 MIBSTAT(oversize_received),
1191 MIBSTAT(jabber_received),
1192 MIBSTAT(mac_receive_error),
1193 MIBSTAT(bad_crc_event),
1194 MIBSTAT(collision),
1195 MIBSTAT(late_collision),
1196 };
1197
1198 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1199 {
1200 struct mv643xx_eth_private *mp = netdev_priv(dev);
1201 int err;
1202
1203 err = mii_ethtool_gset(&mp->mii, cmd);
1204
1205 /*
1206 * The MAC does not support 1000baseT_Half.
1207 */
1208 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1209 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1210
1211 return err;
1212 }
1213
1214 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1215 {
1216 struct mv643xx_eth_private *mp = netdev_priv(dev);
1217 u32 port_status;
1218
1219 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1220
1221 cmd->supported = SUPPORTED_MII;
1222 cmd->advertising = ADVERTISED_MII;
1223 switch (port_status & PORT_SPEED_MASK) {
1224 case PORT_SPEED_10:
1225 cmd->speed = SPEED_10;
1226 break;
1227 case PORT_SPEED_100:
1228 cmd->speed = SPEED_100;
1229 break;
1230 case PORT_SPEED_1000:
1231 cmd->speed = SPEED_1000;
1232 break;
1233 default:
1234 cmd->speed = -1;
1235 break;
1236 }
1237 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1238 cmd->port = PORT_MII;
1239 cmd->phy_address = 0;
1240 cmd->transceiver = XCVR_INTERNAL;
1241 cmd->autoneg = AUTONEG_DISABLE;
1242 cmd->maxtxpkt = 1;
1243 cmd->maxrxpkt = 1;
1244
1245 return 0;
1246 }
1247
1248 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1249 {
1250 struct mv643xx_eth_private *mp = netdev_priv(dev);
1251
1252 /*
1253 * The MAC does not support 1000baseT_Half.
1254 */
1255 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1256
1257 return mii_ethtool_sset(&mp->mii, cmd);
1258 }
1259
1260 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1261 {
1262 return -EINVAL;
1263 }
1264
1265 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1266 struct ethtool_drvinfo *drvinfo)
1267 {
1268 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1269 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1270 strncpy(drvinfo->fw_version, "N/A", 32);
1271 strncpy(drvinfo->bus_info, "platform", 32);
1272 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1273 }
1274
1275 static int mv643xx_eth_nway_reset(struct net_device *dev)
1276 {
1277 struct mv643xx_eth_private *mp = netdev_priv(dev);
1278
1279 return mii_nway_restart(&mp->mii);
1280 }
1281
1282 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1283 {
1284 return -EINVAL;
1285 }
1286
1287 static u32 mv643xx_eth_get_link(struct net_device *dev)
1288 {
1289 struct mv643xx_eth_private *mp = netdev_priv(dev);
1290
1291 return mii_link_ok(&mp->mii);
1292 }
1293
1294 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1295 {
1296 return 1;
1297 }
1298
1299 static void mv643xx_eth_get_strings(struct net_device *dev,
1300 uint32_t stringset, uint8_t *data)
1301 {
1302 int i;
1303
1304 if (stringset == ETH_SS_STATS) {
1305 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1306 memcpy(data + i * ETH_GSTRING_LEN,
1307 mv643xx_eth_stats[i].stat_string,
1308 ETH_GSTRING_LEN);
1309 }
1310 }
1311 }
1312
1313 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1314 struct ethtool_stats *stats,
1315 uint64_t *data)
1316 {
1317 struct mv643xx_eth_private *mp = netdev_priv(dev);
1318 int i;
1319
1320 mib_counters_update(mp);
1321
1322 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1323 const struct mv643xx_eth_stats *stat;
1324 void *p;
1325
1326 stat = mv643xx_eth_stats + i;
1327
1328 if (stat->netdev_off >= 0)
1329 p = ((void *)mp->dev) + stat->netdev_off;
1330 else
1331 p = ((void *)mp) + stat->mp_off;
1332
1333 data[i] = (stat->sizeof_stat == 8) ?
1334 *(uint64_t *)p : *(uint32_t *)p;
1335 }
1336 }
1337
1338 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1339 {
1340 if (sset == ETH_SS_STATS)
1341 return ARRAY_SIZE(mv643xx_eth_stats);
1342
1343 return -EOPNOTSUPP;
1344 }
1345
1346 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1347 .get_settings = mv643xx_eth_get_settings,
1348 .set_settings = mv643xx_eth_set_settings,
1349 .get_drvinfo = mv643xx_eth_get_drvinfo,
1350 .nway_reset = mv643xx_eth_nway_reset,
1351 .get_link = mv643xx_eth_get_link,
1352 .set_sg = ethtool_op_set_sg,
1353 .get_strings = mv643xx_eth_get_strings,
1354 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1355 .get_sset_count = mv643xx_eth_get_sset_count,
1356 };
1357
1358 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1359 .get_settings = mv643xx_eth_get_settings_phyless,
1360 .set_settings = mv643xx_eth_set_settings_phyless,
1361 .get_drvinfo = mv643xx_eth_get_drvinfo,
1362 .nway_reset = mv643xx_eth_nway_reset_phyless,
1363 .get_link = mv643xx_eth_get_link_phyless,
1364 .set_sg = ethtool_op_set_sg,
1365 .get_strings = mv643xx_eth_get_strings,
1366 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1367 .get_sset_count = mv643xx_eth_get_sset_count,
1368 };
1369
1370
1371 /* address handling *********************************************************/
1372 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1373 {
1374 unsigned int mac_h;
1375 unsigned int mac_l;
1376
1377 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1378 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1379
1380 addr[0] = (mac_h >> 24) & 0xff;
1381 addr[1] = (mac_h >> 16) & 0xff;
1382 addr[2] = (mac_h >> 8) & 0xff;
1383 addr[3] = mac_h & 0xff;
1384 addr[4] = (mac_l >> 8) & 0xff;
1385 addr[5] = mac_l & 0xff;
1386 }
1387
1388 static void init_mac_tables(struct mv643xx_eth_private *mp)
1389 {
1390 int i;
1391
1392 for (i = 0; i < 0x100; i += 4) {
1393 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1394 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1395 }
1396
1397 for (i = 0; i < 0x10; i += 4)
1398 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1399 }
1400
1401 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1402 int table, unsigned char entry)
1403 {
1404 unsigned int table_reg;
1405
1406 /* Set "accepts frame bit" at specified table entry */
1407 table_reg = rdl(mp, table + (entry & 0xfc));
1408 table_reg |= 0x01 << (8 * (entry & 3));
1409 wrl(mp, table + (entry & 0xfc), table_reg);
1410 }
1411
1412 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1413 {
1414 unsigned int mac_h;
1415 unsigned int mac_l;
1416 int table;
1417
1418 mac_l = (addr[4] << 8) | addr[5];
1419 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1420
1421 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1422 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1423
1424 table = UNICAST_TABLE(mp->port_num);
1425 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1426 }
1427
1428 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1429 {
1430 struct mv643xx_eth_private *mp = netdev_priv(dev);
1431
1432 /* +2 is for the offset of the HW addr type */
1433 memcpy(dev->dev_addr, addr + 2, 6);
1434
1435 init_mac_tables(mp);
1436 uc_addr_set(mp, dev->dev_addr);
1437
1438 return 0;
1439 }
1440
1441 static int addr_crc(unsigned char *addr)
1442 {
1443 int crc = 0;
1444 int i;
1445
1446 for (i = 0; i < 6; i++) {
1447 int j;
1448
1449 crc = (crc ^ addr[i]) << 8;
1450 for (j = 7; j >= 0; j--) {
1451 if (crc & (0x100 << j))
1452 crc ^= 0x107 << j;
1453 }
1454 }
1455
1456 return crc;
1457 }
1458
1459 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1460 {
1461 struct mv643xx_eth_private *mp = netdev_priv(dev);
1462 u32 port_config;
1463 struct dev_addr_list *addr;
1464 int i;
1465
1466 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1467 if (dev->flags & IFF_PROMISC)
1468 port_config |= UNICAST_PROMISCUOUS_MODE;
1469 else
1470 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1471 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1472
1473 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1474 int port_num = mp->port_num;
1475 u32 accept = 0x01010101;
1476
1477 for (i = 0; i < 0x100; i += 4) {
1478 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1479 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1480 }
1481 return;
1482 }
1483
1484 for (i = 0; i < 0x100; i += 4) {
1485 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1486 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1487 }
1488
1489 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1490 u8 *a = addr->da_addr;
1491 int table;
1492
1493 if (addr->da_addrlen != 6)
1494 continue;
1495
1496 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1497 table = SPECIAL_MCAST_TABLE(mp->port_num);
1498 set_filter_table_entry(mp, table, a[5]);
1499 } else {
1500 int crc = addr_crc(a);
1501
1502 table = OTHER_MCAST_TABLE(mp->port_num);
1503 set_filter_table_entry(mp, table, crc);
1504 }
1505 }
1506 }
1507
1508
1509 /* rx/tx queue initialisation ***********************************************/
1510 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1511 {
1512 struct rx_queue *rxq = mp->rxq + index;
1513 struct rx_desc *rx_desc;
1514 int size;
1515 int i;
1516
1517 rxq->index = index;
1518
1519 rxq->rx_ring_size = mp->default_rx_ring_size;
1520
1521 rxq->rx_desc_count = 0;
1522 rxq->rx_curr_desc = 0;
1523 rxq->rx_used_desc = 0;
1524
1525 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1526
1527 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1528 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1529 mp->rx_desc_sram_size);
1530 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1531 } else {
1532 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1533 &rxq->rx_desc_dma,
1534 GFP_KERNEL);
1535 }
1536
1537 if (rxq->rx_desc_area == NULL) {
1538 dev_printk(KERN_ERR, &mp->dev->dev,
1539 "can't allocate rx ring (%d bytes)\n", size);
1540 goto out;
1541 }
1542 memset(rxq->rx_desc_area, 0, size);
1543
1544 rxq->rx_desc_area_size = size;
1545 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1546 GFP_KERNEL);
1547 if (rxq->rx_skb == NULL) {
1548 dev_printk(KERN_ERR, &mp->dev->dev,
1549 "can't allocate rx skb ring\n");
1550 goto out_free;
1551 }
1552
1553 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1554 for (i = 0; i < rxq->rx_ring_size; i++) {
1555 int nexti;
1556
1557 nexti = i + 1;
1558 if (nexti == rxq->rx_ring_size)
1559 nexti = 0;
1560
1561 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1562 nexti * sizeof(struct rx_desc);
1563 }
1564
1565 return 0;
1566
1567
1568 out_free:
1569 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1570 iounmap(rxq->rx_desc_area);
1571 else
1572 dma_free_coherent(NULL, size,
1573 rxq->rx_desc_area,
1574 rxq->rx_desc_dma);
1575
1576 out:
1577 return -ENOMEM;
1578 }
1579
1580 static void rxq_deinit(struct rx_queue *rxq)
1581 {
1582 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1583 int i;
1584
1585 rxq_disable(rxq);
1586
1587 for (i = 0; i < rxq->rx_ring_size; i++) {
1588 if (rxq->rx_skb[i]) {
1589 dev_kfree_skb(rxq->rx_skb[i]);
1590 rxq->rx_desc_count--;
1591 }
1592 }
1593
1594 if (rxq->rx_desc_count) {
1595 dev_printk(KERN_ERR, &mp->dev->dev,
1596 "error freeing rx ring -- %d skbs stuck\n",
1597 rxq->rx_desc_count);
1598 }
1599
1600 if (rxq->index == mp->rxq_primary &&
1601 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1602 iounmap(rxq->rx_desc_area);
1603 else
1604 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1605 rxq->rx_desc_area, rxq->rx_desc_dma);
1606
1607 kfree(rxq->rx_skb);
1608 }
1609
1610 static int txq_init(struct mv643xx_eth_private *mp, int index)
1611 {
1612 struct tx_queue *txq = mp->txq + index;
1613 struct tx_desc *tx_desc;
1614 int size;
1615 int i;
1616
1617 txq->index = index;
1618
1619 txq->tx_ring_size = mp->default_tx_ring_size;
1620
1621 txq->tx_desc_count = 0;
1622 txq->tx_curr_desc = 0;
1623 txq->tx_used_desc = 0;
1624
1625 size = txq->tx_ring_size * sizeof(struct tx_desc);
1626
1627 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1628 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1629 mp->tx_desc_sram_size);
1630 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1631 } else {
1632 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1633 &txq->tx_desc_dma,
1634 GFP_KERNEL);
1635 }
1636
1637 if (txq->tx_desc_area == NULL) {
1638 dev_printk(KERN_ERR, &mp->dev->dev,
1639 "can't allocate tx ring (%d bytes)\n", size);
1640 goto out;
1641 }
1642 memset(txq->tx_desc_area, 0, size);
1643
1644 txq->tx_desc_area_size = size;
1645 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1646 GFP_KERNEL);
1647 if (txq->tx_skb == NULL) {
1648 dev_printk(KERN_ERR, &mp->dev->dev,
1649 "can't allocate tx skb ring\n");
1650 goto out_free;
1651 }
1652
1653 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1654 for (i = 0; i < txq->tx_ring_size; i++) {
1655 struct tx_desc *txd = tx_desc + i;
1656 int nexti;
1657
1658 nexti = i + 1;
1659 if (nexti == txq->tx_ring_size)
1660 nexti = 0;
1661
1662 txd->cmd_sts = 0;
1663 txd->next_desc_ptr = txq->tx_desc_dma +
1664 nexti * sizeof(struct tx_desc);
1665 }
1666
1667 return 0;
1668
1669
1670 out_free:
1671 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1672 iounmap(txq->tx_desc_area);
1673 else
1674 dma_free_coherent(NULL, size,
1675 txq->tx_desc_area,
1676 txq->tx_desc_dma);
1677
1678 out:
1679 return -ENOMEM;
1680 }
1681
1682 static void txq_reclaim(struct tx_queue *txq, int force)
1683 {
1684 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1685 unsigned long flags;
1686
1687 spin_lock_irqsave(&mp->lock, flags);
1688 while (txq->tx_desc_count > 0) {
1689 int tx_index;
1690 struct tx_desc *desc;
1691 u32 cmd_sts;
1692 struct sk_buff *skb;
1693 dma_addr_t addr;
1694 int count;
1695
1696 tx_index = txq->tx_used_desc;
1697 desc = &txq->tx_desc_area[tx_index];
1698 cmd_sts = desc->cmd_sts;
1699
1700 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1701 if (!force)
1702 break;
1703 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1704 }
1705
1706 txq->tx_used_desc = tx_index + 1;
1707 if (txq->tx_used_desc == txq->tx_ring_size)
1708 txq->tx_used_desc = 0;
1709 txq->tx_desc_count--;
1710
1711 addr = desc->buf_ptr;
1712 count = desc->byte_cnt;
1713 skb = txq->tx_skb[tx_index];
1714 txq->tx_skb[tx_index] = NULL;
1715
1716 if (cmd_sts & ERROR_SUMMARY) {
1717 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1718 mp->dev->stats.tx_errors++;
1719 }
1720
1721 /*
1722 * Drop mp->lock while we free the skb.
1723 */
1724 spin_unlock_irqrestore(&mp->lock, flags);
1725
1726 if (cmd_sts & TX_FIRST_DESC)
1727 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1728 else
1729 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1730
1731 if (skb)
1732 dev_kfree_skb_irq(skb);
1733
1734 spin_lock_irqsave(&mp->lock, flags);
1735 }
1736 spin_unlock_irqrestore(&mp->lock, flags);
1737 }
1738
1739 static void txq_deinit(struct tx_queue *txq)
1740 {
1741 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1742
1743 txq_disable(txq);
1744 txq_reclaim(txq, 1);
1745
1746 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1747
1748 if (txq->index == mp->txq_primary &&
1749 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1750 iounmap(txq->tx_desc_area);
1751 else
1752 dma_free_coherent(NULL, txq->tx_desc_area_size,
1753 txq->tx_desc_area, txq->tx_desc_dma);
1754
1755 kfree(txq->tx_skb);
1756 }
1757
1758
1759 /* netdev ops and related ***************************************************/
1760 static void handle_link_event(struct mv643xx_eth_private *mp)
1761 {
1762 struct net_device *dev = mp->dev;
1763 u32 port_status;
1764 int speed;
1765 int duplex;
1766 int fc;
1767
1768 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1769 if (!(port_status & LINK_UP)) {
1770 if (netif_carrier_ok(dev)) {
1771 int i;
1772
1773 printk(KERN_INFO "%s: link down\n", dev->name);
1774
1775 netif_carrier_off(dev);
1776 netif_stop_queue(dev);
1777
1778 for (i = 0; i < 8; i++) {
1779 struct tx_queue *txq = mp->txq + i;
1780
1781 if (mp->txq_mask & (1 << i)) {
1782 txq_reclaim(txq, 1);
1783 txq_reset_hw_ptr(txq);
1784 }
1785 }
1786 }
1787 return;
1788 }
1789
1790 switch (port_status & PORT_SPEED_MASK) {
1791 case PORT_SPEED_10:
1792 speed = 10;
1793 break;
1794 case PORT_SPEED_100:
1795 speed = 100;
1796 break;
1797 case PORT_SPEED_1000:
1798 speed = 1000;
1799 break;
1800 default:
1801 speed = -1;
1802 break;
1803 }
1804 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1805 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1806
1807 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1808 "flow control %sabled\n", dev->name,
1809 speed, duplex ? "full" : "half",
1810 fc ? "en" : "dis");
1811
1812 if (!netif_carrier_ok(dev)) {
1813 netif_carrier_on(dev);
1814 netif_wake_queue(dev);
1815 }
1816 }
1817
1818 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1819 {
1820 struct net_device *dev = (struct net_device *)dev_id;
1821 struct mv643xx_eth_private *mp = netdev_priv(dev);
1822 u32 int_cause;
1823 u32 int_cause_ext;
1824
1825 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1826 (INT_TX_END | INT_RX | INT_EXT);
1827 if (int_cause == 0)
1828 return IRQ_NONE;
1829
1830 int_cause_ext = 0;
1831 if (int_cause & INT_EXT) {
1832 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1833 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1834 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1835 }
1836
1837 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1838 handle_link_event(mp);
1839
1840 /*
1841 * RxBuffer or RxError set for any of the 8 queues?
1842 */
1843 if (int_cause & INT_RX) {
1844 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1845 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1846 rdl(mp, INT_MASK(mp->port_num));
1847
1848 napi_schedule(&mp->napi);
1849 }
1850
1851 /*
1852 * TxBuffer or TxError set for any of the 8 queues?
1853 */
1854 if (int_cause_ext & INT_EXT_TX) {
1855 int i;
1856
1857 for (i = 0; i < 8; i++)
1858 if (mp->txq_mask & (1 << i))
1859 txq_reclaim(mp->txq + i, 0);
1860
1861 /*
1862 * Enough space again in the primary TX queue for a
1863 * full packet?
1864 */
1865 if (netif_carrier_ok(dev)) {
1866 spin_lock(&mp->lock);
1867 __txq_maybe_wake(mp->txq + mp->txq_primary);
1868 spin_unlock(&mp->lock);
1869 }
1870 }
1871
1872 /*
1873 * Any TxEnd interrupts?
1874 */
1875 if (int_cause & INT_TX_END) {
1876 int i;
1877
1878 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1879
1880 spin_lock(&mp->lock);
1881 for (i = 0; i < 8; i++) {
1882 struct tx_queue *txq = mp->txq + i;
1883 u32 hw_desc_ptr;
1884 u32 expected_ptr;
1885
1886 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1887 continue;
1888
1889 hw_desc_ptr =
1890 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1891 expected_ptr = (u32)txq->tx_desc_dma +
1892 txq->tx_curr_desc * sizeof(struct tx_desc);
1893
1894 if (hw_desc_ptr != expected_ptr)
1895 txq_enable(txq);
1896 }
1897 spin_unlock(&mp->lock);
1898 }
1899
1900 return IRQ_HANDLED;
1901 }
1902
1903 static void phy_reset(struct mv643xx_eth_private *mp)
1904 {
1905 int data;
1906
1907 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1908 if (data < 0)
1909 return;
1910
1911 data |= BMCR_RESET;
1912 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1913 return;
1914
1915 do {
1916 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1917 } while (data >= 0 && data & BMCR_RESET);
1918 }
1919
1920 static void port_start(struct mv643xx_eth_private *mp)
1921 {
1922 u32 pscr;
1923 int i;
1924
1925 /*
1926 * Perform PHY reset, if there is a PHY.
1927 */
1928 if (mp->phy_addr != -1) {
1929 struct ethtool_cmd cmd;
1930
1931 mv643xx_eth_get_settings(mp->dev, &cmd);
1932 phy_reset(mp);
1933 mv643xx_eth_set_settings(mp->dev, &cmd);
1934 }
1935
1936 /*
1937 * Configure basic link parameters.
1938 */
1939 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1940
1941 pscr |= SERIAL_PORT_ENABLE;
1942 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1943
1944 pscr |= DO_NOT_FORCE_LINK_FAIL;
1945 if (mp->phy_addr == -1)
1946 pscr |= FORCE_LINK_PASS;
1947 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1948
1949 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1950
1951 /*
1952 * Configure TX path and queues.
1953 */
1954 tx_set_rate(mp, 1000000000, 16777216);
1955 for (i = 0; i < 8; i++) {
1956 struct tx_queue *txq = mp->txq + i;
1957
1958 if ((mp->txq_mask & (1 << i)) == 0)
1959 continue;
1960
1961 txq_reset_hw_ptr(txq);
1962 txq_set_rate(txq, 1000000000, 16777216);
1963 txq_set_fixed_prio_mode(txq);
1964 }
1965
1966 /*
1967 * Add configured unicast address to address filter table.
1968 */
1969 uc_addr_set(mp, mp->dev->dev_addr);
1970
1971 /*
1972 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1973 * frames to RX queue #0.
1974 */
1975 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1976
1977 /*
1978 * Treat BPDUs as normal multicasts, and disable partition mode.
1979 */
1980 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1981
1982 /*
1983 * Enable the receive queues.
1984 */
1985 for (i = 0; i < 8; i++) {
1986 struct rx_queue *rxq = mp->rxq + i;
1987 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1988 u32 addr;
1989
1990 if ((mp->rxq_mask & (1 << i)) == 0)
1991 continue;
1992
1993 addr = (u32)rxq->rx_desc_dma;
1994 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1995 wrl(mp, off, addr);
1996
1997 rxq_enable(rxq);
1998 }
1999 }
2000
2001 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2002 {
2003 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2004 u32 val;
2005
2006 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2007 if (mp->shared->extended_rx_coal_limit) {
2008 if (coal > 0xffff)
2009 coal = 0xffff;
2010 val &= ~0x023fff80;
2011 val |= (coal & 0x8000) << 10;
2012 val |= (coal & 0x7fff) << 7;
2013 } else {
2014 if (coal > 0x3fff)
2015 coal = 0x3fff;
2016 val &= ~0x003fff00;
2017 val |= (coal & 0x3fff) << 8;
2018 }
2019 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2020 }
2021
2022 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2023 {
2024 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2025
2026 if (coal > 0x3fff)
2027 coal = 0x3fff;
2028 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2029 }
2030
2031 static int mv643xx_eth_open(struct net_device *dev)
2032 {
2033 struct mv643xx_eth_private *mp = netdev_priv(dev);
2034 int err;
2035 int oom;
2036 int i;
2037
2038 wrl(mp, INT_CAUSE(mp->port_num), 0);
2039 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2040 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2041
2042 err = request_irq(dev->irq, mv643xx_eth_irq,
2043 IRQF_SHARED, dev->name, dev);
2044 if (err) {
2045 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2046 return -EAGAIN;
2047 }
2048
2049 init_mac_tables(mp);
2050
2051 napi_enable(&mp->napi);
2052
2053 oom = 0;
2054 for (i = 0; i < 8; i++) {
2055 if ((mp->rxq_mask & (1 << i)) == 0)
2056 continue;
2057
2058 err = rxq_init(mp, i);
2059 if (err) {
2060 while (--i >= 0)
2061 if (mp->rxq_mask & (1 << i))
2062 rxq_deinit(mp->rxq + i);
2063 goto out;
2064 }
2065
2066 rxq_refill(mp->rxq + i, INT_MAX, &oom);
2067 }
2068
2069 if (oom) {
2070 mp->rx_oom.expires = jiffies + (HZ / 10);
2071 add_timer(&mp->rx_oom);
2072 }
2073
2074 for (i = 0; i < 8; i++) {
2075 if ((mp->txq_mask & (1 << i)) == 0)
2076 continue;
2077
2078 err = txq_init(mp, i);
2079 if (err) {
2080 while (--i >= 0)
2081 if (mp->txq_mask & (1 << i))
2082 txq_deinit(mp->txq + i);
2083 goto out_free;
2084 }
2085 }
2086
2087 netif_carrier_off(dev);
2088 netif_stop_queue(dev);
2089
2090 port_start(mp);
2091
2092 set_rx_coal(mp, 0);
2093 set_tx_coal(mp, 0);
2094
2095 wrl(mp, INT_MASK_EXT(mp->port_num),
2096 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2097
2098 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2099
2100 return 0;
2101
2102
2103 out_free:
2104 for (i = 0; i < 8; i++)
2105 if (mp->rxq_mask & (1 << i))
2106 rxq_deinit(mp->rxq + i);
2107 out:
2108 free_irq(dev->irq, dev);
2109
2110 return err;
2111 }
2112
2113 static void port_reset(struct mv643xx_eth_private *mp)
2114 {
2115 unsigned int data;
2116 int i;
2117
2118 for (i = 0; i < 8; i++) {
2119 if (mp->rxq_mask & (1 << i))
2120 rxq_disable(mp->rxq + i);
2121 if (mp->txq_mask & (1 << i))
2122 txq_disable(mp->txq + i);
2123 }
2124
2125 while (1) {
2126 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2127
2128 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2129 break;
2130 udelay(10);
2131 }
2132
2133 /* Reset the Enable bit in the Configuration Register */
2134 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2135 data &= ~(SERIAL_PORT_ENABLE |
2136 DO_NOT_FORCE_LINK_FAIL |
2137 FORCE_LINK_PASS);
2138 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2139 }
2140
2141 static int mv643xx_eth_stop(struct net_device *dev)
2142 {
2143 struct mv643xx_eth_private *mp = netdev_priv(dev);
2144 int i;
2145
2146 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2147 rdl(mp, INT_MASK(mp->port_num));
2148
2149 napi_disable(&mp->napi);
2150
2151 del_timer_sync(&mp->rx_oom);
2152
2153 netif_carrier_off(dev);
2154 netif_stop_queue(dev);
2155
2156 free_irq(dev->irq, dev);
2157
2158 port_reset(mp);
2159 mib_counters_update(mp);
2160
2161 for (i = 0; i < 8; i++) {
2162 if (mp->rxq_mask & (1 << i))
2163 rxq_deinit(mp->rxq + i);
2164 if (mp->txq_mask & (1 << i))
2165 txq_deinit(mp->txq + i);
2166 }
2167
2168 return 0;
2169 }
2170
2171 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2172 {
2173 struct mv643xx_eth_private *mp = netdev_priv(dev);
2174
2175 if (mp->phy_addr != -1)
2176 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2177
2178 return -EOPNOTSUPP;
2179 }
2180
2181 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2182 {
2183 struct mv643xx_eth_private *mp = netdev_priv(dev);
2184
2185 if (new_mtu < 64 || new_mtu > 9500)
2186 return -EINVAL;
2187
2188 dev->mtu = new_mtu;
2189 tx_set_rate(mp, 1000000000, 16777216);
2190
2191 if (!netif_running(dev))
2192 return 0;
2193
2194 /*
2195 * Stop and then re-open the interface. This will allocate RX
2196 * skbs of the new MTU.
2197 * There is a possible danger that the open will not succeed,
2198 * due to memory being full.
2199 */
2200 mv643xx_eth_stop(dev);
2201 if (mv643xx_eth_open(dev)) {
2202 dev_printk(KERN_ERR, &dev->dev,
2203 "fatal error on re-opening device after "
2204 "MTU change\n");
2205 }
2206
2207 return 0;
2208 }
2209
2210 static void tx_timeout_task(struct work_struct *ugly)
2211 {
2212 struct mv643xx_eth_private *mp;
2213
2214 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2215 if (netif_running(mp->dev)) {
2216 netif_stop_queue(mp->dev);
2217
2218 port_reset(mp);
2219 port_start(mp);
2220
2221 __txq_maybe_wake(mp->txq + mp->txq_primary);
2222 }
2223 }
2224
2225 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2226 {
2227 struct mv643xx_eth_private *mp = netdev_priv(dev);
2228
2229 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2230
2231 schedule_work(&mp->tx_timeout_task);
2232 }
2233
2234 #ifdef CONFIG_NET_POLL_CONTROLLER
2235 static void mv643xx_eth_netpoll(struct net_device *dev)
2236 {
2237 struct mv643xx_eth_private *mp = netdev_priv(dev);
2238
2239 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2240 rdl(mp, INT_MASK(mp->port_num));
2241
2242 mv643xx_eth_irq(dev->irq, dev);
2243
2244 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2245 }
2246 #endif
2247
2248 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2249 {
2250 struct mv643xx_eth_private *mp = netdev_priv(dev);
2251 return smi_reg_read(mp, addr, reg);
2252 }
2253
2254 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2255 {
2256 struct mv643xx_eth_private *mp = netdev_priv(dev);
2257 smi_reg_write(mp, addr, reg, val);
2258 }
2259
2260
2261 /* platform glue ************************************************************/
2262 static void
2263 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2264 struct mbus_dram_target_info *dram)
2265 {
2266 void __iomem *base = msp->base;
2267 u32 win_enable;
2268 u32 win_protect;
2269 int i;
2270
2271 for (i = 0; i < 6; i++) {
2272 writel(0, base + WINDOW_BASE(i));
2273 writel(0, base + WINDOW_SIZE(i));
2274 if (i < 4)
2275 writel(0, base + WINDOW_REMAP_HIGH(i));
2276 }
2277
2278 win_enable = 0x3f;
2279 win_protect = 0;
2280
2281 for (i = 0; i < dram->num_cs; i++) {
2282 struct mbus_dram_window *cs = dram->cs + i;
2283
2284 writel((cs->base & 0xffff0000) |
2285 (cs->mbus_attr << 8) |
2286 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2287 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2288
2289 win_enable &= ~(1 << i);
2290 win_protect |= 3 << (2 * i);
2291 }
2292
2293 writel(win_enable, base + WINDOW_BAR_ENABLE);
2294 msp->win_protect = win_protect;
2295 }
2296
2297 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2298 {
2299 /*
2300 * Check whether we have a 14-bit coal limit field in bits
2301 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2302 * SDMA config register.
2303 */
2304 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2305 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2306 msp->extended_rx_coal_limit = 1;
2307 else
2308 msp->extended_rx_coal_limit = 0;
2309
2310 /*
2311 * Check whether the TX rate control registers are in the
2312 * old or the new place.
2313 */
2314 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2315 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2316 msp->tx_bw_control_moved = 1;
2317 else
2318 msp->tx_bw_control_moved = 0;
2319 }
2320
2321 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2322 {
2323 static int mv643xx_eth_version_printed = 0;
2324 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2325 struct mv643xx_eth_shared_private *msp;
2326 struct resource *res;
2327 int ret;
2328
2329 if (!mv643xx_eth_version_printed++)
2330 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2331 "driver version %s\n", mv643xx_eth_driver_version);
2332
2333 ret = -EINVAL;
2334 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2335 if (res == NULL)
2336 goto out;
2337
2338 ret = -ENOMEM;
2339 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2340 if (msp == NULL)
2341 goto out;
2342 memset(msp, 0, sizeof(*msp));
2343
2344 msp->base = ioremap(res->start, res->end - res->start + 1);
2345 if (msp->base == NULL)
2346 goto out_free;
2347
2348 mutex_init(&msp->phy_lock);
2349
2350 msp->err_interrupt = NO_IRQ;
2351 init_waitqueue_head(&msp->smi_busy_wait);
2352
2353 /*
2354 * Check whether the error interrupt is hooked up.
2355 */
2356 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2357 if (res != NULL) {
2358 int err;
2359
2360 err = request_irq(res->start, mv643xx_eth_err_irq,
2361 IRQF_SHARED, "mv643xx_eth", msp);
2362 if (!err) {
2363 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2364 msp->err_interrupt = res->start;
2365 }
2366 }
2367
2368 /*
2369 * (Re-)program MBUS remapping windows if we are asked to.
2370 */
2371 if (pd != NULL && pd->dram != NULL)
2372 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2373
2374 /*
2375 * Detect hardware parameters.
2376 */
2377 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2378 infer_hw_params(msp);
2379
2380 platform_set_drvdata(pdev, msp);
2381
2382 return 0;
2383
2384 out_free:
2385 kfree(msp);
2386 out:
2387 return ret;
2388 }
2389
2390 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2391 {
2392 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2393
2394 if (msp->err_interrupt != NO_IRQ)
2395 free_irq(msp->err_interrupt, msp);
2396 iounmap(msp->base);
2397 kfree(msp);
2398
2399 return 0;
2400 }
2401
2402 static struct platform_driver mv643xx_eth_shared_driver = {
2403 .probe = mv643xx_eth_shared_probe,
2404 .remove = mv643xx_eth_shared_remove,
2405 .driver = {
2406 .name = MV643XX_ETH_SHARED_NAME,
2407 .owner = THIS_MODULE,
2408 },
2409 };
2410
2411 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2412 {
2413 int addr_shift = 5 * mp->port_num;
2414 u32 data;
2415
2416 data = rdl(mp, PHY_ADDR);
2417 data &= ~(0x1f << addr_shift);
2418 data |= (phy_addr & 0x1f) << addr_shift;
2419 wrl(mp, PHY_ADDR, data);
2420 }
2421
2422 static int phy_addr_get(struct mv643xx_eth_private *mp)
2423 {
2424 unsigned int data;
2425
2426 data = rdl(mp, PHY_ADDR);
2427
2428 return (data >> (5 * mp->port_num)) & 0x1f;
2429 }
2430
2431 static void set_params(struct mv643xx_eth_private *mp,
2432 struct mv643xx_eth_platform_data *pd)
2433 {
2434 struct net_device *dev = mp->dev;
2435
2436 if (is_valid_ether_addr(pd->mac_addr))
2437 memcpy(dev->dev_addr, pd->mac_addr, 6);
2438 else
2439 uc_addr_get(mp, dev->dev_addr);
2440
2441 if (pd->phy_addr == -1) {
2442 mp->shared_smi = NULL;
2443 mp->phy_addr = -1;
2444 } else {
2445 mp->shared_smi = mp->shared;
2446 if (pd->shared_smi != NULL)
2447 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2448
2449 if (pd->force_phy_addr || pd->phy_addr) {
2450 mp->phy_addr = pd->phy_addr & 0x3f;
2451 phy_addr_set(mp, mp->phy_addr);
2452 } else {
2453 mp->phy_addr = phy_addr_get(mp);
2454 }
2455 }
2456
2457 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2458 if (pd->rx_queue_size)
2459 mp->default_rx_ring_size = pd->rx_queue_size;
2460 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2461 mp->rx_desc_sram_size = pd->rx_sram_size;
2462
2463 if (pd->rx_queue_mask)
2464 mp->rxq_mask = pd->rx_queue_mask;
2465 else
2466 mp->rxq_mask = 0x01;
2467 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2468
2469 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2470 if (pd->tx_queue_size)
2471 mp->default_tx_ring_size = pd->tx_queue_size;
2472 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2473 mp->tx_desc_sram_size = pd->tx_sram_size;
2474
2475 if (pd->tx_queue_mask)
2476 mp->txq_mask = pd->tx_queue_mask;
2477 else
2478 mp->txq_mask = 0x01;
2479 mp->txq_primary = fls(mp->txq_mask) - 1;
2480 }
2481
2482 static int phy_detect(struct mv643xx_eth_private *mp)
2483 {
2484 int data;
2485 int data2;
2486
2487 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2488 if (data < 0)
2489 return -ENODEV;
2490
2491 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2492 return -ENODEV;
2493
2494 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2495 if (data2 < 0)
2496 return -ENODEV;
2497
2498 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2499 return -ENODEV;
2500
2501 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2502
2503 return 0;
2504 }
2505
2506 static int phy_init(struct mv643xx_eth_private *mp,
2507 struct mv643xx_eth_platform_data *pd)
2508 {
2509 struct ethtool_cmd cmd;
2510 int err;
2511
2512 err = phy_detect(mp);
2513 if (err) {
2514 dev_printk(KERN_INFO, &mp->dev->dev,
2515 "no PHY detected at addr %d\n", mp->phy_addr);
2516 return err;
2517 }
2518 phy_reset(mp);
2519
2520 mp->mii.phy_id = mp->phy_addr;
2521 mp->mii.phy_id_mask = 0x3f;
2522 mp->mii.reg_num_mask = 0x1f;
2523 mp->mii.dev = mp->dev;
2524 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2525 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2526
2527 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2528
2529 memset(&cmd, 0, sizeof(cmd));
2530
2531 cmd.port = PORT_MII;
2532 cmd.transceiver = XCVR_INTERNAL;
2533 cmd.phy_address = mp->phy_addr;
2534 if (pd->speed == 0) {
2535 cmd.autoneg = AUTONEG_ENABLE;
2536 cmd.speed = SPEED_100;
2537 cmd.advertising = ADVERTISED_10baseT_Half |
2538 ADVERTISED_10baseT_Full |
2539 ADVERTISED_100baseT_Half |
2540 ADVERTISED_100baseT_Full;
2541 if (mp->mii.supports_gmii)
2542 cmd.advertising |= ADVERTISED_1000baseT_Full;
2543 } else {
2544 cmd.autoneg = AUTONEG_DISABLE;
2545 cmd.speed = pd->speed;
2546 cmd.duplex = pd->duplex;
2547 }
2548
2549 mv643xx_eth_set_settings(mp->dev, &cmd);
2550
2551 return 0;
2552 }
2553
2554 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2555 {
2556 u32 pscr;
2557
2558 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2559 if (pscr & SERIAL_PORT_ENABLE) {
2560 pscr &= ~SERIAL_PORT_ENABLE;
2561 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2562 }
2563
2564 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2565 if (mp->phy_addr == -1) {
2566 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2567 if (speed == SPEED_1000)
2568 pscr |= SET_GMII_SPEED_TO_1000;
2569 else if (speed == SPEED_100)
2570 pscr |= SET_MII_SPEED_TO_100;
2571
2572 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2573
2574 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2575 if (duplex == DUPLEX_FULL)
2576 pscr |= SET_FULL_DUPLEX_MODE;
2577 }
2578
2579 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2580 }
2581
2582 static int mv643xx_eth_probe(struct platform_device *pdev)
2583 {
2584 struct mv643xx_eth_platform_data *pd;
2585 struct mv643xx_eth_private *mp;
2586 struct net_device *dev;
2587 struct resource *res;
2588 DECLARE_MAC_BUF(mac);
2589 int err;
2590
2591 pd = pdev->dev.platform_data;
2592 if (pd == NULL) {
2593 dev_printk(KERN_ERR, &pdev->dev,
2594 "no mv643xx_eth_platform_data\n");
2595 return -ENODEV;
2596 }
2597
2598 if (pd->shared == NULL) {
2599 dev_printk(KERN_ERR, &pdev->dev,
2600 "no mv643xx_eth_platform_data->shared\n");
2601 return -ENODEV;
2602 }
2603
2604 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2605 if (!dev)
2606 return -ENOMEM;
2607
2608 mp = netdev_priv(dev);
2609 platform_set_drvdata(pdev, mp);
2610
2611 mp->shared = platform_get_drvdata(pd->shared);
2612 mp->port_num = pd->port_number;
2613
2614 mp->dev = dev;
2615
2616 set_params(mp, pd);
2617
2618 spin_lock_init(&mp->lock);
2619
2620 mib_counters_clear(mp);
2621 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2622
2623 if (mp->phy_addr != -1) {
2624 err = phy_init(mp, pd);
2625 if (err)
2626 goto out;
2627
2628 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2629 } else {
2630 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2631 }
2632 init_pscr(mp, pd->speed, pd->duplex);
2633
2634 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2635
2636 init_timer(&mp->rx_oom);
2637 mp->rx_oom.data = (unsigned long)mp;
2638 mp->rx_oom.function = oom_timer_wrapper;
2639
2640
2641 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2642 BUG_ON(!res);
2643 dev->irq = res->start;
2644
2645 dev->hard_start_xmit = mv643xx_eth_xmit;
2646 dev->open = mv643xx_eth_open;
2647 dev->stop = mv643xx_eth_stop;
2648 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2649 dev->set_mac_address = mv643xx_eth_set_mac_address;
2650 dev->do_ioctl = mv643xx_eth_ioctl;
2651 dev->change_mtu = mv643xx_eth_change_mtu;
2652 dev->tx_timeout = mv643xx_eth_tx_timeout;
2653 #ifdef CONFIG_NET_POLL_CONTROLLER
2654 dev->poll_controller = mv643xx_eth_netpoll;
2655 #endif
2656 dev->watchdog_timeo = 2 * HZ;
2657 dev->base_addr = 0;
2658
2659 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2660 /*
2661 * Zero copy can only work if we use Discovery II memory. Else, we will
2662 * have to map the buffers to ISA memory which is only 16 MB
2663 */
2664 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2665 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2666 #endif
2667
2668 SET_NETDEV_DEV(dev, &pdev->dev);
2669
2670 if (mp->shared->win_protect)
2671 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2672
2673 err = register_netdev(dev);
2674 if (err)
2675 goto out;
2676
2677 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2678 mp->port_num, print_mac(mac, dev->dev_addr));
2679
2680 if (dev->features & NETIF_F_SG)
2681 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2682
2683 if (dev->features & NETIF_F_IP_CSUM)
2684 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2685
2686 if (mp->tx_desc_sram_size > 0)
2687 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2688
2689 return 0;
2690
2691 out:
2692 free_netdev(dev);
2693
2694 return err;
2695 }
2696
2697 static int mv643xx_eth_remove(struct platform_device *pdev)
2698 {
2699 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2700
2701 unregister_netdev(mp->dev);
2702 flush_scheduled_work();
2703 free_netdev(mp->dev);
2704
2705 platform_set_drvdata(pdev, NULL);
2706
2707 return 0;
2708 }
2709
2710 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2711 {
2712 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2713
2714 /* Mask all interrupts on ethernet port */
2715 wrl(mp, INT_MASK(mp->port_num), 0);
2716 rdl(mp, INT_MASK(mp->port_num));
2717
2718 if (netif_running(mp->dev))
2719 port_reset(mp);
2720 }
2721
2722 static struct platform_driver mv643xx_eth_driver = {
2723 .probe = mv643xx_eth_probe,
2724 .remove = mv643xx_eth_remove,
2725 .shutdown = mv643xx_eth_shutdown,
2726 .driver = {
2727 .name = MV643XX_ETH_NAME,
2728 .owner = THIS_MODULE,
2729 },
2730 };
2731
2732 static int __init mv643xx_eth_init_module(void)
2733 {
2734 int rc;
2735
2736 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2737 if (!rc) {
2738 rc = platform_driver_register(&mv643xx_eth_driver);
2739 if (rc)
2740 platform_driver_unregister(&mv643xx_eth_shared_driver);
2741 }
2742
2743 return rc;
2744 }
2745 module_init(mv643xx_eth_init_module);
2746
2747 static void __exit mv643xx_eth_cleanup_module(void)
2748 {
2749 platform_driver_unregister(&mv643xx_eth_driver);
2750 platform_driver_unregister(&mv643xx_eth_shared_driver);
2751 }
2752 module_exit(mv643xx_eth_cleanup_module);
2753
2754 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2755 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2756 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2757 MODULE_LICENSE("GPL");
2758 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2759 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
kernel-based virtual machine