include/asm-powerpc/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef _ASM_POWERPC_SYSTEM_H
   5 #define _ASM_POWERPC_SYSTEM_H
   6
   7 #include <linux/kernel.h>
   8
   9 #include <asm/hw_irq.h>
  10 #include <asm/atomic.h>
  11
  12 /*
  13  * Memory barrier.
  14  * The sync instruction guarantees that all memory accesses initiated
  15  * by this processor have been performed (with respect to all other
  16  * mechanisms that access memory).  The eieio instruction is a barrier
  17  * providing an ordering (separately) for (a) cacheable stores and (b)
  18  * loads and stores to non-cacheable memory (e.g. I/O devices).
  19  *
  20  * mb() prevents loads and stores being reordered across this point.
  21  * rmb() prevents loads being reordered across this point.
  22  * wmb() prevents stores being reordered across this point.
  23  * read_barrier_depends() prevents data-dependent loads being reordered
  24  *      across this point (nop on PPC).
  25  *
  26  * We have to use the sync instructions for mb(), since lwsync doesn't
  27  * order loads with respect to previous stores.  Lwsync is fine for
  28  * rmb(), though. Note that rmb() actually uses a sync on 32-bit
  29  * architectures.
  30  *
  31  * For wmb(), we use sync since wmb is used in drivers to order
  32  * stores to system memory with respect to writes to the device.
  33  * However, smp_wmb() can be a lighter-weight eieio barrier on
  34  * SMP since it is only used to order updates to system memory.
  35  */
  36 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  37 #define rmb()  __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
  38 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  39 #define read_barrier_depends()  do { } while(0)
  40
  41 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  42
  43 #ifdef __KERNEL__
  44 #ifdef CONFIG_SMP
  45 #define smp_mb()        mb()
  46 #define smp_rmb()       rmb()
  47 #define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
  48 #define smp_read_barrier_depends()      read_barrier_depends()
  49 #else
  50 #define smp_mb()        barrier()
  51 #define smp_rmb()       barrier()
  52 #define smp_wmb()       barrier()
  53 #define smp_read_barrier_depends()      do { } while(0)
  54 #endif /* CONFIG_SMP */
  55
  56 /*
  57  * This is a barrier which prevents following instructions from being
  58  * started until the value of the argument x is known.  For example, if
  59  * x is a variable loaded from memory, this prevents following
  60  * instructions from being executed until the load has been performed.
  61  */
  62 #define data_barrier(x) \
  63         asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  64
  65 struct task_struct;
  66 struct pt_regs;
  67
  68 #ifdef CONFIG_DEBUGGER
  69
  70 extern int (*__debugger)(struct pt_regs *regs);
  71 extern int (*__debugger_ipi)(struct pt_regs *regs);
  72 extern int (*__debugger_bpt)(struct pt_regs *regs);
  73 extern int (*__debugger_sstep)(struct pt_regs *regs);
  74 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  75 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  76 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  77
  78 #define DEBUGGER_BOILERPLATE(__NAME) \
  79 static inline int __NAME(struct pt_regs *regs) \
  80 { \
  81         if (unlikely(__ ## __NAME)) \
  82                 return __ ## __NAME(regs); \
  83         return 0; \
  84 }
  85
  86 DEBUGGER_BOILERPLATE(debugger)
  87 DEBUGGER_BOILERPLATE(debugger_ipi)
  88 DEBUGGER_BOILERPLATE(debugger_bpt)
  89 DEBUGGER_BOILERPLATE(debugger_sstep)
  90 DEBUGGER_BOILERPLATE(debugger_iabr_match)
  91 DEBUGGER_BOILERPLATE(debugger_dabr_match)
  92 DEBUGGER_BOILERPLATE(debugger_fault_handler)
  93
  94 #else
  95 static inline int debugger(struct pt_regs *regs) { return 0; }
  96 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  97 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  98 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
  99 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
 100 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 101 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 102 #endif
 103
 104 extern int set_dabr(unsigned long dabr);
 105 extern void print_backtrace(unsigned long *);
 106 extern void show_regs(struct pt_regs * regs);
 107 extern void flush_instruction_cache(void);
 108 extern void hard_reset_now(void);
 109 extern void poweroff_now(void);
 110
 111 #ifdef CONFIG_6xx
 112 extern long _get_L2CR(void);
 113 extern long _get_L3CR(void);
 114 extern void _set_L2CR(unsigned long);
 115 extern void _set_L3CR(unsigned long);
 116 #else
 117 #define _get_L2CR()     0L
 118 #define _get_L3CR()     0L
 119 #define _set_L2CR(val)  do { } while(0)
 120 #define _set_L3CR(val)  do { } while(0)
 121 #endif
 122
 123 extern void via_cuda_init(void);
 124 extern void read_rtc_time(void);
 125 extern void pmac_find_display(void);
 126 extern void giveup_fpu(struct task_struct *);
 127 extern void disable_kernel_fp(void);
 128 extern void enable_kernel_fp(void);
 129 extern void flush_fp_to_thread(struct task_struct *);
 130 extern void enable_kernel_altivec(void);
 131 extern void giveup_altivec(struct task_struct *);
 132 extern void load_up_altivec(struct task_struct *);
 133 extern int emulate_altivec(struct pt_regs *);
 134 extern void giveup_spe(struct task_struct *);
 135 extern void load_up_spe(struct task_struct *);
 136 extern int fix_alignment(struct pt_regs *);
 137 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
 138 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 139
 140 #ifndef CONFIG_SMP
 141 extern void discard_lazy_cpu_state(void);
 142 #else
 143 static inline void discard_lazy_cpu_state(void)
 144 {
 145 }
 146 #endif
 147
 148 #ifdef CONFIG_ALTIVEC
 149 extern void flush_altivec_to_thread(struct task_struct *);
 150 #else
 151 static inline void flush_altivec_to_thread(struct task_struct *t)
 152 {
 153 }
 154 #endif
 155
 156 #ifdef CONFIG_SPE
 157 extern void flush_spe_to_thread(struct task_struct *);
 158 #else
 159 static inline void flush_spe_to_thread(struct task_struct *t)
 160 {
 161 }
 162 #endif
 163
 164 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 165 extern void cacheable_memzero(void *p, unsigned int nb);
 166 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 167 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 168 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 169 extern int die(const char *, struct pt_regs *, long);
 170 extern void _exception(int, struct pt_regs *, int, unsigned long);
 171 #ifdef CONFIG_BOOKE_WDT
 172 extern u32 booke_wdt_enabled;
 173 extern u32 booke_wdt_period;
 174 #endif /* CONFIG_BOOKE_WDT */
 175
 176 struct device_node;
 177 extern void note_scsi_host(struct device_node *, void *);
 178
 179 extern struct task_struct *__switch_to(struct task_struct *,
 180         struct task_struct *);
 181 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 182
 183 struct thread_struct;
 184 extern struct task_struct *_switch(struct thread_struct *prev,
 185                                    struct thread_struct *next);
 186
 187 /*
 188  * On SMP systems, when the scheduler does migration-cost autodetection,
 189  * it needs a way to flush as much of the CPU's caches as possible.
 190  *
 191  * TODO: fill this in!
 192  */
 193 static inline void sched_cacheflush(void)
 194 {
 195 }
 196
 197 extern unsigned int rtas_data;
 198 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 199 extern unsigned long memory_limit;
 200 extern unsigned long klimit;
 201
 202 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 203
 204 /*
 205  * Atomic exchange
 206  *
 207  * Changes the memory location '*ptr' to be val and returns
 208  * the previous value stored there.
 209  */
 210 static __inline__ unsigned long
 211 __xchg_u32(volatile void *p, unsigned long val)
 212 {
 213         unsigned long prev;
 214
 215         __asm__ __volatile__(
 216         LWSYNC_ON_SMP
 217 "1:     lwarx   %0,0,%2 \n"
 218         PPC405_ERR77(0,%2)
 219 "       stwcx.  %3,0,%2 \n\
 220         bne-    1b"
 221         ISYNC_ON_SMP
 222         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 223         : "r" (p), "r" (val)
 224         : "cc", "memory");
 225
 226         return prev;
 227 }
 228
 229 #ifdef CONFIG_PPC64
 230 static __inline__ unsigned long
 231 __xchg_u64(volatile void *p, unsigned long val)
 232 {
 233         unsigned long prev;
 234
 235         __asm__ __volatile__(
 236         LWSYNC_ON_SMP
 237 "1:     ldarx   %0,0,%2 \n"
 238         PPC405_ERR77(0,%2)
 239 "       stdcx.  %3,0,%2 \n\
 240         bne-    1b"
 241         ISYNC_ON_SMP
 242         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 243         : "r" (p), "r" (val)
 244         : "cc", "memory");
 245
 246         return prev;
 247 }
 248 #endif
 249
 250 /*
 251  * This function doesn't exist, so you'll get a linker error
 252  * if something tries to do an invalid xchg().
 253  */
 254 extern void __xchg_called_with_bad_pointer(void);
 255
 256 static __inline__ unsigned long
 257 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 258 {
 259         switch (size) {
 260         case 4:
 261                 return __xchg_u32(ptr, x);
 262 #ifdef CONFIG_PPC64
 263         case 8:
 264                 return __xchg_u64(ptr, x);
 265 #endif
 266         }
 267         __xchg_called_with_bad_pointer();
 268         return x;
 269 }
 270
 271 #define xchg(ptr,x)                                                          \
 272   ({                                                                         \
 273      __typeof__(*(ptr)) _x_ = (x);                                           \
 274      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 275   })
 276
 277 #define tas(ptr) (xchg((ptr),1))
 278
 279 /*
 280  * Compare and exchange - if *p == old, set it to new,
 281  * and return the old value of *p.
 282  */
 283 #define __HAVE_ARCH_CMPXCHG     1
 284
 285 static __inline__ unsigned long
 286 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 287 {
 288         unsigned int prev;
 289
 290         __asm__ __volatile__ (
 291         LWSYNC_ON_SMP
 292 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 293         cmpw    0,%0,%3\n\
 294         bne-    2f\n"
 295         PPC405_ERR77(0,%2)
 296 "       stwcx.  %4,0,%2\n\
 297         bne-    1b"
 298         ISYNC_ON_SMP
 299         "\n\
 300 2:"
 301         : "=&r" (prev), "+m" (*p)
 302         : "r" (p), "r" (old), "r" (new)
 303         : "cc", "memory");
 304
 305         return prev;
 306 }
 307
 308 #ifdef CONFIG_PPC64
 309 static __inline__ unsigned long
 310 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
 311 {
 312         unsigned long prev;
 313
 314         __asm__ __volatile__ (
 315         LWSYNC_ON_SMP
 316 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 317         cmpd    0,%0,%3\n\
 318         bne-    2f\n\
 319         stdcx.  %4,0,%2\n\
 320         bne-    1b"
 321         ISYNC_ON_SMP
 322         "\n\
 323 2:"
 324         : "=&r" (prev), "+m" (*p)
 325         : "r" (p), "r" (old), "r" (new)
 326         : "cc", "memory");
 327
 328         return prev;
 329 }
 330 #endif
 331
 332 /* This function doesn't exist, so you'll get a linker error
 333    if something tries to do an invalid cmpxchg().  */
 334 extern void __cmpxchg_called_with_bad_pointer(void);
 335
 336 static __inline__ unsigned long
 337 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 338           unsigned int size)
 339 {
 340         switch (size) {
 341         case 4:
 342                 return __cmpxchg_u32(ptr, old, new);
 343 #ifdef CONFIG_PPC64
 344         case 8:
 345                 return __cmpxchg_u64(ptr, old, new);
 346 #endif
 347         }
 348         __cmpxchg_called_with_bad_pointer();
 349         return old;
 350 }
 351
 352 #define cmpxchg(ptr,o,n)                                                 \
 353   ({                                                                     \
 354      __typeof__(*(ptr)) _o_ = (o);                                       \
 355      __typeof__(*(ptr)) _n_ = (n);                                       \
 356      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 357                                     (unsigned long)_n_, sizeof(*(ptr))); \
 358   })
 359
 360 #ifdef CONFIG_PPC64
 361 /*
 362  * We handle most unaligned accesses in hardware. On the other hand
 363  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 364  * powers of 2 writes until it reaches sufficient alignment).
 365  *
 366  * Based on this we disable the IP header alignment in network drivers.
 367  * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
 368  * cacheline alignment of buffers.
 369  */
 370 #define NET_IP_ALIGN    0
 371 #define NET_SKB_PAD     L1_CACHE_BYTES
 372 #endif
 373
 374 #define arch_align_stack(x) (x)
 375
 376 /* Used in very early kernel initialization. */
 377 extern unsigned long reloc_offset(void);
 378 extern unsigned long add_reloc_offset(unsigned long);
 379 extern void reloc_got2(unsigned long);
 380
 381 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 382
 383 static inline void create_instruction(unsigned long addr, unsigned int instr)
 384 {
 385         unsigned int *p;
 386         p  = (unsigned int *)addr;
 387         *p = instr;
 388         asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
 389 }
 390
 391 /* Flags for create_branch:
 392  * "b"   == create_branch(addr, target, 0);
 393  * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
 394  * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
 395  * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
 396  */
 397 #define BRANCH_SET_LINK 0x1
 398 #define BRANCH_ABSOLUTE 0x2
 399
 400 static inline void create_branch(unsigned long addr,
 401                 unsigned long target, int flags)
 402 {
 403         unsigned int instruction;
 404
 405         if (! (flags & BRANCH_ABSOLUTE))
 406                 target = target - addr;
 407
 408         /* Mask out the flags and target, so they don't step on each other. */
 409         instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
 410
 411         create_instruction(addr, instruction);
 412 }
 413
 414 static inline void create_function_call(unsigned long addr, void * func)
 415 {
 416         unsigned long func_addr;
 417
 418 #ifdef CONFIG_PPC64
 419         /*
 420          * On PPC64 the function pointer actually points to the function's
 421          * descriptor. The first entry in the descriptor is the address
 422          * of the function text.
 423          */
 424         func_addr = *(unsigned long *)func;
 425 #else
 426         func_addr = (unsigned long)func;
 427 #endif
 428         create_branch(addr, func_addr, BRANCH_SET_LINK);
 429 }
 430
 431 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 432 extern void account_system_vtime(struct task_struct *);
 433 #endif
 434
 435 #endif /* __KERNEL__ */
 436 #endif /* _ASM_POWERPC_SYSTEM_H */