arch/arm/mach-mx2/mach-mx27ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/platform_device.h>
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/map.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/mtd/physmap.h>
  26 #include <linux/i2c.h>
  27 #include <linux/irq.h>
  28 #include <mach/common.h>
  29 #include <mach/hardware.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/time.h>
  33 #include <asm/mach/map.h>
  34 #include <mach/gpio.h>
  35 #include <mach/imx-uart.h>
  36 #include <mach/iomux-mx27.h>
  37 #include <mach/mxc_nand.h>
  38 #include <mach/i2c.h>
  39 #include <mach/imxfb.h>
  40 #include <mach/mmc.h>
  41
  42 #include "devices.h"
  43
  44 /*
  45  * Base address of PBC controller, CS4
  46  */
  47 #define PBC_BASE_ADDRESS        0xf4300000
  48 #define PBC_REG_ADDR(offset)    (void __force __iomem *) \
  49                 (PBC_BASE_ADDRESS + (offset))
  50
  51 /* When the PBC address connection is fixed in h/w, defined as 1 */
  52 #define PBC_ADDR_SH             0
  53
  54 /* Offsets for the PBC Controller register */
  55 /*
  56  * PBC Board version register offset
  57  */
  58 #define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
  59 /*
  60  * PBC Board control register 1 set address.
  61  */
  62 #define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
  63 /*
  64  * PBC Board control register 1 clear address.
  65  */
  66 #define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
  67
  68 /* PBC Board Control Register 1 bit definitions */
  69 #define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
  70
  71 /* to determine the correct external crystal reference */
  72 #define CKIH_27MHZ_BIT_SET      (1 << 3)
  73
  74 static unsigned int mx27ads_pins[] = {
  75         /* UART0 */
  76         PE12_PF_UART1_TXD,
  77         PE13_PF_UART1_RXD,
  78         PE14_PF_UART1_CTS,
  79         PE15_PF_UART1_RTS,
  80         /* UART1 */
  81         PE3_PF_UART2_CTS,
  82         PE4_PF_UART2_RTS,
  83         PE6_PF_UART2_TXD,
  84         PE7_PF_UART2_RXD,
  85         /* UART2 */
  86         PE8_PF_UART3_TXD,
  87         PE9_PF_UART3_RXD,
  88         PE10_PF_UART3_CTS,
  89         PE11_PF_UART3_RTS,
  90         /* UART3 */
  91         PB26_AF_UART4_RTS,
  92         PB28_AF_UART4_TXD,
  93         PB29_AF_UART4_CTS,
  94         PB31_AF_UART4_RXD,
  95         /* UART4 */
  96         PB18_AF_UART5_TXD,
  97         PB19_AF_UART5_RXD,
  98         PB20_AF_UART5_CTS,
  99         PB21_AF_UART5_RTS,
 100         /* UART5 */
 101         PB10_AF_UART6_TXD,
 102         PB12_AF_UART6_CTS,
 103         PB11_AF_UART6_RXD,
 104         PB13_AF_UART6_RTS,
 105         /* FEC */
 106         PD0_AIN_FEC_TXD0,
 107         PD1_AIN_FEC_TXD1,
 108         PD2_AIN_FEC_TXD2,
 109         PD3_AIN_FEC_TXD3,
 110         PD4_AOUT_FEC_RX_ER,
 111         PD5_AOUT_FEC_RXD1,
 112         PD6_AOUT_FEC_RXD2,
 113         PD7_AOUT_FEC_RXD3,
 114         PD8_AF_FEC_MDIO,
 115         PD9_AIN_FEC_MDC,
 116         PD10_AOUT_FEC_CRS,
 117         PD11_AOUT_FEC_TX_CLK,
 118         PD12_AOUT_FEC_RXD0,
 119         PD13_AOUT_FEC_RX_DV,
 120         PD14_AOUT_FEC_RX_CLK,
 121         PD15_AOUT_FEC_COL,
 122         PD16_AIN_FEC_TX_ER,
 123         PF23_AIN_FEC_TX_EN,
 124         /* I2C2 */
 125         PC5_PF_I2C2_SDA,
 126         PC6_PF_I2C2_SCL,
 127         /* FB */
 128         PA5_PF_LSCLK,
 129         PA6_PF_LD0,
 130         PA7_PF_LD1,
 131         PA8_PF_LD2,
 132         PA9_PF_LD3,
 133         PA10_PF_LD4,
 134         PA11_PF_LD5,
 135         PA12_PF_LD6,
 136         PA13_PF_LD7,
 137         PA14_PF_LD8,
 138         PA15_PF_LD9,
 139         PA16_PF_LD10,
 140         PA17_PF_LD11,
 141         PA18_PF_LD12,
 142         PA19_PF_LD13,
 143         PA20_PF_LD14,
 144         PA21_PF_LD15,
 145         PA22_PF_LD16,
 146         PA23_PF_LD17,
 147         PA24_PF_REV,
 148         PA25_PF_CLS,
 149         PA26_PF_PS,
 150         PA27_PF_SPL_SPR,
 151         PA28_PF_HSYNC,
 152         PA29_PF_VSYNC,
 153         PA30_PF_CONTRAST,
 154         PA31_PF_OE_ACD,
 155         /* OWIRE */
 156         PE16_AF_OWIRE,
 157         /* SDHC1*/
 158         PE18_PF_SD1_D0,
 159         PE19_PF_SD1_D1,
 160         PE20_PF_SD1_D2,
 161         PE21_PF_SD1_D3,
 162         PE22_PF_SD1_CMD,
 163         PE23_PF_SD1_CLK,
 164         /* SDHC2*/
 165         PB4_PF_SD2_D0,
 166         PB5_PF_SD2_D1,
 167         PB6_PF_SD2_D2,
 168         PB7_PF_SD2_D3,
 169         PB8_PF_SD2_CMD,
 170         PB9_PF_SD2_CLK,
 171 };
 172
 173 static struct mxc_nand_platform_data mx27ads_nand_board_info = {
 174         .width = 1,
 175         .hw_ecc = 1,
 176 };
 177
 178 /* ADS's NOR flash */
 179 static struct physmap_flash_data mx27ads_flash_data = {
 180         .width = 2,
 181 };
 182
 183 static struct resource mx27ads_flash_resource = {
 184         .start = 0xc0000000,
 185         .end = 0xc0000000 + 0x02000000 - 1,
 186         .flags = IORESOURCE_MEM,
 187
 188 };
 189
 190 static struct platform_device mx27ads_nor_mtd_device = {
 191         .name = "physmap-flash",
 192         .id = 0,
 193         .dev = {
 194                 .platform_data = &mx27ads_flash_data,
 195         },
 196         .num_resources = 1,
 197         .resource = &mx27ads_flash_resource,
 198 };
 199
 200 static struct imxi2c_platform_data mx27ads_i2c_data = {
 201         .bitrate = 100000,
 202 };
 203
 204 static struct i2c_board_info mx27ads_i2c_devices[] = {
 205 };
 206
 207 void lcd_power(int on)
 208 {
 209         if (on)
 210                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
 211         else
 212                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 213 }
 214
 215 static struct imx_fb_videomode mx27ads_modes[] = {
 216         {
 217                 .mode = {
 218                         .name           = "Sharp-LQ035Q7",
 219                         .refresh        = 60,
 220                         .xres           = 240,
 221                         .yres           = 320,
 222                         .pixclock       = 188679, /* in ps (5.3MHz) */
 223                         .hsync_len      = 1,
 224                         .left_margin    = 9,
 225                         .right_margin   = 16,
 226                         .vsync_len      = 1,
 227                         .upper_margin   = 7,
 228                         .lower_margin   = 9,
 229                 },
 230                 .bpp            = 16,
 231                 .pcr            = 0xFB008BC0,
 232         },
 233 };
 234
 235 static struct imx_fb_platform_data mx27ads_fb_data = {
 236         .mode = mx27ads_modes,
 237         .num_modes = ARRAY_SIZE(mx27ads_modes),
 238
 239         /*
 240          * - HSYNC active high
 241          * - VSYNC active high
 242          * - clk notenabled while idle
 243          * - clock inverted
 244          * - data not inverted
 245          * - data enable low active
 246          * - enable sharp mode
 247          */
 248         .pwmr           = 0x00A903FF,
 249         .lscr1          = 0x00120300,
 250         .dmacr          = 0x00020010,
 251
 252         .lcd_power      = lcd_power,
 253 };
 254
 255 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 256                               void *data)
 257 {
 258         return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
 259                            "sdhc1-card-detect", data);
 260 }
 261
 262 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 263                               void *data)
 264 {
 265         return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
 266                            "sdhc2-card-detect", data);
 267 }
 268
 269 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 270 {
 271         free_irq(IRQ_GPIOE(21), data);
 272 }
 273
 274 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 275 {
 276         free_irq(IRQ_GPIOB(7), data);
 277 }
 278
 279 static struct imxmmc_platform_data sdhc1_pdata = {
 280         .init = mx27ads_sdhc1_init,
 281         .exit = mx27ads_sdhc1_exit,
 282 };
 283
 284 static struct imxmmc_platform_data sdhc2_pdata = {
 285         .init = mx27ads_sdhc2_init,
 286         .exit = mx27ads_sdhc2_exit,
 287 };
 288
 289 static struct platform_device *platform_devices[] __initdata = {
 290         &mx27ads_nor_mtd_device,
 291         &mxc_fec_device,
 292         &mxc_w1_master_device,
 293 };
 294
 295 static struct imxuart_platform_data uart_pdata[] = {
 296         {
 297                 .flags = IMXUART_HAVE_RTSCTS,
 298         }, {
 299                 .flags = IMXUART_HAVE_RTSCTS,
 300         }, {
 301                 .flags = IMXUART_HAVE_RTSCTS,
 302         }, {
 303                 .flags = IMXUART_HAVE_RTSCTS,
 304         }, {
 305                 .flags = IMXUART_HAVE_RTSCTS,
 306         }, {
 307                 .flags = IMXUART_HAVE_RTSCTS,
 308         },
 309 };
 310
 311 static void __init mx27ads_board_init(void)
 312 {
 313         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
 314                         "mx27ads");
 315
 316         mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
 317         mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
 318         mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
 319         mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
 320         mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
 321         mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
 322         mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
 323
 324         /* only the i2c master 1 is used on this CPU card */
 325         i2c_register_board_info(1, mx27ads_i2c_devices,
 326                                 ARRAY_SIZE(mx27ads_i2c_devices));
 327         mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
 328         mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
 329         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
 330         mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
 331
 332         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 333 }
 334
 335 static void __init mx27ads_timer_init(void)
 336 {
 337         unsigned long fref = 26000000;
 338
 339         if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
 340                 fref = 27000000;
 341
 342         mx27_clocks_init(fref);
 343 }
 344
 345 static struct sys_timer mx27ads_timer = {
 346         .init   = mx27ads_timer_init,
 347 };
 348
 349 static struct map_desc mx27ads_io_desc[] __initdata = {
 350         {
 351                 .virtual = PBC_BASE_ADDRESS,
 352                 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
 353                 .length = SZ_1M,
 354                 .type = MT_DEVICE,
 355         },
 356 };
 357
 358 static void __init mx27ads_map_io(void)
 359 {
 360         mx27_map_io();
 361         iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
 362 }
 363
 364 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
 365         /* maintainer: Freescale Semiconductor, Inc. */
 366         .phys_io        = MX27_AIPI_BASE_ADDR,
 367         .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 368         .boot_params    = MX27_PHYS_OFFSET + 0x100,
 369         .map_io         = mx27ads_map_io,
 370         .init_irq       = mx27_init_irq,
 371         .init_machine   = mx27ads_board_init,
 372         .timer          = &mx27ads_timer,
 373 MACHINE_END